72A0TxSTM8G13KWI 128Mx72 SDRAM DIMM Registered, Refresh, 3.3V with
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128M Registered PC100/133 SDRAM DIMM Registered PC100/133 SYNCHRONOUS DRAM DIMM
72A0TxSTM8G13KWI 128Mx72 SDRAM DIMM Registered, Refresh, 3.3V with
Assignment
Pin# Pin# DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB0 DQMB1 A10/AP DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CAS* DQMB4 DQMB5 RAS* Pin# DQMB2 DQMB3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Pin# CKE0 DQMB6 DQMB7 DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
General Description
module 128Mx72 bit, chip, DIMM module consisting 64Mx8x2 (Stacked TSOP) SDRAM, Universal Driver Registers, Clock Driver, 256x8 EEPROM serial presence detect. module conforms PC100/133 timing specifications byte data masks.
Features
JEDEC-Standard 168-pin Dual Inline Memory Module (DIMM) Address Control lines Buffered/Registered On-module Based 64Mx8x2 Stacked SDRAM Components Power Supply: 3.3V 0.3V 64ms, 8192-cycle refresh Serial Presence Detect (SPD) LVTTL Compatible Inputs Outputs External Banks First bank controlled with Second bank controlled with Four Internal Banks Pure Power Ground Planes Gold connector
Active
Valid Part Numbers
Part Number 72A0TFSTM8G13KWI 72A0TESTM8G13KWI 72A0THSTM8G13KWI 72A0TGSTM8G13KWI Speed 100Mhz 100Mhz 133Mhz 133Mhz Latency
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Block Diagram
SDRAM DIMM, Bank with SDRAMs
RS0/RS1 RDQMB0 DQ(0:7) RDQMB4 DQ(32:39)
S0-S3 DQMB0 BA0-BAN
RS0-RS3
RDQMB1
RDQMB5
A0-A12
DQ(8:15)
DQ(40:47)
CKE0
RDQMB0 RBA0-RBAN RA0-RA12 RCKE0 RRAS RCAS
REGE
CB(0:7)
RS2/RS3 RDQMB2 DQ(16:23) RDQMB6 DQ(48:55)
RBA0,RBA1 RA0-RA12 RCAS RRAS RCKE0 BA0,BA1: SDRAMs U1-U9 A0-A12: SDRAMs U1-U9 CAS: SDRAMs U1-U9 RAS: SDRAMs U1-U9 CKE0: SDRAMs U1-U9 SDRAMs U1-U9
RDQMB3 DQ(24:31)
RDQMB7 DQ(56:63)
*CLOCK WIRING
CLOCK INPUT *CK0 *CK1 *CK2 *CK3 SDRAMs TERMINATION TERMINATION TERMINATION
SDRAM
CLK0
SDRAM
Bypass: capacitors SDRAM.
Note: Resistor values Ohms
.0022µ 0.22µ
U1-9
SERIAL
SDRAM loads equivalent output.
U1-9
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Descriptions
CLK# REGE DQM0-DQM7 DQ0-DQ63 CB0-7 SDA, Name System Clock Chip Select Clock Enable Address Lines Bank Select Lines Address Strobe Column Address Strobe Write Enable Register Enable Data Masks Data Lines Check Bits Power Supply Ground Write Protect Data/Clock Lines Address Lines Connection Function input signals sampled rising edge clock. Enables disables command decoder. commands disabled when high. Masks system clock freeze current operation next clock cycle, also provides access standby mode (see truth table). Input lines Row/Column address. Selects internal bank accessed during column address latch. Latches address rising edge clock when asserted. Latches column address rising edge clock when asserted. Enables write operation precharge. Buffer/Registered operate transparent mode when REGE low; registered mode with REGE high (all inputs delayed clock). Provides byte mask write operations byte enable read operations. Data input/output lines. Check input/output lines. Power Supply 3.3V±0.3V Ground Serial Presence Detect (SPD) EEPROM write protect. programming inhibited when asserted. Serial Presence Detect (SPD) EEPROM lines. These lines provide bi-directional data transfer over bus. Serial Presence Detect (SPD) EEPROM address lines. These lines used configure SPD. Line connected DIMM.
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Serial Presence Detect Data
Byte Function PC133 PC133 PC100 PC100 Description
36-61 64-125 128-255
Define bytes written into EEPROM Total bytes memory device Fundamental memory type (EDO,SDRAM.) addresses column addresses module rows Data width. .Data width continued Voltage interface SDRAM cycle time SDRAM access from clock DIMM configuration type (non-parity,ECC.) Refresh rate/type Primary SDRAM width Error checking SDRAM width Minimum clock delay back back random column address Burst lengths supported banks each SDRAM device CAS# latencies supported latency Write latency SDRAM module attributes SDRAM device attributes: general SDRAM cycle time SDRAM access from clock SDRAM cycle time SDRAM access from clock precharge time active active delay Minimum pulse width Density each module Command Address signal input setup time Command Address signal input hold time Data signal input setup time Data signal input hold time Superset information (may used future) data revision code Checksum bytes 0-62 Manufacturer's information Intel specification frequency Intel specification CAS# latency support Unused storage locations
SDRAM LVTTL PC100, 7.5ns PC133 6.0ns PC100, 54ns PC133 Normal Self Refresh page/8/4/2/1 (PC100 PC133) latency=0 latency=0 Registered Inputs w/PLL Write1/Read burst/Precharge 7.5ns PC133 CL2, 10ns PC133 CL3, PC100 CL2, 12ns PC100 5.4ns PC133 CL2, PC133 PC100 CL2, PC100 20ns PC100 PC133 CL3, 15ns PC133 20ns PC100, 15ns PC133 20ns (PC100 PC133 CL3), 15ns PC133 50ns PC100, 45ns PC133 512MB PC100, 1.5ns PC133 PC100, 0.8ns PC133 PC100, 1.5ns PC133 PC100, 0.8ns PC133 written PC100, PC133 Calculated Checksum written 100Mhz+ PC100 PC133, PC100 written
NOTE:
Variable Data.
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Simplified Truth Table
Command Register Refresh Mode Register Auto refresh Entry Self Refresh Exit CKEn-1 CKEn RAS* CAS* Column addr (A0-A10) BA0,1 A10/ A12,A11 A9-A0 Code Address Column addr (A0-A10) Note
Bank active address Auto pre-charge Read disable column Auto pre-charge address enable Auto pre-charge Write disable column Auto pre-charge address enable Burst stop Bank Selection Pre-charge Banks Entry Clock Suspend Mode active power down Exit Pre-charge power down mode Entry Exit
operation command (V=Valid, X=Don't care, H=Logic High, L=Logic Low) Notes:
issued only idle state. burst read write with auto pre-charge cannot interrupted. commands issued after burst.
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Absolute Maximum Ratings
Parameter Voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature NOTE: Symbol Iout Topr Value -1.0 14.4 +125 Units
Permanent damage occur absolute maximum ratings exceeded. Device should operated within recommended operating conditions only.
Characteristics 70C, 3.3V 0.3V)
Parameter Supply voltage Supply voltage Input high voltage Input voltage Output high voltage Output voltage Symbol Vcc+0.3 Units Note
Ioh=-2mA Iol=2mA
Current Consumption 70C, 3.3V 0.3V)
Parameter Operating current (One bank active) Precharge standby current power down mode Symbol ICC1 ICC2P ICC2PS ICC2N Precharge standby current nonpower down mode ICC2NS Test Condition Burst length tRC(min) ,IO= CKE0 (max), CKE0,CKE1 (max), CKE0,CKE1 (min), min, S0*-S3*= (min) Input signals changed once during clock cycles CKE0,CKE1 (min), (max), Input signals stable CKE0 (min), min, S0*-S3*= (min) Input signals changed once during clock cycles CKE0 (min), (max), Input signals stable Page Burst, multiple banks active, tCCD 2CLK (min) CKE0 PC100 CL2/3 2484 129.6 129.6 PC133 2808 129.6 86.4 PC133 2808 129.6 86.4 388.8 388.8 388.8 Unit Note
Active standby current non-power down mode Burst Operating Current Refresh Current Self Refresh Current Latency
ICC3N ICC3NS ICC4 ICC5 ICC6
1296 2592 3996
1296 3348 3996
1296 3348 3996
Capacitance 70C, 3.3V 0.3V,
Parameter Input capacitance (Am, BA0,CKEm) Input capacitance (DQMBm) Input capacitance (CAS*, RAS*, WE*) Input capacitance (CKm) Input capacitance (SDA,SCL,SAm) Input/Output capacitance (DQm,CBm) CI/O Symbol Units Note
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Characteristics 70C, 3.3V 0.3V,
Parameter Cycle time Cycle time Symbol tCMS tCKS tCMH tCKH tPDE tRRD (min) tRCD (min) (min) tRAS (min) tRSC (min) PC133 8000 1000 1000 PC133 1000 1000 8000 PC100 1000 1000 8000 PC100 1000 1000 8000 Units Note
valid output delay valid output delay Output data hold time Output valid High-Z high pulse width pulse width Command setup time Address setup time Clock enable setup time Data input setup time Command hold time Address hold time Clock enable hold time Data input hold time Power down exit setup time active active delay RAS* CAS* delay precharge time active time cycle time Mode Register Active Delay Latency
Notes Overshoot: (MAX) 2.0V Undershoot: (MIN) 2.0V Typical peak current consumption. Measured with outputs open. Assumes minimum column address update cycle: tCCD(min). Parameters depend programmed Latency. Assumed input rise fall time=1ns. time tPDE elapse after asserting resume normal operation when exiting power down mode. Timings listed discrete SDRAM components. registered mode, address control signals delayed clock cycle. buffered mode, address control signals must first propagate through buffer.
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Command Input Timing tCMS tCMS tCMS tCMS A0-A11 BS0,1 tCKS tCKH tCKS tCKS tCKH tCMH tCMS
Read Timing Read Latency
A0-A1 BS0,1
VALID DATA
VALID DATA
Read Command
Burst Length
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Control Timing Input Data (Word Mask) tCMH DQ0~7
VALID DATA
tCMS tCMH
tCMS
VALID DATA
VALID DATA
VALID DATA
(Clock Mask) tCKH DQ0~7
VALID DATA
tCKS
tCKS
VALID DATA
VALID DATA
VALID DATA
Control Timing Output Data (Output Enable) tCMH DQ0~7 (Clock Mask) tCKH DQ0~7
VALID DATA VALID DATA
tCMS tCMH
tCMS
VALID DATA
VALID DATA
VALID DATA
tCKS
tCKH
tCKS
VALID DATA
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Mode Register Cycle tRSC tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH
Next Command
Register Data
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
128M Registered PC100/133 SDRAM DIMM
Outline Drawing
FRONT VIEW
SIDE VIEW .100" .100"
BACK VIEW
.260"
Note: Drawing component location only, assembly have components installed.
128Mx72 Registered PC100/133 DIMM DS1129-72A0T 08/01/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
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