6480YsSWM4G05TWE 8Mx64 SDRAM SODIMM Unbuffered, Refresh, 3.3V with Gen

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6480YsSWM4G05TWE 8Mx64 SDRAM SODIMM Unbuffered, Refresh, 3.3V with Gen

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SDRAM SODIMM PC100/133 SYNCHRONOUS SMALL OUTLINE DRAM DIMM
6480YsSWM4G05TWE 8Mx64 SDRAM SODIMM Unbuffered, Refresh, 3.3V with General Description
module 8Mx64 bit, chip, SODIMM module consisting 8Mx16 (TSOP) SDRAM 256x8 EEPROM serial presence detect. module conforms PC100/133 specifications, unbuffered, byte data masks.
Assignment
Pin# Symbol DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB0 DQMB4 DQMB1 DQMB5 Pin# Symbol DQ40 DQ41 DQ10 DQ42 DQ11 DQ43 DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 CKE0 RAS* CAS* Pin# Symbol DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 Pin# Symbol A10/AP DQMB2 DQMB6 DQMB3 DQMB7 DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63
Features
Fully PC100/133 Compliant JEDEC-Standard 144-pin Small Outline Dual Inline Memory Module (SODIMM) Unbuffered Based 8Mx16 SDRAM Components Power Supply: 3.3V 0.3V 64ms, 4096-cycle refresh Serial Presence Detect (SPD) LVTTL Compatible Inputs Outputs External Bank Four Internal Banks Pure Power Ground Planes Gold connector
Valid Part Numbers
Part Number 6480YFSWM4G05TWE 6480YESWM4G05TWE 6480YHSWM4G05TWE 6480YGSWM4G05TWE Speed 100Mhz 100Mhz 133Mhz 133Mhz Latency
Active
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Block Diagram
SDRAM SODIMM, 1BANKs with SDRAMs
DQMB0 DQ(0:7) DQMB4
DQ(32:39)
DQMB1
DQMB5
DQ(8:15)
DQ(40:47)
S0/S1 DQMB2 DQ(16:23) DQMB6
DQ(48:55)
DQMB3
DQMB7
DQ(24:31)
DQ(56:63)
*CLOCK WIRING CLOCK INPUT *CK0 *CK1 *CK2 *CK3 SDRAM SDRAM TERMINATION TERMINATION TERMINATION CKE0 SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs
wire Clock loading Table/Wiring diagrams.
SERIAL
Bypass: Three 0.10uF capacitor SDRAMs device.
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Descriptions
DQM0-DQM7 DQ0-DQ63 SDA, Name System Clock Chip Select Clock Enable Address Lines Bank Select Lines Address Strobe Column Address Strobe Write Enable Data Masks Data Lines Power Supply Ground Data/Clock Lines Connection Function input signals sampled rising edge clock. Enables disables command decoder. commands disabled when high. Masks system clock freeze current operation next clock cycle, also provides access standby mode (see truth table). Input lines Row/Column address. Selects internal bank accessed during column address latch. Latches address rising edge clock when asserted. Latches column address rising edge clock when asserted. Enables write operation precharge. Provides byte mask write operations byte enable read operations. Data input/output lines. Power Supply 3.3V±0.3V Ground Serial Presence Detect (SPD) EEPROM lines. These lines provide bi-directional data transfer over bus. Line connected DIMM.
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Serial Presence Detect Matrix
Byte Function PC133
PC133
PC100
PC100
Description
128-255
Define bytes written into EEPROM Total bytes memory device Fundamental memory type (EDO,SDRAM.) addresses column addresses module rows Data width. .Data width continued Voltage interface SDRAM cycle time SDRAM access from clock DIMM configuration type (non- parity,ECC.) Refresh rate/type Primary SDRAM width Error checking SDRAM width Minimum clock delay back back random column address Burst lengths supported banks each SDRAM device CAS# latencies supported latency Write latency SDRAM module attributes SDRAM device attributes: general SDRAM cycle time SDRAM access from clock SDRAM cycle time SDRAM access from clock precharge time active active delay Minimum pulse width Density each module Command Address signal input setup time Command Address signal input hold time Data signal input setup time Data signal input hold time Superset information (may used future) data revision code Checksum bytes 0-62 Manufacturer's information Intel cification frequency Intel specification CAS# latency support Unused storage locations
SDRAM LVTTL PC100, 7.5ns PC133 6.0ns PC100, 54ns PC133 non-parity Normal/Sel page/8/4/2/1 (PC100 PC133) latency=0 latency=0 Unbuffered Write1/Read burst/Precharge 7.5ns PC133 CL2, 10ns PC133 CL3, PC100 CL2, 12ns PC100 5.4ns PC133 CL2, PC133 PC100 CL2, PC100 20ns PC100 PC133 CL3, 15ns PC133 20ns PC100, 15ns PC133 20ns (PC100 PC133 CL3), 15ns PC133 50ns PC100, 45ns PC133 64MB PC100, 1.5ns PC133 PC100, 0.8ns PC133 PC100, 1.5ns PC133 PC100, 0.8ns PC133 written PC100, PC133 Calculated Checksum written 100Mhz+ PC100 PC133, PC100 written
NOTE:
Variable Data.
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Simplified Truth Table
mmand Register Refresh Mode Register Auto refresh Entry Self Refresh Exit CKEn-1 CKEn RAS* CAS* BA0,1 A10/AP Code Address Column addr (A0-A7) Column addr (A0-A7) A9-A0 Note
Bank active address Read column Auto precharge disable address Auto precharge enable Write column Auto precharge disable address Auto precharge enable Burst stop Bank Selection Precharge Banks Clock Suspend Mode Entry active power down Exit Entry Precharge power down mode Exit
operation command (V=Valid, X=Don't care, H=Logic High, L=Logic Low) Notes
issued only idle state. burst read write with auto precharge cannot interrupted. commands issued after burst. sampled positive clock edge results Hi-Z within cycles, however data immediately invalid should ignored.
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Absolute Maximum Ratings
Parameter Voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature NOTE: Symbol Iout Topr Value -1.0 +125 Units
Permanent damage occur absolute maximum ratings exceeded. Device should operated within recommended operating conditions only.
Characteristics 70C, 3.3V 0.3V)
Parameter Supply voltage Supply voltage Input high voltage Input voltage Output high voltage Output voltage Symbol Vcc+0.3 Units Note
Ioh=-2mA Iol=2mA
Current Consumption 70C, 3.3V 0.3V)
Parameter Operating current (One bank active) Precharge standby current power down mode Symbol ICC1 ICC2P ICC2PS ICC2N Precharge standby current nonpower down mode ICC2NS Test Condition Burst length tRC(min) ,IO= CKE0 (max), CKE0,CKE1 (max), CKE0,CKE1 (min), min, S0*-S3*= (min) Input signals changed once during clock cycles CKE0,CKE1 (min), (max), Input signals stable CKE0 (min), min, S0*-S3*= (min) Input signals changed once during clock cycles CKE0 (min), (max), Input signals stable Page Burst, multiple banks active, 2CLK (min) CKE0 PC100 CL2/3 PC133 PC133 Unit Note
Active standby current non-power down mode Burst Operating Current Refresh Current Self Refresh Current Latency
ICC3N ICC3NS ICC4 ICC5 ICC6
1296
1488
1584
Capacitance 70C, 3.3V 0.3V,
Parameter Input capacitance (Am, BA0,CKEm) Input capacitance (DQMBm) Input capacitance (CAS*, RAS*, WE*) Input capacitance (CKm) Input capacitance (SDA,SCL,SAm) Input/Output capacitance (DQm,CBm) CI/O Symbol 15.2 15.2 Units Note
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Characteristics 70C, 3.3V 0.3V,
Parameter Cycle time Cycle time Symbol tCMS tCKS tCMH tCKH tPDE tRRD (min) tRCD (min) (min) tRAS (min) tRSC (min) PC133 8000 1000 1000 PC133 1000 1000 8000 PC100 1000 1000 8000 PC100 1000 1000 8000 Units Note
valid output delay valid output delay Output data hold time Output valid High-Z high pulse width pulse width Command setup time Address setup time Clock enable setup time Data input setup time Command hold time Address hold time Clock enable hold time Data input hold time Power down exit setup time active active delay RAS* CAS* delay precharge time active time cycle time Mode Register Active Delay Latency
Notes Overshoot: (MAX) 2.0V Undershoot: (MIN) 2.0V Typical peak current consumption. Measured with outputs open. Assumes minimum column address update cycle: (min). Parameters depend programmed Latency. Assumed input rise fall time=1ns. time elapse after asserting resume normal operation when exiting power down mode. Timings listed discrete SDRAM components.
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Command Input Timing tCMS tCMS tCMS tCMS A0-A11 BS0,1 tCKS tCKH tCKS tCKS tCKH tCMH tCMS
Read Timing Read Latency
A0-A1 BS0,1
VALID DATA
VALID DATA
Read Command
Burst Length
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Control Timing Input Data (Word Mask) tCMH DQ0~7
VALID DATA
tCMS
VALID DATA
VALID DATA
VALID DATA
(Clock Mask) tCKH DQ0~7
VALID DATA
tCKS
VALID DATA
VALID DATA
VALID DATA
Control Timing Output Data (Output Enable) tCMH DQ0~7 (Clock Mask) tCKH DQ0~7
VALID DATA VALID DATA
tCMS tCMH
tCMS
VALID DATA
VALID DATA
VALID DATA
tCKS
VALID DATA
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM
Mode Register Cycle
Next Command
Register Data
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.
SDRAM SODIMM OUTLINE DRAWING
SIDE VIEW .055" .055"
.150"
FRONT VIEW
BACK VIEW
8Mx64 SODIMM DS851- 6480Y 3/21/01
Technologies Reserves right change products specifications without notice ©2001 Technologies, Inc.

6480YsSWM4G05TWE 8Mx64 SDRAM SODIMM Unbuffered, Refresh, 3.3V with Gen

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