Development Software Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog

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Development Software Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog

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2.5-Gbps Programmable Serial InterfaceHigh-speed (HS) Programmable Serial Interface(PSITM) 2.48- 2.5-Gbps serial signaling rate Full Bellcore jitter compliance Flexible parallel-to-serial conversion transmit path Flexible serial-to-parallel conversion receive path Multiple selectable loopback/loop-through modes 100K usable gates CPLD logic 240K integrated memory 192K synchronous asynchronous SRAM true Dual-Port FIFO Internal transmit receive phase-locked loops (PLLs) Logic dedicated Spread Aware Transmit FIFO flexible variable phase clocking Differential serial input with internal termination DC-restoration Differential serial output with source-matched impedance user-programmable I/Os VoltI/O interface Programmable 1.5V, 1.8V, 2.5V, 3.3V Multiple standards LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), GTL+ Fully PCI-compliant (Rev. 2.2) Direct interface standard fiber-optic modules Designed drive: Fiberoptic modules Copper cables Circuit board traces Backplane links Box-to-box links Chip-to-chip communication Extremely flexible clocking options Four global clocks additional product term clocks Clock polarity every register Carry chain logic fast efficient arithmetic operations JTAG programming interface with boundary scan support Power-saving mode Supported standards: SONET OC-48 STM-16 InfiniBand- Custom 2.5-Gbps interface
Development Software
Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog context sensitive editing Active-HDL graphical finite state machine editor Active-HDL post-synthesis timing simulator Architecture Explorer detailed design analysis Static Timing Analyzer critical path analysis Available Windows® 2000, 4.0, Supports Cypress programmable logic products
2.5-Gbps Family-Standards Supported
Device SONET/SDH High Speed CYS25G01K100 CYP25G01K100 SONET/SDH (OC48/STM16) InfiniBand Custom
2.5-Gbps Family-General Device Typical Gates Macrocells 1536 Cluster Memory (Kbits) Channel Memory (Kbits) Maximum UserProgrammable Package Offering 456-BGA 1.27-mm pitch)
25G01K100 46K-144K
2.5-Gbps Family-Performance
Device 25G01K100 Channels Link Speed Gbps Total Bandwidth Gbps fMAX2(Logic)[1] (MHz) Logic Speed- Pin-to-Pin[1] (ns)
Note: section titled Switching Characteristics definition.
Cypress Semiconductor Corporation Document 38-02021 Rev.
3901 North First Street
Jose, 95134 408-943-2600 Revised December 2002
2.5-Gbps Programmable Serial Interface
GCLK[1:0] RXCLK TXCLK
Clock
GCTL[3:0]
GCLK[1:0], RXCLK, TXCLK
Bank
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0], RXCLK, TXCLK
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
GCLK[1:0], RXCLK, TXCLK
Bank
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Cluster
Cluster
Channel
Phase Align Buffer
Deserializer
Serializer
Serial Signal Bank
Figure High-speed PSIBlock Diagram (25G01K100) with Bank Structure
Document 38-02021 Rev.
Page
XCVR CNTRL
Bank
Bank
2.5-Gbps Programmable Serial Interface
Functional Description
2.5-Gbps point-to-point point-to-multipoint programmable communications building block allowing manipulation transfer data over high-speed serial links Gbps serial link. 2.5-Gbps designed combine high speed, predictable timing, high density, power, ease complex programmable logic devices (CPLD) with serializing/deserializing (SERDES) capability high-speed serial transceivers. architecture device based logic block clusters (LBC) serial transceiver blocks that connected horizontal vertical routing channels. Each features eight individual logic blocks (LB) macrocells cluster memory blocks. Adjacent each channel memory block which externally accessible through interface. Each transmit channel transceiver accepts parallel characters, converts serial data. Each receive channel accepts serial data converts 16-bit parallel data, presents these characters routing channels Programmable Logic. High-speed Transceiver transceiver operation high-speed programmable serial interface devices self-contained single block. separate Transmit (TXPLL) Receive Clock Data Recovery PLL) phase align buffer flexible clocking. transmit channel accepts 16-bit input character from routing channels passes character phase align buffer. This character then serialized output differential output drivers Gbps. receive channel accepts serial bit-stream from differential receiver. This bit-stream deserialized 16-bit character presented routing channels device. block also features loop-back loop-through modes simplified design debugging. transceiver block interfaces routing channels device through highly configurable datapath cells. specific architecture operation transceiver blocks please refer Serial Transceiver Operation section (page 14). internal interfacing transceiver blocks high-speed device occur through port definition high-speed transceiver block. internal signals their definition described "Pin Signal Description" section (page 38). These internal signals routed programmable logic instantiation port mapping them through hardware description using Warp Software.
REFCLK±
System
Programmable Host Interface
Optical Transceiver
Optical Fiber Links
Serial Data OUT- Serial OUT+ Data
Figure High-speed System Connections with Optical Interface Standard Datapath Cell Figure block diagram datapath cell. datapath cell contains three-state transmit buffer, receive buffer, register that configured transmit receive register. Transceiver Enable (TE) selected from four global control signals(GCTL[0:3]) from Output Control Channel (OCC) signals. transmit enable configured always enabled always disabled controlled remaining inputs mux. selection done that includes inputs. global clocks(GCLK[1:0], TXCLK RXCLK) selected clock datapath cell register. clock output input clock polarity that allows transmit/receive register clocked either edge clock. Global Routing Description routing architecture block device made horizontal vertical (H&V) routing channels. These routing channels allow signals move among I/Os, logic blocks memories. addition horizontal vertical routing channels that interconnect banks, channel memory blocks, transceiver blocks logic block clusters, each contains Programmable Interconnect Matrix(PIMTM), which used route signals among logic blocks cluster memory blocks LBC. Figure block diagram routing channels that interface within architecture.
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2.5-Gbps Programmable Serial Interface
Registered
From Output
Receive
Routing Channel
Output Control Channel
Global Control Signals
Global Clock Signals
Register Receive
Transmit
Register Enable Clock Polarity
Signal
Clock
Register Reset
Figure Block Diagram Standard Datapath Cell Logic Block Cluster (LBC) architecture consists several logic block clusters, each which have eight Logic Blocks (LBs) cluster memory blocks connected PIM, shown Figure Each cluster memory block consists 8-Kbit single-port RAM, which configurable synchronous asynchronous. cluster memory blocks cascaded with other cluster memory blocks within same well other LBCs implement larger memory functions. cluster memory block specifically utilized designer, Cypress's Warp software automatically implement large blocks logic. LBCs interface with each other horizontal vertical routing channels.
Block
Cluster Memory Block
Cluster
Cluster Memory Block
Channel Memory Block
Channel memory outputs drive dedicated tracks horizontal vertical routing channels
Block
H-to-V V-to-H
inputs from cells drive dedicated tracks horizontal vertical routing channels
Figure Routing Interface
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2.5-Gbps Programmable Serial Interface
Clock Inputs [1:0],
Logic lock
Logic lock
Logic lock
Logic lock
Logic lock
Logic lock
Logic lock
Logic lock
luster
luster
arry hain
Inputs From orizontal outing hannel
Inputs From Vertical outing hannel
utputs orizontal ertical cluster-to-channel
Figure Logic Block Cluster Diagram Logic Block basic building block programmable logic block architecture. consists product term array, intelligent product-term allocator, macrocells. Product Term Array Each features programmable product term array. This array accepts inputs from PIM. These inputs originate from device pins macrocell feedbacks well cluster memory channel memory feedbacks. Active active HIGH versions each these inputs generated create full 72-input field. product terms array created from inputs. product terms, general-purpose macrocells remaining three product terms used asynchronous asynchronous reset product terms. final product term Product Term clock (PTCLK) shared macrocells within Product Term Allocator Through product term allocator, Warp software automatically distributes product terms needed among macrocells product term allocator provides important capabilities without affecting performance: product term steering product term sharing. Product Term Steering Product term steering process assigning product terms macrocells needed. example, macrocell requires product terms while another needs just three, product term allocator will "steer" product terms macrocell three other. devices, product terms steered individual basis. number between 1and product terms steered macrocell. Product Term Sharing Product term sharing process using same product term among multiple macrocells. example, more than function more product terms equation that common other functions, those product terms only created once. product term allocator allows sharing across groups four macrocells variable fashion. software automatically takes advantage this capability that user does have intervene. Note that neither product term sharing product term steering have effect speed product. steering sharing configurations have been incorporated timing specifications devices.
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2.5-Gbps Programmable Serial Interface
Macrocell Within each there macrocells. Each macrocell accepts product terms from product term array. these product terms output either registered combinatorial mode. Figure displays block diagram macrocell. register asynchronously preset asynchronously reset macrocell level with separate preset reset product terms. Each these product terms features programmable polarity. This allows registers preset reset based expression expression. gate macrocell allows many different types equations realized. used polarity implement true complement form equation product term array toggle turn flip-flop into flip-flop. carry-chain input allows additional flexibility implementation different types logic. macrocell utilize carry chain logic implement adders, subtractors, magnitude comparators, parity tree, even generic logic. output macrocell either registered combinatorial. Carry Chain Logic macrocell features carry chain logic which used fast efficient implementation arithmetic operations. carry logic connects macrocells four total macrocells. Effective data path operations implemented
(fro
through carry-in arithmetic, which drives through circuit quickly. Figure shows that carry chain logic within macrocell consists product terms (CPT0 CPT1) from input carry-in carry logic. inputs carry chain connected directly product terms PTA. output carry chain generates carry-out next macrocell well local carry input that connected input input mux. Carry-in configuration inputs gate. This gate provides method segmenting carry chain macrocell Macrocell Clocks Clocking register highly flexible. Four global synchronous clocks (GCLK[1:0], RXCLK TXCLK) Product Term clock (PTCLK) available each macrocell register. Furthermore, clock polarity within each macrocell allows register clocked rising falling edge (see macrocell diagram Figure PRESET/RESET Configurations macrocell register asynchronously preset reset using PRESET RESET mux. Both signals active high controlled either Preset/Reset product terms (PRC[1:0] Figure GND. situations where PRESET RESET active same time, RESET takes priority over PRESET.
PRESET
CPT0 CPT1
PSET
TXCLK TCLK rity
PRC[1:0]
RESET
Figure Macrocell
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Embedded Memory 2.5-Gbps family contains types embedded memory blocks. channel memory block placed intersection horizontal vertical routing channels. Each channel memory block 4096 bits size configured asynchronous synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), synchronous FIFO memory. memory organization configurable second type memory block located within each referred cluster memory block. Each contains cluster memory blocks that 8192 bits size. Similar channel memory blocks, cluster memory blocks configured configured either asynchronous synchronous Single-Port ROM. Cluster Memory Each cluster device contains 8192-bit cluster memory blocks. Figure block diagram cluster memory block interface cluster memory block cluster PIM. output cluster memory block optionally registered perform synchronous pipelining register asynchronous read write operations. output registers contain asynchronous RESET which used type sequential logic circuits (e.g., state machines). There four global clocks local clock available input output registers. local clock input registers independent used output registers. local clock generated user-design macrocell comes from pin. Cluster Memory Initialization cluster memory powers undefined state, user-defined known state during configuration. facilitate look-up-table (LUT) logic applications, cluster memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory architecture includes embedded memory block each crossing point horizontal vertical routing channels. channel memory 4096-bit embedded memory block that configured asynchronous synchronous Single-Port RAM, Dual-Port RAM, ROM, synchronous FIFO memory. Data, address, control inputs channel memory driven from horizontal vertical routing channels. data FIFO logic outputs drive dedicated tracks horizontal vertical routing channels. clocks channel memory block selected from four global clocks inputs from horizontal vertical channels. clock muxes also include polarity each clock that user choose inverted clock. Dual-Port (Channel Memory) Configuration Each port distinct address inputs, well separate data control inputs that accessed simultaneously. inputs Dual-Port memory driven from horizontal vertical routing channels. data outputs drive dedicated tracks routing channels. interface routing such that Port Dual-Port interfaces primarily with horizontal routing channel Port interfaces primarily with vertical routing channel.
rite
Decode (1024 Rows)
Write Pulse
Local
1024x8 SRAM
RESET XCLK Local
Figure Block Diagram Cluster Memory Block
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clocks each port Dual-Port configuration selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs dualport memory also registered. Clocks output registers also selected from four global clocks local clocks. clock polarity port allows true complement polarity input output clocking purposes. Arbitration Dual-Port configuration Channel Memory Block provides arbitration when both ports access same address same time. Depending memory operation being attempted, port always gets priority. Table details which port gets priority read write operations. active-LOW `Address Match' signal generated when address collision occurs. Table Arbitration Result: Address Match Signal Becomes Active Port Port Result Arbitration Comment Both ports read same time Port requests first then will read current data. output will then change newly written data Port Port requests first then will read current data. output will then change newly written data Port Port blocked until Port finished writing port FIFO also registered. clock polarity port allows using true complement polarity read write operations. write operation controlled clock write enable pin. read operation controlled clock read enable pin. enable pins sourced from horizontal vertical channels. Channel Memory Initialization channel memory powers undefined state, user-defined known state during configuration. facilitate logic applications, channel memory blocks initialized with given data when device configured power applications, user cannot write memory blocks. Channel Memory Routing Interface Similar outputs, channel memory blocks feature dedicated tracks horizontal vertical routing channels data outputs flag outputs, shown Figure This allows channel memory blocks expanded easily. These dedicated lines routed pins chip outputs other clusters used logic equations.
channel memory inputs driven from routing channels
Read Read arbitration required Write Read Port gets priority
4096-bit Dual Port Array
Configurable Async/Sync Dual Port Sync FIFO Configurable 4Kx1, 2Kx2, 1Kx4 512x8 block sizes
Global Clock Signals
Read Write Port gets priority
GCLK[3:0]
Vertical Channel
Write Write Port gets priority
channel memory outputs drive dedicated tracks routing channels
Horizontal Channel
FIFO (Channel Memory) Configuration channel memory blocks also configurable synchronous FIFO RAM. FIFO mode operation, channel memory block supports normal FIFO operations without general-purpose logic resources device. FIFO block contains necessary FIFO flag logic, including read write address pointers. FIFO flags include empty/full flag (EF), half-full flag (HF), programmable almost-empty/full (PAEF) flag output. FIFO configuration ability perform simultaneous read write operations using separate clocks. These clocks tied together single operation independently asynchronous read/write (with reference each other) applications. data control inputs FIFO block driven from horizontal vertical routing channels. data flag outputs driven onto dedicated routing tracks both horizontal vertical routing channels. This allows FIFO blocks expanded using multiple FIFO blocks same horizontal vertical routing channel without speed penalty. FIFO mode, write read ports controlled separate clock enable signals. clocks each port selected from four global clocks local clocks. local clock sourced from horizontal channel other from vertical channel. data outputs from read Document 38-02021 Rev. Figure Block Diagram Channel Memory Block Banks interfaces horizontal vertical routing channels pins through banks. There several banks device shown Figure I/Os from bank located same section package layout convenience. There exist kinds banks; fixed-signal banks user programmable banks. first fixed signal bank Serial Signal Bank. This bank includes differential serial data transmission receive signals. second bank Transceiver Control Bank. This bank includes static signal pins required configuration operation transceiver blocks each devices. Each device several types user programmable banks. table next column (PSI programmable Banks) indicates availability each type programmable bank. Supported standards each bank addressed appropriate VREF VCCIO voltages. VREF VCCIO pins bank must connected same VREF VCCIO voltage respectively. This requirement restricts number standards supported bank given
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2.5-Gbps Programmable Serial Interface
time. also dictates standard used GCTL[3:0] pins. architecture defining each programmable bank consists several cells, where each cell contains input/output register, output enable register, programmable slew rate control programmable hold control logic. Each cell drives output device; cell also supplies input device that connects dedicated track associated routing channel. There four dedicated inputs (GCTL[3:0]) that used Global Control Signals available every cell. These global control signals used output enables, register resets register clock enables shown Figure Each global control originates from particular bank though they used control cell device. input signalling standard particular global control signal same standard bank from which originates. Table Standards Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL 1.15 1.15 0.68 0.68 0.68 0.68 1.35 1.35 VREF 1.25 1.25 0.75 0.75 VCCIO Termination Voltage (VTT)
Bank Bank Bank Bank Bank
Serial Bank
XCVR CNTL
Banks Global Controls GCTL[0] Bank GCTL[1] GCTL[2] GCTL[3]
Bank Bank Bank
Figure Bank Block Diagram Programmable Banks Device Flexible SemiFlexible Specific VCCIO VREF
Banks Global CLKs GCLK[0] Bank GCLK[1]
25G01K100 Bank[0:3,
Bank[4] Bank[6:7] VCCIO=3.3V 1.5V 0.68-0.90V
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2.5-Gbps Programmable Serial Interface
Registered
From Output
Input
Routing Channel
Output Control Channel
Global Control Signals
Global Clock Signals
Register Input
Output
Register Enable Clock Polarity
Hold
Clock
Slew Rate Control
Register Reset
Figure Block Diagram Cell Cell Figure block diagram cell. cell contains three-state input buffer, output buffer, register that configured input output register. output buffer slew rate control option that used configure output slower slew rate. input device output each configured registered combinatorial, however only path configured registered given design. output enable selected from four global control signals from signals. output enable configured always enabled always disabled controlled remaining inputs mux. selection done that includes inputs. global clocks selected clock cell register. clock output input clock polarity that allows input/output register clocked either edge clock. Slew Rate Control output buffer slew rate control option. This allows ouput buffer slew fast rate V/ns) slow rate V/ns). I/Os default fast slew rate. designs concerned with meeting emissions standards slow edge provides lower system noise. designs requiring very high performance fast edge rate provides maximum system performance. Programmable Hold each pin, user-programmable bus-hold included. Bus-hold, which improved version popular internal Device 25G01K100 pull-up resistor, weak latch connected that does degrade device's performance. latch, bus-hold maintains last state when placed high-impedance state, thus reducing system noise businterface applications. Bus-hold additionally allows unused device pins remain unconnected board, which particularly useful during prototyping designers route signals device without cutting trace connections GND. more information, application note "Understanding Bus-Hold Feature Cypress CPLDs." Clocks four primary internal global clock trees CPLD portion device (INTCLK[3:0]). Each these clock trees distributes clock signal every cluster, channel memory, cell CPLD. global clock trees designed such that clock skew minimized while maintaining acceptable clock delay. Each internal global clocks choose from input sources clock signal: derived output another shown table below. ININTCLK[0] TCLK[1] GCLK[0] GCLK[1] INTCLK[2] TXCLK INTCLK[3] RXCLK
GCLK[0] GCLK[1] accessible through pins device package. TXCLK RXCLK provided internally device. TXCLK (transmit clock) intended data transfer from CPLD block transmit channel transceiver block. RXCLK (receive clock) intended data transfer from receive channel transceiver block CPLD block. TXCLK RXCLK also used logic inside CPLD block, e.g., data processing.
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Clock Tree Distribution global clock tree performs primary functions. First, clock tree generates four internal global clocks multiplexing four reference clocks derived from Transceiver Blocks from package pins four driven clocks. Second, clock tree distributes four global clocks every cluster, channel memory, block, datapath cell die. global clock tree designed such that clock skew minimized while maintaining acceptable clock delay. Spread AwarePLL 2.5-Gbps device features on-chip designed using Spread Awaretechnology applications. general, PLLs used implement time-division-multiplex circuits achieve higher performance with fewer device resources. example, system that operates 32-bit data path that runs implemented with 16-bit circuitry that runs internally MHz. PLLs also used take advantage positioning internally generated clock edges shift performance towards improved setup, hold clock-to-out times. There several frequency multiply (X1, X16) divide (/1, /16) options available create wide range clock frequencies from single clock input (GCLK[0]). increased flexibility, there seven phase shifting options which allow clock skew/de-skew 45°, 90°, 135°, 180°, 225°, 270°, 315°. Spread Aware feature refers ability track spread-spectrum input clock such that spread seen output clock with staying locked. total
amount spread input clock should limited 0.6% fundamental frequency. Spread Aware feature supported only with multiply options. Voltage Controlled Oscillator (VCO), core designed operate within frequency range MHz. Hence, multiply option combined with input (GCLK[0]) frequency should selected such that this operating frequency requirement met. This demonstrated Table (columns Another feature this ability drive output clock (INTCLK) chip clock other devices board, shown Figure below. This off-chip clock half frequency output clock through register (I/O register macrocell register). This also used board deskewing purpose driving output clock off-chip, routing other devices board feeding back PLL's external feedback input (GCLK[1]). When this feature used, only limited multiply, divide phase shift options used. Table describes valid multiply divide options that used without external feedback. Table describes valid multiply divide options that used with external feedback. Table describes valid phase shift options that used with without external feedback. Table example effect available divide phase shift options output MHz. also shows effect division duty cycle resultant clock. Note that duty cycle 50-50 when output divided even number. Also note that phase shift applies output divided output.
CLK1
Lock
CLK1
CLK0
TXCLK
RXCLK
GCLK[1:0]
Figure Block Diagram Spread Aware CYP25G01K100
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Table Multiply Divide Options-without INTCLK1 Feedback Input Frequency (GCLK[0]) fPLLI (MHz) DC-12.5 100-133 50-133 33.3-88.7 25-66 20-53.2 16.6-44.3 12.5-33 12.5-16.625 Valid Multiply Options Value Output Frequency (MHz) 100-133 100-266 100-266 100-266 100-266 100-266 100-266 200-266 Value 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) DC-12.5 6.25-133 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 Off-chip Clock Frequency DC-6.25 3.125-66 3.125-133 3.1-266 3.125-133 3.1-133 3.1-133 3.125-133 3.125-133
Table Multiply Divide Options-with External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63 Value Output Frequency (MHz) 100-266 100-266 100-266 100-266 125-266 150-266 200-266 Value Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-266 50-133 33.33-88.66 25-66.5 25-53.2 25-44.34 25-33.25 Off-chip Clock Frequency 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63
Table Phase Shift Options with without INTCLK1 Feedback Without External Feedback 0°,45°, 90°, 135°, 180°, 225°, 270°, 315° Table Timing Clock Phases Divide Options Output Frequency Divide Factor Timing Model important feature 2.5-Gbps simplicity timing. combinatorial registered/synchronous delays worst case system performance static shown specs section) long data routed through same horizontal vertical channels. Figure illustrates true timing model programmable device. synchronous clocking macrocells, delay incurred from macrocell clock macrocell clock separate Period (ns) Duty Cycle% 40-60 33-67 40-60 (ns) (ns) (ns) 135° (ns) 180° (ns) 225° (ns) 270° (ns) 315° (ns) With External Feedback
within same cluster, well separate within different clusters. This shown tSCS tSCS2 Figure combinatorial paths, input output (from corner corner device), incurs worst-case delay 100K gate regardless amount logic which horizontal vertical channels used. This shown Figure synchronous systems, input set-up time output macrocell register clock output time shown parameters tMCS tMCCO shown
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Figure These measurements output synchronous clock, regardless logic placement. features: dedicated delays penalty using 0-16 product terms added delay steering product terms added delay sharing product terms output bypass delays. simple timing model 2.5-Gbps eliminates unexpected performance penalties.
tSCS
GCLK[1:0], RXCLK, TXCLK
Channel
Channel
Channel
Channel
Cluster
Cluster
SRAM
tMCS
Cluster
Cluster
Cluster
Cluster
SRAM
GCLK[1:0], RXCLK, TXCLK
tSCS2
Channel
Channel
Channel
Channel
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
GCLK[1:0], TXCLK, RXCLK
Channel
Channel
Channel
Channel
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
Cluster
tMCCO
Figure Timing Model 100K gate Devices
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Serial Transceiver Operation
transceiver block highly configurable transceiver designed support reliable transfer large quantities data, using high-speed serial links, from multiple sources multiple destinations. This block supports serialization 16-bit dataword transmit side, clock recovery deserialization receive side. interconnection between serial transceiver block embedded programmable logic specified using hardware description Warp Software. bit-rate clock generated Transmit clock multiplier. TXD[15] most significant output word, transmitted first serial interface. Serial Output Driver serial interface Output Driver makes high-performance differential (Current Mode Logic) provide source-matched driver transmission lines. This driver receives data from Transmit Shifters receive loopback data. outputs have signal swings equivalent that standard LVPECL drivers, capable driving AC-coupled optical modules transmission lines. Receive Data Path Serial Line Receivers differential line receiver, IN±, available accepting input serial data stream. serial line receiver inputs accommodate high wire interconnect filtering losses transmission line attenuation (VSE peak-topeak differential), AC-coupled +3.3V powered fiber-optic interface modules. common-mode tolerance these line receivers accommodates wide range signal termination voltages. Lock Data Control Line Receiver routed clock data recovery monitored status signal detect (SD) status LOCKREF received data stream outside normal frequency range (±100 ppm). This status presented (Line Fault Indicator) output signal, which changes asynchronously cases when LOCKREF goes from HIGH LOW. Otherwise, changes synchronously REFCLK. Clock/Data Recovery extraction bit-rate clock recovery data bits from received serial stream performed Clock/Data Recovery (CDR) block. clock extraction function performed high-performance embedded that tracks frequency incoming stream aligns phase internal bitrate clock transitions selected serial data stream. accepts character-rate (bit-rate reference clock REFCLK input. This REFCLK input used ensure that (within CDR) operating correct frequency (rather than some harmonic bit-rate), improve acquisition time, limit unlocked frequency excursions when data present serial inputs. Regardless type signal present, will attempt recover data stream from frequency recovered data stream outside limits range controls, will track REFCLK instead data stream. When frequency selected data stream returns valid frequency, allowed track received data stream. frequency REFCLK required within ±100 frequency clock that drives REFCLK signal remote transmitter ensure lock incoming data stream.
High-speed Transceiver Operation
Registering TXD[15:0] Data Before enters Serial Transceiver Block Before 16-bit parallel input data TXD[15:0] enters serial transceiver block, required register this data standard data path cell without output enables. also required that these datapath cells clocked rising edge global TXCLK. Transmit Data Path registered 16-bit parallel input data from programmable device input into input register serial transceiver block. This input register clocked using TXCLK, which four global clocks programmable logic. Phase-Align Buffer Data from input register passed phase-align buffer (FIFO). This buffer used absorb clock phase differences between transmit input clock entering serial transceiver internal character clock. Initialization phase-align buffer takes place when FIFO_RST signal asserted LOW. When FIFO_RST returned HIGH, present input clock phase relative TXCLK set. Once set, input clock allowed skew time half character period either direction relative REFCLK (i.e., ±180). This time shift allows delay path character clock (relative REFCLK) change operating voltage temperature while effecting desired operation. FIFO_RST asynchronous signal. FIFO_ERR transmit FIFO Error indicator. When HIGH, transmit FIFO either under overflowed. FIFO externally reset logically reset logic clear error indication action taken, internal clearing mechanism will clear FIFO nine clock cycles. When FIFO being reset, output data 1010. Transmit Clock Multiplier Transmit Clock Multiplier accepts external clock REFCLK input, multiplies that clock generate bit-rate clock (2.5 Gbps) transmit shifter. operating serial signaling rate allowable range REFCLK frequencies listed High-speed Transceiver Timing Parameter Values table under "REFCLK Timing Parameters" (see page 24). REFCLK± input standard LVPECL input. Serializer parallel data from phase-align buffer passed Serializer which converts parallel data serial data using
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External Filter circuit uses external capacitors filter. 0.1-µF capacitor needs connected between RXCN1 RXCP1. Similarly 0.1-µF capacitor needs connected between RXCN2 RXCP2. recommended packages dielectric material these capacitors 0805 0603 X7R. These capacitors should surface mount packages placed close possible device. Deserializer circuit extracts bits from serial data stream clocks these bits into Deserializer bit-clock rate. Deserializer converts serial data into parallel data. RXD[15] most significant output word received first serial interface. This RXD[15:0] data output registered programmable device. Registering RXD[15:0] Data Before Enters Programmable Before RXD[15:0] enters programmable required register these signals standard datapath cells without output enables. also required clock these standard datapath cells using rising edge global RXCLK. Loopback/Timing Modes High-speed supports various loopback modes described below. Facility Loopback (Line Loopback With Retiming) When LINELOOP signal HIGH, Facility Loopback mode activated high-speed serial receive data (IN±) presented high-speed transmit output (OUT±) after retiming. Facility Loopback mode, high-speed receive data (IN±) also converted parallel data presented low-speed receive data output pins (RXD[15:0]). receive recovered clock also divided down presented speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback With Retiming) When DIAGLOOP signal HIGH, transmit data looped back PLL, replacing IN±. Data looped back from parallel inputs parallel outputs. data looped back internal serial interface goes through transmit shifter receive CDR. ignored this mode. Line Loopback Mode (Non-retimed Data) When LOOPA signal HIGH, serial data directly buffered transmit serial data. data serial output retimed. Loop Timing Mode When LOOPTIME signal HIGH, bypassed receive bit-rate clock used transmit side shifter. Reset Modes serial transceiver logic circuits serial transceiver block reset using RESET FIFO_RST signals. When RESET LOW, logic circuits serial transceiver except FIFO internally reset. When FIFO_RST LOW, FIFO logic reset. Power-down Mode serial transceiver High-speed transceiver block provide power-down signal PWRDN. When LOW, this signal powers down entire serial transceiver block minimal power dissipation state. RESET FIFO_RST signals should asserted along with PWRDN signal ensure low-power dissipation.
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REFCLK+ TXCLK FIFO_RST TXD[0:15] FIFO_ERR TXCLK Input Register FIFO Recovered Bit-Clock Lock-to-Ref LOOPTIME DIAGLOOP Shifter Output Register RXCLK RXD[0:15]
Shifter
LINELOOP LOOPA
Lock-to-Data/ Clock Control Logic
PWRDN LOCKREF OUT+
RESET
Figure High-speed Transceiver Logic Block Diagram[2]
Note: signal names outside dotted have dedicated pins package. Other signals internal must port-mapped programmable logic using hardware description Warp software.
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2.5-Gbps Programmable Serial Interface
IEEE 1149.1-compliant JTAG Operation 2.5-Gbps IEEE standard 1149.1 JTAG interface both Boundary Scan operations. Four dedicated pins reserved each device Test Access Port (TAP). serial transceiver block this device does support JTAG since most blocks serial transceiver block analog. Hence serial transceiver portion part JTAG test chain. Boundary Scan 2.5-Gbps supports Bypass, Sample/Preload, Extest, Intest, Idcode Usercode boundary scan instructions. JTAG interface shown Figure
Instruction Register
There multiple configuration options available issuing IEEE 1149.1 JTAG instructions PSI. first method with programming cable software. With this method, pins devices system routed connector edge printed circuit board. programming cable then connected between this connector. simple configuration file instructs software programming operations performed devices system. software then automatically completes necessary data manipulations required accomplish configuration, reading, verifying, other functions. systems with embedded controllers/processors, controller/processor used configure PSI. software assists this method converting device file into serial stream that contains instruction information addresses data locations configured. controller/processor then simply directs this stream chain devices complete desired reconfiguration diagnostic operations. Contact your local sales office information availability this option. Programming on-chip EEPROM device CPLD block programmed issuing appropriate IEEE 1149.1 JTAG instruction. This done automatically using ISR/STAPL software. configuration bits sent from through JTAG port into programming cable. data then passed internal EEPROM through Non-Volatile (NV) port CPLD block. more information program through ISR/STAPL, please refer ISR/STAPL User Guide. Third-Party Programmers Cypress support available wide variety third-party programmers. major programmers (including Micro, System General, Hi-Lo) support family.
TCLK
JTAG CONTROLLER
Bypass Reg. Boundary Scan idcode Usercode Prog.
Data Registers
Figure JTAG Interface In-System Reprogramming(ISRTM) In-System Reprogramming combination capability program reprogram device on-board, ability support design changes without changing system timing device pinout. This combination means design changes during debug field upgrades cause board respins. 2.5-Gbps implements providing JTAG compliant interface on-board programming, robust routing resources pinout flexibility, simple timing model consistent system performance. Configuration CPLD block 2.5-Gbps designed with SelfBoot capability. embedded on-chip EEPROM used store configuration data. devices, programming defined loading user's design into internal EEPROM. Configuration, other hand, defined loading user's design into volatile CPLD block. Configuration begin ways. initiated toggling Reconfig from HIGH, issuing appropriate IEEE 1149.1 JTAG instruction device JTAG interface. There IEEE 1149.1 JTAG instructions that initiate configuration PSI. Self Config instruction causes (re)configure with data store internal EEPROM. Load Config instruction causes (re)configure with data provided other sources such Automatic Test Equipment (ATE), embedded micro-controller/processor JTAG port.
Development Software Support
Warp Warp state-of-the-art design environment designing with Cypress programmable logic. Warp utilizes subset IEEE 1076/1164 VHDL IEEE 1364 Hardware Description Language (HDL) design entry. Warp accepts VHDL Verilog input, synthesizes optimizes entered design, outputs configuration bitstream desired device. simulation, Warp provides graphical waveform simulator well VHDL Verilog Timing Models. VHDL Verilog open, powerful, non-proprietary Hardware Description Languages (HDLs) that standards behavioral design entry simulation. allows designers learn single language that useful facets design process. Third-party Software Cypress products supported number third-party design entry simulation tools. Refer third-party software data sheet contact your local sales office list currently supported third party vendors.
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature .-65°C +150°C Soldering Temperature. 220°C Ambient Temperature with Power Applied. -40°C +85°C Junction Temperature 135°C relative Ground Potential. -0.5V 4.2V VCCIO relative Ground Potential. -0.5V 4.6V Voltage Applied Outputs High-Z State -0.5V 4.5V Range Commercial Output Current into LVCMOS Outputs (LOW). Input voltage. .-0.5V 4.5V Current into Outputs. mA[3] Static Discharge Voltage. 1100V (per MIL-STD-883, Method 3015) Latch-up Current.
Operating Range
Ambient Temperature +70°C VDDQ
3.3V 1.4V 1.6V
Operating Range
Range Commercial Ambient Temperature +70°C Junction Temperature +85°C Output Condition 3.3V 2.5V 1.8V 1.5V VCCIO 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V 3.3V 0.3V VCCJTAG/ VCCCNFG Same VCCIO VCCPLL Same VCEP 3.3V 0.3V
Test Waveforms High-speed Transceiver Block
3.0V Vth=1.4V 2.0V 0.8V 3.0V 2.0V 0.8V Vth=1.4V VICLL VICHH
LVTTL Input Test Waveform
VIEHH VIELL
Input Test Waveform
LVPECL Input Test Waveform
Test Loads High-speed Transceiver Block
3.3V OUTPUT (Includes fixture probe capacitance) OUT+ OUT-
Test Load
Note: current into outputs with HSTL with HSTL
Test Load
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Electrical Characteristics Over Operating Range
Characteristics VCCIO 3.3V VCCIO 2.5V VCCIO 1.8V Parameter Description VDRINT VDRIO IOS[4] IBHL IBHH IBHLO IBHHO Capacitance Parameter CI/O CPCI CCLK CINPECL CSD1 CINC1 Description Input/Output Capacitance compliant Capacitance Clock Signal Capacitance PECL Input Capacitance Input Capacitance Input Capacitance Test Conditions VCCIO 25°C VCCIO 25°C VCCIO 25°C 3.3V 25°C 3.3V 25°C 3.3V 25°C Min. Max. Unit Data Retention Voltage (config data lost below this) Data Retention VCCIO Voltage (config data lost below this) Input Leakage Current Output Leakage Current Output Short Circuit Current 3.6V VCCIO VCCIO Max., VOUT 0.5V +250 -250 Test Conditions Min. Max. Min. Max. Min. Max. Unit -160 +200 -200 -160 +150 -150
-160
Input Hold Sustaining Current Min., VPIN Input Hold HIGH Sustaining Current Min., VPIN Input Hold Overdrive Current Max. Input Hold HIGH Overdrive Current Max.
Characteristics (I/O) Input/Output Standard LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVCMOS LVCMOS3 LVCMOS2 VREF VCCIO -0.1 -0.1 -0.1 -1.0 -2.0 LVCMOS18 3.3V -0.5 (Min.) VCCIO 0.2V VCCIO 0.2V (Max.) 0.45 0.1VCCIO 0.65VC VCCIO+0.3
Min. Max.
Min. Max. 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.7V
VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V VCCIO -0.3V 2.0V VCCIO -0.3V 2.0V 1.7V VCCIO -0.3V VCCIO -0.3V
VCCIO-0.45V 0.9VCCIO
-0.3V 0.35V
CCIO
0.5VCC VCCIO+0.5
-0.5V 0.3VC
Note: more than output should tested time. Duration short circuit should exceed second. VOUT=0.5V been chosen avoid test problems caused tester ground degradation. Tested initially after design process changes that affect these parameters.
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Characteristics (I/O) Input/Output Standard GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL VREF VCCIO Note VCCIO-1.1V VCCIO-0.9V (Min.) mA[6] (Max.) 0.54 0.35 Min. VREF+ VREF+ VCCIO+0.3 VREF+ VCCIO+0.3 VREF+ VCCIO+0.3 0.18 VREF+ VCCIO+0.3 0.18 VREF+ VCCIO+0.3 VREF+ VCCIO+0.3 VREF+ VCCIO+0.3 VREF+ VCCIO+0.3 Min. -0.3 Max. Min. Max. VREF- -0.3V VREF- -0.3V VREF- -0.3V VREF- 0.18 -0.3V VREF- 0.18 -0.3V VREF- -0.3V VREF- -0.3V VREF- -0.3V VREF- Max. VIEHH Max. VIELL Min. differential load differential load 1200 Unit
1.15 1.35 1.15 1.35 0.68 0.68 0.68 0.68
-7.6 VCCIO-0.62V -15.2 VCCIO-0.43V 15.2 VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V VCCIO-0.4V
Parameter LVTTL Inputs VIHT VILT IIHT IILT VINSGLE VDIFFE VIEHH VIELL IIEH IIEL VOHC VOLC IACCM VACCM ZMSE IDSHORT VDIFFOC VSGLOC
Description Input HIGH Voltage Input Voltage Input HIGH Current Input Current Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input Voltage Input HIGH Current Input Current Output HIGH Voltage (VCC Referenced) Output Voltage (VCC Referenced) Common Mode Current Common Mode Voltage Differential Output Impedance Single Ended Output Impedance Single Ended Output Impedance Matching Within Single Lane Short Circuit Current Output Differential Swing Output Single Ended Swing
Test Conditions 2.0V, High 0.5V -3.0V, High 0.8V Max., Max.,
REFCLK LVPECL-compatible Inputs
1.45 -200 0.15 -100 1600
Transmitter Differential CML-compatible Outputs
differential load differential load
1000
Notes: "Power-up Sequence Requirements" VCCIO requirement. resistor terminated termination voltage 1.5V.
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Parameter VICHH VICLL ZVTT LCMR VRSD VRMAX VDIFFC VINSGLC Description Highest Input HIGH Voltage Lowest Input Voltage Impedance Differential Return Loss Common Mode Return Loss Voltage Threshold Maximum Input Voltage (p-p) Input Differential Voltage Input Single-ended Swing 2000 1000 Test Conditions Min. Max. Unit Receiver Differential Compatible Inputs
Configuration Parameters Parameter tRECONFIG Description Reconfig time before goes HIGH Min. Unit
)-(O
Figure Differential Parameters Waveforms Power-up Sequence Requirements Upon power-up, outputs remain three-stated until pins have powered nominal voltage part completed configuration. part will start configuration until VCC, VDDQ, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCEP have reached nominal voltage. pins powered order. This includes VCC, VDDQ, VCCIO, VCCJTAG, VCCCNFG, VCCPLL VCEP. VCCIOs bank should tied same potential powered together. VCCIOs (even unused banks) need powered least 1.5V before configuration completed. Maximum ramp time VCCs should nominal voltage
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Switching Characteristics
Timing Parameter Values Parameter Combinatorial Mode Parameters tPRR tPRO Delay from input, through cluster channel associated with that input, output horizontal vertical channel associated with that cluster Global control output enable Global control output disable Asynchronous macrocell RESET PRESET recovery time from input horizontal vertical channel associated with cluster macrocell Asynchronous macrocell RESET PRESET from input horizontal vertical channel associated with cluster that macrocell output those same channels Asynchronous macrocell RESET PRESET minimum pulse width, from input macrocell farthest cluster horizontal vertical channel associated with Set-up time input macrocell cluster channel associated with that input pin, relative global clock Hold time input macrocell cluster channel associated with that input pin, relative global clock Global clock output macrocell output horizontal vertical channel associated with cluster that macrocell Set-up time input cell register associated with that pin, relative global clock Hold time input cell register associated with that pin, relative global clock Clock output cell register output associated with that register Macrocell clock macrocell clock through array logic within same cluster Macrocell clock macrocell clock through array logic different clusters same channel register clock macrocell clock cluster channel register associated with Macrocell clock register clock horizontal vertical channel associated with cluster that macrocell Clock output disable (high-impedance) Clock output enable (low-impedance) Maximum frequency with internal feedback-within same cluster Maximum frequency with internal feedback-within different clusters opposite ends horizontal vertical channel Set-up time macrocell used input register, from input product term clock Hold time macrocell used input register Product term clock output delay from input Register register delay through array logic different clusters same channel using product term clock Adder signal switch from horizontal vertical channel vice-versa Cluster Cluster delay adder (through channels channel PIM) Description Min. Max. Unit
tPRW
Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2
Product Term Clocking Parameters tMCSPT tMCHPT tMCCOPT tSCS2PT
Channel Interconnect Parameters tCHSW tCL2CL
Note: tCHSW signals making horizontal vertical channel switch vice versa.
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Switching Characteristics
Timing Parameter Values (continued) Parameter Miscellaneous Parameters tCPLD tMCCD tMCCJ tDWSA tDWOSA tLOCK fPLLO fPLLI Delay from input cluster PIM, through macrocell cluster, back cluster input. This parameter added tSCS parameters each extra pass through AND/OR array required given signal path Adder carry chain logic macrocell Maximum cycle cycle jitter time delay with skew adjustment delay without skew adjustment Lock time Output frequency Input frequency 12.5 -150 -150 Description Min. Max. Unit
0.25
Parameters -1.35 -0.85
Cluster Memory Timing Parameter Values Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD Cluster memory access time. Delay from address change read data Write enable pulse width Address set-up beginning write enable Address hold after write enable with both signals from same block Data set-up write enable Data hold after write enable Clock cycle time flow-through read write operations (from macrocell register through cluster memory back macrocell register same cluster) Clock cycle time pipelined read write operations (from cluster memory input register through memory cluster memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Cluster memory input clock macrocell clock same cluster Cluster memory output clock macrocell clock same cluster Macrocell clock cluster memory input clock same cluster Macrocell clock cluster memory output clock same cluster Asynchronous cluster memory access time from input cluster output cluster Description Min. Max. Unit
Synchronous Mode Parameters tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 tCLMCLAA
Internal Parameters
Channel Memory Timing Parameter Values Parameter Dual-Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA Channel memory access time. Delay from address change read data Write enable pulse width Address set-up beginning write enable Description Min. Max. Unit
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Channel Memory Timing Parameter Values (continued) tCHMHA tCHMSD tCHMHD tCHMBA Address hold after write enable with both signals from same block Data set-up write enable Data hold after write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time flow through read write operations (from macrocell register through channel memory back macrocell register same cluster) Clock cycle time pipelined read write operations (from channel memory input register through memory channel memory output register) Address, data, set-up time inputs, relative global clock Address, data, hold time inputs, relative global clock Global clock data valid output pins flow through data Global clock data valid output pins pipelined data Channel memory synchronous dual-port address match (busy, clock data valid) Channel memory input clock macrocell clock same cluster Channel memory output clock macrocell clock same cluster Macrocell clock channel memory input clock same cluster Macrocell clock channel memory output clock same cluster Read write minimum clock cycle time Data, read enable, write enable set-up time relative inputs Data, read enable, write enable hold time relative inputs Data access time output pins from rising edge read clock (read clock data valid) Channel memory FIFO read clock macrocell clock read data Macrocell clock channel memory FIFO write clock write data Read write clock respective flag output output pins Read write clock macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset Flag Data Output Time Read/Write Clock Skew Time Full Flag Read/Write Clock Skew Time Empty Flag Read/Write Clock Skew Time Boundary Flags Asynchronous channel memory access time from input channel memory output channel memory 10.0
Dual-Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 tCHMCHAA
Synchronous FIFO Data Parameters
Synchronous FIFO Flag Parameters
Internal Parameters
High-speed Transceiver Timing Parameter Values Parameter Transceiver Interfacing Timing Parameters tTXCLK tRXCLK TXCLK Frequency (must frequency coherent REFCLK) TXCLK Period RXCLK Frequency RXCLK Period 154.5 6.38 154.5 6.38 156.5 6.47 156.5 6.47 Description Min. Max. Unit
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High-speed Transceiver Timing Parameter Values Parameter REFCLK Timing Parameters tREF tREFP tREFD tREFT tREFR tREFF tREFJ Serial Outputs tDRF tUID[9] Serial Outputs tRISE tFALL Output Rise Time (20-80%, balanced load) Output Fall Time (80-20%, balanced load) Driver Rise/Fall Time (20-80% rise, 80-20% fall, balanced load) Unit Interval REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance (relative received serial data) REFCLK Rise Time REFCLK Fall Time REFCLK Jitter
Description
Min. 154.5 6.38 -100
Max. 156.5 6.47 +100
Unit
Figure phase noise requirements
Jitter Specifications CYP25G01K100 (Non-SONET)
tEYE tJDR tJTR opening serial inputs Deterministic Jitter allowed serial inputs Total Jitter allowed serial inputs Deterministic Jitter serial outputs Total Jitter serial outputs 0.41 0.65 0.17 0.35
Jitter Specifications CYS25G01K100 (SONET)
Parameter tTJ-TXPLL tTJ-RXPLL Description Total Output Jitter (p-p)[10]
[10]
Min.
Typical[11] 0.03 0.007 0.035 0.008
Max.[11] 0.04 0.008 0.05 0.01
Unit
Total Output Jitter (rms)[10] Total Output Jitter (p-p) Total Output Jitter (rms)[10]
Note: required meet SONET output frequency specification. Measured with serial rate Gbps. P-to-P jitter values measured using SONET filter. Typical room temperature, Max.
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Phase Noise Limits CYS25G01K100(SONET) REFCLK Source
CYS25G0101DX Reference Clock Phase Noise Limits
Phase Noise (dBc)
-105
-115
-125
-135
-145
-155 1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Frequency (Hz)
Figure Phase Noise Limits REFCLK Inputs CYS25G01K100 Jitter Transfer CYS25G01K100 (SONET) RXPLL
Figure Jitter Transfer CYS25G01K100 Jitter Tolerance CYS25G01K100 (SONET)
Figure Jitter Tolerance CYS25G01K100
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Input Output Standard Timing Delay Adjustments
timing specifications this data sheet specified based 3.3V compliant inputs outputs (fast slew Input/Output Standard LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V GTL+ SSTL3 SSTL3 SSTL2 SSTL2 HSTL HSTL HSTL HSTL Output Delay Adjustments (ns) tIOD 2.75 0.16 0.14 0.41 -0.14 0.02
[13]
rates[12]). Apply following adjustments inputs outputs configured operate other standards.
Input Delay Adjustments(ns) tIOIN tCKIN tIOREGPIN
0.05 0.6[13]
0.9[13]
-0.15 -0.4 -0.02 -0.22 0.94 0.79 0.77 0.44
Notes: "slow slew rate" output delay adjustments, refer Warp software's static timing analyzer results. These delays based falling edge output. rising edge delay depends size pull resistor termination voltage.
Switching Waveforms General Switching Waveforms
Combinatorial Output
INPUT COMBINATORIAL OUTPUT
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Switching Waveforms (continued)
Registered Output with Synchronous Clocking (Macrocell)
INPUT tMCS SYNCHRONOUS CLOCK tMCH
REGISTERED OUTPUT tMCCO
Registered Input Cell
DATA INPUT tIOS tIOH
INPUT REGISTER CLOCK
tIOCO
REGISTERED OUTPUT
Clock Clock
INPUT REGISTER CLOCK tICS tSCS
MACROCELL REGISTER CLOCK
Clock Clock
DATA INPUT tMCSPT CLOCK tSCS2PT
Asynchronous Reset/Preset
RESET/PRESET INPUT tPRO REGISTERED OUTPUT
tPRW
tPRR CLOCK
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Switching Waveforms (continued)
Output Enable/Disable
GLOBAL CONTROL INPUT OUTPUTS
Cluster Memory Asynchronous Timing
READ WRITE READ
ADDRESS CLUSTER INPUT)
WRITE ENABLE
tCLMPWE
INPUT
tCLMCLAA
tCLMCLAA
OUTPUT
Cluster Memory Asynchronous Timing
READ ADDRESS PIN)
tCLMSA tCLMHA
WRITE
READ
WRITE ENABLE
tCLMPWE
INPUT
tCLMSD tCLMAA tCLMHD tCLMAA
OUTPUT
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Switching Waveforms (continued)
Cluster Memory Synchronous Timing
READ WRITE READ
GLOBAL CLOCK
tCLMS tCLMH tCLMCYC1
ADDRESS
tCLMS tCLMH tCLMS tCLMH
WRITE ENABLE
REGISTERED INPUT
tCLMDV1 tCLMDV1 tCLMDV1
REGISTERED OUTPUT
Cluster Memory Internal Clocking
MACROCELL INPUT CLOCK
tCLMMACS1 tMACCLMS1
CLUSTER MEMORY INPUT CLOCK
tCLMMACS2 tMACCLMS2
CLUSTER MEMORY OUTPUT CLOCK
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Switching Waveforms (continued)
Cluster Memory Output Register Timing (Asynchronous Inputs)
ADDRESS
WRITE ENABLE
INPUT tCLMCYC2
GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2
EGISTERED OUTPUT
Cluster Memory Output Register Timing (Synchronous Inputs)
ADDRESS
WRITE ENABLE
INPUT tCLMCYC2 GLOBAL CLOCK (INPUT REGISTER) tCLMS tCLMH
GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2
REGISTERED OUTPUT
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Switching Waveforms (continued)
Channel Memory Asynchronous Timing
ADDRESS
An-1
An+1
An+2
tCHMSA
tCHMPWE
tCHMHA
WRITE ENABLE
tCHMSD
tCHMHD
DATA INPUT
tCHMAA
tCHMAA
OUTPUT
Dn-1
Dn+1
Channel Memory Internal Clocking
MACROCELL INPUT CLOCK tMACCHMS1
tCHMMACS1 CHANNEL MEMORY INPUT CLOCK
tCHMMACS2
tMACCHMS2
CHANNEL MEMORY OUTPUT CLOCK
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Switching Waveforms (continued)
Channel Memory Internal Clocking
MACROCELL INPUT CLOCK tCHMMACS FIFO READ CLOCK
tMACCHMS FIFO WRITE CLOCK tCHMMACF FIFO READ WRITE CLOCK
Channel Memory SRAM Flow Through Timing
CLOCK tCHMCYC1 tCHMS tCHMH
ADDRESS
An-1
An+1
An+2
An+3
WRITE ENABLE
tCHMS
tCHMH
DATA INPUT
Dn-1
Dn+1
Dn+3
tCHMDV1
tCHMDV1
tCHMDV1
tCHMDV1
OUTPUT
Dn-1
Dn+1
Dn+2
Dn+3
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Switching Waveforms (continued)
Channel Memory SRAM Pipeline Timing
CLOCK tCHMCYC2 tCHMS
tCHMH
ADDRESS
An-1
tCHMH
An+1
An+2
An+3
tCHMS WRITE ENABLE
tCHMS
tCHMH
DATA INPUT
Dn-1
Dn+1
Dn+3
tCHMDV2
tCHMDV2
tCHMDV2
OUTPUT
Dn-1
Dn+1
Dn+2
Dual-Port Asynchronous Address Match Busy Signal
ADDRESS
ADDRESS
An-1
An+1
tCHMBA tCHMBA ADDRESS MATCH
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Switching Waveforms (continued)
Dual-Port Synchronous Address Match Busy Signal
CLOCK
ADDRESS
An-1
ADDRESS
Bn-1 tCHMS
tCHMS
Bn+1
ADDRESS MATCH
tCHMBDV tCHMBDV
Channel Memory Synchronous FIFO Empty/Write Timing
PORT CLOCK tCHMCLK tCHMFS tCHMFH
WRITE ENABLE
REGISTERED INPUT
Dn+1
EMPTY FLAG (active low)
tCHMSKEW2
tCHMFO
tCHMFO
PORT CLOCK
READ ENABLE
tCHMFRDV
REGISTERED OUTPUT
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Switching Waveforms (continued)
Channel Memory Synchronous FIFO Full/Read Timing
PORT CLOCK tCHMCLK tCHMFS tCHMFH
READ ENABLE tCHMFRDV
REGISTERED OUTPUT
FULL FLAG (active low) tCHMSKEW1 tCHMFO tCHMFO
PORT CLOCK
WRITE ENABLE tCHMS tCHMH
REGISTERED INPUT
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT CLOCK tCHMCLK tCHMFH
tCHMFS
WRITE ENABLE
PROGRAMMABLE ALMOST-EMPTY FLAG (active LOW) tCHMSKEW3 tCHMFO tCHMFO
PORT CLOCK
tCHMFS READ ENABLE
tCHMFH
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Switching Waveforms (continued)
PORT CLOCK tCHMCLK WRITE ENABLE tCHMFO PROGRAMMABLE ALMOST-FULL FLAG (active LOW) tCHMFO
tCHMSKEW3
PORT CLOCK
READ ENABLE
Channel Memory Synchronous FIFO Master Reset Timing
tCHMFRS MASTER RESET INPUT tCHMFRSR
READ ENABLE WRITE ENABLE tCHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS REGISTERED OUTPUT
tCHMFRSF
tCHMFRSF
Optical Module Limiting Amplifier OUT+
ohms
CYS25G01K100
ohms OUTIN-
ohms
Figure Serial Input Termination
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ohms ohms OUT-
OUT+
CYS25G01K100
Internally source matched drive differential Transmission Lines
Figure Serial Output Termination
=3.3V lock ource 82.5 =3.3V 82.5
Figure REFCLK Oscillator Termination
=3.3V lock ource 82.5 =3.3V 82.5 0.01 0.01
Figure AC-Coupled REFCLK Oscillator Termination
Signal Description
Name CCLK CDONE CDATA GCLK0-1 GCTL0-3 IO/VREF0 IO/VREF1 IO/VREF2 IO/VREF3 IO/VREF4 IO/VREF5 Function Output Output Input Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Signal Description Configuration Clock serial interface with external boot PROM Flag indicating that configuration complete receive configuration data from external boot PROM Global Input Clock signals through Other global clocks TXCLK RXCLK. Chip select external boot PROM Global Control signals through Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Dual function pin: Reference Voltage Bank Page Standard Device Signals
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2.5-Gbps Programmable Serial Interface
Signal Description (continued)
Name IO6/Lock HSTLREF MSEL Reconfig CRST TXD[15:0] TXCLK Function Input/Output Input/Output Input Input Input Output Input Input Output Input Internal Internal Input Output Dual function pin: Bank lock output signal Reference Voltage HSTL Specific Banks Mode Select start configuration Reset signal interface with external boot PROM JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select Parallel Transmit Data Inputs serial transceiver block. 16-bit word, sampled TXCLK. TXD[15] most significant (the first transmitted) Parallel Transmit Data Input Clock serial transceiver block. Divide selected transmit bit-rate clock. four global clocks programmable logic. Parallel Receive Data Output from serial transceiver block. These outputs change following RXCLK. RXD[15] most significant output word, received first serial interface Receive Clock Output from serial transceiver block. Divide bit-rate clock extracted from received serial stream. four global clocks programmable. Common Mode Termination. Capacitor (0.1 shunt common mode noise Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Positive) Receive Loop Filter Capacitor (Positive) Signal Description
Transmit Path Signals
Receive Path Signals RXD[15:0] Internal
RXCLK
Internal
CMSER RXCN1 RXCN2 RXCP1 RXCP2 REFCLK±
Analog Analog Analog Analog Analog
Transceiver Control Status Signals Differential LVPECL Reference Clock. This clock input used timing reference transmit input receive PLLs. derivative this input clock also used clock transmit parallel interface Internal Line Fault Indicator Output Signal. When LOW, this signal indicates that selected receive data stream been detected invalid either input receive being operated outside specified limits Reset logic functions serial transceiver block except transmit FIFO Receive Lock Reference Input Signal. When LOW, receive locks REFCLK instead received serial data stream Signal Detect. When LOW, receive locks REFCLK instead received serial data stream Transmit FIFO Error Output Signal. When HIGH transmit FIFO either under overflowed. FIFO must reset clear error indication Transmit FIFO Reset Input Signal. When LOW, pointers transmit FIFO maximum separation Device Power Down Input Signal. When LOW, logic drivers disabled placed into standby condition where only minimal power dissipated
RESET LOCKREF FIFO_ERR FIFO_RST PWRDN
Internal Internal LVTTL input Internal Internal Internal
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2.5-Gbps Programmable Serial Interface
Signal Description (continued)
Name DIAGLOOP Function Internal Signal Description Diagnostic Loopback Control Input Signal. When HIGH, transmit data routed through receive clock data recovery presented RXD[15:0] outputs. When LOW, received serial data routed through receive clock data recovery presented RXD[15:0] outputs Line Loopback Control Input Signal. When HIGH, received serial data looped back from receive transmit after being reclocked recovered clock. When LINELOOP LOW, data passed OUT± line driver controlled LOOPA. When both LINELOOP LOOPA LOW, data passed OUT± line driver generated transmit shifter Analog Line Loopback Input Signal. When LINELOOP LOOPA HIGH, received serial data looped back from receive input buffer transmit output buffer, routed through clock data recovery PLL. When LOOPA LOW, data passed OUT± line driver controlled LINELOOP Loop Time Mode Input Signal. When HIGH, extracted receive bit-clock replaces transmit bit-clock. When LOW, REFCLK input multiplied generate transmit clock Differential Serial Data Output. This differential output (+3.3V referenced) capable driving terminated transmission lines commercial fiberoptic transmitter modules Differential Serial Data Input. This differential input accept serial data stream deserialization clock extraction +3.3V Supply (operating voltage) Signal Power Ground +3.3V Quiet Power Quiet Ground +1.5V Supply HSTL Outputs Power Power Power Power Power Power Power Power Power Ground Power bank bank bank bank bank bank JTAG pins Configuration port logic Ground logic Self-Bootsolution embedded boot PROM Transceiver Loop Control Signals
LINELOOP
Internal
LOOPA
Internal
LOOPTIME
Internal
Serial OUT± Differential output Differential input Power Ground
Power VCCQ VSSQ VDDQ VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCJTAG VCCCFG VCCPLL GNPLL VCEP
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2.5-Gbps Programmable Serial Interface
Configurations
456-ball (25G01K100): View
HSTLREF GCTL0
VDDQ VDDQ
VDDQ
HSTLREF VDDQ
VDDQ
GCTL
HSTLREF HSTLREF
HSTLREF VDDQ
HSTLREF VDDQ VDDQ
VDDQ
HSTLREF IO6/ Lock
HSTLREF
IO/VRE
IO/VRE VSSQ
GCLK1
IO/VRE
HSTLB HSTL- HSTLREF
IO/VR
GCTL2 GCTL1 VDDQ
HSTLREF
VCCPL VDDQ VDDQ IO/VRE
VCCIO5 VCCIO5 VCCIO VCCJT VSSQ VSSQ VSSQ VSSQ
IO/VRE VCCIO0 GCLK0
VCCIO0 VCCIO0 IO/VRE VCEP IO/VRE GNPLL
VSSQ VSSQ VSSQ
VSSQ
IO/VRE
RXCN1 RXCP1 RXCN2 RXCP2 VCCQ VSSQ VSSQ VSSQ VCCQ VCCQ VCCQ VCCQ VSSQ
VCCIO1 IO/VRE
VSSQ VSSQ CMSE VSSQ OUT+ OUTVCCQ VCCQ VCCQ IO/VRE VCCIO IO/VRE
IO/VR IO/VRE
REF- VCCIO4 CLK+ REF- VCCIO4 CLKIO4 IO/VRE IO/VRE IO/VRE IO/VRE VCEP
VCCIO1 IO/VRE
CDONE VCCIO1 CDAT RECON
VCCCF VCCIO2 VCCIO2 VCCIO2 VCCIO IO/VRE IO/VRE
VDDQ VCCIO VCCIO IO/VRE
VCCIO4 IO/VRE IO/VRE
CRST CCLK
VDDQ VDDQ
VCCIO3 VCCIO3 IO/VRE IO/VRE
MSEL IO/VRE
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2.5-Gbps Programmable Serial Interface
K100
Standard Cypress Designator SONET 1.5Gbps 2.5Gbps Commercial Industrial
Package Type
channel
Standard Power 3.3V-Vcc
K100 100K gates
Ordering Information
Device 25G01K100 Channels Link Speed Gbps Gbps Ordering Code CYP25G01K100V1-MGC CYS25G01K100V1-MGC Package Name Package Type Operating Range Commercial
456MGC 456-ball Ball Grid Array 456MGC 456-ball Ball Grid Array
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2.5-Gbps Programmable Serial Interface
Package Diagram
456-ball Ball Grid Array 2.33 BG456
51-85133-*A
trademark IDT. InfiniBand trademark InfiniBand Trade Association. trademark Micron, IDT, Cypress Semiconductor Corporation. Windows registered trademark Microsoft Corporation. SpeedWave ViewDraw trademarks ViewLogic. Warp registered trademark, NoBL, Programmable Interconnect Matrix, PIM, Spread Aware, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, Programmable Serial Interface, trademarks, Cypress Semiconductor Corporation. product company names mentioned this document trademarks their respective holders.
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Cypress Semiconductor Corporation, 2002. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
2.5-Gbps Programmable Serial Interface
Document History Page
Document Title: 2.5-Gbps Programmable Serial Interface Document Number: 38-02021 REV. 106745 107726 109064 120882 Orig. Issue Date Change 05/25/01 06/04/01 09/07/01 12/13/02 Description Change Change from Spec #38-01093 38-02021 Updated Marketing Part Numbers Added feature CHAR data Revised data sheet reflect only 2.5-Gbps single channel 100K programmable logic data. Added SONET jitter specs jitter performance data CYS25G01K100. Added REFCLK phase noise limits plot CYS25G01K100. Changed title. Updated logic data with additional multiplication factors available. Added sections titled "Registering TXD[15:0] Data Before enters Serial Transceiver Block" "Registering RXD[15:0] Data before enters Programmable under major section called "Serial Transceiver Operation." Updated some Timing Parameter Values. Updated Output Differential Swing Input Differential Voltage.
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Development Software Warp® IEEE 1076/1164 VHDL IEEE 1364 Verilog

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