µPD98409 ALIGHT CONTROLLER DESCRIPTION µPD98409 (NEASCO

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µPD98409 ALIGHT CONTROLLER DESCRIPTION µPD98409 (NEASCO

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INTEGRATED CIRCUIT
µPD98409
ALIGHT CONTROLLER
DESCRIPTION
µPD98409 (NEASCOT-S40C high-performance chip segmentation reassembly Acells. Provided with (Peripheral Component Interconnect) interface control memory supporting MPEG packet transfer engine function mitigate workload transferring compressed image data, this chip ideal specifications (STB) interface with Anetwork. µPD98409 conforms AForum recommendations AAL5-SAR sublayer Alayer functions. Detailed descriptions functions, etc., given following user's manual. sure read design purposes.
µPD98409 User's Manual: S12776E
FEATURES
Conforms AForum interface (5/3.3 32/64 bits, MHz) Conforms Local Specification Revision AAL-5 sublayer Alayer functions Hardware support AAL-5 processing (non-AAL-5 processing supported software) Supports virtual channels (VC) (64-VC control memory) traffic shapers transmission scheduling MPEG packet transfer engine mitigating workload compressed image data transfer Receive FIFO cells device I/F: UTOPIA Level-1 interface (octet/cell level handshake) JTAG boundary scan test functions 0.35-µm CMOS process, +5/+3.3-V power supply interface +5/+3.3-V power supply interface +3.3 +3.3-V single power supply
ORDERING INFORMATION
Part Number Package 240-pin plastic (fine pitch)
µPD98409GN-LMU
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S12775EJ3V0DS00 (3rd edition) Date Published April 2002 CP(K) Printed Japan
mark
shows major revised points.
1997, 1998
µPD98409
EXAMPLE SYSTEM CONFIGURATION
ASTB
Line interface
PD98409
MPEG decoder block
Memory
BLOCK DIAGRAM
Receive data FIFO cells) MPEG packet transfer engine Receive interface Receive controller UTOPIA interface
interface
interface block
controller
Sequencer
Control memory interface
Control memory VCs) control interface
Transmit controller Transmit interface Transmit data FIFO cells) UTOPIA interface
Data Sheet S12775EJ3V0DS
µPD98409
CONFIGURATION (Top View) 240-pin plastic (fine pitch)
RSTOUT_B PHYSEL1 JRST_B RST_B LASTB
AD30
AD31
VDD3
VDD5
VDD5
VDD3
VDD3
VDD3
VDD3
AD29 AD28 AD27 AD26 VDD5 AD25 AD24 PCBE3_B IDSEL VDD5 AD23 AD22 AD21 AD20 VDD3 AD19 AD18 AD17 AD16 PCBE2_B FRAME_B IRDY_B TRDY_B VDD5 DEVSEL_B STOP_B PERR_B SERR_B PCBE1_B VDD3 AD15 AD14 AD13 AD12 VDD5 AD11 AD10 VDD5 PCBE0_B VDD5
VDD3
VDD3 PHCE_B PHOE_B VDD3 PHRW_B PHINT_B VDD3 VDD3 TCLK TENBL_B TSOC FULL_B/TXCLAV RSOC RENBL_B EMPTY_B/RXCLAV VDD3 RCLK
VDD3
VDD5
VDD5
VDD3
VDD3
VDD3
INTR_B
GNT_B
REQ_B
BUSCLK
E2PCLK
E2PDO
E2PDI
connection. Leave this open. Input with pull-down resistor internal test. recommended this level. this level.
E2PCS
VDD3
PD98409GN-LMU
Data Sheet S12775EJ3V0DS
µPD98409
NAMES AD31_AD0 BUSCLK CA8-CA0 CD7-CD0 DEVSEL_B E2PCLK E2PCS E2PDI E2PDO FRAME_B FULL_B/TxCLAV GNT_B IDSEL INTR_B IRDY_B JRST_B LA5-LA0 LASTB PCBE_B3PCBE_B0 PERR_B PHCE_B Parity Error Chip Enable Cycle Frame Buffer Full Cell Available Ground Grant Select Interrupt Initiator Ready JTAG Test JTAG Test JTAG Test JTAG Test JTAG Test Internal Test Internal Test Parity Command Byte Enables RSTOUT_B Rx7-Rx0 SERR_B STOP_B TCLK TENBL_B TRDY_B TSOC Tx7-Tx0 VDD3 VDD5 Reset Output Receive Data System Error Stop Transmit Clock Transmit Enable Target Ready Transmit Start Cell Transmit Data +3.3 Power Supply Power Supply Address/Data Clock Device Address Device Data Device Select Clock EEPROM
PHINT_B PHOE_B PHRW_B PHYSEL1 PO3-PO0 RCLK RENBL_B REQ_B RSOC RST_B
Interrupt Output Enable Read/Write Select Generic Output Port Receive Clock Receive Enable Request Receive Start Cell Reset
EEPROM Chip Select Serial Data Input from EEPROM Serial Data Output EEPROM
EMPTY_B/RxCLA Empty Cell Available
Data Sheet S12775EJ3V0DS
µPD98409
CONTENTS FUNCTION.6
Device Interface Pin. 1.1.1 UTOPIA interface. 1.1.2 device control interface. Interface Pins. Serial EEPROM Interface Pins JTAG Boundary Scan Pins. Other Pins Power Ground Pins.
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING.34 RECOMMENDED SOLDERING CONDITIONS
Data Sheet S12775EJ3V0DS
µPD98409
FUNCTION
function µPD98409 descibed below. detailed explanation each pin, points noted using pins given µPD98409 User's Manual (Document Number: S12776E). sure refer this user's manual. following describes levels tables. LV-TTL input connected CMOS output output input connected input, 5/3.3 input CMOS output CMOS output, output: 5/3.3 output Device Interface device interfaces include UTOPIA interface through which µPD98409 transfers Acells with device, control interface which µPD98409 controls device. 1.1.1 UTOPIA interface (1/2)
Name Rx7-Rx0 119, Level LV-TTL Function Receive Data Bus. through constitute 8-bit input which inputs data received from network byte format from device. µPD98409 loads data rising edge RCLK. Receive Start Cell. RSOC signal input synchronization with first byte cell data from device. This signal remains high while first byte header input through Rx0. Receive Enable. RENBL_B signal indicates device that µPD98409 ready receive data next clock cycle. Output Buffer Empty/Rx Cell Available. This signal notifies µPD98409 that there cell data transferred receive FIFO that receive data supplied device. When UTOPIA interface octet-level handshake mode, this signal serves EMPTY_B, indicating that data through invalid current clock cycle. cell-level handshake mode, serves RxCLAV, indicating that there cell supplied next after transfer current cell completed. Receive Clock. This synchronization clock used transfer cell data with device receive side. system clock input BUSCLK output from this Transmit Data Bus. through constitute 8-bit output which outputs transmit data byte format device. µPD98409 outputs data rising edge TCLK. Transmit Start Cell. TSOC signal output synchronization with first byte transmit cell data.
RSOC
LV-TTL
RENBL_B
EMPTY_B/ RxCLAV
LV-TTL
RCLK
Tx7-Tx0
144,
TSOC
Data Sheet S12775EJ3V0DS
µPD98409
(2/2)
Name TENBL_B Level Transmit Enable. TENBL_B signal indicates device that data been output through current clock cycle. FULL_B/ TxCLAV LV-TTL Buffer Full/Tx Cell Available. This signal notifies µPD98409 that input buffer device full that device receive more data. When UTOPIA interface octet-level handshake mode, device inputs inactive level receive cell data. celllevel handshake mode, device inputs signal that indicates that device receive next cell data after current cell been completely transferred. TCLK Transmit Clock. This synchronization clock used transfer cell data with device transmission side. system clock input BUSCLK output from this Function
1.1.2 device control interface
Name PHRW_B Level Function Read/Write. µPD98409 indicates direction which device controlled, using PHRW_B. Read Write PHOE_B Output Enable. µPD98409 enables output from device making PHOE_B Chip Enable. µPD98409 makes PHCE_B access device. Interrupt. This interrupt input signal from device. device indicates µPD98409 that interrupt source, inputting level PHINT_B. Reset Output. This signal reset device. µPD98409 makes this duration clock cycles when level input RST_B software reset executed. device data. through constitute 8-bit data bus. These pins threestate pins. They used transfer data with device. device address. through constitute 9-bit address that outputs address device during read/write operation.
PHCE_B PHINT_B
LV-TTL
RSTOUT_B
CD7-CD0
154, 155, 159, 175, 170,
3-state
LV-TTL
CA8-CA0
Data Sheet S12775EJ3V0DS
µPD98409
Interface Pins µPD98409 employs 32-bit interface interface with host. This interface conforms "PCI Local Specification Revision 2.1". (1/2)
Name AD31-AD0 238, 239, 3-state Level Function Address/data. AD31 through bits multiplexed address data signals. When µPD98409 operates master, drives address first clock, transfers data second clock onward.
PCBE3_B PCBE2_B PCBE1_B PCBE0_B
3-state
command byte enable. These signals define "bus commands" (generated transaction) address phase. data phase, they indicate which byte lane holds valid data. PCBE3_B corresponds byte (bits through 24), PCBE0_B corresponds byte (bits through Parity. This signal inputs/outputs even parity AD31 through PCBE3_B through PCBE0_B pins including signal. When µPD98409 operates master, signal output address write data phases. When µPD98409 operates target, signal output read data phase. Frame. This signal indicates start period transaction. When this signal becomes active, indicates start transaction. While active, data transferred. When next data transfer phase last data transaction, this signal becomes inactive. Target ready. This signal goes when target device ready complete transaction current data phase. This signal used pairs with IRDY_B. When both IRDY_B TRDY_B low, read/write data transfer executed. Initiator ready. This signal goes when initiator ready complete transaction current data phase. This signal used pairs with TRDY_B. When both IRDY_B TRDY_B low, read/write data transfer executed. both FRAME_B IRDY_B inactive, cycle executed, wait cycles inserted until both IRDY_B TRDY_B become active.
3-state
FRAME_B
Sustained 3-state
TRDY_B
Sustained 3-state
IRDY_B
Sustained 3-state
Data Sheet S12775EJ3V0DS
µPD98409
(2/2) Name STOP_B Sustained 3-state Sustained 3-state Level Function Stop. This signal goes when target device requests master device stop current transaction. Device select. This signal goes when µPD98409 operates target recognizes address after FRAME_B signal become active. When µPD98409 operates master, samples this signal check whether target device been selected. Initialization device select. This signal inputs high level when configuration register µPD98409 read/written. Request. µPD98409 requests arbiter mastership making this signal low. Grant. This signal goes when arbiter grants µPD98409 mastership. Parity error. This signal indicates that µPD98409 detected parity error. enabled when "Parity Error Response" configuration register System error. This signal indicates that µPD98409 detected address parity error. enabled when both "Parity Error Response" "System Error Enable" bits configuration register Interrupt output. Pull this because outputs open-drain signal. INTR_B informs that interrupt (not masked) register set. clock. clock input pin. inputs clock MHz. Reset. RST_B signal initializes µPD98409 starting). When level input RST_B, internal state machine registers µPD98409 reset, 3-state signals into highimpedance state. When this signal input while µPD98409 operating, operating status that time lost. Keep input RST_B least duration clock cycle. access µPD98409 least clocks after been reset.
DEVSEL_B
IDSEL
REQ_B
ONote
GNT_B
PERR_B
Sustained 3-state
SERR_B
N-ch open-drain
INTR_B
N-ch open-drain
BUSCLK RST_B
Note Although "PCI Local Specification Revision 2.1" specifies that REQ_B into highimpedance state while level input RST_B pin, REQ_B µPD98409 outputs high level.
Data Sheet S12775EJ3V0DS
µPD98409
Serial EEPROM Interface Pins µPD98409 interface serial EEPROM supporting MICROWIRE contents configuration register loaded from EEPROM connected. EEPROM, "NM93C46L" National Semiconductor Corp. recommended.
Name E2PCS Level Function EEPROM chip select. chip select signal EEPROM. Leave this open when used. EEPROM data input. This connected data output EEPROM. Pull open this when used. EEPROM data output. This connected data input EEPROM. Pull open this when used. EEPROM clock. This supplies clock necessary data transfer with EEPROM. outputs clock input BUSCLK divided Leave this open when used.
interface.
Some
E2PDI
Internally pulled
E2PDO
E2PCLK
Data Sheet S12775EJ3V0DS
µPD98409
JTAG Boundary Scan Pins (These functions supported request.)
Name Level LV-TTL JTAG Test Data Input. used input data JTAG boundary scan circuit register. Normally, this high level. 3-state JTAG Test Data Output. used output data from JTAG boundary scan circuit register. changes output falling edge clock input pin. Normally, leave this open. LV-TTL JTAG Test Clock. This used supply clock JTAG boundary scan circuit register. Normally, this high level. LV-TTL JTAG Test Mode Select. Normally, this high level. JRST_B LV-TTL JTAG Test Reset. This initializes JTAG boundary scan circuit register. Normally, this level. Function
Remark
Processing JTAG boundary scan pins used (during normal operation) reason that JRST_B grounded when used (during normal operation) better prevent malfunctioning JTAG logic. JTAG also processed either following ways: Reset JTAG logic without using JRST_B Reset JTAG logic using pins keep reset status (the JRST_B pulled up). (pull input clock cycles more pin. Reset JTAG logic using JRST_B Input pulse same width RST_B µPD98409 JRST_B pin. both JRST_B pins pulled kept high, JTAG logic released from reset status. Therefore, normal operation affected. input level pins pulling them down
Data Sheet S12775EJ3V0DS
µPD98409
Other Pins
Name PHYSEL1 Level LV-TTL Internal test pin. Input level this pin. PO3-PO0 CMOS General-purpose output port. General-purpose output port pins. These pins output value written GPOR register. Internal test pins. Leave these pins open during normal operation. Internal test pin. Leave this open during normal operation. Function
LA5-LA0 LASTB
185, 187,
Power Ground Pins
Name VDD3 100, 120, 130, 140, 151, 160, 169, 181, 190, 201, 206, 220, 234, 101, 110, 112, 121, 122, 127, 129, 137, 139, 145, 150, 156, 161, 168, 174, 179, 180, 186, 191, 196, 200, 207, 213, 215, 221, 223, 228, 233, Function +3.3-V power supply. These pins supply +3.3 chip. power supply. These pins supply chip when +5-V interface used. Supply +3.3 these pins when +3.3-V interface used. Ground. Connect ground.
VDD5
Data Sheet S12775EJ3V0DS
µPD98409
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD3 VDD5 Input voltage
Note
Conditions
Ratings -0.5 +4.6
Unit
VDD3 VDD5 Except PCI, VDD3
-0.5 +6.6 -0.5 +6.6 -5.5 +11.0 -0.5 +6.6 -0.5 +4.6 -0.5 +6.6 +150
Output voltage
Except PO0-PO3, VDD3 PO3-PO0, VDD3
Output current
Except PO0-PO3 PO3-PO0
Operating ambient temperature Storage temperature
Tstg
Note VDD5: Dedicated power supply clamping diode Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Recommended Operating Conditions
Parameter Supply voltage Symbol VDD3 VDD5
Note
Conditions
MIN.
TYP. 5.00
MAX. 5.25 VDD5 VDD5 +0.8 +0.8
Unit
+3.3
4.75
VDD5Note Operating ambient temperature High-level input voltage VIH1 VIH2 VIH3 Low-level input voltage VIL1 VIL2
Input pins except RST_B pins except RST_B Input pins except
-0.5
Note VDD5: Dedicated power supply clamping diode
Data Sheet S12775EJ3V0DS
µPD98409
Charateristics +70°C, VDD3 +3.3 ±0.3
Parameter High-level output voltage Symbol VOH1 VOH2 Low-level output voltage VOL1 VOL2 VOL3 VOL4 Supply current Input leakage current (normal input) Input leakage current (E2PDI with pull-up resistor) Conditions -2.0
Note Note
MIN.
TYP.
MAX.
Unit
-12.0
mANote
Note Note Note
0.55 0.55 0.40 0.40 ±10-4
12.0
fCLK MHz, normal transmission/ reception VDD3
Notes
VOH1 applies output pins except pins PO3-PO0. VOH2 applies pins PO3-PO0. VOL1 applies output pins AD31-AD0, PCBE3_B-PCBE0_B, PAR, REQ_B INTR_B. VOL2 applies output pins FRAME_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, PERR_B. VOL3 applies pins other than output pins pins other than pins PO3-PO0. VOL4 applies pins PO3-PO0.
Capacitance +25°C, VDD3
Parameter Input capacitance Output capacitance capacitance Symbol COUT CI/O Conditions MIN. TYP. MAX. Unit
Data Sheet S12775EJ3V0DS
µPD98409
Characteristics +70°C, VDD3 +3.3 BUSCLK input
Parameter cycle time high-level width low-level width amplitude through rate Symbol tCYCLK tCLKH tCLKL VPPCLK slewCLK Conditions MIN. TYP. MAX. Unit V/ns
input
Parameter low-level width through rate
;;;;;;; @@@;;;@ ;;;@@@; @@@@@@@ ;;;;;;;
(MIN.) VPPCLK (MAX.) tCLKH tCLKL tCYCLK
Symbol tRSTL slewRST
Conditions
MIN. tCYCLK
TYP.
MAX.
Unit mV/ns
Data Sheet S12775EJ3V0DS
µPD98409
Interface master read
Parameter CLKFRAME_B valid time CLKAD (Address) valid time CLKAD (Address) float time (Data) setup time (Data) hold time CLKPCBE_B valid time CLKPCBE_B float time CLKIRDY_B valid time CLKIRDY_B float time TRDY_B setup time TRDY_B hold time DEVSEL_B setup time DEVSEL_B hold time CLKPAR valid time CLKPAR float time setup time hold time CLKPERR_B valid time CLKPERR_B float time Symbol tDFRAME tDADDR tDADDRF tSDATA tHDATA tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tDPAR tDPARF tSPAR tHPAR tDPERR tDPERRF
Note
Conditions
MIN.
TYP.
MAX.
Unit
Note
Note Note
Note
Notes
Relaxed specification from Local Specification Revision Relaxed specification from Local Specification Revision
Data Sheet S12775EJ3V0DS
µPD98409
master read
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PERR_B
@@@@ ;;;; @@@@@@@ ;;;;;;; @@@@@@@@ ;;;;;;;; @@@@ ;;;; ;;;; @@@@ ;;;; @@@@ ;;;; @@@@@ ;;;;;
tDFRAME tDADDR tDADDRF tSDATA tHDATA (Data) (Address) tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tDPAR tDPARF tSPAR tHPAR (output) (input) tDPERR tDPERRF
Data Sheet S12775EJ3V0DS
µPD98409
master write
Parameter FRAME_B valid time (Address) valid time data valid time data float time PCBE_B valid time PCBE_B float time IRDY_B valid time IRDY_B float time TRDY_B setup time TRDY_B hold time DEVSEL_B setup time DEVSEL_B hold time valid time float time PERR_B setup time PERR_B hold time Symbol tDFRAME tDADDR tDDATA tDDATAF tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tDPAR tDPARF tSPERR tHPERR
Note
Conditions
MIN.
TYP.
MAX.
Unit
Note Note
Note
Notes
Relaxed specification from Local Specification Revision Relaxed specification from Local Specification Revision
Data Sheet S12775EJ3V0DS
µPD98409
master write
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PERR_B
@@;; ;;@@ @@@@ ;;;;
tDFRAME tDADDR (Address) tDPCBE
tDDATA
tDIRDY
tSTRDY
tSDEVSEL
tDPAR (output)
@@@@ ;;;; @@@@ ;;;; @@@@ ;;;; @@@@ ;;;;
tDDATAF (Data) tDPCBEF tDIRDYF tHTRDY tHDEVSEL tDPARF (output) tSPERR
tHPERR
Data Sheet S12775EJ3V0DS
µPD98409
Target read
Parameter FRAME_B setup time FRAME_B hold time (Address) setup time (Address) hold time (Data) valid time (Data) float time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time TRDY_B valid time TRDY_B float time DEVSEL_B valid time DEVSEL_B float time setup time hold time valid time float time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPAR tDPARF tSPERR tHPERR
Note
Conditions
MIN.
Note
TYP.
MAX.
Unit
Note
2Note
Note Note
Note
Notes
Relaxed specification from Local Specification Revision Relaxed specification from Local Specification Revision
Data Sheet S12775EJ3V0DS
µPD98409
Target read
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PERR_B
@@@@ ;;;; @@@@ ;;;; @;;@ ;;;; @;;;
tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF
(Address)
(Data)
tSPCBE
tHPCBE
tSIRDY
tHIRDY
tDTRDYF
tDTRDY
tDDEVSELF
tDDEVSEL
tSPAR
tHPAR
tDPAR
tDPARF
(input)
(output)
tHPERR
tSPERR
Data Sheet S12775EJ3V0DS
µPD98409
Target write
Parameter FRAME_B setup time FRAME_B hold time (Address) setup time (Address) hold time (Data) setup time (Data) hold time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time TRDY_B valid time TRDY_B float time DEVSEL_B valid time DEVSEL_B float time setup time hold time PERR_B valid time PERR_B float time Symbol tSFRAME tHFRAME tSADDR tHADDR tSDATA tHDATA tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPERR tDPERRF
Note
Conditions
MIN.
Note
TYP.
MAX.
Unit
Note
Note
2Note
Note Note
Notes
Relaxed specification from Local Specification Revision Relaxed specification from Local Specification Revision
Data Sheet S12775EJ3V0DS
µPD98409
Target write
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PERR_B
@@@@ ;;;; @@;; ;;@@ @@@@ ;;;; @@@@ ;;;; @@@@ ;;;;
tSFRAME tHFRAME tSADDR tHADDR tSDATA tHDATA
(Address)
(Data)
tSPCBE
tHPCBE
tSIRDY
tHIRDY
tDTRDYF
tDTRDY
tDDEVSELF
tDDEVSEL
tSPAR
tHPAR
(input)
(input)
tDPERR
tDPERRF
Data Sheet S12775EJ3V0DS
µPD98409
arbitration
Parameter REQ_B valid time GNT_B setup time GNT_B hold time Symbol tDREQ tSGNT tHGNT Conditions MIN. 2Note TYP. MAX. Unit
Note Relaxed specification from Local Specification Revision arbitration
REQ_B
tDREQ
GNT_B
tSGNT tHGNT
Data Sheet S12775EJ3V0DS
µPD98409
Configuration read
Parameter FRAME_B setup time FRAME_B hold time (Address) setup time (Address) hold time (Data) valid time (Data) float time PCBE_B setup time PCBE_B hold time IDSEL setup time IDSEL hold time IRDY_B setup time IRDY_B hold time TRDY_B valid time TRDY_B float time DEVSEL_B valid time DEVSEL_B float time valid time float time setup time hold time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIDSEL tHIDSEL tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tDPAR tDPARF tSPAR tHPAR tSPERR tHPERR
Note
Conditions
MIN.
Note
TYP.
MAX.
Unit
Note
2Note
Note Note Note
Note
Notes
Relaxed specification from Local Specification Revision Relaxed specification from Local Specification Revision
Data Sheet S12775EJ3V0DS
µPD98409
Configuration read
tSFRAME FRAME_B
tSADDR AD31-AD0
tSPCBE PCBE3_BPCBE0_B
tSIDSEL IDSEL
IRDY_B
TRDY_B
DEVSEL_B
PERR_B
@;;@@@ ;@@;;;; @@@@ ;;;; @@@@ ;;;; @@@@@@ ;;;;;; ;;;; @@@@ ;;;;
tHFRAME tHADDR tDDATA tDDATAF
(Address)
(Data)
tHPCBE
tHIDSEL
tSIRDY
tHIRDY
tDTRDYF
tDTRDY
tDDEVSELF
tDDEVSEL
tSPAR
tHPAR
tDPAR
tDPARF
(input)
(output)
tHPERR
tSPERR
Data Sheet S12775EJ3V0DS
µPD98409
EEPROM Interface
Parameter E2PCLK high-level width E2PCLK low-level width E2PCLK E2PCS valid time E2PCS E2PCLK P2PCLK E2PDO valid time E2PDI E2PCLK setup time E2PCLK E2PDI hold time E2PCS E2PDI (Status) valid delay time E2PCS E2PDI (Status) invalid delay time Symbol tWE2PCLKH tWE2PCLKL tDE2PCS tSE2PCS tDE2PDO tSE2PDI tHE2PDI tDE2PSTV tDE2PSTI Conditions MIN. TYP. MAX. Unit
tCYCLK tCYCLK tCYCLK tCYCLK tCYCLK tCYCLK
EEPROM interface
E2PCLK
tDE2PCS E2PCS
tDE2PDO E2PDO
E2PDI (READ) E2PDI (Status)
@@@@ ;;;; @@@@ ;;;;
tWE2PCLKH tWE2PCLKL tSE2PCS tSE2PDI tHE2PDI tDE2PSTV
tDE2PCS
(Status)
tDE2PSTI
Data Sheet S12775EJ3V0DS
µPD98409
UTOPIA Interface Transmission operation
Parameter TCLK delay time TCLK TSOC delay time TCLK TENBL_B delay time FULL_B setup time FULL_B hold time Symbol tDTX tDTSOC tDTEN tSFULL tHFULL Conditions MIN. TYP. MAX. Unit
Reception operation
Parameter setup time hold time RSOC setup time RSOC hold time RCLK RENBL_B delay time EMPTY_B setup time EMPTY_B hold time Symbol tSRX tHRX tSRSOC tHRSOC tDREN tSEMPT tHEMPT Conditions MIN. TYP. MAX. Unit
Data Sheet S12775EJ3V0DS
µPD98409
;;;;;; @@@@@@ ;;;;;; ;;;;;; @@@@@@ ;;;;;; ;;;;;;;; @@@@@@@@ ;;;;;;;;
INVALID `00H' tDTEN tDTEN
Transmission operation
UTOPIA interface
Tx7-Tx0
TENBL_B
FULL_B
TSOC
TCLK
;;;;; @@@@@ ;;;;; ;;;;; @@@@@ ;;;;; ;;;;; @@@@@ ;;;;;
tDTSOC
tSFULL
tHFULL
tDTX
tDTSOC
H1-H4: Aheader P1-P9: Payload data
Data Sheet S12775EJ3V0DS
µPD98409
;;;;;; @@@@@@ ;;;;;; ;;;;;; @@@@@@ ;;;;;;
INVALID
UTOPIA interface
Reception operation
;;;;;;;; @@@@@@@@ ;;;;;;;; ;;;;;;;; @@@@@@@@ ;;;;;;;; ;;;;; @@@@@ ;;;;; ;;;;; @@@@@ ;;;;; ;;;;; @@@@@ ;;;;;
INVALID tHRSOC tHRX tSEMPT tHEMPT tSRX tSRSOC
Data Sheet S12775EJ3V0DS
tDREN
tDREN
EMPTY_B
Rx7-Rx0
RSOC
RCLK
RENBL_B
H1-H4: Aheader P1-P7: Payload data
µPD98409
Status Access Write
Parameter delay time PHRW_B delay time PHCE_B delay time delay time PHCE_B float time Symbol tDPCA tDPHRW tDPHCE tDPCD tFPCD 1tCYCLK Conditions MIN. TYP. MAX. 1tCYCLK Unit
Write timing
tDPCA CA8-CA0
PHRW_B
PHCE_B
PHOE_B
CD7-CD0
Read
Parameter setup time hold time delay time
@@@@@@@ ;;;;;;;
clock clocks clock tDPHRW tDPHCE tDPHCE tDPCD tFPCD (output)
Symbol tSPCD tHPOECD tDPCA tDPHRW tDPHCE tDPHOE Conditions
tDPCA
tDPHRW
MIN.
TYP.
MAX.
Unit
PHRW_B delay time PHCE_B delay time PHOE_B delay time
Data Sheet S12775EJ3V0DS
µPD98409
Read timing
;;;; ;;;; @@@@ ;;;;;;;; @@@@@@@@ ;;;;;;;; ;;;; @@@@ ;;;; ;;;;;;;;; @@@@@@@;; ;;;;;;;@@ ;;;;;; @@@@@@ ;;;;;; ;;;;;; ;;;; @@;; ;;@@ @@@@@@ ;;;;;; ;;;; @;;; ;@@@ ;;;; @@@@ ;;;;
tDPHCE tHPOECD tDPHOE clocks clocks clocks tDPCA clock tDPCA tDPHRW tDPHCE tDPHOE tSPCD CD7-CD0 CA8-CA0 PHRW_B
Data Sheet S12775EJ3V0DS
PHOE_B
PHCE_B
(input)
µPD98409
Others
Parameter PHINT_B setup time PHINT_B hold time delay time RSTOUT_B delay time RSTOUT_B output pulse width Symbol tSPHI tHPHI tDPO tDRSTO tWRSTO Conditions MIN. TYP. MAX. Unit tCYCLK
Other timing
PHINT_B
PO3-PO0
RSTOUT_B
@@@@@@@@@@@ ;;;;;;;;;;;
tSPHI tHPHI tDPO tDRSTO tWRSTO
Data Sheet S12775EJ3V0DS
µPD98409
PACKAGE DRAWING
240-PIN PLASTIC (FINE PITCH) (32x32)
detail lead
ITEM MILLIMETERS 34.6±0.2 32.0±0.2 32.0±0.2 34.6±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.3±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 3.2±0.1 0.4±0.1 MAX.
NOTE
Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
P240GN-50-LMU, MMU, SMU-4
Data Sheet S12775EJ3V0DS
µPD98409
RECOMMENDED SOLDERING CONDITIONS
Solder product under following recommended conditions. details recommended soldering conditions, refer Information Document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods soldering conditions other than those recommended, consult NEC. Table 4-1. Recommended Soldering Conditions Surface Mount Type µPD98409GN-LMU: 240-pin plastic (fine pitch)
Symbol Recommended Condition IR35-203-1
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. (210°C min.), Number times: once, Number days: 3Note (Afterwards, prebaking necessary 125°C hours.) Package peak temperature: 215°C, Time: seconds max. (200°C min.), Number times: once, Number days: 3Note (Afterwards, prebaking necessary 125°C hours.) temperature: max., Time: seconds max. (per side device)
VP15-203-1
Partial heating
Note Number days storage after pack been opened. storage conditions 25°C, 65%RH max. Caution different soldering methods together (except partial heating).
Data Sheet S12775EJ3V0DS
µPD98409
[MEMO]
Data Sheet S12775EJ3V0DS
µPD98409
[MEMO]
Data Sheet S12775EJ3V0DS
µPD98409
[MEMO]
Data Sheet S12775EJ3V0DS
µPD98409
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S12775EJ3V0DS
µPD98409
NEASCOT-S40C EEPROM trademarks Corporation. MICROWIRE trademark National Semiconductor Corporation.
information this document current April, 2002. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98409 ALIGHT CONTROLLER DESCRIPTION µPD98409 (NEASCO

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