Description T2803 low-power applications 2.45 band. QFN48-package
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Supply-voltage Range (Regulated) Auxiliary Voltage Regulator On-chip (3.2 Current Consumption Low-cost External Components Mechanical Tuning Required Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz) Fast Settling Synthesizer (864 Channel Spacing) Preamplifier with Output Power 2.45 Programmable Power Levels) Ramp-signal Generator Power Ramping Power Control External SiGe Power Amplifier (T7024 T7026)
Description
T2803 low-power applications 2.45 band. QFN48-packaged complete transceiver including image rejection mixer, amplifier, demodulator, baseband filter, RSSI, preamplifier, power-ramping generator power amplifiers, integrated synthesizer, fully integrated Gaussian data filter mechanical tuning necessary production.
WDECT/ISM Single-chip Transceiver T2803 Preliminary
Figure Block Diagram
MIXER IF_IN MIXER RF_IN DEMOD FILTER RAMP_OUT RAMP_SET RAMP RAMP RSSI TX_DATA DEMOD RSSI IF_TANK BB_OUT DEMOD TANK
SWITCH
TX_OUT DRIVER
3-WIRE
CLOCK DATA ENABLE
CTRL LOGIC
RX_ON TX_ON PU_RX/TX PU_PLL
VREG_VCO VS_VCO VREG VS_REG GND_VCO PU_REG REG_CTRL VTUNE
I_CPSW
REF_CLK
Rev. 4572D-DECT-07/03
Table Functional Block Description
Name DEMOD AMP1 AMP2 MIXER RAMP RSSI DRIVER TX/RX SWITCH Description Auxiliary voltage regulator Baseband filter Charge pump converter demodulator tuning Demodulator Gaussian filter transmit data intermediate frequency amplifier intermediate frequency amplifier Image rejection mixer Programmable counter Phase detector Ramp-signal generator Reference counter Received signal-strength indicator Buffer amplifier TX_OUT Switches signal MIXER respectively DRIVER Voltage-controlled oscillator Voltage regulator
Configuration
Figure Pinning QFN48
MIXER_OUT2 MIXER_OUT1 PU_RX/TX TX_DATA VS_MIXER PU_PLL GND_PLL TX_ON RX_ON RAMP_SET I_CPSW
CLOCK DATA ENABLE REF_CLK PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP
RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI
T2803
DAC_DEC
REG_DEC
VTUNE
BB_CF
T2803
4572D-DECT-07/03
DEMOD_TANK1
DEMOD_TANK2
VREG_VCO
GND_VCO
VS_VCO
BB_OUT
GND1
T2803
Description
Symbol Function
VS_PLL
Configuration
CLOCK
3-wire-bus: Clock input
DATA
3-wire-bus: Data input
CLOCK DATA ENABLE 1,2,3
ENABLE
3-wire-bus: Enable input
GND_PLL
VS_PLL
REF_CLK
Reference-frequency input
REF_CLK
GND_PLL
Lock-detect output
GND_PLL
PU_REG
PU_REG
Power-up input auxiliary voltage regulator
GND_PLL
4572D-DECT-07/03
Description (Continued)
Symbol Function
VS_PLL VS_REG VS_CP VS_VCO
Configuration
GND1 GND2 GND3 GND_VCO GND_CP
VS_PLL
supply voltage
VS_IF
VS_MIXER
GND_PLL
VS_REG VS_PLL REG_CTRL
VREG
Auxiliary voltage-regulator output
VREG
REG_CTRL
Auxiliary voltage-regulator control output
VS_REG
Auxiliary voltage-regulator supply voltage
GND_PLL
GND_CP VS_CP
Charge-pump ground Charge-pump supply voltage Charge-pump output
VS_CP VS_PLL GND_PLL GND_CP
T2803
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T2803
Description (Continued)
Symbol Function Configuration
VS_VCO VS_PLL VREG_VCO GND_PLL
VS_VCO VREG_VCO GND_VCO
voltage-regulator supply voltage voltage-regulator control output ground
GND_VCO
VREG_VCO VS_PLL
VTUNE
tuning voltage input
VTUNE GND_PLL GND_VCO
VS_PLL VS_REG VS_CP VS_VCO
GND1 GND2 GND3 GND_VCO GND_CP
GND1
Ground
VS_IF
VS_MIXER
GND_PLL
4572D-DECT-07/03
Description (Continued)
Symbol Function Configuration
VS_MIXER
VS_IF DEMOD TANK2
DEMOD_TANK1
Demodulator tank circuit
DEMOD TANK1
DEMOD_TANK2
Demodulator tank circuit
GND2 GND1
VREG_VCO VS_PLL DAC_DEC
DAC_DEC
Decoupling
GND_PLL GND_VCO
VREG_VCO VS_IF
REG_DEC
Decoupling VCO_REG
REG_DEC GND2 GND_VCO
VS_IF
BB_CF
Baseband filter corner-frequency control input
BB_CF GND2 GND1
T2803
4572D-DECT-07/03
T2803
Description (Continued)
Symbol Function Configuration
VS_IF
BB_OUT
Baseband filter output
BB_OUT GND2 VS_IF
GND1
RSSI
Received signal strength indicator output
RSSI
GND2
VS_IF
IF_TANK1
tank circuit
IF_TANK1 IF_TANK2
IF_TANK2
tank circuit
GND2
VS_PLL VS_REG VS_CP VS_VCO
GND1 GND2 GND3 GND_VCO GND_CP
GND2
Ground
VS_IF
VS_MIXER
GND_PLL
4572D-DECT-07/03
Description (Continued)
Symbol Function
VS_MIXER
Configuration
RF_IN1
input image reject mixer
RF_IN1 RF_IN2
RF_IN2
input image reject mixer
GND2
VS_PLL VS_REG VS_CP VS_VCO
GND1 GND2 GND3 GND_VCO GND_CP
GND3
Ground
VS_IF
VS_MIXER
GND_PLL
TX_OUT
TX_OUT
driver amplifier output
GND3
T2803
4572D-DECT-07/03
T2803
Description (Continued)
Symbol Function Configuration
VS_PLL VS_REG VS_CP VS_VCO
GND1 GND2 GND3 GND_VCO GND_CP
VS_IF
amplifier supply voltage
VS_IF
VS_MIXER
GND_PLL
VS_IF
IF_IN1
input amplifier
IF_IN1
IF_IN2
IF_IN2
input amplifier
GND2
VS_MIXER VS_IF
RAMP_OUT
Ramp-generator output power ramping
RAMP_OUT
GND2
4572D-DECT-07/03
Description (Continued)
Symbol Function Configuration
VS_MIXER VS_IF RAMP
RAMP_SET
Slew-rate setting ramping signal
GND2
VS_IF
RX_ON
control input
RX_ON TX_ON
TX_ON
control input
GND2 GND1
VS_MIXER
VS_IF
MIXER_OUT1
Mixer output filter
MIXER_ OUT1
MIXER_ OUT2
MIXER_OUT2
Mixer output filter
GND2
T2803
4572D-DECT-07/03
T2803
Description (Continued)
Symbol Function
VS_PLL
Configuration
VS_REG VS_CP
GND1
GND2
VS_MIXER
Mixer supply voltage
VS_VCO
GND3
GND_PLL
ground
VS_IF
GND_VCO GND_CP
VS_MIXER
VS_PLL
GND_PLL
Open loop enable input
GND_PLL
PU_RX/TX
PU_RX/TX
RX/TX power-up input
GND18
4572D-DECT-07/03
Description (Continued)
Symbol Function Configuration
140k
PU_PLL
power-up input
VS_PLL
VS_PLL
TX_DATA
data input Gaussian filter
TX_DATA
2.5k
GND_PLL
VS_PLL
I_CPSW
Charge-pump current control input
I_CPSW
GND_PLL
T2803
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T2803
Functional Description
Receiver
signal RF_IN image rejection mixer IR_MIXER with differential outputs MIXER_OUT1 MIXER_OUT2 driving IF-SAW filter 110.592 112.32 MHz. IF_AMP1 IF_AMP2 amplifiers with external IF_TANK integrated RSSI function feed signal demodulator DEMOD working MHz) finally integrated baseband filter demodulator tunning production integrated 5-bit digital-to-analog (D/A) converter provided control on-chip varicap diode. transmit data TX_DATA filtered integrated Gaussian Filter fully integrated operating twice output frequency. After modulation signal frequency-divided TX/RX SWITCH TX_DRIVER. This bus-controlled driver amplifier supplies typically output power TX_OUT. ramp-signal generator RAMP_GEN, providing ramp signal RAMP_OUT external power amplifier, integrated. slope ramp signal controlled capacitor RAMP_SET pin. IR_MIXER, TX_DRIVER programmable counter driven fully integrated (including on-chip inductors varactors). output signal frequencydivided supply desired frequency TX_DRIVER, 0/90 degree phase shifter IR_MIXER used phase detector (fPD 1.728 MHz). Open loop modulation supported. integrated bandgap-stabilized voltage regulator with external low-cost transistor implemented. Multiple power-down current saving modes provided.
Transmitter
Synthesizer
Power Supply
4572D-DECT-07/03
Figure Principle
RF_IN
Programable counter Main counter Swallow counter fVCO (SMC SSC) fVCO ext. loop filter Phase frequency detector 1.728 driver Charge pump Divider Mixer GF_DATA
Gaussian filter
Reference counter REF_CLK 10.368 13.824
6.912
0.576 Mbit/s
reference Frequency REF_CLK Baseband controller
TX_DATA
T2803
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T2803
following table shows frequencies DECT band plus additional channels extended DECT band. Intermediate frequencies 110.592 112.32 supported. Table Frequencies
Mode fIF/MHz Channel 110.592 (for 10.368 REF_CLK recommended) 112.320 (for 13.824 REF_CLK recommended) fANT/MHz 2401.056 2401.920 2481.408 2482.272 2401.056 2401.920 2481.408 2482.272 2401.056 2401.920 2481.408 2482.272 fVCO/MHz 2401.056 2401.920 2481.408 2482.272 2290.646 2291.328 2370.816 2371.680 2288.736 2289.600 2369.088 2369.952 2779 2780 2872 2873 2651 2652 2744 2745 2649 2650 2742 2743
Formula fANT fVCO SSC) fANT SSC)
Control Signals
Table Control Signals Functions
Signal I_CPSW PU_REG PU_RX/TX PU_PLL RX_ON TX_ON Data Word Functions Charge pump current control Activates voltage regulator supplying complete transceiver Activates RX/TX blocks Activates circuits: Activates circuits: BBF, DEMOD, AMP, MIXER Activates circuits: TX-DRIVER, RAMP GEN, Starts RAMP SIGNAL RAMP Activates open loop mode Activates
4572D-DECT-07/03
Table Control Signals Modes
Modes PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON filter Demodulator amplifiers RSSI mixer switch switch driver Ramp generator Programmable counter Voltage-controlled oscillator Gaussian filter Phase detector/charge pump Reference counter Typical current consumption Mode Mode RSSI Only
Serial Programming
transceiver programmed 3-wire (CLOCK, DATA ENABLE). After setting enable signal condition, rising edge clock signal, data transferred into shift register, starting with MSB-bit. When enable signal returned high condition, programmed information loaded into addressed latches according address condition (last bit). Additional leading bits ignored there check made many pulses arrived during enable condition. During enable condition, current increased speed logic. programming transceiver separated into data words. Data word controls mainly channel information together with settings, which closely related with channel. Data word holds setup information, which adjusted during production.
T2803
4572D-DECT-07/03
T2803
Data Word
Data bits Address GFCS
CPCS
care
Data Word
TEST DEMODDAC/RAMPDAC
care
Data Word Programs
Settings
With Reference Counter bits
(Reference Counter) REF_CLK 10.368 13.824
With Main Counter bits
(Main Counter)
With Swallow Counter bits
(Swallow Counter)
4572D-DECT-07/03
Selection
With
Selection Mode
Gaussian Filter On/off
With used only mode.
(Gaussian Filter)
GFCS Adjustment
With bits Only mode effective setting frequency deviation modulation.
GFCS (Gaussian Filter Settings) GFCS 100% 110% 120% 130%
CPCS Adjustment
With bits Used adjust charge pump current. This used compensate change tuning sensitivity over frequency device tolerances.
CPCS (Charge-Pump Current Settings) CPCS
T2803
4572D-DECT-07/03
T2803
Data Word Programs
DEMODDAC Adjustment
With bits Only mode effective. Used tune demodulator center frequency allows compensate tolerances external components T2803.
Demod Voltage fIFcenter
RAMPDAC Adjustment Mode
With bits Only mode effective. Used control power external adjusting ramping voltage.
RAMPDAC Voltage RAMP_OUT) VRAMP_OUT 1.68
TEST Mode Settings
With bits normal operation Lock detect output used. other settings test only.
Signal Lock Detect Output Lock detect out/2 out/2 care Lock detect out/2 out/2 GFTEST: Mode Active Active Active Active Active Active Active Active
4572D-DECT-07/03
Output Power Settings
With bits maximum power dBm) external recommended.
(Output Power Settings)
Figure 3-wire Protocol Timing Diagram
DATA CLOCK ENABLE TPER
16525
Table 3-wire Protocol Table
Description Clock period time data clock Hold time data clock Clock pulse width time enable clock Hold time enable data Time between protocols Symbol TPER Minimum Value Unit
Figure DATA Timing
RefCLK
TX_DATA
Set-up time DATA Hold time DATA
When using REFCLK 10.368 MHz, must considered falling rising edge REFCLK
T2803
4572D-DECT-07/03
T2803
Absolute Maximum Ratings
voltages refer
Parameters Supply voltage regulator Supply voltage Logic input voltage Junction temperature Storage temperature Pins Pins Symbol VS_REG Tjmax Tstg Min. Max. Unit
Thermal Resistance
Parameters Junction ambient Symbol
RthJA
Value
Unit
Operating Range
Parameters Supply voltage regulator Supply voltage Supply voltage charge pump Ambient temperature Pins Symbol VS_REG VSCP Tamb Min. Typ. Max. Unit
Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG Tamb 25°C
Parameters mixer (Pins Input impedance Image rejection ratio noise figure Conversion gain Input intercept point Output impedance amplifier (Pins Input impedance Lower cut-off frequency Upper cut-off frequency Power gain Bandwidth external tank circuit Noise figure Pins Pins (differential) fl3dB fu3dB BW3dB 1200 j480 Pins (single ended) Pins Pins (single ended) Rload Pins (single ended) (differential) NFDSB= NFSSB Gconv IIP3 ZOUT j145 Test Conditions/Pins Symbol Min. Typ. Max. Unit
4572D-DECT-07/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG Tamb 25°C
Parameters RSSI (Pins RSSI sensitivity RSSI compression RSSI dynamic range RSSI resolution RSSI rise time RSSI fall time Quiescent output voltage Maximum output voltage Slope RSSI steady dBµV, dBµV, dBµV IF_IN1, IF_IN2, dBµV IF_IN1, IF_IN2, IR-mixer input Quality factor external tank circuit approximately fres FIF/2, Nominal deviation signal kHz, (see protocol E10) IF_IN1,2; Pins IF_IN1,2; Pins Pmin Pmax Vout Vout dBµV dBµV Test Conditions/Pins Symbol Min. Typ. Max. Unit
demodulator, BB-filter (Pins Co-channel rejection ratio Sensitivity CCRR V/MHz
Amplitude recovered signal Corner frequency Output voltage range DEMOD_DAC range VCOs Frequency range Tuning gain Frequency control voltage range Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter External reference input frequency External reference input voltage Scaling factor reference counter Charge pump (Pin Output current Output current Current scaling Leakage current
VoutDC DfIFcenter fvco fvco Gtune Vtune SPSC 2289 2289
VS-1 2483 2483 32/33 10.368 13.824
mVpp MHz/V
coupled sinewave, coupled sinewave,
fREF_CLK VREF_CLK
mVRMS
VVS_CP/2, I_CPSW `1', VVS_CP/2, I_CPSW `0', ICP_nom CPCS ICP_step (see protocol
ICP_nom ICP_nom ICP_step
±7.5 ±1.2 ±100
T2803
4572D-DECT-07/03
T2803
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG Tamb 25°C
Parameters data filter clock Frequency deviation Frequency deviation scaling driver (Pin Maximum output power Minimum output power leakage Output impedance Ramp generator (Pins Minimum output voltage Maximum output voltage Rise time Fall time Lock detect output, test mode output Leakage current Saturation voltage Output voltage regulator (Pins Output voltage 3-wire Clock fClock 6.912 Logic input levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, OLE, TX_DATA, DATA_HOLD) (Pins High input level input level High input current input current VSVCO VREG_VCO (see protocol E10) Cramp Cramp locked `1', unlocked test modes (see protocol VSREG Vmin Vmax GFFM GFFM_nom GFCS (see protocol (see protocol E12) (see protocol E12) mode GHz, Test Conditions/Pins taps filter Symbol fTXFCLK GFFM_nom GFCS Min. Typ. 6.912 ±400 Max. Unit Gaussian transmit filter (Gaussian shape 0.5)
Pleak ZOUT
13+j40
Lock detect test mode output (Pin VREG
Auxiliary regulator (Pins
4572D-DECT-07/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG Tamb 25°C
Parameters Standby control (Pins Power PU_REG PU_RX/TX PU_PLL High input level Standby PU_REG PU_RX/TX PU_PLL input level Power PU_REG PU_RX/TX PU_PLL High input current Standby PU_xxxx input current Settling time active operation Settling time standby active operation Settling time active operation standby Total supply current VPU_REG VPU_RX/TX VPU_PLL Test Conditions/Pins Symbol Min. Typ. Max. Unit
VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF
Pins Switched from Switched from Switched from standby RSSI only active)
IPU_REG IPU_RX/TX IPU_PLL
IPU,OFF
tsoa tssa tsas
Power supply (Pins
Standby current Supply current
PU_RX/TX VVS_CP lock condition,
T2803
4572D-DECT-07/03
T2803
Figure Typical Application Circuit
RAMP_OUT TX_OUT
RF_IN
Filter 112B
GND3 RF_IN2 RF_IN1 VS_IF GND2 RSSI
RSSI
IF_IN2
IF_IN1
RAMP_OUT
TX_OUT
RAMP_SET RX_ON TX_ON RX_ON TX_ON
IF_TANK2
IF_TANK1
BB_OUT BB_CF REG_DEC DAC_DEC
BB_OUT
MIXER_OUT1 MIXER_OUT2 VS_MIXER GND_PLL PU_RX/TX PU_PLL TX_DATA
I_CPSW
T2803
DEMOD_TANK2 DEMOD_TANK1 GND1 VTUNE GND_VCO VREG_VCO
PU_RX/TX PU_PLL
REF_CLOCK
TX_DATA
ENABLE
VS_VCO
REG_CTRL GND_CP PU_REG VS_REG VS_PLL VS_CP
I_CPSW
CLOCK DATA
VREG
CLOCK DATA ENABLE REF_CLK
PU_REG
BC808
similar
tantal
tantal
4572D-DECT-07/03
Ordering Information
Extended Type Number T2803-PLH Package QFN48 Remarks Taped reeled
Package Information
T2803
4572D-DECT-07/03
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4572D-DECT-07/03
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