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MARS1G2 T-LT (TSOT021G2) SONET/SDH 155/622 Mbits/s Overhead Path Processor
next generation system chip devices Agere Systems' multiapplication rate solutions MARSfamily framers. Transmission convergence SONET/SDH terminal/ADM functionality linear ring networks. Versatile supports 155/622 Mbits/s SONET/ overhead path processor solutions. Low-power 1.6/3.3 operation.
T1.105: SONET-Basic Description including Multiplex Structure, Rates, Formats. T1.105.02 SONET-Payload Mappings. T1.105.03 SONET-Jitter Network Interfaces. T1.105.06 SONET Physical Layer Specifications. T1.105.07 SONET-Sub-STS-1 Interface Rates Formats Specification. ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification. IETF 2615: over SONET/SDH. IETF 1661: Point-to-Point Protocol (PPP). IETF 1662: HDLC-like Framing.
SONET/SDH Interface
Interface
Termination quad STS-3/STM-1 dual STS-12/ STM-4. Supports overhead processing transport path overhead bytes. Optional insertion extraction overhead bytes serial overhead interface. pointer processing align receive frame system frame. STS-1 granularity cross connect between receive, mate, STM, data payloads. Support linear networks; UPSR BLSR ring networks. Full path termination extraction/insertion. SONET/SDH compliant condition alarm reporting. Handles concatenation levels STS-3c STS-24c multiples e.g., etc.). Built-in diagnostic loopback modes. Compliant with following Telcordia Technologies®, ANSI®, standards: GR-253 CORE: SONET Transport Systems: Common Generic Criteria. ITU-T G.707: Network Node Interface Synchronous Digital Hierarchy. ITU-T G.803: Architecture Transport Networks Based Synchronous Digital Hierarchy.
Built-in redundant STS/Sbackplane interface using LVDS technology. Mate-to-mate backplane interface using LVDS technology 1:1, BLSR, UPSR network support. Optional (32-bit) STS/Sinterface. IEEE® 1149.1 port with BIST, scan, boundry scan.
Microprocessor Interface
synchronous. 16-bit address 16-bit data interface. Synchronous asynchronous modes available. Configurable operate with most commercial microprocessors.
MARS1G2 T-LT (TSOT021G2) SONET/SDH 155/622 Mbits/s Overhead Path Processor
Description
MARS1G2 T-LT SONET/SDH overhead path processor provides versatile solution quad OC-3 dual OC-12, linear ring datacom/telecom applications. Constructed using COM2 CMOS modular process, this device incorporates integrated SONET/SDH section/line/path termination, pointer processing, cross connect blocks. Communication with MARS1G2 T-LT device accomplished through generic microprocessor interface. device supports separate address data buses. With this device, support different types applications OC-3/OC-12 data equipment possible, enabling dramatic system cost reduction ease development extremely competitive solutions. interface rates supported dual STS-12/STM-4 quad STS-3/STM-1. concatenation levels supported this device STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, STS-21c, STS-24c.
MATE INTERFACE
LINE INTERFACE
SWITCHING PATH SWITCH OVERHEAD PROCESSOR INSERT INTERFACE BLOCK SINTERFACE* DUAL SBACKPLANE INTERFACE
DUAL STM-4/STS-12 QUAD STM-1/STS-3
STMLSI LINE SWITCH POINTER PROCESSOR
TXCLK
TRANSPORT OVERHEAD TERMINATION
DUAL STM-4/STS-12 QUAD STM-1/STS-3
CONNECTION MEMORY
(PTR INTER)
OVERHEAD PROCESSOR MONITOR
CONTROL
MISCELLANEOUS
TXTOAC RXTOAC TOAC INTERFACE
INTERFACE
GPIO/STMDCC
Note: path terminator. Slow-speed interface (STMLSI) available.
Figure MARS1G2 T-LT Block Diagram
Agere Systems Inc.
MARS1G2 T-LT (TSOT021G2) SONET/SDH 155/622 Mbits/s Overhead Path Processor
Target Applications Supported
MARS1G2 T-LT (792-Pin PBGA)
This SONET/SDH add/drop multiplexer device targets following applications. Figure device interface speed/rate information:
PON. Access/core router.
MATE INTERFACE Mbits/s Mbits/s LVDS)
LINE INTERFACE
SWITCHING SINTERFACE*
INTERFACE BLOCK
DUAL Mbits/s LVPECL) QUAD Mbits/s LVPECL) TXCLK
PATH SWITCH OVERHEAD PROCESSOR INSERT
DUAL SBACKPLANE INTERFACE (DUAL Mbits/s Mbits/s LVDS)
STMLSI LINE SWITCH POINTER PROCESSOR
TRANSPORT OVERHEAD TERMINATION
DUAL Mbits/s LVPECL) QUAD Mbits/s LVPECL)
CONNECTION MEMORY
(PTR INTER)
OVERHEAD PROCESSOR MONITOR
CONTROL
MISCELLANEOUS
TXTOAC RXTOAC
INTERFACE
GPIO/STMDCC
Slow-speed interface (STMLSI) available.
Figure MARS1G2 T-LT Device Interface Speed/Rate Diagram
Agere Systems Inc.
Telcordia Technologies trademark Telcordia Technologies, Inc. ANSI registered trademark American National Standards Institute, Inc. IEEE registered trademark Institute Electrical Electronics Engineers, Inc.
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway Allentown, 18109-9138 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Agere, Agere Systems, Agere logo trademarks Agere Systems Inc. MARS trademark Agere Systems Inc.
Copyright 2003 Agere Systems Inc. Rights Reserved
April 2003 PB03-088SONT

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