Agere Systems PayloadPlus® Network Processor chip provides wire-speed

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Agere Systems PayloadPlus® Network Processor chip provides wire-speed

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Network Processor Chip (APP750NP APP750TM)
Agere Systems PayloadPlus® Network Processor chip provides wire-speed deeppacket processing high performance packetprocessing systems. This software-compatible, programmable chip consists chips- APP750NP classification engine (NP10) APP750traffic manager (TM10)-and follows successful Agere Systems 2.5G PayloadPlus chip set. This chip provides full carrier-class packet processing functionality, including classification, policing, statistics, queueing, scheduling, shaping, buffer management packet/cell modification. three-chip configuration-one NP10 TM10s- provides full duplex Gb/s packet processing functionality. additional NP10 added egress classification required. PayloadPlus solution requires only DRAM small amount SRAM external memory provide high-performance functionality. content addressable memory (CAM) required. chip supports complex packet classification policies, including multifield IPv4/ IPv6 classification, PPPoE, L2TP, MPLS, etc., with large amount headroom future classification needs. OEMs Agere Systems high-level Functional Programming Language (FPL) specify packet classification policies. Statistics, policing, packet modification functions performed on-chip compute engines that programmed using C-like Agere Scripting Language (ASL).
SPI4
SPI4
SERDES 10x2.5GSERDES Switch
NP10
Framer
TM10
SERDES SPI4
Fabric
SPI4
SPI4
TM10
SPI4
NP10
(optional)
SERDES SERDES
PORT CARD
Fabric Backpressure Host
32/64 33/66
Host
SPI4 POS-PHY Level interface SERDES high-speed serial interface
Network Processor System Diagram
Product Brief November 2002 Features
NP10 Network Processors
External scheduling port allow OEMs support proprietary switch fabric implementations (for example, credit-based flow control, global scheduling) and/or proprietary packet scheduling implementations.
Full line-rate performance with packet sizes greater than equal bytes long Supports complex multifield packet classification with large amount headroom future classification needs. Supports wire-speed access control list (ACL) processing, even with thousands rules.
Programmable packet modification, including support for: Adding/removing software-defined headers trailers Modifying data anywhere packet Forward congestion marking
Multiprotocol customer-programmable classification: POS, MPLS, IPv4/v6, ATM, Frame Relay, Ethernet, VLANs, access control lists, link aggregation, etc. OEMs easily supplement protocols standards they support with simple software upgrades. DRAM-based classification rule memory supports over million IPv4 routes with separate information each VPN. CAMs required. Uses high-level network processor programming languages-Functional Programming Language (FPL) Agere Scripting Language (ASL)-preserving investments classification, policing, statistics, packet modification programming. provides order magnitude reduction (compared C/C++) number lines code required specify packet classification policies. eliminates need complex hand-optimization assembly microcode achieve wire-speed performance. Programmable per-flow statistics policing allows OEMs implement highly differentiated admission control billing policies. Full carrier-class traffic management functionality help maximize amount premium traffic that reliably served, with support for: Hierarchical weighted fair queuing (WFQ) with excellent bandwidth delay guarantees VPNs with traffic isolation service-level agreements (SLAs) Dynamic bandwidth QoS/CoS modification enable real-time dynamic service provisioning million packet handling behavior types with buffer management profiles behavior type allow finegrained service differentiation Random early detection (RED) weighted (WRED) external packet buffer memory direction
Wire-speed fragmentation Full multicast support with ability individually schedule modify each packet/cell copy Port based rate shaping media ports Configurations include OC192c, 4xOC48c, 1G/10G Ethernet, 192xDS3, etc. compliant host interface allow easy interfacing variety host microprocessors other support logic Both cell- frame-based fabrics supported with programmable OEMs readily interface wide variety switch fabrics with minimal glue logic effort. Support simple interface third-party fabrics using off-the-shelf FPGAs Complete Agere Systems fiber-to-fabric line card reference design with supporting software FPGA-based hardware emulation system software simulator provides complete pre-silicon hardware software development support.
Applications
Target applications include multiprotocol core edge switches routers, multiservice optical core edge devices service-aware switches provisioning platforms.
NP10 Network Processors
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18109-3286 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-2588-1122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, (44) 1344
Agere Systems, Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. PayloadPlus trademark Agere Systems, Inc. PayloadPlus registered trademark Agere Systems Inc.
Copyright 2001 Agere Systems, Inc. Rights Reserved Printed U.S.A.
November 2002 PB01-137NP-2; replaces PB01-137NP

Agere Systems PayloadPlus® Network Processor chip provides wire-speed

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