IR1175 Synchronous Rectifier Driver Provides constant proper

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IR1175 Synchronous Rectifier Driver Provides constant proper

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Preliminary Data Sheet 60178-D
IR1175
Synchronous Rectifier Driver
Provides constant proper gate drive power MOSFETs regardless transformer output Minimizes loss power MOSFET body drain diode conduction Stand alone operation ties primary side Schmitt trigger input with double pulse suppression allows operation noisy environments High peak current drive capability High speed operation 2MHz Adaptable multiple topologies (such singleended forward, double-ended forward)
Product Summary
IO+/- (peak) Fmax lead time 5Vdc 2A/2A 2MHz 500nsec
Description
IR1175 high speed CMOS controller designed drive N-channel power MOSFETs used synchronous rectifiers high current, high frequency forward converters with output voltages equal below 5VDC. Schmitt trigger inputs with double pulse suppression allow controller operate noisy environments. circuit does require ties primary side derives operating power directly from secondary. circuit functions anticipating transformer output transitions, then turns power MOSFETs before transitions transformer minimize body drain diode conduction reduce associated losses. Turn on/off lead time adjusted accommodate variety power MOSFET sizes circuit conditions. IR1175 also provides gate drive overlap/dead-time control external components further minimize diode conduction nulling effects secondary loop device package inductance.
Packages
IR1175S
Lead Surface Mount (SSOP-20)
IR1175SS
Lead SOIC (MS-013AC)
IR1175
Lead PDIP (MS-001AD)
IR1175
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage device occur.
Symbol
RthJC RthJA
Definition
Supply voltage Input clamp current Power dissipation (SSOP-20) Thermal resistance (SSOP-20) junction-to-case Thermal resistance (SSOP-20) junction-to-ambient Junction temperature Storage temperature Lead temperature (soldering, seconds)
Min.
Max.
28.5 90.5
Units
°C/W °C/W
Recommended Operating Conditions
Symbol
Freq Rbias Cd1/Cd2
Definition
Supply voltage operating range Ambient temperature Operating frequency Required bias resistor (+/- Voltage UVSET Maximum voltage inputs Capacitance pins DTIN1 DTIN2
Min.
1.75
Typ.
69.8
Max.
2.25
Units
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IR1175
Dynamic Electrical Characteristics
Vdd=5V, Rbias 69.8K unless otherwise specified.
Symbol
Iqdd Freq UVSET+ UVSETVxth+ VxthTadv Isink (peak) Isource (peak)
Definition
Supply voltage operating range quiescent current (Vin=0 Iout=0) Operating frequency UVSET positive going threshold UVSET negative going threshold X1/X2 Input positive going threshold X1/X2 Input negative going threshold Externally adjustable lead time (advance) Externally adjustable dead-time Q1,Q2 output sink current (Vdd=5.0V, pulsed, usec) Q1,Q2 output source current (Vdd=5.0V, pulsed, usec) High level voltage (Iout 20mA) level voltage (Iout 20mA) Input output delay (PLL bypassed, cross coupled mode)
Min.
1.10
Typ.
Max.
2000
Units
nsec nsec
4.50 1.15
nsec
Gate turn-on rise time (C1=1000pf, Vdd=5V) Gate turn-off fall time (C1=1000pf, Vdd=5V) Cross-over voltage (Vdd=5Vdc, DTIN shorted DTOUT, C1=1000pf) Fig.
nsec nsec nsec KHz/ Volt
Rbias Vbias Tjitter Ichgpump Vchgpump Kvco_dc
Required bias resistor Voltage Rbias Phase-lock loop output jitter Charge pump output current VFLTR pin) Charge pump output voltage VFLTR pin) gain
1.25
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IR1175
Lead Definitions Assignments
Symbol Description
AVDD DTIN1 RADV1 VFLTR1 RVCO1 UVSET RBIAS AVSS RVCO2 VFLTR2 RADV2 DTIN2 Power MOSFET drivers Output gate drive power MOSFET Input sets dead time used with DTOUT1 Output sets lead time (advance) Output loop filter output Output sets center frequency output Input transformer input Power internal logic Input sets UVLO+ this pulled below 1.25VDC externally, then both outputs will (disabled) Output connected 69.8K resistor sets operating current Ground logic supply (AVDD) Input transformer input Output sets center frequency output Output loop filter Output sets lead time (advance) Input sets dead time used with DTOUT2 Ground MOSFET driver supply (VDD) Output gate drive power MOSFET
DTOUT1 Output sets dead time output used with DTIN1
DTOUT2 Output sets dead time used with DTIN2
*VDD DTOUT2 DTIN2 RADV1 VFLTRI RVCO1 AVDD UVSET
DTOUT1 DTIN1 RADV2 VFLTR2 RVCO2 AVSS RBIAS
*VDD DTOUT2 DTIN2 RADV1 VFLTRI RVCO1 AVDD UVSET
DTOUT1 DTIN1 RADV2 VFLTR2 RVCO2 AVSS RBIAS
*VDD DTOUT2 DTIN2 RADV1 VFLTRI RVCO1 AVDD UVSET
DTOUT1 DTIN1 RADV2 VFLTR2 RVCO2 AVSS RBIAS
IR1175S
(SSOP-20)
IR1175SS
SOIC (wide body)
IR1175
PDIP www.irf.com
IR1175
Fig. Typical application circuit when supply Vout
Fig. Typical application circuit when supply Vout www.irf.com
IR1175
Fig. Gate drive characteristics definitions
Phase Lock Loop Design Equations:
Resistor Ceter Frequency: Rvco [Vchgpump(VDC) fvco(KHz)] Kvco dc(KHz/Volt) Example (A): Choose Vchgpump 1.5V, desired frequency (fvco) 300KHz Rvco [1.5 /300] Hz/Volt 44.33 Small Signal gain VCO: Kvco_ac (KHz/Volt) Kvco_dc (KHz/Volt)/(7 Rvco(K) Example (B): Choosing same conditions example Kvco_ac 44.33) 199.9 KHz/volt
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IR1175
-PLL rqec:
=2fn(KHz)= Ichpump(uA) Kvco_ac(KHz/V) C(nF)
Choose Cf=C/16 -PLL Dampi
(KOhms) C(nF) fn(KHz)
Typi mped) Ciial -Advance
Tadv(nsec) RADV (KOhms)*10
here RADV RADV1 orRADV2 ground. eitne Exampl C:RADV=10Kohms wilr Tadv=10*10-10 nsec esul 6-Dead cltos
(For Vdd=5
here resistance between pins DTIN1 DTOUT1 DTIN2 DTOUT2.Cdti ground. aaiac Exampl D:Rdt=10Kohm Cdt=22pF wilr Td=156.8 nsec esul
Fig. loop filter component definitions
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IR1175
Fig. IR1175 Block Diagram www.irf.com
IR1175
Case Outline
Lead Surface Mount (SSOP-20)
01-6057 01-3078 (MS013AC)
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IR1175
Case Outline
Lead SOIC
01-6070 01-3080 (MS013AC)
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IR1175
Case Outline
Lead PDIP
01-6069 01-3079 (MS001AD)
WORLD HEADQUARTERS: Kansas St., Segundo, California 90245 Tel: (310) 252-7105 Data specifications subject change without notice. 1/7/2002
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IR1175 Synchronous Rectifier Driver Provides constant proper

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