Ultra Power 10/100 Ethernet Transceiver with Auto_MDIX DESCRIPTIO

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Ultra Power 10/100 Ethernet Transceiver with Auto_MDIX DESCRIPTIO

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AC101L
Ultra Power 10/100 Ethernet Transceiver with Auto_MDIX
DESCRIPTION AC101L single channel, power, 10/100BASE-TX/FX Transceiver. AC101L integrated voltage regulator allow operation from single 3.3V 2.5V supply source. device contains full-duplex 10BASE-T/100BASE-TX/100BASE-FX Fast Ethernet transceiver, which performs physical layer interface functions. AC101L highly integrated solution combining encoder/decoder, link monitor, auto-negotiation selection, parallel detection, adaptive equalization, clock/ data recovery, base line wander correction, multi mode transmitter, scrambler/descrambler, Fault (FEF), auto MDI/MDIX circuitry. fully compliant with IEEE802.3 802.3u standards. 3.3V tolerant 2.5V capable Integrated voltage regulator allow operation from single 3.3V 2.5V supply source 10/100 TX/FX Full-Duplex Half-Duplex FEFI 100FX 48-pin TQFP Industrial Temp (-40°C +85°C) CMOS Fully compliant with IEEE 802.3 802.3u MII/RMII Interface Baseline Wander Compensation Multi-Function outputs Cable length indicator auto-MDI/MDIX Eight programmable interrupts Diagnostic registers
100RX
RXN/RXP
Data Interface Interface
Framer Carrier 4B/5B
Clock Recov. Link Monitor Signal Detect 25Mhz
TP_PMD MLT3 Stream Cipher
100TX
TXN/TXP
10RX
10BASE-T
10TX
Serial Interface Serial Management Interface Register
Control Status
Gen. Test/LED Control
25Mhz
Auto Negotiation
PHYAD[4:0]
XTLI/CLKIN
Drivers
Figure AC101L Functional Block Diagram
AC101L-DS01-RDC 16215 Alton Parkway P.O. 57013 Irvine, 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710 02/20/02
REVISION HISTORY
Revision AC101L-DS00-R AC101L-DS01-R Date 01/02/02 02/20/02 Change Description Initial release. Second release. Updated figure figure
Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, 92619-7013 Copyright 2002 Broadcom Corporation rights reserved Printed U.S.A.
Broadcom® pulse logo® registered trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
Preliminary Data Sheet
02/20/02
AC101L
TABLE CONTENTS
Section Functional Description.
Encoder/Decoder Link Monitor. Carrier Sense (CRS)/RXDV Collision Detection. Auto-Negotiation Parallel Detection Analog Adaptive Equalizer Clock Recovery Baseline Wander Correction Multi Mode Transmitter. Stream Cipher Scrambler/Descrambler (Far Fault) Transmit Driver. HP-Auto MDI/MDIX Interface RMII SMI. Physical Layer Interfaces
Section Descriptions Section Diagram. Section Operational Description
Reset Power Source Power Saving Mode Clock Source Isolate Mode Loop Back Mode Interrupt Mode Operation
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AC101L
Preliminary Data Sheet
02/20/02
Interface.12 Configuration Section [3:0] Event Table
Section Register Description
Register Summary Register Control Register Register Status Register Register Identifier Register Register Identifier Register Register Auto-Negotiation Advertisement Register Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Register Auto-Negotiation Expansion Register Register Auto-Negotiation Next Page Transmit Register Register Interrupt Level Control Register Register Interrupt Control/Status Register Register Diagnostic Register Register Power/Loopback Register Register Cable Measurement Capability Register Register Receive Error Counter Register Power Management Register Register Operation Mode Register Register Recent Received Packet Common Registers.24 Common Register (Map Reg. Mode Control Register Common Register (Map Reg. Page a28.[15:12]=0000) Test Mode Register Common Register (Map Reg. Page a28.[15:12]=0001) Blink Rate Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting1 Register Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting2 Register Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting1 Register Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting2 Register Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 Register Common Register (Map Reg. Page a.28.[15:12]=0011) LED2 Setting2 Register Common Register (Map Reg. Page a.28[.15:12]=0011) LED3 Setting1 Register Common Register (Map Reg. Page a.28.[15:12]=0011) LED3 Setting2 Register
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Page Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
Section 4B/5B Code-Group. Section Read/Write Sequence. Section Timing Characteristics
Clock Timing Reset Timing Management Data Interface Timing. 100BASE-TX/FX Transmit System Timing 100BASE-TX/FX Receive System Timing 10BASE-T Transmit System Timing 10BASE-T Receive System Timing RMII Transmit Timing RMII Receive Timing Copper Application Termination.
Section Electrical Characteristics.
Absolute Maximum Ratings Recommended Operating Conditions. Electrical Characteristics
Section Fiber Application Termination. Section Power Ground Filtering Section Mechanical Information. Section Thermal Specifications Section Ordering Information.
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AC101L
Preliminary Data Sheet
02/20/02
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Preliminary Data Sheet
02/20/02
AC101L
LIST FIGURES
Figure AC101L Functional Block Diagram Figure AC101L Pinout Diagram. Figure Reset Timing Figure Management Interface Timing. Figure 100BASE-T Transmit Timing. Figure 100BASE-T Receive Timing. Figure 10BASE-T Transmit Timing. Figure 10BASE-T Receive Timing. Figure RMII Transmit Timing Figure RMII Receive Timing Figure Application Figure Application Figure Power Ground Filtering Figure Quad Flat Pack Outline
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AC101L
Preliminary Data Sheet
02/20/02
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Page viii Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
LIST TABLES
Table Pinout Signal Definitions. Table [3:0] Event Table Table Register Summary. Table Register Control Register Table Register Status Register. Table Register Identifier Register. Table Register Identifier Register. Table Register Auto-Negotiation Advertisement Register Table Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Table Register Auto-Negotiation Expansion Register Table Register Auto-Negotiation Next Page Transmit Register Table Register Interrupt Level Control Register. Table Register Interrupt Control/Status Register. Table Register Diagnostic Register Table Register Power/Loopback Register Table Register Cable Measurement Capability Register. Table Register Receive Error Counter Table Register Power Management Register. Table Register Operation Mode Register Table Register Recent Received Packet. Table Common Register (Map Reg. Mode Control Register. Table Common Register (Map Reg. Page a28.[15:12]=0000) Test Mode Register. Table Common Register (Map Reg. Page a28.[15:12]=0001) Blink Rate. Table Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting1 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting2 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting1 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting2 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED2 Setting2 Register. Table Common Register (Map Reg. Page a.28[.15:12]=0011) LED3 Setting1 Register. Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED3 Setting2 Register. Table 4B/5B Code-Group Table
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AC101L
Preliminary Data Sheet
02/20/02
Table Read/Write Sequence Table Clock Timing Table Reset Timing Table Management Interface Timing Table 100BASE-X Transmit System Timing Table 100BASE-TX/FX Receive System Timing Table 10BASE-T Transmit System Timing Table 10BASE-T Receive System Timing Table RMII Transmit Timing.36 Table RMII Receive Timing.37 Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Electrical Characteristics.40 Table Thermal Parameters
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Page Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
AC101L single-chip, Fast Ethernet transceiver. performs physical layer interface functions 100BASE-TX full- half-duplex twisted-pair cable, 10BASE-T full- half-duplex cable. configure 100BASE-FX full- half-duplex transmission over fiber optic cable when pair with external fiber optic line driver receiver. chip performs 4B5B, MLT3, NRZI, Encoder/Decoder, Link monitor, auto-negotiation selection, adaptive equalization, clock/data recovery, base line wander correction, multi mode transmitter, scrambler/descrambler, Fault (FEF), auto-MDI/MDIX. connected switch controller through side, connects directly media other side through transformer Twisted Pair (TP) mode, fiber optic module mode. fully compliant with IEEE 802.3 803.3u standards.
ENCODER/DECODER
100BASE-TX 100BASE-FX modes, AC101L transmits receives data stream twisted pair fiber optic cable. When transmit enable asserted, nibble wide bit) data from transmit data pins encoded into 5-bit code groups inserted into transmit data stream. 4B5B encoding shown Section "4B/5B Code-Group" page transmit packet encapsulated replacing first nibbles preamble with start stream delimiter (J/K codes) appending stream delimiter (T/R codes) packet. When transmit error input asserted during packet, error code group sent place corresponding data code group. transmitter sends repeatedly idle code group between packets. 100BASE-TX mode, encode data stream scrambled stream cipher block then serialized encoded into MLT3 signal level. multi mode transmit (digital analog converter) used drive MLT3 data onto twisted pair cable. Following baseline wander correction, adaptive equalization clock/data recovery 100BASE-TX mode, receive data stream converted from MLT3 serial data. data descrambled stream cipher block then deserialized aligned into 5-bit code groups. 100BASE-FX mode, scrambling function bypassed data NRZII encoded. multi mode transmit drives differential Positive (PECL) levels external fiber optic transmitter. Baseline wander correction, adaptive equalization, stream cipher descrambling functions bypass NRZI decoding used instead MLT3. 5-bit code groups decoded into data nibbles. start stream delimiter replaced with preamble nibbles stream delimiter idle codes replaced with zeros. decoded data driven onto receive data pins. When invalid code group detected data stream, AC101L asserts RXER signal. 10BASE-T mode, Manchester encoding decoding performed data stream. multi mode transmit performs pre-equalization meters cable.
LINK MONITOR
100BASE-TX mode, receive signal energy detected monitoring receive pair transitions signal level. signal levels qualified using squelch detect circuits. When signal certain valid signal detected receive pair minimum period time, link monitor enter link pass state transmit receive functions enabled. 100BASE-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly signal (PIN 28). 10BASE-T mode, link pulse detection circuit constantly monitors RXP/RXN pins present valid link pulses.
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AC101L
Preliminary Data Sheet
02/20/02
CARRIER SENSE (CRS)/RXDV
Carrier sense asserted asynchronously pins soon activity detected receive data stream. RXDV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RXDV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. However, carrier sense asserted valid detected immediately, RXER asserted instead RXDV. 10BASE-T mode, asserted asynchronously when valid preamble data activity detected RXIP RXIN pins. half-duplex mode, activated during data transmit. full-duplex mode, activated during data receiving only.
COLLISION DETECTION
half-duplex mode, collision detect asserted whenever carrier sense asserted transmission progress.
AUTO-NEGOTIATION
Auto-negotiation selection 100BASE-Twisted pair only, operating 100BASE-Fiber PHY. 100BASE-TX mode, auto-negotiation enabled disabled hardware software control. When auto-negotiation function enable, 100BASE-TX automatically chooses mode operation advertising abilities comparing them with those received from it's link partner. 100BASE-TX configured advertise 100BASE-TX full-duplex 100BASE-TX half-duplex. default auto-negotiation mode configured reset read value ANEN/LED3 signal (pin SPD100/LED1.
0.13 0.12 4.8/1.14 4.7/1.13 4.6/1.12 4.5/1.11
Speed select ANEN Enable Duplex 100BASE-TX Full-Duplex 100BASE-TX 10BASE-T Full-Duplex 10BASE-T
default value SPD100 Enable Auto-negotiation. Disable Auto-negotiation. default value !ANEN DUPLEX default value this SPD100 DUPLEX default value SPD100 (ANEN !DUPLEX) default value this DUPLEX (ANEN !SPD100) default value ANEN (!SPD100 !DUPLEX)
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Preliminary Data Sheet
02/20/02
AC101L
PARALLEL DETECTION
Because there many devices field that support ANEN process, must still communicated with, necessary detect link through Parallel Detection process. parallel detection circuit enabled absence FLPs. circuit able detect: Normal Link Pulse (NLP) 10BASE-T receive data 100BASE-TX idle
mode operation gets configured based technology incoming signal. above detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10BASE-T 100BASE-TX systems, while maintaining flexibility auto-negotiation.
ANALOG ADAPTIVE EQUALIZER
analog adaptive equalizer removes Inter Symbol Interference (ISI) created transmission channel media. designed accommodate maximum meters cable. AT&T 1061 cable this length typically attenuation MHz. typical attenuation 100-meter cable worst case cable attenuation around 24-26 defined TP-PMD specification. amplitude phase distortion from cable causes which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability changes equalizer frequency response according cable length. equalizer will tune itself automatically cable, compensating amplitude phase distortion introduced cable.
CLOCK RECOVERY
equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal Phase Locked Loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. recovered clock also used generate RX_CLK signal. requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time, after power-on, less than transitions. maintain lock run-lengths data bits absence signal transitions. When valid data present, (i.e., when de-asserted) will switch lock TX_CLK. This provides continuously running RX_CLK. interface, 5-bit data RXD[4:0] synchronized RX_CLK.
BASELINE WANDER CORRECTION
100BASE-TX data stream always balanced because receive signal must pass through transformer, offset differential receive input wander. This effect, known baseline wander, greatly reduce noise immunity receiver. 100BASE-TX automatically compensates baseline wander removing offset from input signal, thereby significantly reduces chance receive symbol error. baseline wander circuit required 100BASE-FX PHY.
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AC101L
Preliminary Data Sheet
02/20/02
MULTI MODE TRANSMITTER
multi-mode transmitter transmits MLT3 coded symbols 100BASE-TX mode, NRZI coded symbols 100BASE-FX mode. utilizes current drive output, which well balanced produces very noise transmit signals. PECL voltage levels produced with resistive terminations 100BASE-FX mode. serialized data bypasses scrambler 4B/5B encoder mode. output data NRZI PECL signals. PECL level signals used drive Fiber-transmitter.
STREAM CIPHER SCRAMBLER/DESCRAMBLER
100BASE-TX mode, transmit data stream scramble reduce radiated emissions twisted pair cable. data scrambled exclusive ORing signal with output 11-bit wide Linear Feedback Shift Register (LFSR), which produces 2047 repeating sequence. scrambler reduces peak emission randomly spreading signal energy over transmit frequency range eliminating peaks certain frequencies. receiver descrambles incoming data stream exclusive ORing with same sequence generated transmitter. descrambler detect state transmit LFSR looking sequence representing consecutive idle codes. descrambler locks scrambler state after detecting sufficient number consecutive idle code group. receiver does attempt decode data stream unless de-scrambler locked. When locked, descrambler continuously monitor data stream make sure that lost synchronization. receive data stream expected contain inter-packet idle periods. descrambler does detect enough idle code within becomes unlocked receive decoder disable. descrambler always forced into unlock state when link failure condition detected. Stream cipher descrambler used 100BASE-FX mode.
(FAR FAULT)
Auto-negotiation provides mechanism inform link partner that remote fault occurred. However, autonegotiation disabled 100BASE-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive ones followed logic zero. This pattern repeated three times. FEFI will signal under three conditions: When activity received from link partner, When clock recovery circuit detects signal error lock error, When management entity sets transmit Far-End-Fault bit.
FEFI mechanism enabled default 100BASE-FX mode, disabled 100BASE-TX 10BASE-T modes. register setting changed software after reset.
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Preliminary Data Sheet
02/20/02
AC101L
TRANSMIT DRIVER
100BASE-TX mode, transmit function converts synchronous 4-bit data nibbles from pair Mbps differential serial data streams. serial data transmitted over network twisted-pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel serial, NRZI, MLT-3 encoding. entire operation synchronous clock. Both clocks generated on-chip clock synthesizer that locked external clock source. 100BASE-FX, transmit driver does perform filtering, utilizes current drive output that well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. 10BASE-T mode, interface used, Parallel Serial logic used convert 4-bit data into serial stream through output wave shaping driver. wave shaper reduces emission filtering harmonics, therefore eliminating need external filter.
HP-AUTO MDI/MDIX
This feature will able detect required cable connection type straight through crossed over make correction automatically.
INTERFACE
Media Independent Interface (MII) 18-wire MAC/PHY interface described 802.3u. purpose interface allow layer devices attach variety physical layer devices through common interface. operates either Mbps Mbps, dependent speed physical layer. With clocks running either MHz, 4-bit data clocked between PHY, synchronously with Enable Error signals. time lock incoming signal from wire interface, will generate RX_CLK either Mbps Mbps. receipt valid data from wire interface, RXDV goes active signaling that valid data will presented RXD[3:0] pins speed RX_CLK. transmission data from MAC, TXEN presented indicating presence valid data TXD[3:0]. TXD[3:0] sampled synchronous TX_CLK during time that TXEN valid.
RMII
Reduced Media Independent Interface (RMII) used connect with MAC. obtain their clock from common source, such clock oscillator. This clock shared ports within transmitting receiving data individual 2-bit data buses. RXDV muxed together indicate when there valid data receive bus. 100M mode RXD[1:0] sampled every cycle REFCLK. mode RXD[1:0] sampled every 10th cycle REFCLK. RXER generated indicate receive error MAC. TXEN generated indicate when there valid data transmit bus. 100M mode will read bits from TXD[1:0] each cycle REFCLK. mode will read bits data from TXD[1:0] every 10th cycle REFCLK.
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AC101L
Preliminary Data Sheet
02/20/02
PHYs internal registers accessible only through 2-wire Serial Management Interface (SMI). clock input PHY, which used latch data instructions PHY. clock speed from MHz. MDIO bidirectional connection used write instructions write data read data from PHY. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than that data presented synchronous MDC. MDC/MDIO common signal pair PHYs design. Therefore, each needs have unique physical address. physical address using pins defined PHYAD[4:0]. These input signals strapped externally sampled reset negated. idle, responsible pull MDIO line high state. Therefore, 1.5K Ohms resistor required connect MDIO line VCC.
PHYSICAL LAYER INTERFACES
Twisted Pair (TP) interface with Auto-MDI/MDIX selection, Fiber Interface with PECL signaling supported interfaces. selection these interfaces performed reset time SD/FXEN signal (pin 28). Pull enable interface, connect Fiber module enable interface.
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Page Physical Layer Interfaces Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
Many have multiple functions. multi-function pins will designated bolding number. separate descriptions these pins will listed proper sections. Designers must assure that they have identified modes operation prior final design. Signal Types: Bidirection Power Ground Analog Input Analog Output Digital Pull Down Digital Pull Active
Digital pins Bidirectional pins.
Table Pinout Signal Definitions Name RXDV/CRSDV Type Description +2.5V Power supply. Ground Ground RXDV (active HIGH output): Receive data valid output signal mode. RXDV actives HIGH indicate that receive frame progress, that data stream present output pins valid. CRSDV (active HIGH output): Carrier Sense/Data Valid output signal RMII mode. CRSDV asserted high when media idle. RMII_mode (Reset read input): pull HIGH configure chip into RMII mode. Default mode. RX_CLK (Out put): Receive clock mode. RX_CLK 100BASE output 10BASE. This clock recovered from incoming data cable inputs. ISOLATE (Reset Read Input): Pull HIGH isolate from MII. output pins high impedance. input pins still respond data. This allows multiple attached same interface. RXER (active HIGH output): asserted indicate that invalid symbol detected both RMII mode. Ground +2.5V Power supply. TXER (active HIGH input): Transmit error interface. When TXER asserted more TX_CLK periods while TXEN also asserted, shall emit more symbols that part valid data delimiter somewhere frame being transmitted. relative position error within frame need preserved. TX_CLK (Output): Transmit clock signal mode. TX_CLK 25MHz output 100BASE 2.5MHz 10BASE. This clock continuously driven output, generated from (Crystal input) pin.
RMII_mode/ RX_CLK
ISOLATE/RXER
TXER
TX_CLK
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AC101L
Preliminary Data Sheet
02/20/02
Table Pinout Signal Definitions (Cont.) Name TXEN Type Description TXEN (active HIGH input): Transmit Enable signal RMII interface. TXEN asserted indicate that valid data present TXD[3:0]. TXD0: transmit data input RMII interface. TXD1: transmit data input RMII interface. TXD2: transmit data input interface. TXD3: transmit data input interface. (active HIGH output): Collision detects signal interface. halfduplex mode, active high output indicate that collision occurred. full-duplex mode, remains low. REPEATER (Reset Read Input): Active High chip Repeater mode. (active HIGH output): Carrier sense signal interface. asserted when twisted pair media idle de-asserted when idle valid stream delimiter detected. Ground +2.5V Power supply. PHYAD0 (Reset Read Input): Pull High Address MII/RMII management function. INTR (Output): interrupt output enable. active value will invert reset read value. BURNIN# (Reset Read Input): Active chip Burn-in Test mode. LED0 (Output): active, default behavior when chip linkup condition, BLINK when chip detects transmits receive activity. SPD100 (Reset Read Input): ANEN Low, SPD100 will port speed Reg. ANEN High, SPD100 will used 100Mb Half, 100Mb Full bits Register LED1 (Output): active, default behavior when chip 100Mbps, when chip Mbps. DUPLEX (Reset Read Input): ANEN Low, DUPLEX will port Full Duplex mode Reg. ANEN High, DUPLEX will used 10Mb FDX, 100Mb bits Register LED2 (Output): active, default behavior when chip Full duplex, when chip half-duplex. ANEN (Reset Read Input): Auto-negotiation Enable Twisted Pair Port. Pull high enable Auto-negotiation. Pull disable Auto-negotiation. LED3 (Output): active, default behavior BLINK when chip detect collision half-duplex. PDOWN# (input): Power down input. Pull will both Fiber port into power down mode. This regular input. reset read signal. +2.5V Power supply. Receive port mode. Transmit port MDIX mode.
TXD0 TXD1 TXD2 TXD3
REPEATER/
PHYAD0/INTR
BURNIN#/ LED0
SPD100/LED1
DUPLEX/LED2
ANEN/LED3
PDOWN#
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Page Descriptions Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
Table Pinout Signal Definitions (Cont.) Name SD/FXEN Type Description Receive port mode. Transmit port MDIX mode. SD/FXEN (Analog input): Pull enable mode. Connect fiber module Enable mode, also served Signal Detect input. Ground Ground Bias resister connection. Connect resister GND. +2.5V supply Analog Bias, modules. Ground Transmit mode. Receive MDIX mode. Transmit mode. Receive MDIX mode. +2.5 from chip regulator. Ground Ground XTAL output. XTAL input. RMII mode defined CLK_REF=50 clock input. Mode: designed connect MHz., XTAL 25MHz OSC. Power supply input. Reset input. active. MDIO (Input/ Output): Management Data I/O. This serial input/output used read from write register. data value MDIO valid latched rising edge MDC. This requires resistor pull-up. (Input): Management Data Clock. clock input must provided allow management function. This SCHMTT trigger input. PHYAD1 (Reset Read Input): Pull High Address MII/RMII management function. RXD3: Receive data output signal interface. PHYAD2 (Reset Read Input): Pull High Address MII/RMII management function. RXD2: Receive data output signal interface. PHYAD3 (Reset Read Input): Pull High Address MII/RMII management function. RXD1: Receive data output signal MII/RMII interface. PHYAD4 (Reset Read Input): Pull High Address MII/RMII management function. RXD0: Receive data output signal MII/RMII interface.
RBIAD VCCPLL VCC25OUT
VCC33IN RST# MDIO
PHYAD1/ RXD3
PHYAD2/ RXD2
PHYAD3/ RXD1
PHYAD4/ RXD0
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AC101L
Preliminary Data Sheet
02/20/02
PHYAD4/RXD0 PHYAD3/RXD1 PHYAD2/RXD2 PHYAD1/RXD3
RST#
VCC33IN
MDIO
RXDV/CRSDV RMII_mode/RX_CLK ISOLATE/RXER TXER TXEN TXD0 TXD1
VCC25OUT VCCPLL RBIAD SD/FXEN
AC101L
48TQFP_7x7mm
BURNIN#_L/LED0
SPD100/LED1
REPEATER/CRS
PHYAD0/INTR
DUPLEX/LED2
ANEN/LED3
TXD2
TXD3
Figure AC101L Pinout Diagram
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Page Diagram Document AC101L-DS01-RDC
PDOWN#
Preliminary Data Sheet
02/20/02
AC101L
RESET
reset three ways: During initial power Hardware Reset: (See "Pin Descriptions" page Software Reset: (See "Register Description" page 14).
POWER SOURCE
chip provide board 3.3V input 2.5V output regulator, with capability drive current. 2.5V will supply operation, include LEDs. recommended limit current below LED. 2.5V power shall decoupled provide digital, analog pins chip.
POWER SAVING MODE
power consumption device significantly reduced built-in power management features. Separate power supply lines used power 10BASE-T circuitry 100BASE-TX circuitry. Therefore, circuits turned-on turned-off independently. When operate 100BASE-TX mode, 10BASE-T circuitry powered down. following power management features supported: Power Down Mode: (See register descriptions). During power down mode, device still able interface through management interface. Energy Detect/Power Saving Mode: Energy detect mode turns power select internal circuitry when there live network connected. Energy Detect (ED) circuit always turned monitor there signal energy present media. management circuitry also powered ready respond management transaction. transmit circuit still send link pulses with minimum power consumption. valid signal received from media, device will power resume normal transmit/receive operation. Valid Data Detection Mode: This achieved writing Receive Clock Register Control Bit. During this mode, there data other than idles coming receive clock (RX_CLK) will turn off. This could save power attached media access controller. RX_CLK will resume operation clock period prior assertion RXDV. receive clock will again shut clock cycles after RXDV gets deasserted.
CLOCK SOURCE
clock source this chip from pin. mode, connect Xtal (crystal). When operate RMII mode, this shall connected MHz, clock reference. internal circuit will determine operation mode upon reset read RX_CLK/RMII_SEL signal, decide weather divide done this clock provide internal clock reference.
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AC101L
Preliminary Data Sheet
02/20/02
ISOLATE MODE
When AC101L into isolate mode, inputs (TXD[3:0}, TXEN, TXER) ignore, outputs (TX_CLK, COL, CRS, RX_CLK, RXDV, RXER, RXD[3:0] high impedance. Only management pins (MDC, MDIO) operate normally. Pull HIGH reset write register chip into isolate mode.
LOOP BACK MODE
Local loop back provided testing purpose. enabled writing Reg. local loop back routes transmitted data through transmit path back receiving path's clock data recovery module. loop back data presented bits symbol format. This loop back used check operation 5-bit symbol decoder phase locked loop circuitry. local loop back, output forced logic TXOP/N outputs tristated.
INTERRUPT MODE
INTR will asserted whenever eight selectable interrupt events occur. Assertion state high programmable through INTR_LEVL register bit. selection made setting appropriate upper half Interrupt Control/Status register. When INTR goes active, interface required read Interrupt Control/Status register determine which event caused interrupt. Status bits read only clear read. When INTR asserted, held high impedance state.
OPERATION
INTERFACE
interface fully configurable through register setting. connection (source/sink current) depends default setting. default mode LED0 Link/Act LED1 Speed LED2 Duplex LED3
CONFIGURATION SECTION
However, LEDs fully configurable other operation modes. Each 16-bit registers define operation. "Common Registers" page Table "LED [3:0] Event Table," page configure LEDs work with other operation mode other than default mode:
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Page Isolate Mode Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
[3:0] EVENT TABLE
[3:0] configurable. following events defined AC101L operation: Table [3:0] Event Table [3:0] Bit# Description Duplex Collision Speed Speed Transmit Activity Transmit/Receive Activity Receive Activity Link
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AC101L
Preliminary Data Sheet
02/20/02
first seven registers register defined specification. addition these required registers several Altima Communications Inc. specific registers. There reserved registers and/or bits that Altima internal only. following standard registers supported. (Register numbers Decimal format, values format):
Note When writing registers recommended that read/modify/write operation performed,
unintended bits unwanted states. This applies registers, including those with reserved bits.
Legend: Read Write Access Self Clearing Latch Until cleared Reading Read Only Cleared Read Latch High Until Cleared Reading
REGISTER SUMMARY
Table Register Summary Register Registers Registers 8-31 8-15 18,19 22-31 Reserved Interrupt Level Control Register Interrupt Control/Status Register Reserved Cable measurement capability Register Receive Error Counter Register Reserved XXXX 03C0 0000 XXXX XXXX 0304 XXXX Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register 3000 7849 0022 5521 01E1 0001 0004 2001 Description Default
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Page Register Description Document AC101L-DS01-RDC
Preliminary Data Sheet
02/20/02
AC101L
REGISTER CONTROL REGISTER
Table Register Control Register Reg.bit 0.15 0.14 Name Reset Loop back Description reset. This self-clearing. Mode RW/SC Default
Enable loop back mode. This will loop back ignore activity cable media. Normal operation. Mbps Mbps default value SPD100 Enable Auto-Negotiate process (overrides 0.13 0.8) Disable Auto-Negotiate process. Mode selection controlled 0.8, 0.13 default value ANEN
0.13
Speed Select
SPD100
0.12
ANEN Enable
ANEN
0.11
Power Down
Power down. blocks except will turned off. Setting PDOWN# (24) will achieve same result. Normal operation. Electrically isolate from MII. still able response SMI. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. default value !ANEN DUPLEX Enable collision test, which issues signal response assertion TXEN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. Disable test.
0.10
Isolate
Restart ANEN Duplex Mode
RW/SC
Description
Collision Test
0.[6:0]
Reserved
0000000
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REGISTER STATUS REGISTER
Table Register Status Register Reg.bit 1.15 1.14 Name 100BASE-T4 100BASE-TX Full-Duplex Description Permanently tied zero indicates 100BASE-T4 capability. 100BASE-TX full-duplex capable. 100BASE-TX full-duplex capable. default value SPD100 DUPLEX 100BASE-TX half-duplex capable. half-duplex capable. default value SPD100 (ANEN !DUPLEX). 10BASE-T full-duplex capable. 10BASE-T full-duplex capable. default value DUPLEX (ANEN !SPD100) 10BASE-T half-duplex capable. 10BASE-T half-duplex capable. default value ANEN (!SPD100 !DUPLEX) Mode Default Description
1.13
100BASE-TX Half-Duplex
Description
1.12
10BASE-T Full-Duplex
Description
1.11
10BASE-T Half-Duplex
Description
1.[10:7]
Reserved Preamble Suppression
able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset.
0000
ANEN Complete Auto-Negotiate process completed. Reg. valid after this set. Auto-negotiate process completed. Remote Fault Remote fault condition detected. remote fault. This will remain until cleared reading register Able perform Auto-Negotiation function, default value determined ANEN pin. Unable perform Auto-Negotiation function. Link established. link fails, this will cleared remain until register read again. Link gone down. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one.
RO/LH
ANEN Ability
ANEN
Link Status
RO/LL
Jabber Detect Extended Capability
RO/LH
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AC101L
REGISTER IDENTIFIER REGISTER
Table Register Identifier Register Reg.bit 2.[15:0] Name OUI* Description Composed through 18th bits Organizationally Unique Identifier (OUI), respectively. Mode Default 0022(H)
Based 0010A9 (Hex)
REGISTER IDENTIFIER REGISTER
Table Register Identifier Register Reg.bit 3.[15:10] 3.[9:4] 3.[3:0] Name Model Number Revision Number Description Assigned 19th through 24th bits OUI. manufacturer's model number. Four-bit manufacturer's revision number. Mode Default 010101 010010 0001
Based 0010A9 (Hex)
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REGISTER AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table Register Auto-Negotiation Advertisement Register Reg.bit 4.15 4.14 4.[13:11] 4.10 Name Next Page Acknowledge Reserved FDFC Full-Duplex Flow Control. Advertise that DTE(MAC) implemented both optional control layer pause function specified clause annex 802.3u. does support flow control. Technology supported. This always 100BASE-TX full-duplex capable. 100BASE-TX full-duplex capable. default value SPD100 DUPLEX 100BASE-TX half-duplex capable. half-duplex capable. default value SPD100 (ANEN !DUPLEX) 10BASE-T full-duplex capable. 10BASE-T full-duplex capable. default value DUPLEX (ANEN !SPD100) 10BASE-T half-duplex capable. 10BASE-T half-duplex capable. default value ANEN (!SPD100 !DUPLEX) Protocol Selection [00001] IEEE 802.3. Description Description Next Page enabled. Next Page disabled. This will internally after receiving consecutive consistent bursts. Mode Default
100BASE-T4 100BASE-TX Full-Duplex
100BASE-TX
Description
10BASE-T Full Duplex
Description
10BASE-T
Description
4.[4:0]
Selector Field
00001
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AC101L
REGISTER AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER/LINK PARTNER NEXT PAGE MESSAGE
Table Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Reg.bit 5.15 5.14 5.[13:10] 5.[4:0] Name Next Page Acknowledge Reserved 100BASE-T4 100BASE-TX Full Duplex 100BASE-TX 10BASE-T Full Duplex 10BASE-T Selector Field 100BASE-T4 supported Link Partner. 100BASE-T4 supported Link Partner. 100BASE-TX full-duplex supported Link Partner. 100BASE-TX full-duplex supported Link Partner. 100BASE-TX half-duplex supported Link Partner. 100BASE-TX half-duplex supported Link Partner. Mbps full-duplex supported Link Partner. Mbps full-duplex supported Link Partner. Mbps half-duplex supported Link Partner. Mbps half-duplex supported Link Partner. Protocol Selection [00001] IEEE 802.3. 00001 Description Link partner desires Next Page transfer. Link partner does desire Next Page transfer. Link Partner acknowledges reception words. acknowledged Link Partner. Mode Default
*When this register used Next Page Message, definition same Register
REGISTER AUTO-NEGOTIATION EXPANSION REGISTER
Table Register Auto-Negotiation Expansion Register Reg.bit 6.[15:5] Name Reserved Parallel Detection Fault Description Mode Fault detected parallel detection logic, this fault RO/LH more than technology detecting concurrent link condition. This only cleared reading Register using management interface. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. Next page supported. Default
Link Partner Next Page Able Next Page Able Page Received
This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon read this register. Link partner Auto-Negotiation capable. Link partner Auto-Negotiation capable.
Link Partner ANEN-Able
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REGISTER AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table Register Auto-Negotiation Next Page Transmit Register Reg.bit 7.15 7.14 7.13 7.12 7.11 17.[10:0] Name Reserved ACK2 TOG_TX CODE Message page. Unformatted page. Will comply with message. comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Unformatted Code Field. Description Another Next Page desired. other Next Page Transfer desired. Mode Default
REGISTER INTERRUPT LEVEL CONTROL REGISTER
Table Register Interrupt Level Control Register Reg.bit 16.15 16.14 16.13 16.12 16.11 Name Repeater INTR_LEVL TXJAM Disable Description Repeater mode, full- duplex will inactive, only responses receive activity. test function disabled. INTR will active high. INTR will active low. Force send pattern. Normal operation. Disable Carrier Integrity Monitor. Enable Carrier Integrity Monitor. Mode Default Repeater
Test Inhibit Disable 10BASE-T testing. Enable 10BASE-T testing, which will generate pulse following completion packet transmission. Reserved Auto Polarity Disable Disable Auto Polarity detection/correction. Enable Auto Polarity detection/correction.
16.[10:6] 16.5 16.4
Reverse Polarity Reverse Polarity when Reg. 16.5 Normal Polarity when Reg. 16.5 Reg. 16.5 writing this will reverse polarity transmitter. Reserved
16.[3:0]
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AC101L
REGISTER INTERRUPT CONTROL/STATUS REGISTER
Table Register Interrupt Control/Status Register Reg.bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Name Jabber_IE RXER_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Status_ Change_IE R_Fault_IE ANEN_Comp_IE Jabber_Int RXER_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Not_OK R_Fault_Int Description Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Change Interrupt Enable. Remote Fault Interrupt Enable. Auto-Negotiation Complete Interrupt Enable. This when jabber event detected. This when RXER transitions high. This when page received during ANEN. This when parallel detect fault detected. Mode Default
This when with acknowledge received. This when link status switches from status NonOK status (Fail Ready). This when remote fault detected.
ANEN _Comp This when ANEN complete.
REGISTER DIAGNOSTIC REGISTER
Table Register Diagnostic Register Reg. 18.[15] 18.[14] 18.[13] 18.[12] 18.11 18.10 18.9 18.8 18.[7:0] Name Reserved Reserved Force link pass 10BT Force link pass 100TX Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Enable Force link pass 10BT. Disable Force link pass 10BT. Force link pass 100TX. Disable Force link pass 100TX. Reserved Reserved Reserved Reserved Reserved Mode RO/RC Default
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REGISTER POWER/LOOPBACK REGISTER
Table Register Power/Loopback Register Reg. 19.[14:7] 19.6 19.5 Name Reserved Reserved Disable watch timer decipher Power Mode disable Reserved Reserved Link Integrity Test Jabber disable Description Reserved Reserved Disable watch timer. Enable advanced power saving mode. Enable advanced power saving mode. Disable advanced power saving mode. Reserved Reserved Auto-Negotiation test mode, send instead order test receive integrity. Sending Auto-Negotiation test mode. Disable jabber. Mode Default
19.4 19.3 19.1
19.0
REGISTER CABLE MEASUREMENT CAPABILITY REGISTER
Table Register Cable Measurement Capability Register Reg.bit 20.15 20.14 20.[13:9]
a20.8
Name Reserved Reserved Reserved Adaptation disable Cable measurement capability
Description Reserved Reserved Disable Adaptation. Enable Adaptation.
Mode
Default
20.[7:4]
These bits used cable length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment MHz. value read back from equalizer, measured value absolute. Reserved
20.[3:0]
Reserved
want value 20.[7:4], must turn 20.8 turn 20.14. this will reject receive packets.
REGISTER RECEIVE ERROR COUNTER
Table Register Receive Error Counter Reg.bit 21.[15:0] Name RXER Counter Description Count Receive Error Events. Mode Default
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AC101L
REGISTER POWER MANAGEMENT REGISTER
Table Register Power Management Register Reg.bit 22.[15:14] 22.13 22.12 22.11 22.10 22.9 22.8 22.[7:6] 22.5 22.4 22.3 22.2 22.1 22.0 Name Reserved PD_PLL PD_EQUAL PD_BT_RCVR PD_LP PD_EN_DET PD_FX Reserved MSK_PLL MSK_EQUAL MSK_BT_RCVR MSK_LP MSK_EN_DET MSK_FX Force power circuit. Force power equalizer circuit. Force power 10BASE-T receiver. Force power link pulse receiver. Force power energy detect circuit. Force power circuit. Power down circuit. Power down equalizer circuit. Power down 10BASE-T receiver. Power down link pulse receiver. Power down energy detect circuit. Power down circuit. Description Mode Default
REGISTER OPERATION MODE REGISTER
Table Register Operation Mode Register Reg.bit 23.[15:14] 23.13 23.12 23.11 23.10 23.9 23:8 23.[7:6] 23.5 23.[4:0] Name Reserved Clk_rclk_save Reserved Scramble disable Reserved Pcsbp Reserved Reserved Reserved Reserved XXXXX Enable bypass mode. Disable PCS. Disable scrambler. Enable scrambler. rclk save mode. Rclk will shut after cycles each packet. Description Mode Default
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REGISTER RECENT RECEIVED PACKET
Table Register Recent Received Packet Reg.bit 24.[15:0] Name CRC16 Description CRC16 value displayed. system level test purpose. Mode Default 0000H
COMMON REGISTERS
following registers mapped Reg28-31 PHY. Reg28.[15:12] used page select. There multiple pages Reg29-31, depends value Reg. 28[15:12]
COMMON REGISTER (MAP REG. MODE CONTROL REGISTER
Table Common Register (Map Reg. Mode Control Register Reg. Name Description Select Multiple Common Register Pages. Reserved Enable Interface. Reserved chip Reduce mode. Reserved Event Select. Receive activity. activity. Mode Default 0000 0000
a.28.[15:12] Page Selection a.28.[11:7] a.28.6 a.28.5 a.28.4 a.28.3 a.28.2 Reserved MII_enable Reserved RMII_enable Reserved select
a.28.1 a.28.0
Reserved Reserved
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AC101L
COMMON REGISTER (MAP REG. PAGE A28.[15:12]=0000) TEST MODE REGISTER
Table Common Register (Map Reg. Page a28.[15:12]=0000) Test Mode Register Reg.bit A0.29.15 Name Description Mode 0000 Normal operation. Enable burn test mode. Normal operation. Disable digital output. Normal operation. Normal operation. Reduce timer auto-neg testing. Normal operation. Default 00100 0000
Reduce_mcount Reduce millisecond counter micro second.
A0.29.[14:10] Reserved A0.29.[9:8] A0.29.[7:4] A0.29.3 A0.29.2 A0.29.1 A0.29.0 Reserved Test Mode Burn Output Disable Reserved Reduce Timer
COMMON REGISTER (MAP REG. PAGE A28.[15:12]=0001) BLINK RATE
Table Common Register (Map Reg. Page a28.[15:12]=0001) Blink Rate Reg.bit Name Description Mode blink rate. blink rate this number Default Default 00000000 00010000
A1.29.[15:8] Reserved A1.29.[7:0] Blink Rate
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0001) LED0 SETTING1 REGISTER
Default operation LED0 when Link; BLINK when Activity. Table Common Register (MAP REG. PAGE A.28.[15:12]=0001) LED0 SETTING1 REGISTER Reg.bit A1.30.[15:13] A1.30.12 A1.30.[11:9] A1.30.8 A1.30.[7:0] Name Reserved Force Reserved Force Blink Force LED0 off. Force LED0 Description Mode Default 0000 00000100
Blink Mask. When bits one, corresponding event will cause blink.
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COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0001) LED0 SETTING2 REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0001) LED0 Setting2 Register Reg.bit A1.31. [15:8] A1.31. [7:0] Name Description Mode Default 00000001 00000000
Mask. When bits one, corresponding event will cause turn Mask. When bits one, corresponding event will cause turn off.
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0010) LED1 SETTING1 REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting1 Register Reg.bit Name Description Mode Force LED1 Force LED1 off. Default 00000000
A2.29.[15:13] Reserved A2.29.12 A2.29.[11:9] A2.29.8 A2.29.[7:0] Force Reserved Force Blink
Blink Mask. When bits one, corresponding event will cause blink.
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0010) LED1 SETTING2 REGISTER
Default Operation LED1 when Mbps. Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED1 Setting2 Register Reg.bit A2.30.[15:8] A2.30.[7:0] Name Description Mode Default 00100000 00000000
Mask. When bits one, corresponding event will cause turn Mask. When bits one, corresponding event will cause turn off.
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0010) LED2 SETTING1 REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 Register Reg.bit A2.31.[15:13] A2.31.12 Name Reserved Force Force LED2 Description Mode Default
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AC101L
Table Common Register (Map Reg. Page a.28.[15:12]=0010) LED2 Setting1 Register (Cont.) Reg.bit A2.31.[11:9] A2.31.8 A2.31.[7:0] Name Reserved Force Blink Force LED2 Off. Description Mode Default 00000000
Blink Mask. When bits one, corresponding event will cause blink.
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0011) LED2 SETTING2 REGISTER
Default Operation LED2 when Duplex. Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED2 Setting2 Register Reg.bit A3.29.[15:8] A3.29.[7:0] Name Description Mask. When bits one, corresponding event will cause turn Mask. When bits one, corresponding event will cause turn off. Mode Default 10000000 00000000
COMMON REGISTER (MAP REG. PAGE A.28[.15:12]=0011) LED3 SETTING1 REGISTER
Default Operation LED3 BLINK when COL. Table Common Register (Map Reg. Page a.28[.15:12]=0011) LED3 Setting1 Register Reg.bit A3.30.[15:13] A3.30.12 A3.30.[11:9] A3.30.8 A3.30.[7:0] Name Reserved Force Reserved Force Blink Force LED3 Off. Force LED3 Description Mode Default 0100000
Blink Mask. When bits one, corresponding event will cause blink.
COMMON REGISTER (MAP REG. PAGE A.28.[15:12]=0011) LED3 SETTING2 REGISTER
Table Common Register (Map Reg. Page a.28.[15:12]=0011) LED3 Setting2 Register Reg.bit A3.31.[15:8] A3.31.[7:0] Name Description Mode Default 00000000 00000000
Mask. When bits one, corresponding event will cause turn Mask. When bits one, corresponding event will cause turn off.
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ction Code -Group
Table 4B/5B Code-Group Table Symbol Name Invalid Code Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code CODE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0101 0101 Undefined Undefined CODE 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Idle Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol.
Idle Control Codes
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AC101L
ction ad/Wr quence
Table Read/Write Sequence Read/Write Sequence Pream bits) Read Write Start bits) OpCode bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
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ction Timing Char acte ristics
CLOCK TIMING
Table Clock Timing Parameter XTAL input Cycle Time XTAL input High/Low Time XTAL input Rise/Fall Time REF_CLK Cycle Time (RMII) REF_CLK High/Low Time (RMII) REF_CLK Rise/Fall Time (RMII) Symbol CK_CYCLE CK_HI CK_LO CK_EDGE Units
RESET TIMING
Table Reset Timing Parameter Reset Pulse Length Period with stable XTAL input Activity after Hardware Reset Reset Rise Fall Time Symbol RESET_LEN RESET_WAIT RESET_WAIT Units
CK_EDGE
CK_EDGE
XTAL Input
CK_HI CK_LO
Normal activity begins here
CK_CYCLE RESET_EDGE
RESET#
RESET_LEN RESET_EDGE RESET_WAIT
Figure Reset Timing
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AC101L
MANAGEMENT DATA INTERFACE TIMING
Table Management Interface Timing Parameter Cycle Time High/Low Rise/Fall Time MDIO input Setup Time rising MDIO input Hold Time from rising MDIO output Delay from rising Symbol MDC_CYCLE MDC_RISE MDC_FALL MDIO_SETUP MDIO_HOLD MDIO_DELAY Units
MDC_CYCLE MDC_FALL MDIO_SETUP MDIO (Into AC101L) MDIO_HOLD MDIO_SETUP
MDC_RISE
MDIO_HOLD
MDIO (From AC101L) MDIO_DELAY
Figure Management Interface Timing
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100BASE-TX/FX TRANSMIT SYSTEM TIMING
Table 100BASE-X Transmit System Timing Parameter TX_CLK period TX_CLK High period TX_CLK period TXEN TXEN sampled TXEN sampled !TXEN !TXEN sampled !CRS !TXEN sampled !COL Propagation Delay TXD[3:0], TXEN, TXER Hold Symbol tCKH tCKL tCSA tCLA tCSD tCLD tTXH Conditions RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N(FXTP/N) From rising edge TX_CLK From rising edge TX_CLK 39.998 18.000 18.000 40.000 20.000 20.000 40.002 22.000 22.000 Units
TXD[3:0], TXEN, TXER Setup tTXS
tCKH
TX_CLK
Start Packet tCKL
Packet
tTXS
TXEN
tTX_T tTXH
TXD[3:0] TX_ER
TXOP/N
FXTP/N
tTCS tTCLA
tTCS tTCLD
100Base-TX/FX Transmit Timing
Figure 100BASE-T Transmit Timing
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AC101L
100BASE-TX/FX RECEIVE SYSTEM TIMING
Table 100BASE-TX/FX Receive System Timing Parameter RX_CLK period RX_CLK High period RX_CLK period /J/K RXDV assert /J/K assert /J/K assert /T/R !RXDV /T/R !CRS /T/R !COL Propagation Delay RXD[3:0], RXDV, RXER Setup RXD[3:0], RXDV, RXER Hold Symbol tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH Conditions RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N(FXRP/N) RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK 39.998 18.000 18.000 40.000 20.000 20.000 40.002 22.000 22.000 Units
tCKH
RX_CLK
Start Packet tCKL
Packet
RXDV RXD[3:0] RXER RXDV
tRDV tRXS tRXH
tRDV
/J/K RXIP/N
/T/R
FXRP/N
tRCSA
tRCSD
tRCLA
100Base-TX/FX Receive Timing
tRCLD
Figure 100BASE-T Receive Timing
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Preliminary Data Sheet
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10BASE-T TRANSMIT SYSTEM TIMING
Table 10BASE-T Transmit System Timing Parameter TX_CLK period TX_CLK High period TX_CLK period TXEN TXEN sampled TXEN sampled !TXEN !TXEN sampled !CRS !TXEN sampled !COL Propagation Delay TXD[3:0], TXEN, TXER Hold tCKH tCKL tTCSA tTCLA tTCSD tTCLD tTXH Conditions RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N From rising edge TX_CLK From rising edge TX_CLK 399.98 180.00 180.00 400.00 200.00 200.00 400.02 220.00 220.00 Units
TXD[3:0], TXEN, TXER Setup tTXS
tCKH
TX_CLK
Start Packet tCKL
Packet
tTXS
TXEN
tTX_T tTXH
TXD[3:0] TX_ER
TXOP/N
tTCS tTCLA
tTCS tTCLD
10Base-T Transmit Timing
Figure 10BASE-T Transmit Timing
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AC101L
10BASE-T RECEIVE SYSTEM TIMING
Table 10BASE-T Receive System Timing Parameter RX_CLK period RX_CLK High period RX_CLK period RXDV !RXDV !CRS !COL Propagation Delay RXD[3:0], RXDV, RXER Setup RXD[3:0], RXDV, RXER Hold Symbol tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH Conditions RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK 399.98 180.00 180.00 400.00 200.00 200.00 400.02 220.00 220.00 Units
tCKH
RX_CLK
Start Packet tCKL
Packet
RXDV RXD[3:0] RXER RXDV RXIP/N
tRDV tRXS tRXH
tRDV
tRCSA
tRCSD
tRCLA
10Base-T Receive Timing
tRCLD
Figure 10BASE-T Receive Timing
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Preliminary Data Sheet
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RMII TRANSMIT TIMING
Table RMII Transmit Timing Parameter REFCLK period REFCLK High period REFCLK period Propagation Delay TXD[1:0], TXEN Setup TXD[1:0], TXEN Hold Symbol tCKH tCKL tTXS tTXH Conditions From TXD[1:0] TXOP/N(FXTP/N) From rising edge REFCLK From rising edge REFCLK 19.999 9.000 9.000 20.000 10.000 10.000 20.001 11.000 11.000 Units
tCKH
REFCLK
Start Packet tCKL
Packet
tTXS
TXEN
tTX_T tTXH
TXD[1:0]
TXOP/N
FXTP/N
TXOP/N 100Base-TX/FX 10Base RMII Transmit Timing
Figure RMII Transmit Timing
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AC101L
RMII RECEIVE TIMING
Table RMII Receive Timing Parameter REFCLK period REFCLK High period REFCLK period Propagation Delay RXD[1:0], CRS_DV, RXER Setup RXD[1:0], CRS_DV, RXER Hold Symbol tCKH tCKL tRDVA tRXS tRXH Conditions From rising edge REFCLK From rising edge REFCLK 19.999 9.000 9.000 20.000 10.000 10.000 20.001 11.000 11.000 Units
From RXIP/N(FXRP/N) RXD[1:0]
tCKH
REFCLK
Start Packet tCKL
Packet
CRS_DV RXD[1:0] RXER
tRDV tRXS tRXH
tRDV
/J/K RXIP/N
/T/R
FXRP/N RXIP/N 100Base-TX/FX 10Base-T RMII Receive Timing
Figure RMII Receive Timing
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COPPER APPLICATION TERMINATION
2.5V .1uF .1uF
49.9_1/16W_1%
49.9_1/16W_1%
49.9_1/16W_1%
49.9_1/16W_1%
Auto MDI/MDIX Magnetic
RJ45
AC101L
RD2.5V
4578
.1uF
.1uF
75_1/16W_5% 75_1/16W_5%
75_1/16W_5% 75_1/16W_5%
1000PF_2KV
Auto MDI/MDIX Magnetics: BEL: S558-5999-W2; PULSE: H1102; HALO: TG110-S050N2
Figure Application
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AC101L
ction Electr ristics
NOTE: following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Input Current Storage Temperature Electrostatic Discharge Symbol VESD GND-0.3 GND-0.3 +125 1000 Units
RECOMMENDED OPERATING CONDITIONS
Table Recommended Operating Conditions Parameter Supply voltage AC101L Supply voltage AC101L High level input voltage High level input voltage level input voltage level input voltage Differential input voltage Common mode input voltage Common mode input voltage Ambient Operating Temperature AC101L
tolerate
Symbol VIDIFF VICM VICM
VCC33IN VCC, VCCPLL, VCC25OUT Digital inputs Digital inputs
Operating Mode 100BASE-FX 100BASE-FX 100BASE-FX 100BASE-TX 100BASE-FX
3.135 2.375 2.2V
3.465 2.625 VCCa
Units
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Document AC101L-DS01-RDC Electrical Characteristics Page
AC101L
Preliminary Data Sheet
02/20/02
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics Parameter Supply Current Supply Current Power Down Mode High Level Output Voltage High Level Output Voltage Level Output Voltage Level Output Voltage Differential Output Voltage Input Current Bias Voltage Symbol VODIFF VBIAS Pins VCC, VCC25OUT, VCCPLL VCC, VCC25OUT, VCCPLL Digital Outputs Digital Outputs Digital inputs w/Pullup Resistor RBIAD Conditions 100BASE-TX -12mA VCC=2.5V Driving Load Magnetic Module Driving Load Magnetic Module 100BASE-FX Mode VCC-1.5 1.18 VCC+1.5 1.30 VCC-0.4 Units
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Preliminary Data Sheet
02/20/02
AC101L
APPLICATION
3_3V 2_5V
3_3V
3_3V
.1uF .1uF .1uF .1uF
BLM11A601S
Z=50 Z=50 Z=50
.1uF .1uF
Z=50 Z=50 Z=50 RDSD
SD/FXEN
Z=50 Z=50
.1uF .1uF
RxVcc RxVee TxVcc TxVee
AC101L
BLM11A601S
0.01UF
0.01UF
HFBR-5903
Figure Application
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AC101L
Preliminary Data Sheet
02/20/02
10UF .1uF
3_3V
RXD0/PHYAD4 RXD1/PHYAD3 RXD2/PHYAD2 RXD3/PHYAD1 MDIO RST_L VCC33IN GND8 GND7
Place CAPs close possible each power AC101L 2_5V
.1uF
0.01UF
2_5V
.1uF 22UF
0.01UF .1uF
TXD2 TXD3 CRS/REPEATER GND3 INTR/PHYAD0 LED0/BURNIN_L LED1/SPD100 LED2/DUPLEX LED3/ANEN PDOWN
0.01UF
GND1 RXDV/CRSDV RXC/RMII_mode AC101L RXER/ISOLATE GND2 TQFP_7x7mm TXER TXEN TXD0 TXD1
VCC25OUT GND6 VCCPLL RBIAD GND5 GND4 SD/FXEN
2_5V
VCCPLL 2.2UF
2_5V
.1uF 0.01UF
.1uF
0.01UF
Figure Power Ground Filtering
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2_5V
Preliminary Data Sheet
02/20/02
AC101L
Section Mechanic Infor mation
Figure Quad Flat Pack Outline
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AC101L
Preliminary Data Sheet
02/20/02
ction Therm cific ations
Table Thermal Parameters Airflow (feet minute) Theta 53.9 51.2 24.7 48.6 47.5
Theta junction temperature
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Preliminary Data Sheet
02/20/02
AC101L
Part Number AC101LKQT Package 48TQFP Ambient Temperature
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AC101L
Preliminary Data Sheet
02/20/02
Altima Communications, Inc.
Wholly Owned Subsidiary Broadcom Corporation
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
Broadcom® Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
Document AC101L-DS01-RDC

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