Simplified Truth Table. Function Truth Table (Note Function Truth Tabl
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Preliminary W942504AH BANKS SDRAM
Simplified Truth Table. Function Truth Table (Note Function Truth Table CKE.
SIMPLIFIED STATE DIAGRAM FUNCTIONAL DESCRIPTION
Power Sequence. Command Function Read Operation Write Operation Precharge Burst Termination Refresh Operation Power Down Mode Mode Register Operation
TIMING WAVEFORMS.27
Command Input Timing Timing Signals Read Timing (Burst Length Write Timing (Burst Length
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Mode Register (MRS) Timing. Extend Mode Register (EMRS) Timing Auto Precharge Timing (Read Cycle, CL=2) Auto Precharge Timing (Write Cycle) Read interrupted Read Burst Read Stop Read Interrupted Write Read Interrupted Precharge Write Interrupted Write Write Interrupted Read Write Interrupted Read Write Interrupted Precharge Bank Interleave Read Operation Bank Interleave Read Operation Bank Interleave Read Operation Auto Refresh Cycle. Active Power Down Mode Entry Exit Timing Precharged Power Down Mode Entry Exit Timing Self Refresh Entry Exit Timing.
PACKAGE DIMENSION
TSOP
Preliminary W942504AH
GENERAL DESCRIPTION
W942504AH CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized 16,777,216 words banks bits. Using pipelined architecture 0.175 process technology, W942504AH delivers data bandwidth 286M words second (-7). fully comply with personal computer industrial standard, W942504AH sorted into three speed grades: compliant MHz/CL2.5 DDR266/CL2 specification, compliant DDR266/CL2.5 specification, compliant DDR200/CL2 specification Inputs reference positive edge (except CKE). timing reference point differential clock when signals cross during transition. Write Read data synschronized with both edges (Data Strobe). having programmable Mode Register, system change burst length, latency cycle, interleave sequential burst maximize performance. W942504AH ideal main memory high performance applications.
FEATURES
2.5V ±0.2V Power Supply Clock Frequency Double Data Rate architecture; data transfers clock cycle Differential Clock Inputs (CLK edge-aligned with data Read; center-aligned with data Write Latency:
Burst Length: Auto Refresh Self Refresh Precharged Power Down Active Power Down Write Data Mask Write Latency Refresh Cycles Interface: SSTL-2 Packaged TSOP 66-pin, mil, 0.65 pitch
PARAMETERS
SYM. DESCRIPTION MIN./MAX.
tRAS IDD1 IDD4 IDD6
Clock Cycle Time
Min. Min. Min. Min. Max. Max. Max.
Active Precharge Command Period Active Ref/Active Command Period Operation Current (Single bank) Burst Operation Current Self-Refresh Current
Publication Release Date: August 2001 Revision
Preliminary W942504AH
CONFIGURATION
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
Preliminary W942504AH
DESCRIPTION
NUMBER 28-32, 35-42 NAME FUNCTION Address DESCRIPTION Multiplexed pins column address. address: A12. Column address: A11. (A10 used Auto Precharge) Select bank activate during address latch time, bank read/write during column address latch time.
26,27
BS0,
Bank Select
Data Input/ input output data synchronized with both Output edges DQS. Bi-directional signal. input signal during write Data Strobe operation output signal during read operation. Edgealigned with read data, Center-aligned with write data. Disable enable command decoder. When command Chip Select decoder disabled, command ignored previous operation continues. Command Inputs Write mask Command inputs (along with define command being entered. When asserted "high" burst write, input data masked. synchronized with both edges DQS.
CLK,
Differential address control input signals sampled crossing clock inputs positive edge negative edge controls clock activation deactivation. When Clock Enable low, Power Down mode, Suspend mode, Self Refresh mode entered. Reference Voltage Power (+2.5V) Ground VREF reference voltage inputs. Power logic circuit inside SDRAM. Ground logic circuit inside SDRAM.
VREF VDDQ
Power Separated power from VDD, used output buffer, improve (+2.5V) noise. buffer Ground Separated ground from VSS, used output buffer, improve buffer noise.
VSSQ
NC1,
connection Connection
Publication Release Date: August 2001 Revision
Preliminary W942504AH
BLOCK DAIAGRAM
CLOCK BUFFER
CONTROL
SIGNAL
GENERATOR COMMAND
DECODER
COLUMN DECODER
COLUMN DECODER
DECODER
CELL ARRAY BANK
DECODER
CELL ARRAY BANK
ADDRESS BUFFER
MODE REGISTER SENSE AMPLIFIER
SENSE AMPLIFIER
PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER BUFFER
COLUMN DECODER
COLUMN DECODER
DECODER
CELL ARRAY BANK
DECODER
CELL ARRAY BANK
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: cell array configuration 8912 2048
Preliminary W942504AH
ABSOLUTE MAXIMUM RATINGS
PARAMETER Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current SYMBOL VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER IOUT RATING -0.3 VDDQ +0.3 -0.3 UNIT
Note: Exposure conditions beyond those listed under Absolute Maximum Ratings adversely affect life reliability device.
RECOMMENDED OPERATING CONDITIONS
70°C)
SYMBOL VDDQ VREF (DC) (DC) VICK (DC) (DC)
PARAMETER Power Supply Voltage Power Supply Voltage (for Buffer) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Voltage (DC) Differential Clock Input Voltage Input Differential Voltage.
inputs (DC)
MIN.
0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 -0.3 0.36
TYP.
0.50 VDDQ VREF
MAX.
UNIT
NOTES 13,15
0.51 VREF 0.04
VDDQ
VREF 0.15
VDDQ VDDQ
VREF 0.31
(AC) (AC) (AC) (AC) VISO (AC)
Input High Voltage (AC) Input Voltage (AC) Input Differential Voltage.
inputs (AC)
VREF 0.31
13,15
VDDQ VDDQ/2 VDDQ/2
Differential input Cross Point Voltage Differential Clock Middle Point
VDDQ/2 VDDQ/2
Note Undershoot Limit VIL(min) -0.9V with pulse width Overshoot Limit VIH(max) VDDQ+0.9V with pulse width VIH(DC) VIL(DC) levels maintain current logic state. VIH(AC) VIL(AC) levels change logic state.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
CAPACITANCE
(VDD VDDQ 2.5V ±0.2V, MHz, 25°C, VOUT(DC) VDDQ/2, VOUT (Peak Peak) 0.2V)
SYM. CCLK CI/O CNC1 CNC2
PARAMETER Input Capacitance (except pins) Input Capacitance (CLK pins) DQS, Capacitance Capacitance Capacitance
MIN.
MAX.
DELTA (MAX.) 0.25
UNIT
Note: These parameters periodically sampled 100% tested. pins have additional capacitance adjustment adjacent capacitance. pins have Power Ground clamp.
LEAKAGE OUTPUT BUFFER CHARACTERISTICS
SYM. II(L) IO(L) (DC) (DC) (DC) (DC) PARAMETER Input Leakage Current
VDDQ, other pins under test
MIN. +0.76 Full Strength -15.2 15.2 Half Strength -10.4 10.4
MAX. -0.76
UNITS
NOTES
Output Leakage Current (Output disabled, VOUT VDDQ) Output High Voltage (Under test load condition) Output Voltage (Under test load condition) Output Minimum Source Current Output Minimum Sink Current Output Minimum Source Current Output Minimum Sink Current
Preliminary W942504AH
CHARACTERISTICS
SYM. IDD0 PARAMETER OPERATING CURRENT: Bank Active-Precharge; min; min; inputs changing twice clock cycle; Address control inputs changing once clock cycle OPERATING CURRENT: Bank Active-Read-Precharge; Burst min; CL=2.5; min; IOUT Address control inputs changing once clock cycle. PRECHARGE-POWER-DOWN STANDBY CURRENT: Banks Idle; Power down mode; max; min; VREF IDLE FLOATING STANDBY CURRENT: min; Banks Idle; min; Address other control inputs changing once clock cycle; Vref IDLE STANDBY CURRENT: min; Banks Idle; min; min; Address other control inputs changing once clock cycle; IDLE QUIET STANDBY CURRENT: min; Banks Idle; min; min; Address other control inputs stable; VREF ACTIVE POWER-DOWN STANDBY CURRENT: Bank Active; Power down mode; max; ACTIVE STANDBY CURRENT: min; min; Bank Active-Precharge; tRAS max; min; inputs changing twice clock cycle; Address other control inputs changing once clock cycle OPERATING CURRENT: Burst=2; Reads; Continuous burst; Bank Active; Address control inputs changing once clock cycle; CL=2.5; min; IOUT=0mA OPERATING CURRENT: Burst=2; Write; Continuous burst; Bank Active; Address control inputs changing once clock cycle; CL=2.5; min; inputs changing twice clock cycle AUTO REFRESH CURRENT: tRFC SELF REFRESH CURRENT: 0.2V RANDOM READ CURRENT: Banks Active Read with activate every 20ns, Auto-Precharge Read every 20ns; Burst=4; tRCD= IOUT= inputs changing twice clock cycle; Address changing once clock cycle
10ns
UNIT
NOTES
IDD1
IDD2P
IDD2F
IDD2N
IDD2Q IDD3P
IDD3N
IDD4R
IDD4W IDD5 IDD6 IDD7
tRCD
COMMAND READ Bank Rowc Bank READ Bank Rowd Bank READ Bank Rowe Bank READ Bank Bank
Bank ADDRESS
RANDOM READ CURRENT Timing (IDD7)
Publication Release Date: August 2001 Revision
Preliminary W942504AH
CHARACTERISTICS OPERATING CONDITION
(Notes: SYM. tRFC tRAS tRCD tRAP tCCD tRRD tDAL MIN. Active Ref/Active Command Period Ref/Active Command Period Active Precharge Command Period Active Read/Write Command Delay Time Active Read with Auto Precharge enable Read/Write(a) Read/Write(b) Command Period Precharge Active Command Period Active(a) Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery Precharge Time Cycle Time Data Access time from CLK, -0.75 -0.75 0.45 0.45 (tCL,tCH) -0.75 1.75 0.35 0.35 0.25 0.75 -0.25 -0.75 -0.75 0.75 0.75 PARAMETER MAX. MIN. -0.75 -0.75 0.45 0.45 (tCL,tCH) -0.75 1.75 0.35 0.35 0.25 0.75 -0.25 -0.75 -0.75 0.75 0.75 MAX. MIN. -0.8 -0.8 0.45 0.45 (tCL,tCH) tHP-1.0 0.35 0.35 0.25 0.75 -0.25 -0.8 -0.8 MAX. UNITS NOTES
100000
100000
100000
0.75 0.75 0.55 0.55
0.75 0.75 0.55 0.55
tDQSCK output access time from CLK, tDQSQ tRPRE tRPST tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIPW tT(SS) tWTR tXSNR tXSRD tREF tMRD Data Strobe Edge Output Data Edge Skew High level width level width half period (minimum actual tCH, tCL) output data hold time from Read Preamble Time Read Postamble Time Setup Time Hold Time input pulse width (for each input) input high pulse width input pulse width falling edge setup time falling edge hold time from Clock Write Preamble Set-up Time Write Preamble Time Write Postamble Time Write command first latching transition UDQS LDQS Skew (x16) Input Setup Time Input Hold Time Control Address input pulse width (for each input) Data-out High-impedance Time from CLK, Data-out Low-impedance Time from CLK, SSTL Input Transition Internal Write Read command delay Exit Self Refresh non-Read command Exit Self Refresh Read command Refresh Time (8k) Mode Register cycle time
0.55 0.55
1.25 0.25
1.25 0.25
1.25 0.25
Preliminary W942504AH
TEST CONDITIONS
PARAMETER Input High Voltage (AC) Input Voltage (AC) Input Reference Voltage Termination Voltage Input Signal Peak Peak Swing Differential Clock Input Reference Voltage Input Difference Voltage. Input Signal Minimum Slew Rate Output timing Measurement Reference Voltage
SYMBOL VREF VSWING VID(AC) SLEW VOTR
VALUE VREF 0.31 VREF 0.31 VDDQ VDDQ (AC) VDDQ
UNIT V/nS
inputs (AC)
VDDQ (AC) SWING (MAX) VREF
Measurement point ohms
(AC)
Output
output
ohms 30pF
SLEW (VIH (AC) (AC))
A.C. TEST LOAD
Notes: Conditions outside limits listed under "ABSOLUTE MAXIMUM RATINGS" cause permanent damage device. voltages referenced VSS, VSSQ. Peak peak noise VREF exceed VREF(DC). 1.95V, 0.35V 1.9V, 0.4V values IOH(DC) based VDDQ=2.3V 1.19V. values IOL(DC) based VDDQ=2.3V 1.11V. These parameters depend cycle rate these values measured cycle rate with minimum values tRC.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
applied directly device. system supply signal termination resistors, expected equal VREF must track variations level VREF. These parameters depend output loading. Specified values obtained with output open.
(10) Transition times measured between min(AC) max(AC).Transition (rise fall) input signals have fixed slope. (11) result nominal calculation with regard contains more than decimal place, result rounded nearest decimal place. (i.e., tDQSS 0.75 tCK, 0.75 5.625 rounded nS.) (12) differential clock cross point voltage where input timing measurement referenced. (13) magnitude difference between input level input level. (14) VISO means {VICK(CLK)+VICK( )}/2. (15) Refer figure below.
VICK VID(AC) VICK VICK VICK
VID(AC)
Differential
VISO VISO(min) VISO(max)
(16) tDQSCK depend clock jitter. These timing measured stable clock.
Preliminary W942504AH
OPERATION MODE
following table shows operation commands.
Simplified Truth Table
A12, SYM. COMMAND DEVICE STATE Idle(3) Any(3) Active(3) Active(3) Active(3) Active Idle Idle Active Idle Idle Idle (Self Refresh) Idle/Active(5) (Power Down) Active Active
CKEN-1
CKEN
DM(4)
BS0,
A11, A9-A0
PREA WRIT WRITA READ READA EMRS AREF SELF SELEX
Bank Active Bank Precharge Precharge Write Write with Auto Precharge Read Read with Auto Precharge Mode Register Extended Mode Regiser Operation Burst Read Device Deselect Auto Refresh Self Refresh Self Refresh Exit Power down mode entry Power down mode exit Data Data write write
PDEX Notes: Valid
Don't Care
level
High level
CKEn signal input level when commands issued. CKEn-1 signal input level clock cycle before commands issued. These state designated BS0, signals. LDM, (W942516AH) Power Down Mode entry burst cycle.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Function Truth Table (Note
CURRENT STATE
ADDRESS
COMMAND
ACTION
NOTES
Idle
Op-Code Op-Code Op-Code Op-Code
NOP/BST READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS NOP/BST READ/READAA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS
ILLEGAL ILLEGAL activating Refresh Self refresh Mode register accessing Begin read: Determine Begin write: Determine ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst Continue burst Burst stop Term burst, read: Determine ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst Continue burst ILLEGAL Term burst, start read: Determine Term burst, start read: Determine ILLEGAL Term burst. precharging ILLEGAL ILLEGAL
active
Read
Write
Preliminary W942504AH
Function Truth Table, continued CURRENT STATE
ADDRESS
COMMAND
ACTION
NOTES
Read with auto prechange
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS
Continue burst Continue burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst Continue burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop-> Idle after Nop-> Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop-> Idle after ILLEGAL ILLEGAL Nop-> active after tRCD Nop-> active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Op-Code Op-Code Op-Code Op-Code
Write with auto precharge
Precharging
activating
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Function Truth Table, continued CURRENT STATE
ADDRESS BS,A10 Op-Code Op-Code
COMMAND
ACTION Nop->ROW active after Nop->ROW active after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Enter precharge after Nop->Enter precharge after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Idle after Nop->Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop->Row after tMRD Nop->Row after tMRD ILLEGAL ILLEGAL ILLEGAL
NOTES
Write recovering
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/ EMRS READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS
Write recovering with auto precharge
Refreshing
Mode register accessing
Notes: entries assume that active (High level) during preceding clock cycle current clock cycle. Illegal bank idle. Illegal bank specified states; Function legal bank indicated Bank Address (BS), depending state that bank. Illegal tRCD satisfied. Illegal tRAS satisfied. Must satisfy burst interrupt condition. Must avoid contention, turn around, and/or satisfy write recovery requirements. Must mask preceding data which don't satisfy Remark: High level, level, High level (Don't care), Valid data
Preliminary W942504AH
Function Truth Table
CURRENT STATE INVALID Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after Maintain power down mode Refer Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer Function Truth Table
ADDRESS
ACTION
NOTES
Self refresh
Power Down
banks idle
Active
state other than listed above
Notes:
Self refresh enter only from banks idle state. Power down enter only from bank idle active state.
Remark:
High level, level, High level (Don't care), V=Valid data
Publication Release Date: August 2001 Revision
Preliminary W942504AH
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
SREF SREFX
IDLE
MRS/EMRS
MODE REGISTER
AREF
AUTO REFRESH
PDEX
ACTIVE POWERDOWN POWER DOWN
PDEX
ACTIVE
Read Read
Write
Write
Read
Write Read
Write Write
Read Read Read
Write
Read
POWER APPLIED
POWER
CHARGE
Automatic Sequence Command Sequence
Preliminary W942504AH
FUNCTIONAL DESCRIPTION
Power Sequence
Apply power attempt state 0.2V), other inputs undefined Apply before same time VDDQ. Apply VDDQ before same time VREF. Start Clock maintain stable condition 200µS(min). After stable power clock, apply take high. Issue EMRS (Extended Mode Register Set) enable establish Output Driver Type. Issue (Mode Register Set) reset device idle with additional cycles(min) clock required Lock) Issue precharge command banks device. Issue more Auto Refresh commands. Issue MRS-Initialize device operation. device operation mode sequence sequence skipped.)
Command Function
Bank Activate Command
"L", "H", "H", BS0, Bank, Address) Bank Activate command activates bank designated (Bank address) signal. addresses latched when this command issued cell data read sense amplifiers. maximum time that each bank held active state specified tRAS (max). After this command issued, Read Write operation executed.
Bank Precharge Command
"L", "H", "L", BS0, Bank, "L", A11, Don't care) Bank Precharge command percharges bank designated precharged bank switched from active state idle state.
Precharge Command
"L", "H", "L", BS0, Don't care, "H", A11, Don't care) Precharge command precharges banks simultaneously. Then banks switched idle state.
Write Command
"H", "L", "L", BS0, Bank, "L", Column Address) write command performs Write operation bank designated write data latched both edges DQS. length write data (Burst Length) column Publication Release Date: August 2001 Revision
Preliminary W942504AH
access sequence (Addressing Mode) must Mode Register power-up prior Write operation.
Write with Auto Precharge Command
"H", "L", "L", BS0, Bank, "H", Column Address) Write with Auto Precharge command performs Precharge operation automatically after Write operation. This command must interrupted other commands.
Read Command
"H", "L", "H", BS0, Bank, "L", Column Address) Read command performs Read operation bank designated read data synchronized with both edges DQS. length read data (Burst Length), Addressing Mode Latency (access time from command clock cycle) must programmed Mode Register power-up prior Read operation.
Read with Auto Precharge Command
"H", "L", "H", BS0, Bank, "H", Column Address) Read with Auto precharge command automatically performs Precharge operation after Read operation. READA tRAS (min) (BL/2) Internal precharge operation begins after BL/2 cycle from Read with Auto Precharge command. tRCD(min) READA tRAS(min) (BL/2) Data read with shortest latency, internal Precharge operation does begin until after tRAS (min) completed. This command must interrupted other command.
Mode Register Command
"L", "L", "L", "L", "L", Register Data) Mode Register command programs values latency, Addressing Mode, Burst Length reset Mode Register. default values Mode Register after power-up undefined, therefore this command must issued during power-up sequence. Also, this command issued while banks idle state. Refer table specific codes.
Extended Mode Register Command
"L", "L", "L", "H", "L", Register data) Extended Mode Register command implemented needed function extensions standard (SDR-SDRAM). Currently only available mode EMRS enable/disable, decoded default value extended mode register defined;
Preliminary W942504AH
therefore this command must issued during power-up sequence enabling DLL. Refer table specific codes.
No-Operation Command
"H", "H", "H") No-Operation command simply performs operation (same command Device Deselect).
Burst Read Stop Command
"H", "H", "L") Burst stop command used stop burst operation. This command only valid during Burst Read operation.
Device Deselect Command
"H") Device Deselect command disables command decoder that Address inputs ignored. This command similar No-Operation command.
Auto Refresh Command
"L", "L", "H", "L", BS0, BS1, Don't care) Auto Refresh command used refresh address provided internal refresh counter. Refresh operation must performed 8192 times within next command issued after tREF from Auto Refresh command. When Auto Refresh command used, banks must idle state.
Self Refresh Entry Command
"L", "L", "H", "L", BS0, BS1, Don't care) Self Refresh Entry command used enter Self Refresh mode. While device Self Refresh mode, input output buffer (except buffer) disabled Refresh operation automatically performed. Self Refresh mode exited taking "high" (the Self Refresh Exit command). During self refresh, DLLl disable.
Self Refresh Exit Command
(CKE "H", "H", "H", "H") This command used exit from Self Refresh mode. subsequent commands issued after tXSNR (tXSRD Read Command) from this command.
Data Write Enable /Disable Command
"L/H" LDM, "L/H") During Write cycle, LDM, signal functions Data Mask control every word input data. signal controls signal controls DQ15.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Read Operation
Issuing Bank Activate command idle bank puts into active state. When Read command issued after tRCD from Bank Activate command, data read sequentially, synchronized with both edges (Burst Read operation). initial read data becomes available after latency from issuing Read command. latency must Mode Register power-up. When Precharge Operation performed bank during Burst Read operation, Burst operation terminated. When Read with Auto Precharge command issued, Precharge operation performed automatically after Read cycle, then bank switched idle state. This command cannot interrupted other commands. Refer diagrams Read operation.
Write Operation
Issuing Write command after tRCD from bank activate command. input data latched sequentially, synchronizing with both edges(rising &falling) after Write command (Burst write operation). burst length Write data (Burst Length) Addressing Mode must Mode Register power-up. When Precharge operation performed bank during Burst Write operation, Burst operation terminated. When Write with Auto Precharge command issued, Precharge operation performed automatically after Write cycle, then bank switched idle state, Write with Auto Precharge command cannot interrupted other command entire burst data duration. Refer diagrams Write operation.
Precharge
There Commands, which perform precharge operation (Bank Precharge Precharge All). When Bank Precharge command issued active bank, bank precharged then switched idle state. Bank Precharge command precharge bank independently other bank hold unprecharged bank active state. maximum time each bank held active state specified tRAS (max). Therefore, each bank must precharged within tRAS(max) from bank activate command. Precharge command used precharge banks simultaneously. Even banks active state, Precharge command still issued. this case, Precharge operation performed only active bank precharge bank then switched idle state.
Burst Termination
When Precharge command used bank Burst cycle, Burst operation terminated. When Burst Read cycle interrupted Precharge command, read operation disabled after clock cycle latency) from Precharge command. When Burst Write cycle interrupted Precharge command input circuit reset same clock cycle which precharge command issued. this case, signal must asserted "high": during prevent writing invalided data cell array.
Preliminary W942504AH
When Burst Read Stop command issued bank Burst Read cycle, Burst Read operation terminated. Burst read Stop command supported during write burst operation. Refer diagrams Burst termination.
Refresh Operation
types Refresh operation performed device: Auto Refresh Self Refresh. repeating Auto Refresh cycle, each bank turn refreshed automatically. Refresh operation must performed 8192 times (rows) within period between Auto Refresh command next command specified tRFC. Self Refresh mode enter issuing Self Refresh command (CKE asserted "low"). while banks idle state. device Self Refresh mode long held "low". case 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must performed within 7.8us before entering after exiting Self Refresh mode. case distributed Auto Refresh commands, distributed auto refresh commands must issued every last distributed Auto Refresh commands must performed within 7.8us before entering self refresh mode. After exiting from Self Refresh mode, refresh operation must performed within Self Refresh mode, input/output buffers disable, resulting lower power dissipation (except buffer). Refer diagrams Refresh operation.
Power Down Mode
types Power Down Mode performed device: Active Standby Power Down Mode Precharge Standby Power Down Mode. When device enters Power Down Mode, input/output buffers disabled resulting power dissipation (except buffer). Power Down Mode enter asserting "low" while device running burst cycle. Taking CKE: "high" exit this mode. When goes high, operation command must input next rising edge. Refer diagrams Power Down Mode.
Mode Register Operation
mode register programmed Mode Register command (MRS/EMRS) when banks idle state. data Mode Register transferred using BS0, address inputs. Mode Register designates operation mode read write cycle. register divided into five filed: Burst Length field length burst data Addressing Mode selected designate column access sequence Burst cycle Latency field assess time clock cycle reset field reset Regular/Extended Mode Register filed select type (Regular/Extended MRS). EMRS cycle implemented extended function (DLL enable/Disable mode) initial value Mode Register (including EMRS) after power undefined; therefore Mode Register command must issued before power operation.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Burst Length field
This field specifies data length column access using pins sets Burst Length words. Burst Length Reserved words words words Reserved
Addressing Mode Select (A3)
Addressing Mode modes; Interleave mode Sequential Mode, When "0", Sequential mode selected. When "1", Interleave mode selected. Both addressing Mode support burst length words. Address sequence Sequential mode column access performed incrementing column address input device. address varied Burst Length following. Addressing Sequence Sequential Mode DATA Data Data Data Data Data Data Data Data ACCESS ADDRESS words(address bits carried from BURST LENGTH words (address bits carried from words (address carried from Addressing mode Sequential Interleave
Preliminary W942504AH
Addressing sequence Interleave mode Column access started from inputted column address performed interleaving address bits sequence shown following. Address Sequence Interleave Mode DATA Data Data Data Data Data Data Data Data ACCESS ADDRESS words words BURST LENGTH words
Latency field
This field specifies number clock cycles from assertion Read command first data read. minimum values Latency depends frequency CLK. Latency Reserved Reserved Reserved Reserved Reserved Reserved
Reset (A8)
This used reset DLL. When "1", reset.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Mode Register /Extended Mode register change bits (BS0, BS1)
These bits used select MRS/EMRS. A12-A0 Regular cycle Extended cycle Reserved
Extended Mode Register field
Switch field (A0) This used select enable disable Output Driver Size Control field (A1) This used select Output Driver Size, both Full strength Half strength based JEDEC standard. Output Driver Full strength Half strength Enable Disable
Reserved field
Test mode entry (A7) This used enter Test mode must normal operation. Reserved bits (A9, A10, A11, A12) These bits reserved future operations. They must normal operation.
Preliminary W942504AH
TIMING WAVEFORMS
Command Input Timing
A0~A12 BS0,
Refer Command Truth Table
Timing Signals
VIH(AC) VIL(AC)
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
Read Timing (Burst Length
READ
tDQSCK tDQSCK tRPST Hi-Z tDQSQ tDQSQ
latency=2 Hi-Z
tDQSCK tRPRE
Preamble
Postamble tDQSQ Hi-Z
Output (Data)
Hi-Z
tDQSCK
tDQSCK
tDQSCK latency=2.5 Hi-Z Preamble tDQSQ Output (Data) Hi-Z tDQSQ tRPRE
tRPST Hi-Z
Postamble tDQSQ Hi-Z
Note: correspondence LDQS, UDQS W942516AH) LDQS UDQS DQ0~7 DQ8~15
Preliminary W942504AH
Timing Waveforms, continued
Write Timing (Burst Length
WRIT
tDSH
tDSS
tDSH
tDSS
device
tWPRES tWPRE
tDQSH
tDQSL
tDQSH
tWPST
Preamble Input (Data) tDQSS device tWPRES tWPRE LDQS Preamble tDSSK tDSSK tDSSK Postamble tDSH tDQSH tDSS tDQSL Postamble tDSH tDQSH tDSS tWPST
DQ0~7
tDQSS tDSSK
tDSH tWPRES tWPRE UDQS Preamble tDQSH
tDSS tDQSL
tDSH tDQSH
tDSS tWPST
Postamble
DQ8~15
tDQSS tDSH
Note: 2DQS's (UDQS uper byte LDQS lower byte).Even bytes used, both UDQS LDQS must toggled.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
DATA MASK (W942508AH /W942504AH)
/CLK
WRIT
tDIPW
Masked
tDIPW
DATA MASK (W942516AH)
/CLK
WRIT
LDQS
DIPW
DQ0~
Masked DIPW
UDQS
tDIPW
DQ8~ DQ15
Masked
tDIPW
Preliminary W942504AH
Timing Waveforms, continued
Mode Register (MRS) Timing
tMRD
NEXT
Register data
Addressing Mode Burst Length Reserved Reserved Reset Latency Mode Register Extended Mode Register "Reserved" should stay during cycle.
Burst Length Sequential Reserved Interleaved Reserved
Reserved
Reserved
Addressing Mode Sequential Interleaved Latency Reserved
Reserved
Reserved Reset EMRS Regular cycle Extended cycle Reserved
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
Extend Mode Register (EMRS) Timing
tMRD EMRS
NEXT
Register data
Reserved Mode Register Extended Mode Register Switch Output Driver
Switch Enable Disable
Output Driver Size Full Strength Hall Strength
EMRS Regular cycle Extended cycle
"Reserved" should stay during EMRS cycle.
Preliminary W942504AH
Timing Waveforms, continued
Auto Precharge Timing (Read Cycle,
tRCD (READA) tRAS (min) (BL/2)
tRAS BL=2 READA
BL=4 READA
BL=8
READA
Notes: shown; same command operation timing with this case, internal precharge operation begin after BL/2 cycle from READA command. represents start internal precharging Read with Auto precharge command cannot interrupted other command.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Auto Precharge Timing (Read Cycle, continued
tRCD/RAP(min) tRCD (READA) tRAS (min) (BL/2)
tRAS BL=2 tRAP tRCD
READA
BL=4 tRAP tRCD READA
BL=8 tRAP tRCD READA
Notes: shown; same command operation timing with this case internal precharge operation does begin until after tRAS (min) command.
represents start internal precharging
Read with Auto Precharge command cannot interrupted other command.
Preliminary W942504AH
Timing Waveforms, continued
Auto Precharge Timing (Write Cycle)
tDAL BL=2 WRITA
tDAL
BL=4 WRITA
tDAL
BL=8 WRITA
Write with Auto Precharge command cannot interrupted other command.
represents start internal precharging
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
Read interrupted Read
READ
READ
READ
READ
READ
tRCD
Address COl,Add,A
tCCD
Col,Add,B
tCCD
Col,Add,C
tCCD
Col,Add,D
tCCD
Col,Add,E
Burst Read Stop
READ
Latency=2
Latency
Latency=2.5
Latency
Preliminary W942504AH
Timing Waveforms, continued
Read Interrupted Write
Latency=2 READ WRIT
Latency=2.5 READ
WRIT
Burst Read cycle must terminated Command avoid conflict.
Read Interrupted Precharge
READ
Latency=2
Latency
Latency=2.5
Latency
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
Write Interrupted Write
WRIT
WRIT
WRIT
WRIT
WRIT
tRCD
Address
tCCD
COl. Add. Col.Add.B
tCCD
tCCD
tCCD
Col. Add.
Col. Add.
Col. Add.
Write Interrupted Read
WRIT
READ
tWTR
Data must masked
Data masked READ command, input ignored.
Preliminary W942504AH
Timing Waveforms, continued
Write Interrupted Read
WRIT
READ
tWTR
Data must masked
Write Interrupted Precharge
WRIT
Data must masked
Data masked command, input ignored.
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
Bank Interleave Read Operation
tRC(b) tRC(a) tRRD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) READAa
tRRD READAb ACTa ACTb
tRP(a) tRP(b)
Preamble CL(a)
Postamble
Preamble
Postamble
CL(b)
ACTa/b Bank Act. bank READAa/b Read with Auto Pre.CMD bank APa/b Auto Pre. bank
Bank Interleave Read Operation
tRC(b) tRC(a) tRRD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb
Preamble CL(a)
Postamble CL(b)
ACTa/b Bank Act. bank READAa/b Read with Auto Pre.CMD bank APa/b Auto Pre. bank
Preliminary W942504AH
Timing Waveforms, continued
Bank Interleave Read Operation
tRC(a) tRRD tRRD tRRD tRRD
ACTa
ACTb tRCD(a) tRAS(a)
ACTc
READAa
ACTd
READAb
ACTa
READAc
tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d)
Preamble CL(a) CL(b)
Postamble Preamble
ACTa/b/c/d Bank Act. bank a/b/c/d READAa/b/c/d Read with Auto Pre.CMD bank a/b/c/d APa/b/c/d Auto Pre. bank a/b/c/d
Bank Interleave Read Operation
tRC(a) tRRD tRRD tRRD tRRD
ACTa tRCD(a)
ACTb
READAa
ACTc
READAb
ACTd
READAc
ACTa
READAd
tRAS(a) tRCD(b) tRAS(b) tRCD(c) tRAS(c)
tRP(a)
tRCD(d) tRAS(d)
Preamble CL(a)
CL(b) CL(c)
CL(b)
ACTa/b/c/d Bank Act. bank a/b/c/d READAa/b/c/d Read with Auto Pre.CMD bank a/b/c/d APa/b/c/d Auto Pre. bank a/b/c/d
Publication Release Date: August 2001 Revision
Preliminary W942504AH
Timing Waveforms, continued
Auto Refresh Cycle
PREA
AREF
AREF
tRFC
tRFC
kept "High" level Auto-Refresh cycle.
Active Power Down Mode Entry Exit Timing
Entry
Exit
Precharged Power Down Mode Entry Exit Timing
Entry
Exit
Preliminary W942504AH
Timing Waveforms, continued
Self Refresh Entry Exit Timing
PREA
SELF
SELFX
Entry
Exit
tXSRD tXSRD
SELF
SELFX
READ
Entry
Exit
Publication Release Date: August 2001 Revision
Preliminary W942504AH
PACKAGE DIMENSION
TSOP
Preliminary W942504AH
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, Creation III, Kwun Tong Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: -27513100 TEL: 886-3-5770066 FAX: -27552064 FAX: -3-5792766 http://www.winbond.com.tw/ Voice Fax-on-demand: -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 First Street, Jose, 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, 115, Sec. -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: -2-27197502
Note: data specifications subject change without notice.
Publication Release Date: August 2001 Revision
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