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LUC4AC01 ACrossbar Element (ACE)
part ATLANTA chip consisting four devices that provide highly integrated, innovative, complete VLSI solution implementing Alayer core Aswitch system. chip enables construction high-performance, feature-rich, cost-effective Aswitches, scalable over wide range switching capacities. This document discusses device.
Facilitates circuit board testing with on-chip IEEE standard boundary scan. Low-power monolithic fabricated CMOS technology, with tolerant TTLlevel compatible I/O. Available 352-pin PBGA package.
Description
Figure shows architecture Aswitch designed with ATLANTA chip set. This document summarizes ATLANTA switch fabrics LUC4AC01 ACrossbar Element (ACE). ATLANTA device provides switching crossbar function three-stage Aswitch fabric. This crossbar element building block larger scalable three-stage switch fabrics OC-12 equivalent ports, Gbits/s systems). interfaces directly ATLANTA LUC4AS01 ASwitch Element (ASX) device used linking switch elements. Nonblocking, lossless, self-routing switch fabrics constructed using ATLANTA chip set. Each configurable provide four crossbars configuration, crossbars configuration, single crossbar configuration. supports novel internal backpressure routing algorithms companion device provides fail-safe access output ports. also provides system diagnostic features. Diagnostic reports include parity errors inputs, loss input port clock.
Features
Functions highly efficient, Gbits/s, Acrossbar element. Allows construction nonblocking, lossless, self-routing three-stage switch fabrics. Supports variable configurations more compact fabric design with higher port density. Each programmed provide crossbars different sizes. Supports port speeds Mbits/s Atraffic. Incorporates independent clocking input ports facilitate robust system designs eliminating clock trees allowing varied clock skews. Uses differential clocking provide noise immunity. Provides system diagnostic features, including detection reporting following error conditions: Input port parity error. Loss input port clock. Supports generic Intel* Motorola compatible 16-bit microprocessor interface with interrupt.
Intel registered trademark Intel Corporation. Motorola registered trademark Motorola, Inc.
IEEE registered trademark Institute Electrical Electronics Engineers, Inc.
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Section
LUC4AC01 ACrossbar Element (ACE)
Description (continued)
INGRESS DIRECTION EGRESS DIRECTION
PORTS
SRAM
SRAM LUC4AS01 LUC4AS01 REDUNDANT BACKPLANE SWITCH FABRIC MICROPROCESSOR INTERFACE LUC4AC01 LUC4AS01 LUC4AC01 LUC4AS01
LUC4AU01
LUC4AB01
MICROPROCESSOR INTERFACE LINE CARD PHYSICAL LAYER INTERFACE (MPHY) BACKPLANE SRAM
PORTS SRAM
LUC4AS01
LUC4AC01
LUC4AS01
LUC4AU01 LUC4B01
LUC4AS01 LUC4AC01 LUC4AS01
MICROPROCESSOR INTERFACE LINE CARD
MICROPROCESSOR INTERFACE REDUNDANT SWITCH FABRIC
5-4554r9
Section
Figure Architecture ASwitch Using ATLANTA Chip
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Lucent Technologies Inc.
LUC4AC01 ACrossbar Element (ACE)
Description (continued)
block diagram brief description functionality each block follows.
INGRESS PORTS
INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR INPUT PROCESSOR SOURCE ARBITER
OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR OUTPUT PROCESSOR
EGRESS PORTS
(DATA) (PARITY) (START CELL) (CLOCK)
(DATA) (PARITY) (START CELL) (CLOCK)
GTSYNC SYSTEM CLOCK (GCLK) GRANT_n
CLOCKING SYNCHRONIZATION FEEDBACK GENERATION
BACKPRESSURE FROM THIRD-STAGE (F3T2 F3T2CLK) RESET (GRST) OUTPUT ENABLE (ACEOE)
MICROPROCESSOR INTERFACE
CONFIGURATION STATUS REGISTERS
TEST ACCESS PORT (JTAG)
TEST ACCESS PORT
5-4515Br6
Figure Block Diagram
Lucent Technologies Inc.
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Section
LUC4AC01 ACrossbar Element (ACE)
staging devices referred three-stage switch fabric. input stage called first stage (expander), output stage called third stage (concentrator). functionally similar ASX, without internal cell buffer handshake protocol between ensures that need store data). Conceptually, first stage expands number paths available switching data, while third stage concentrates data from center stage. three-stage ASX/ACE based switch fabric support ports with Mbits/s rates. 40-port Gbits/s total Athroughput) fabric design would eight devices stage expansion mode.
Description (continued)
Overview
shown Figure data each port clocked into input processor, then routed appropriate output processor. routing arbitration circuit, backpressure feedback generation circuit control movement data into crossbar elements. Control status communicated through 16-bit asynchronous microprocessor interface. Figure shows example ATLANTA-based switch fabric. switch fabric will switch inputs outputs. This achieved
FIRST-STAGE EXPANDER
CENTER-STAGE CROSSBAR
THIRD-STAGE CONCENTRATOR
MODULE
MODULE
MODULE
MODULE INPUT FROM PORT CARDS
MODULE
MODULE OUTPUT PORT CARDS
Section
MODULE
MODULE
MODULE
MODULE
MODULE
MODULE
5-4523R5
Figure Example Mbits/s Switch Fabric Gbits/s throughput)
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Lucent Technologies Inc.
LUC4AC01 ACrossbar Element (ACE) Microprocessor Interface
microprocessor interface (MPI) provides general 16-bit asynchronous interface external processor accessing configuration status registers internal memory. also supports perfunction, maskable interrupts. interface operates identically interface ALM, ABM, ASX. designed support various 16-bit microprocessors with minimal glue logic, directly interface popular Intel Motorola microprocessors.
Description (continued)
Input Processors
input processors responsible accepting data into device. There eight input processors, each port. Each input port eight data bits, parity bit, start cell bit, differential clock. microprocessor must enable appropriate input ports. input processor shifts data checks parity. Input ports clocked independently. input port interface designed minimize risk undetected errors. differential clock provides system noise immunity prevent errors. addition, input processor detects presence input clock reports when input clock lost. input processor also checks incoming parity errors. Parity errors loss clock reported through microprocessor interface.
Test Access Port
incorporates logic support standard fivepin test access port (TAP), compatible with IEEE P1149.1 standard (JTAG), used boundary scan. contains instruction registers, data registers, control logic, instructions. controlled externally JTAG master. gives board-level test capability.
Output Processors
output processors perform opposite functions input processors. They handle shifting data. microprocessor disable output port.
Source Arbiter
source arbiter arbitrates access crossbar outputs center-stage module. source arbiter receives requests from first-stage modules. source arbiter then determines which these requests granted denied, taking into consideration output contention center-stage congestion third-stage modules switch fabric.
Lucent Technologies Inc.
LUCENT TECHNOLOGIES-PROPRIETARY pursuant Company Instructions
Section
LUC4AC01 ACrossbar Element (ACE)
additional information, contact your Microelectronics Group Account Manager following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18103 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 8833, (65) 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 5421 1600, (81) 5421 1700 data requests Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 299, (44) 1734 technical inquiries Europe: CENTRAL EUROPE: (49) 95086 (Munich), NORTHERN EUROPE: (44) 1344 (Bracknell UK), FRANCE: (33) (Paris), SOUTHERN EUROPE: (39) 6601 1800 (Milan) (34) 1700 (Madrid)
Lucent Technologies Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. rights under patent accompany sale such product(s) information.
Copyright 1997 Lucent Technologies Inc. Rights Reserved Printed U.S.A.
March 1997 PN96-066APrinted Recycled Paper

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