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10GbE XGXS
Home Products Intellectual Property Lattice Cores 10GbE XGXS
10GbE XGXS
Overview
Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables creation system solutions Gigabit Ethernet GbE) applications defined IEEE 802.3ae. This Core targets programmable array section ORCA ORT82G5 FPSC provides bridging function between Gigabit Media Independent Interface (XGMII) Gigabit Attachment Unit Interface (XAUI) devices. ORT82G5 high-speed transceiver with aggregate bandwidth 29.6 Gbits/s that targeted towards users need high-speed backplane chip-to-chip interfaces using Ethernet Fibre-Channel based protocols. ORT82G5 eight channels integrated 0.6-3.7 Gbits/s SERDES channels that used 2x10 Gbits/s XAUI interfaces. XAUI high-speed interconnect that offers reduced count specified drive inches trace standard FR-4 material. Each XAUI interface comprises four self-timed 8b/10b encoded serial lanes each operating 3.125 Gbits/s thus capable transferring data aggregate rate Gbits/s. XGMII 156MHz Double Data Rate (DDR), parallel, short-reach interconnect interface (typically less than inches). supports interfacing 10Gb/s Ethernet Media Access Control (MAC) devices. this design, XGXS core implemented FPGA portion device. packet generator/checker MDIO interface also implemented FPGA logic. XGXS core provided with implementation scripts, test benches, documentation allow users integrate functions LAN/WAN applications.
Features
Complete 10Gb Ethernet Extended Sublayer (XGXS) Solution Based ORCA ORT82G5 0.6-3.7 Gbit/s 8b/10b Backplane Interface FPSC.
5/30/2006
10GbE XGXS
Page
Targeted ORT82G5 Programmable Array Section Implements Functionality Conforming IEEE Standard 802.3ae, Including: Media Independent Interface (XGMII). Slip buffers clock domain transfer to/from XGMII interface. Complete translation between XGMII XAUI layers, including 8b/10b encoding decoding Idle, Start, Terminate, Error Sequence code groups sequences, randomized Idle generation XAUI transmit direction. 64-bit data/8-bit control packet generator/checker XGMII side that supports standard compliant CRPAT CJPAT generation checking XAUI interoperability testing. Standard compliant MDIO/MDC interface. Automatic initialization synchronization embedded core. Interface with high-speed SERDES block embedded ORT82G5 that implements standard XAUI. XAUI Functionality Supported Embedded Portion ORT82G5, Including: Eight channels 3.125 Gbits/s serializer/deserializer with 8b10b encoding/decoding (four SERDES channels used this application). XAUI compliant lane-by-lane synchronization. Lane deskew functionality.
Evaluation Configurations
Core Performance Utilization1 Core Configuration xgbe_xgxs_o4_2_002
ORCA4 PFUs LUTs Registers Blocks fMAX (MHz) 2247 5899
Results generated with ispLEVERv.4.2 targeting ORT82G5-3, BM680. numbers include wrapper logic.
Ordering Information
Part Numbers: ORCA XGBE-XGXS-O4-N2 find purchase 10GbE XGXS Core, please contact your local Lattice Sales Office.
5/30/2006

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