KS8721B/BT 2.5V 10/100BasTX/FX Physical Layer Transceiver Rev.

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

KS8721B/BT 2.5V 10/100BasTX/FX Physical Layer Transceiver Rev.

Datasheet Thumbnail

Top Searches for this datasheet

KS8721B/BT
KS8721B/BT
2.5V 10/100BasTX/FX Physical Layer Transceiver Rev.
General Description
Operating volts meet voltage power requirements, KS8721B/BT 10BaseT/100BaseTX/ Physical Layer Transceiver, which provides transmit receive data. contains 10BaseT Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), Physical Coding Sub-layer (PCS) functions. Moreover, KS8721B/BT on-chip 10BaseT output filtering, which eliminates need external filters allows single line magnetics used meet requirements both 100BaseTX 10BaseT. KS8721B/BT automatically configure itself Mbps full half duplex operation, using on-chip AutoNegotiation algorithm. ideal choice physical layer transceiver 100BaseTX/10BaseT applications. Data sheets support documentation found Micrel's site www.micrel.com.
Features
Single chip 100BaseTX/100BaseFX/10BaseT physical layer solution 2.5V CMOS design, power consumption <200mW (excluding output driver current Fully compliant IEEE 802.3u standard Supports Media Independent Interface (MII) Reduced (RMII) Supports 10BaseT, 100BaseTX 100BaseFX with Far_End_Fault Detection Supports power down mode power saving mode Configurable through serial management ports external control pins Supports auto-negotiation manual selection 10/100Mbps speed full/half-duplex mode On-chip built-in analog front filtering both 100BaseTX 10BaseT
Functional Diagram
TXTransmitter
10/100 Pulse Shaper
NRZ/NRZI MLT3 Encoder
4B/5B Encoder Scrambler Parallel/Serial Parallel/Serial Manchester Encoder MII/RMII Registers Controller Interface
TXD3 TXD2 TXD1 TXD0 TXER TXEN MDIO RXD3 RXD2 RXD1 RXD0 RXER RXDV
Adaptive Base Line Wander Correction MLT3 Decoder NRZI/NRZ
Clock Recovery
4B/5B Decoder Descrambler Serial/Parallel
Auto Negotiation 10BaseT Receiver Power Down Saving PWRDWN Manchester Decoder Serial/Parallel
LINK Driver
Micrel, Inc. 2180 Fortune Drive Jose, 95131 (408) 944-0800 (408) 474-1000 http://www.micrel.com
April 2005
M9999-041405
KS8721B/BT
Features (continued)
outputs link, activity, full/half duplex, collision speed Supports back back, media converter applications Supports MDI/MDI-X auto crossover 2.5V/3.3V tolerance Commercial temperature range: +70°C Industrial temperature range: -40°C +85°C Available 48-pin SSOP TQFP
Ordering Information
Part Number KS8721B KS8721BI KSZ8721B KS8721BT KSZ8721BT Temperature Range +70°C -40°C +85°C +70°C +70°C +70°C Package 48-Pin SSOP 48-Pin SSOP 48-Pin SSOP Lead Free 48-Pin TQFP 48-Pin TQFP Lead Free
M9999-041405
April 2005
KS8721B/BT
Revision History
Revision Date 2/29/02 4/01/02 Summary Changes Document Origination (Preliminary) Update timing Spec from page page Change Revision from 1000 1001 control register bit, Control Register control transmit enable/disable register table Editorial Change FXSD/FXEN pin34 Change duplex pin38 0=half 1=full duplex Change 10BT transmit timing 1.0us 2.5us Tlat 2.5us TEST description mode pin26 part number ordering information remove pinout diagram Edited description cloumn Change company logo, disclaimer, contact info Editorial changes Stapping option description Change Register0h bit0, 1=disable 0=enable remote fault register4h bit13. normal operating condition table Thermal data SSOP48 table Reset Timing table Transformer Lists TQFP pinout diagram RMII Charateristics ordering info TQFP package, KS8721B/BTI industrial temperature, KSY8721B/KSY8721BT environmentally friendly part number Change part number from KS8721B KS8721B/BT. Change ordering info. from "KSY" "KSZ" lead free. Change name from RMII_LPBK RMII_BTB Convert format. MDIO pull-up resistor value changed 4.7k. Added note strapping option pins. Updated 1b.0 1b.7 self-clearing. Updated Electrical Characteristic. Updated 1f4:2 resetted. Added additional magnetics qualified transformer. Added reset reference circuit. Added RMII timing specification.
1/31/03
8/29/03
1/24/04
3/16/05
April 2005
M9999-041405
KS8721B/BT
Table Contents
Description Strapping Option Configuration Introduction 100BaseTX Transmit 100BaseTX Receive Clock Synthesizer Scrambler/De-scrambler (100BaseTX only) 10BaseT Transmit 10BaseT Receive Jabber Function (10Base only) Auto-Negotiation Management Interface Data Interface Transmit Clock Receive Clock Transmit Enable Receive Data Valid Error Signals Carrier Sense Collision RMII Signal Definition Reference Clock Carrier Sense/Receive Data Valid Receive Data Transmit Enable Transmit Data Collision Detection RX_ER RMII Characteristics Auto Crossover (Auto MDI/MDI-X) Power Management 100BT Mode Media Converter Option Register Register Basic Conrol Register Basic Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability Register 15h: RXER Counter Register 1bh: Interrupt Control/Status Register Register 1fh: 100BaseTX Controller
M9999-041405
April 2005
KS8721B/BT
Micrel, Inc.
Absolute Maximum Ratings Operating Ratings Electrical Characteristics Timing Diagrams Selection Isolation Transformers Selection Reference Crystals Package Outline Dimensions
April 2005
M9999-041405
KS8721B/BT
Description
Number Name MDIO RXD3/ PHYAD1 Type(Note Ipd/O Function Management Interface (MII) Data I/O: This requires external 4.7K pull-up resistor. Management Interface (MII) Clock Input: This synchronous MDIO data interface Receive Data Output: [3.0], these bits synchronous with RXCLK. When RXDV asserted, [3.0] presents valid data through MII. [3.0] invalid when RXDV de-asserted. pull-up/pull-down value latched PHYADDR during reset. "Strapping Options" section details. Receive Data Output: pull-up/pull-down value latched PHYADDR during reset. "Strapping Options" section details. Receive Data Output: pull-up/pull-down value latched PHYADDR during reset. "Strapping Options" section details. Receive Data Output: pull-up/pull-down value latched PHYADDR during reset. "Strapping Options" section details. Digital /3.3V tolerance power supply. Ground. Receive Data Valid Output: pull-up/pull-down value latched pcs_lpbk during reset. "Strapping Options" section details. Receive Clock Output: Operating 25MHz 100Mbps, 2.5MHz 10Mbps. Receive Error Output: pull-up/pull-down value latched ISOLATE during reset. "Strapping Options" section details. Ground. Digital core 2.5V only power supply. Transmit Error Input. Transmit Clock Output: RMII Reference Clock Input. Transmit Enable Input Transmit Data Input Transmit Data Input Transmit Data Input Transmit Data Input Collision Detect Output: pull-up/pull-down value latched RMII select during reset. "Strapping Options" section details. Digital 2.5/3.3V tolerance power supply.
RXD2/ PHYAD2 RXD1/ PHYAD3 RXD0/ PHYAD4 VDDIO RXDV/ CRSDV/ PCS_LPBK RXER/ISO VDDC TXER TXC/ REFCLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII VDDIO
Ipd/O Ipd/O Ipd/O Ipd/O
Note
Ipd/O Ipu/O Ipd/O
power supply ground input output bi-directional ground input internal pull-up input internal pull-down Ipd/O input internal pull-down during reset, output otherwise Ipu/O input internal pull-up during reset, output otherwise strap pull-up strap pull-down connect
M9999-041405
April 2005
KS8721B/BT
Number Name INT#/ PHYAD0 CRS/ RMII_BTB LED0/TEST Type(Note Ipu/O Ipd/O Function
Management Interface (MII) Interrupt Out: Latched PHYAD[0] during power /reset. "Strapping Options" section details. Carrier Sense Output: pull-up/pull-down value latched RMII during reset when RMII mode selected. "Strapping Options" section details. Ground. Link/Activity Output: Lnk/Act Link Link State Definition "off" "on" "Toggle"
Ipu/O
external pull-down enable test mode only used factory test. LED1/ SPD100/ noFEF Ipu/O Speed Output: Latched SPEED (Register during power-up/reset. "Strapping Options" section details. Speed 10BT 100BT LED2/ DUPLEX Ipu/O State Definition "off" "on"
Full-duplex Output: Latched DUPLEX (register during power-up/ reset. "Strapping Options" section details. Duplex Half Full State Definition "off" "on"
LED3/ NWAYEN
Ipu/O
Collision Output: Latched ANEG_EN (register during power-up/ reset. "Strapping Options" section details. Collison Collision Collision State Definition "off" "on"
Note
VDDRX RXRX+ FXSD/FXEN
Ipd/O
Power Down. Normal operation, 0=Power down, Active low. Analog 2.5V power supply. Receive Input: Differential receive input pins 100BaseTX 10BaseT. Receive Input: Differential receive input 100BaseTX 10BaseT. Fiber Mode Enable Signal Detect Fiber Mode. FXEN mode disable. default "0". "100BT Mode" section more details. Ground. Ground.
power supply ground input output bi-directional input internal pull-up input internal pull-down Ipd/O input internal pull-down during reset, output otherwise Ipu/O input internal pull-up during reset, output otherwise strap pull-up strap pull-down connect
April 2005
M9999-041405
KS8721B/BT
Number
Note
Name REXT VDDRCV TXTX+ VDDTX VDDPLL RST# Type(Note Function External resistor (6.49k) connects REXT GNDRX. Analog 2.5V power supply. Ground Transmit Outputs: Differential transmit output 100BaseTX/FX 10BaseT. Transmit Outputs: Differential transmit output 100BaseTX/FX 10BaseT. Transmitter 2.5V power supply. Ground. Ground. XTAL feedback: Used with Xtal application. Crystal Oscillator Input: Input crystal external 25MHz clock Analog 2.5V power supply. Chip Reset: Active low, minimum 50µs pulse required
power supply ground input output bi-directional input internal pull-up input internal pull-down Ipd/O input internal pull-down during reset, output otherwise Ipu/O input internal pull-up during reset, output otherwise strap pull-up strap pull-down connect
M9999-041405
April 2005
KS8721B/BT
Strapping Options(Note
Number 6,5, 9(3) 11(3) 21(3) 22(3) Name PHYAD[4:1]/ RXD[0:3] PHYAD0/ INT# PCS_LPBK/ RXDV ISO/RXER RMII/COL RMII_BTB SPD100/ FEF/ LED1 DUPLEX/ LED2 NWAYEN/ LED3 Type(Note Ipd/O Ipu/O Ipd/O Ipd/O Ipd/O Ipd/O Ipu/O Enables PCS_LPBK mode power-up/reset. (default) Disable, Enable. Enables ISOLATE mode power-up/reset. (default) Disable, Enable. Enables RMII mode power-up/reset. (default) Disable, Enable. Enable RMII_BTB mode power-up/reset. (default) Disable, Enable. Latched into Register during power-up/reset. 10Mbps, (default) 100Mbps. SPD100 asserted during power-up/reset, this also latched Speed Support register FXEN pulled latched value means Far_End _Fault.) Latched into Register during power-up/reset. Half duplex, (default) Full duplex. Duplex pulled during reset, this also latched Duplex support register Nway (auto-negotiation) Enable. Latched into Register during power-up/ reset. Disable Auto-Negotiation, (default) Enable Auto-Negotiation. Power Down Enable. (default) Normal operation, Power down mode. Description Address latched power-up/reset. default address 00001.
Ipu/O
Note Note
Ipu/O
Strap-in latched during power-up reset. input internal pull-up input internal pull-down Ipd/O input internal pull-down during reset, output otherwise Ipu/O input internal pull-up during reset, output otherwise strap pull-up strap pull-down
Note
Some devices drive pins that designated output (PHY) power resulting incorrect strapping values latched reset. rcommended that external pull down resistor used these applications augment 8721's internal pull down.
April 2005
M9999-041405
KS8721B/BT
Configuration
MDIO R3D3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO RXDV/PCS_LPBK RXER/ISO VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB VDDIO RST# VDDPLL VDDTX
RST# VDDPLL VDDTX VDDRCV REXT
TX39 VDDRCV REXT FXSD/FXEN RX31 VDDRX LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0
MDIO RXD3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO RXDV/PCS_LPBK RXER/ISO
VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB VDDIO
FXSD/FXEN VDDRX LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0
48-Pin SSOP (SM)
48-Pin TQFP (TQ)
M9999-041405
April 2005
KS8721B/BT
Introduction
100BaseTX Transmit
100BaseTX transmit function performs parallel serial conversion, NRZI conversion, MLT-3 encoding transmission. circuitry starts with parallel serial conversion, which converts 25MHz, 4-bit nibbles into serial stream. incoming data clocked positive edge signal. serialized data further converted from NRZI format, then transmitted MLT3 current output. output current external 6.49k resistor transformer ratio. typical rise/fall times complies ANSI TP-PMD standard regarding amplitude balance, overshoot timing jitters. wave-shaped 10BaseT output driver also incorporated into 100BaseTX driver.
100BaseTX Receive
100BaseTX receive function performs adaptive equalization, restoration, MLT-3 NRZI conversion, data clock recovery, NRZI conversion, serial parallel conversion. receiving side starts with equalization filter compensate inter-symbol interference (ISI) over twisted pair cable. Since amplitude loss phase distortion function length cable, equalizer adjust characteristic optimize performance. this design, variable equalizer will make initial estimation based comparisons incoming signal strength against some known cable characteristics, then tunes itself optimization. This ongoing process self adjust against environmental changes such temperature variations. equalized signal then goes through restoration data conversion block. restoration circuit used compensate effect base line wander improve dynamic range. differential data conversion circuit converts MLT3 format back NRZI. slicing threshold also adaptive. clock recovery circuit extracts 125MHz clock from edges NRZI signal. This recovered clock then used convert NRZI signal into format. Finally, serial data converted 4-bit parallel nibbles. synchronized 25MHz generated that nibbles clocked negative edge RCK25 valid receiver positive edge. When valid data present, clock recovery circuit locked 25MHz reference clock both clocks continue run.
Clock Synthesizer
KS8721B/BT generates 125MHz, 25MHz 20MHz clocks system timing. internal crystal oscillator circuit provides reference clock synthesizer.
Scrambler/De-scrambler (100BaseTX only)
purpose scrambler spread power spectrum signal order reduce baseline wander.
10BaseT Transmit
When TXEN (transmit enable) goes high, data encoding transmission will begin. KS8721B/BT will continue encode transmit data long TXEN remains high. data transmission will when TXEN goes low. last transition occurs boundary cell last zero, center cell last one. output driver incorporated into 100Base driver allow transmission with same magnetics. They internally wave-shaped pre-emphasized into outputs with typical 2.5V amplitude. harmonic contents least 27dB below fundamental when driven all-ones Manchester-encoded signal.
10BaseT Receive
receive side, input buffer level detecting squelch circuits employed. differential input receiver circuit performs decoding function. Manchester-encoded data stream separated into clock signal data. squelch circuit rejects signals with levels less than 300mV with short pulse widths order prevent noises input from falsely trigger decoder. When input exceeds squelch limit, locks onto incoming signal KS8721B/BT decodes data frame. This activates carrier sense (CRS) RXDV signals makes receive data (RXD) available. receive clock maintained active during idle periods between data reception.
Jabber Function (10BaseT only)
10BaseT operation, short pulse will after each packet transmitted. This required test 10BaseT transmit/receive path called test. 10BaseT transmitter will disabled will high TXEN High more than 20ms (Jabbering). TXEN then goes more than 250ms, 10BaseT transmitter will re-enabled will Low.
Auto-Negotiation
KS8721B/BT performs auto-negotiation hardware strapping option (pin software (Register 0.12). will automatically choose mode operation advertising abilities comparing them with those received from link partner whenever auto-negotiation enabled. also configured advertise 100BaseTX 10BaseT either full- half-duplex mode (please refer "Auto-Negotiation" auto-negotiation disabled mode. April 2005
M9999-041405
KS8721B/BT
During auto-negotiation, contents Register coded Fast Link Pulse (FLP), will sent link partner under conditions power-on, link-loss re-start. same time, KS8721B/BT will monitor incoming data determine mode operation. Parallel detection circuit will enabled soon either 10BaseT (Normal Link Pulse) 100BaseTX idle detected. operation mode configured based following priority: Priority 100BaseTX, full-duplex Priority 100BaseTX, half-duplex Priority 10BaseT, full-duplex Priority 10BaseT, half-duplex When KS8721B/BT receives burst from link partner with identical link code words (ignoring acknowledge bit), will store these code words Register wait next identical code words. Once KS8721B/BT detects second code words, then configures itself according above-mentioned priority. addition, KS8721B/BT also checks 100BaseTX idle 10BaseT symbol. either detected, KS8721B/BT automatically configures match detected operating speed.
Management Interface
KS8721B/BT supports IEEE 802.3 Management Interface, also known Management Data Input Output (MDIO) Interface. This interface allows upper-layer devices monitor control state KS8721B/BT. MDIO interface consists following: physical connection including data line (MDIO), clock line (MDC) optional interrupt line (INTRPT) specific protocol that runs across above-mentioned physical connection also allows controller communicate with multiple KS8721B/BT devices. Each KS8721B/BT assigned address between PHYAD inputs. internal addressable fourteen 16-bit MDIO registers. Register [0:6] required their functions specified IEEE 802.3 specifications. Additional registers provided expanded functionality. INTPRT functions management data interrupt MII. active High this indicates status change KS8721B/BT based 1fh.9 level control. Register bits 1bh[15:8] interrupt enable bits. Register bits 1bh[7:0] interrupt condition bits. This interrupt cleared reading Register 1bh.
Data Interface
data interface consists separate channels transmitting data from 10/100 802.3 compliant Media Access Controller (MAC) KS8721B/BT, receiving data from line. Normal data transmission implemented Nibble Mode (4-bit wide nibbles). Transmit Clock (TXC): transmit clock normally generated KS8721B/BT from external 25MHz reference source input. transmit data control signals must always synchronized MAC. KS8721B/BT normally samples these signals rising edge TXC. Receive Clock (RXC): 100BaseTX links, receive clock continuously recovered from line. link goes down, auto-negotiation disabled, receive clock operates master input clock TXC). 10BaseT links, receive clock recovered from line while carrier active, operates from master input clock when line idle. KS8721B/BT synchronizes receive data control signals falling edge order stabilize signals rising edge clock with 10ns setup hold times. Transmit Enable: must assert TXEN same time first nibble preamble, de-assert TXEN after last packet. Receive Data Valid: KS8721B/BT asserts RXDV when receives valid packet. Line operating speed mode will determine timing changes following way: 100BaseTX link with mode, RXDV asserted from first nibble preamble last nibble data packet. 10BaseT links, entire preamble truncated. RXDV asserted with first nibble remains asserted until packet. Error Signals: Whenever KS8721B/BT receives error symbol from network, asserts RXER drives "1110" (4B) pins. When asserts TXER, KS8721B/BT will drive symbols Transmit Error define IEEE 802.3 4B/5B code group) line force signaling errors. Carrier Sense (CRS): 100TX links, start-of-stream delimiter, /J/K symbol pair causes assertion Carrier Sense (CRS). end-of-stream delimiter, /T/R symbol pair causes de-assertion CRS. layer will also de-assert IDLE symbols received without /T/R, this case RXER will asserted clock cycle when de-asserted. links, assertion based reception valid preamble, de-assertion reception end-of-frame (EOF) marker.
M9999-041405
April 2005
KS8721B/BT
Collision: Whenever line state half-duplex transmitter receiver active same time, KS8721B/ asserts collision signal, which asynchronous clock.
RMII (Reduced MII) Data Interface
RMII interface specifies count (Reduced) Media Independent Interface (RMII) intended between Ethernet PHYs Switch Repeater ASICs. fully compliant with IEEE 802.3u [2]. This interface following characteristics: capable supporting 10Mbps 100Mbps data rates. single clock reference sourced from from external source). provides independent 2-bit wide (di-bit) transmit receive data paths. uses signal levels, compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Signal Name REF_CLK CRS_DV RXD[1:0] TX_EN TXD[1:0] RX_ER
Note
Direction respect PHY) Input Output Output Input Input Output
Direction respect MAC) Input Output Input Input Output Output Input (Not Required)
Synchronous clock reference receive, transmit control interface Carrier Sense/Receive Data Valid Receive Data Transit Enable Transit Data Receive Error
Unused signals, TXD[3:2], TXER need when RMII using.
Reference Clock (REF_CLK)
REF_CLK continuous 50MHz clock that provides timing reference CRS_DV, RXD[1:0], TX_EN, TXD[1:0], RX_E. REF_CLK sourced external source. Switch implementations choose provide REF_CLK input output depending whether they provide REF_CLK output rely external clock distribution device. Each device shall have input corresponding this clock single clock input multiple PHYs implemented single
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV asserted asynchronously detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode when non-contiguous zeroes bits detected carrier said detected. Loss carrier shall result de-assertion CRS_DV synchronous REF_CLK. long carrier criteria being met, CRS_DV shall remain asserted continuously from first recovered di-bit frame through final recovered di-bit shall negated prior first REF_CLK that follows final di-bit. data RXD[1:0] considered valid once CRS_DV asserted. However, since assertion CRS_DV asynchronous relative REF_CLK, data RXD[1:0] shall "00" until proper receive signal decoding takes place (see definition RXD[1:0] behavior).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] shall transition synchronously REF_CLK. each clock period which CRS_DV asserted, RXD[1:0] transfers bits recovered data from PHY. some cases (e.g. before data recovery during error conditions) pre-determined value RXD[1:0] transferred instead recovered data. RXD[1:0] shall "00" indicate idle when CRS_DV deasserted. Values RXD[1:0] other than "00" when CRS_DV de-asserted reserved out-of-band signalling defined). Values other than "00" RXD[1:0] while CRS_DV de-asserted shall ignored MAC/repeater. Upon assertion CRS_DV, shall ensure that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that presenting di-bits TXD[1:0] RMII trans-mission. TX_EN shall asserted synchronously with first nibble preamble shall remain asserted while di-bits transmitted presented RMII. TX_EN shall negated prior first REF_CLK following final di-bit frame. TX_EN shall transition synchronously with respect REF_CLK. April 2005
M9999-041405
KS8721B/BT
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] shall transition synchronously with respect REF_CLK. When TX_EN asserted, TXD[1:0] accepted transmission PHY. TXD[1:0] shall "00" indicate idle when TX_EN de-asserted. Values TXD[1:0] other than "00" when TX_EN de-asserted reserved out-of-band signalling defined). Values other than "00" TXD[1:0] while TX_EN deasserted shall ignored PHY.
Collision Detection
Since definition CRS_DV TX_EN both contain accurate indication start frame, reliably regenerate signal ANDing TX_EN CRS_DV. During time following successful transmission frame, signal asserted some transceivers self-test. Signal Quality Error (SQE) function will supported reduced lack signal. Historically, present indicate that transceiver located physically remote from functioning. Since reduced only supports chip-to-chip connections PCB, functionality required.
RX_ER
shall provide RX_ER output according rules specified IEEE 802.3u (see Clause Figure 24-11 Receive State Diagram). RX_ER shall asserted more REF_CLK periods indicate that error (e.g. coding error error that capable detecting, that otherwise undetectable sublayer) detected somewhere frame presently being transferred from PHY. RX_ER shall transition synchronously with respect REF_CLK. While CRS_DV de-asserted, RX_ER shall have effect MAC.
RMII Characteristics
Symbol Parameter REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RX_ER Data Set-Up REF_CLK Rising TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK Rising Edge Units
RMII Transmit Timing
20ns
REF_CLK
TXD[1:0] TXEN TXER
Parameter REF_CLK Frequency TXEN, TXD[1:0], TX_EN, Data Setup REF_CLK rising edge TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
Units
M9999-041405
April 2005
KS8721B/BT
RMII Receive Timing
20ns
REF_CLK
RXD[1:0] RXDV RXER
Parameter REF_CLK Frequency RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge Units
Auto Crossover (Auto MDI/MDI-X)
Automatic MDI/MDI-X configuration intended eliminate need crossover cables between similar devices. assignment pin-outs 10/100 BASE-T crossover function cable shown below. This feature eliminate confusion real applications both straight cable crossover cable used. This feature controlled register 1f:13. "Register 1fh-100BaseTX Controller" section details.
10/100 Base-T Media Dependent Interface 10/100 Base-T Media Dependent Interface
Transmit Pair
Receive Pair
Receive Pair
Transmit Pair
Modular Connector (RJ45)
Modular Connector (RJ45) (Repeater Switch)
Figure Straight Through Cable
10/100 BASE-T Media Dependent Interface 10/100 Base-T Media Dependent Interface
Receive Pair
Receive Pair
Transmit Pair
Transmit Pair
Modular Connector (RJ45) (Repeater Switch)
Modular Connector (RJ45) (Repeater Switch)
Figure Crossover Cable April 2005
M9999-041405
KS8721B/BT
Power Management
KS8721B/BT offers following modes power management: Power Down Mode: This mode achieved writing Register 0.11 pulling Low. Power Saving Mode: This mode disabled writing Register 1fh.10. KS8721B/BT will then turn everything except Energy Detect circuits when cable installed. other words, KS8721B/BT will shutdown most internal circuits save power there link. Power saving mode will most effective state when auto-negotiation mode enable.
100BT Mode
100BT mode activated when FXSD/FXEN higher 0.6V (This default pull down). Under this mode, autonegotiation auto-MDIX features disabled. fiber operation FXSD should connect (signal detect) output fiber module. internal threshold FXSD around ±50mV (1.25V ±0.05V). Above this level, considered fiber signal detected, operation summarized following table:
FXSD/FXEN Less than 0.6V Less than 1.25V, greater than 0.6V Greater than 1.25 Condition 100TX mode mode signal detected generated mode signal detected
Table 100BT Mode ensure proper operation, swing fiber module should cover threshold variation. resistive voltage divider recommended adjust voltage range. (Far Fault), repetition special pattern which consists 84-one 1-zero, generated under mode with signal detected." purpose notify sender faulty link. When receiving FEF, LINK will down indicate fault, even with fiber signal detected. transmitter does affect receiving still sends normal transmit pattern from MAC. disabled strapping low. Refer "Strapping Options" section.
Media Converter Operation
KS8721B/BT capable performing media conversion with parts back back RMII loop-back mode indicated diagram. Both parts RMII mode with RMII asserted (pin strapped high). part operating mode other mode. Both parts share common 50MHz oscillator. Under this operation, auto-negotiation side will prohibit 10baseT link TXD2, active High, disable transmitter tri-state. RXD2 serves energy detection indicate there line signal detected. TXD3 should tied RXD3 float. Please contact Micrel Application Note.
KS8721B
+/TxC/ Ref_CLK
TxC/ Ref_CLK
KS8721B
(Fiber Mode)
Fiber Module
Figure Fiber Module
M9999-041405
April 2005
KS8721B/BT
Register
Register Description Basic Control Register Basic Status Register Identifier Identifier Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability RXER Counter Register Interrupt Control/Status Register 100BaseTX Control Register
Address
Name
Description
Mode(Note Default
Register Basic Control 0.15 0.14 0.13 0.12 0.11 0.10 0.6:1 Reset Loop-back Speed Select (LSB) Auto-Negotiation Enable Power Down Isolate Restart Auto-Negotiation Duplex Mode Collision Test Reserved Disable Transmitter enable transmitter disable transmitter software reset. self-clearing loop-back mode; normal operation 100Mbps; 10Mbps Ignored Auto-Negotiation enabled (0.12 enable auto-negotiation process (override 0.13 0.8) disable auto-negotiation process power down mode; normal operation electrical isolation from TX+/TX0 normal operation restart auto-negotiation process normal operation. self-clearing full duplex; half duplex enable test; disable test RW/SC RW/SC SPD100 NWAYEN DUPLEX
Register Basic Status 1.15 1.14 1.13 1.12 1.11
Note
100BaseT4 100BaseTX Full Duplex 100BaseTX Half Duplex 10BaseT Full Duplex 10BaseT Half Duplex
capable; capable capable 100BaseX full duplex capable 100BaseX full duplex capable 100BaseX half duplex capable 100BaseX half duplex 10Mbps with full duplex 10Mbps with full duplex capability 10Mbps with half duplex 10Mbps with half duplex capability
Read/Write, Read only, Self clear, Latch High, Latch Low. Some default values strap-in. "Srapping Options."
April 2005
M9999-041405
KS8721B/BT
Address 1.10:7 Name Reserved Preamble Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability preamble suppression; normal preamble auto-negotiation process completed auto-negotiation process completed remote fault; remote fault capable perform auto-negotiation unable perform auto-negotiation link link down Description Mode(Note RO/LH RO/LL
Default
jabber detected; jabber detected. Default RO/LH supports extended capabilities registers
Register Identifier 2.15:0 Number Assigned through 18th bits Organizationally Unique Identifier (OUI). Micrel's 0010A1 (hex) 0022h
Register Identifier 3.15:10 3.9:4 3.3:0 Number Model Number Revision Number Assigned 19th through 24th bits Organizationally Unique Identifier (OUI). Micrel's 0010A1 (hex) manufacturer's model number Four manufacturer's model number 000101 100001 1001
Register Auto-Negotiation Advertisement 4.15 4.14 4.13 4.12 4.10 Next Page Reserved Remote Fault Reserved Pause 100BaseT4 100BaseTX Full Duplex pause function supported; pause function capable; capability with full duplex; full duplex capability remote fault supported; remote fault next page capable; next page capability. SPD100 DUPLEX SPD100 DUPLEX 00001
4.4:0
100BaseTX 10BaseT Full Duplex 10BaseT Selector Field
capable; capability 10Mbps with full duplex 10Mbps full duplex capability 10Mbps capable; 10Mbps capability [00001] IEEE 802.3
Register Auto-Negotiation Link Partner Ability 5.15 5.14 5.13 5.12
Note
Next Page Acknowledge Remote Fault Reserved
next page capable; next page capability link code word received from partner link code word received remote fault detected; remote fault
Read/Write, Read only, Self clear, Latch High, Latch Low. Some default values strap-in. "Srapping Options."
M9999-041405
April 2005
KS8721B/BT
Address 5.11:10 Name Pause Description 5.10 PAUSE Asymmetric PAUSE (link partner) Symmetric PAUSE Symmetric Asymmetric PAUSE (local device) capable; capability with full duplex; full duplex capability capable; capability 10Mbps with full duplex 10Mbps full duplex capability 10Mbps capable; 10Mbps capability [00001] IEEE 802.3 Mode(Note
Default
5.4:0
BaseT4 100BaseTX Full Duplex 100BaseTX 10BaseT Full Duplex 10BaseT Selector Field
00001
Register Auto-Negotiation Expansion 6.15:5 Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able fault detected parallel detection fault detected parallel detection. link partner next page capability link partner does have next page capability local device next page capability local device does have next page capability page received; page received link partner auto-negotiation capability link partner does have auto-negotiation capability RO/LH RO/LH
Register Auto-Negotiation Next Page 7.15 7.14 7.13 7.12 7.11 7.10:0 Next Page Reserved Message Page Acknowledge2 Toggle Message Field message page; unformatted page will comply with message cannot comply with message previous value transmitted link code word equaled logic One; logic Zero 11-bit wide field encode 2048 messages additional next page(s) will follow; last page
Register Link Partner Next Page Ability 8.15 8.14 8.13 8.12 8.11 Next Page Acknowledge Message Page Acknowledge2 Toggle additional Next Page(s) will follow; last page successful receipt link word successful receipt link word Message Page; Unformatted Page able information able information previous value transmitted Link Code Word equal logic zero; previous value transmitted Link Code Word equal logic
8.10:0
Note
Message Field
Read/Write, Read only, Self clear, Latch High, Latch Low. Some default values strap-in. "Srapping Options."
April 2005
M9999-041405
KS8721B/BT
Address Name Description Mode(Note
Default
Register RXER Counter 15.15:0 RXER Counter Error counter RX_ER each package 0000
Register Interrupt Control/Status Register 1b.15 1b.14 1b.13 1b.12 1b.11 1b.10 1b.9 1b.8 1b.7 1b.6 1b.5 1b.4 1b.3 1b.2 1b.1 1b.0 Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Enable Link Interrupt Enable Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Interrupt Enable Jabber Interrupt; 0=Disable Jabber Interrupt Enable Receive Error Interrupt Disable Receive Error Interrupt Enable Page Received Interrupt Disable Page Received Interrupt Enable Parallel Detect Fault Interrupt Disable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Disable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Disable Link Down Interrupt Enable Remote Fault Interrupt Disable Remote Fault Interrupt Enable Link Interrupt Disable Link Interrupt Jabber Interrupt Occurred Jabber Interrupt Does Occurred Receive Error Occurred Receive Error Does Occurred Page Receive Occurred Page Receive Does Occurred Parallel Detect Fault Occurred Parallel Detect Fault Does Occurred Link Partner Acknowledge Occurred Link Partner Acknowledge Does Occurred Link Down Occurred Link Down Does Occurred Remote Fault Occurred Remote Fault Does Occurred Link Interrupt Occurred Link Interrupt Does Occurred RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC RO/SC
Register 100BaseTX Controller 1f.15:14 1f:13 1f.12 1f.11 Reserved Pairswap Disable Energy Detect Force Link Disable MDI/MDIX; Enable MDI/MDIX Presence Signal RX+/- Analog Wire Pair Signal Setected RX+/1 Force Link Pass; Normal Link Operation This bypasses control logic allow transmitter send pattern even there link. Enable Ppower Saving; Disable Interrupt Active High; Active Enable Jabber Counter; Disable Auto-Negotiation Complete; Nomplete
1f.10 1f.9 1f.8 1f.7
Note
Power Saving Interrupt Level Enable Jabber Auto-Negotiation Complete
Read/Write, Read only, Self clear, Latch High, Latch Low. Some default values strap-in. "Srapping Options."
M9999-041405
April 2005
KS8721B/BT
Address 1f.6 1f.5 1f.4:2 Name Enable Pause (Flow-Control Result) Isolate Description flow control capable; flow control isolate mode; isolated Mode(Note
Default
Operation Mode Indication [000] still auto-negotiation [001] 10BaseT half duplex [010] 100BaseTX half duplex [011] reserved [101] 10BaseT full duplex [110] 100BaseTX full duplex [111] PHY/MII isolate Enable Test Disable Data Scrambling enable test; disable disable scrambler; enable
1f.1 1f.0
Note
Read/Write, Read only, Self clear, Latch High, Latch Low. Some default values strap-in. "Srapping Options."
April 2005
M9999-041405
KS8721B/BT
Absolute Maximum Ratings (Note
Supply Voltage (VDDC, VDD_PLL, VDD_TX, VDD_RCV, VDD_RX) -0.5V +3.0V (VDDIO) -0.5V +4.0V Input Voltage -0.5V +4.0V Output Voltage -0.5V +4.0V Lead Temperature (soldering, sec.) 270°C Storage Temperature (TS) -55°C +150°C
Operating Ratings (Note
Supply Voltage (VDDC, VDD_PLL, VDD_TX, VDD_RCV, VDD_RX) +2.375V +2.625V (VDDIO) +2.375V +2.625V +3.0V +3.6V Ambient Temperature (TA) -0°C +70°C Package Thermal Resistance (Note TQFP (JA) 69.64°C/W SSOP (JA) 42.91°C/W
Electrical Characteristics (Note
2.5V ±5%; +70°C; unless noted; bold values indicate -40°C +85°C; unless noted. Symbol Parameter Condition Units Total Supply Current (including output driver current) IDD1 IDD2 IDD3 IDD5 Inputs Outputs |IOZ| Output High Voltage Output Voltage Output Tr-State Leakage -4mA (I/O) -0.4 Input High Voltage Input Voltage Input Current (I/O) -0.8 Normal 100BaseTX Normal 10BaseT (50% utilization) Power Saving Mode 100BaseTX Power Down Mode
100BaseTX Receive RX+/RX- Differential Input Resistance Propagation Delay from magnetics RDTX
100BaseTX Transmit (measured differentially after transformer) VIMB Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance from each output from each output 0.95 1.05
100BaseTX Transmit (measured differentially after transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage ISET Propagation Delay Jitters
Note Note Note Note Exceeding absolute maximum rating damage device. device guaranteed function outside operating rating. Unused inputs must always tied appropriate logic voltage level (Ground VDD). (heat spreader) package. Specification packaged product only.
±0.5 0.75 from TDTX magentics
ns(pk-pk
M9999-041405
April 2005
KS8721B/BT
Symbol Parameter Condition
Units
10BaseTX Receive RXC100 RXC10 TXC100 TXC10 RX+/RX- Differential Input Resistance Squelch Threshold 5MHz square wave
10BaseTX Transmit (measured differentially after transformer) Peak Differential Output Voltage Jitters Added Rise/Fall Time from each output from each output ±3.5
Clock Outputs Crystal Oscillator Receive Clock, 100TX Receive Clock, Receive Clock Jitters Transmit Clock, 100TX Transmit Clock, Transmit Clock Jitters ns(pk-pk) ns(pk-pk)
April 2005
M9999-041405
KS8721B/BT
Timing Diagrams
tHD2 tSU2 tSU1 tCRS1 tCRS2 tLAT
Valid Data
TXEN
tHD1
TXD[3:0]
TXP/TXM
Timing
TXEN
tSQE
tSQEP
Figure 10BaseT Transmit Timing
Symbol tSU1 tSU2 tHD1 tHD2 tCRS1 tCRS2 tLAT tSQE tSQEP
Parameter [3:0] Set-Up High TXEN Set-Up High [3:0] Hold After High TXEN Hold After High TXEN High Asserted Latency TXEN De-Asserted Latency TXEN High TXP/TXM Output Latency) (SQE) Delay Aftter TXEN Ae-Asserted (SQE) Pulse Duration
Units
Table 10BaseT Transmit Timing Parameters
M9999-041405
April 2005
KS8721B/BT
tSU2
TXEN
tHD2 tHD1
tSU1
TXD[3:0], TXER Data
tCRS2
tCRS1 tLAT
TX+/TX-
Symbol
Figure 100BaseT Transmit Timing
Symbol tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT
Parameter [3:0] Set-Up High TXEN Set-Up High [3:0] Hold After High TXER Hold After High TXEN Hold After High TXEN High Asserted Latency TXEN De-Asserted Latency TXEN High TX+/TX- Output Latency)
Units
Table 100BaseT Transmit Timing Parameters
April 2005
M9999-041405
KS8721B/BT
RX+/RX-
Start Stream
Stream
tCRS1 tCRS2 tRLAT
RXDV
RXD[3:0] RXER
Figure 100BaseT Receivce Timing
Symbol tRLAT tCRS1 tCRS2
Parameter Period Pulse Width Pulse Width [3:0], RXER, RXDV Set-Up Rising Edge [3:0], RXER, RXDV Hold from Rising Edge Latency, Aligned "Start Stream" Asserted "End Stream" De-Asserted
Units
Table 100BaseT Receive Timing Parameters
M9999-041405
April 2005
KS8721B/BT
Burst
Burst
TX+/TX-
tFLPW tBTB
Clock Pulse TX+/TX-
Data Pulse
Clock Pulse
Data Pulse
tCTD
tCTC
Figure Auto-Negotiation/Fast Link Pulse Timing
Symbol tBTB tFLPW tCTD tCTC
Parameter Burst Burst Burst Width Clock/Data Pulse Width Clock Pulse Data Pulse Clock Pulse Clock Pulse Number Clock/Data Pulses Burst
Units
Table Auto-Negotiation/Fast Link Pulse Timing
April 2005
M9999-041405
KS8721B/BT
tMD1
MDIO (Into Chip)
tMD2
Valid Data Valid Data
tMD3
MDIO (Out Chip) Valid Data
Figure Serial Management Interface Timing
Symbol tMD1 tMD2 tMD3
Parameter Period MDIO Set-Up (MDIO input) MDIO Hold after (MDIO input) MDIO Valid (MDIO output)
Units
Table Serial Management Interface Timing
M9999-041405
April 2005
KS8721B/BT
Supply Voltage
RST_N
Strap-In Value Strap-In Output
Figure Reset Timing
Symbol
Parameter Stable Supply Voltages Reset High Configuration Set-Up Time Configuration Hold Time Reset Strap-In Output
Units
Table Reset Timing Parameters
Reset Circuit Diagram
Micrel recommendeds following discrete reset circuit shown Figure when powering KS8721B/BT device. application where reset circuit signal comes from another device (e.g., CPU, FPGA, etc), recommend reset circuit shown Figure
KS8721B/BT 10µF
CPU/FPGA RST_OUT_n
1N4148
Figure Recommended Reset Circuit.
1N4148 KS8721B/BT 10µF
Figure Recommended Circuit Interfacing with CPU/FPGA Reset power-on-reset, provide necessary ramp rise time reset Micrel device. reset from CPU/FPGA provides warm reset after power also recommended power core voltage earlier than VDDIO voltage. worst case, both core VDDIO voltages should come same time. April 2005
M9999-041405
KS8721B/BT
Selection Isolation Transformer(Note
simple isolation transformer needed line interface. isolation transformer with integrated common-mode choke recommended exceeding requirements. following table gives recommended transformer characteristics.
Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.)
Note
Value 350µH 0.4µH 12pF 1.0dB 1500Vrms
Test Condition
100mV, KHz, 1MHz (min.)
0MHz 65MHz
IEEE 802.3u standard 100BaseTX assumes transformer loss 0.5dB. transmit line transformer, insertion loss 1.3dB compensated increasing line drive current means reducing ISET resistor value.
Selection Reference Crystal
oscillator crystal with following typical characteristics recommended.
Characteristics Name Frequency Frequency Tolerance (max.) Load Capacitance (max.) Series Resistance (max.) Value 25.00000 ±100 Units
Single Port Magnetic Manufacturer Pulse Fuse Transpower Delta LanKom Integrated Transformers Pulse Pulse
Part Number H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S
Auto MDIX
Number Ports
J0011D21 J00-0061
Table Qualified Transformer Lists
M9999-041405
April 2005
KS8721B/BT
Package Information
48-Pin SSOP (SM)
April 2005
M9999-041405
KS8721B/BT
48-Pin TQFP (TQ)
MICREL INC. 2180 FORTUNE DRIVE JOSE, 95131
(408) 944-0800
(408) 474-1000
http://www.micrel.com
This information furnished Micrel this data sheet believed accurate reliable. However responsibility assumed Micrel use. Micrel reserves right change circuitry specifications time without notification customer. Micrel Products designed authorized components life support appliances, devices systems where malfunction product reasonably expected result personal injury. Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform reasonably expected result significant injury user. Purchaser's sale Micrel Products life support appliances, devices systems Purchaser's risk Purchaser agrees fully indemnify Micrel damages resulting from such sale. 2002 Micrel, Incorporated. M9999-041405
April 2005

KS8721B/BT 2.5V 10/100BasTX/FX Physical Layer Transceiver Rev.

Top Searches for this datasheet

Other recent searches