Flash Memory (1Mb (Model Number: LHF00L28) Spec. Issue Date:

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LHF00L28
Flash Memory (1Mb
(Model Number: LHF00L28)
Spec. Issue Date: 2004 Spec FM045032
LHF00L28
Handle this document carefully contains material protected international copyright law. reproduction, full part, this material prohibited without express written permission company. When using products covered herein, please observe conditions written herein precautions outlined following paragraphs. event shall company liable damages resulting from failure strictly adhere these conditions precautions. products covered herein designed manufactured following application areas. When using products covered herein equipment listed Paragraph (2), even following application areas, sure observe precautions given Paragraph (2). Never products equipment listed Paragraph (3). Office electronics Instrumentation measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than trunk lines Those contemplating using products covered herein following equipment which demands high reliability, should first contact sales representative company then accept responsibility incorporating into design fail-safe operation, redundancy, other appropriate measures ensuring reliability safety equipment overall system. Control safety devices airplanes, trains, automobiles, other transportation equipment Mainframe computers Traffic control systems leak detectors automatic cutoff devices Rescue security equipment Other safety devices safety equipment, etc. products covered herein following equipment which demands extremely high performance terms functionality, reliability, accuracy. Aerospace equipment Communications equipment trunk lines Control equipment nuclear power industry Medical equipment related life support, etc. Please direct queries comments regarding interpretation above three Paragraphs sales representative company. Please direct queries regarding products covered herein sales representative company.
Rev. 2.45
LHF00L28
CONTENTS
PAGE 48-Lead TSOP (Normal Bend) Pinout Descriptions. Memory Identifier Codes Address Read Operation Block Address Program.
PAGE Electrical Specifications Absolute Maximum Ratings. Operating Conditions 1.2.1 Capacitance. 1.2.2 Input/Output Test Conditions. 1.2.3 Characteristics.
Operation. Command Definitions Functions Block Lock Block Lock-Down. Block Locking State Transitions upon Command Write. Block Locking State Transitions upon WP#/ACC Transition Status Register Definition. 1.2.4 Characteristics Read-Only Operations. 1.2.5 Characteristics Write Operations 1.2.6 Reset Operations. 1.2.7 Block Erase, Full Chip Erase, Program Program Performance. Related Document Information
Rev. 2.45
LHF00L28
LHF00L28 16Mbit Flash MEMORY
16-M density with 16-bit Interface Read Operation 70ns Power Operation 2.7V Read Write Operations Automatic Power Savings Mode reduces ICCR Static Mode Enhanced Code Data Storage Typical Erase/Program Suspends (One Time Program) Block 4-Word Factory-Programmed Area 4-Word User-Programmable Area Operating Temperature -40°C +85°C CMOS Process (P-type silicon substrate) Flexible Blocking Architecture Eight 4-Kword Parameter Blocks 32-Kword Block Fifteen 64-Kword Blocks Parameter Location Enhanced Data Protection Features Individual Block Lock Block Lock-Down with Zero-Latency blocks locked power-up device reset. Block Erase, Full Chip Erase, Word Program Lockout during Power Transitions Automated Erase/Program Algorithms 3.0V Low-Power 10µs/Word (Typ.) Programming 12.0V Glue Logic 9µs/Word (Typ.) Production Programming 0.8s Erase (Typ.) Cross-Compatible Command Support Basic Command Common Flash Interface (CFI) Extended Cycling Capability Minimum 100,000 Block Erase Cycles 48-Lead TSOP (Normal Bend) ETOXTM* Flash Technology designed rated radiation hardened
product power, high density, cost, nonvolatile read/write storage solution wide range applications. product operate VCC=2.7V-3.6V. voltage operation capability greatly extends battery life portable applications. memory array block architecture utilizes Enhanced Data Protection features, which provides maximum flexibility safe nonvolatile code data storage. Special (One Time Program) block provides area store permanent code such unique number. ETOX trademark Intel Corporation.
Rev. 2.45
LHF00L28
RST# WP#/ACC RY/BY#
48-LEAD TSOP STANDARD PINOUT 12mm 20mm VIEW
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
Figure 48-Lead TSOP (Normal Bend) Pinout
Rev. 2.45
LHF00L28
Table Descriptions Symbol A19-A0 DQ15-DQ0 Type INPUT INPUT/ OUTPUT Name Function ADDRESS INPUTS: Inputs addresses. DATA INPUTS/OUTPUTS: Inputs data commands during (Command User Interface) write cycles, outputs data during memory array, status register, query code, identifier code reads. Data pins float high-impedance (High when chip outputs deselected. Data internally latched during erase program cycle. CHIP ENABLE: Activates device's control logic, input buffers, decoders sense amplifiers. CE#-high (VIH) deselects device reduces power consumption standby levels. RESET: When (VIL), RST# resets internal automation inhibits write operations which provides data protection. RST#-high (VIH) enables normal operation. After power-up reset mode, device automatically read array mode. RST# must during power-up/down. OUTPUT ENABLE: Gates device's outputs during read cycle. WRITE ENABLE: Controls writes array blocks. Addresses data latched rising edge (whichever goes high first). WRITE PROTECT: When WP#/ACC VIL, locked-down blocks cannot unlocked. Erase program operation executed blocks which locked locked-down. When WP#/ACC VIH, lock-down disabled. Applying 12.0V±0.3V WP#/ACC provides fast erasing fast programming mode. this mode, WP#/ACC power supply pin. Applying 12.0V±0.3V WP#/ACC during erase/program only done maximum 1,000 cycles each block. WP#/ connected 12.0V±0.3V total hours maximum. this 12.0V+0.3V beyond these limits reduce block cycling capability cause permanent damage.
INPUT
RST#
INPUT
INPUT INPUT
WP#/ACC
INPUT/ SUPPLY
RY/BY#
READY/BUSY#: Indicates status internal (Write State Machine). When low, performing internal operation (block erase, full chip erase, program OPEN DRAIN program). RY/BY#-High indicates that ready commands, OUTPUT block erase suspended program inactive, program suspended, device reset mode. SUPPLY SUPPLY DEVICE POWER SUPPLY (2.7V-3.6V): With VCCVLKO, write attempts flash memory inhibited. Device operations invalid voltage (see Characteristics) produce spurious results should attempted. GROUND: float ground pins. CONNECT: Lead internally connected; driven floated.
Rev. 2.45
LHF00L28
[A19-A0]
FFFFF FF000 FEFFF FE000 FDFFF FD000 FCFFF FC000 FBFFF FB000 FAFFF FA000 F9FFF F9000 F8FFF F8000 F7FFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000
4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 32-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block
Figure Memory (Top Parameter)
Rev. 2.45
LHF00L28
Table Identifier Codes Address Read Operation Code Manufacturer Code Device Code Block Lock Configuration Code Manufacturer Code Device Code Block Unlocked Block Locked Block Locked-Down Block Locked-Down Lock 00080H 00081-00088H Block Address Address [A19-A0] 00000H 00001H Data [DQ15-DQ0] 00B0H 00A4H OTP-LK Notes
NOTES: Block Address beginning location block address. DQ15-DQ2 reserved future implementation. OTP-LK=OTP Block Lock configuration. OTP=OTP Block data.
Rev. 2.45
LHF00L28
[A19-A0]
000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H 000080H
Reserved Future Implementation (DQ15-DQ2)
Customer Programmable Area Lock (DQ1) Factory Programmed Area Lock (DQ0)
Figure Block Address Program (The area outside 80H~88H cannot used.)
Rev. 2.45
LHF00L28
Table Operation(1, Mode Read Array Output Disable Standby Reset Read Identifier Codes/OTP Read Query Read Status Register Write 4,5,6 Notes RST# Address Table Appendix DQ15-0 DOUT High High High Table Appendix DOUT RY/BY#
High High High High
NOTES: Refer Characteristics voltages. control pins addresses. RST# GND±0.2V ensures lowest power consumption. Command writes involving block erase, full chip erase, program program reliably executed when VCC=2.7V-3.6V. Refer Table valid during write operation. Never hold same timing. Refer Appendix LHF00LXX series more information about query code. RY/BY# when (Write State Machine) executing internal block erase, full chip erase, program program algorithms. High during when busy, block erase suspend mode (with program inactive), program suspend mode, reset mode.
Rev. 2.45
LHF00L28
Table Command Definitions(10) Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Block Erase Program Suspend Block Erase Program Resume Block Lock Clear Block Lock Block Lock-down Program Cycles Req'd First Cycle Notes Oper
Second Cycle Data Write Write Write Write Write Write Write Read Read Read Oper
Addr(2)
Addr(2)
Data(3)
Write Write Write Write Write Write Write Write Write Write Write Write Write Write
NOTES: operations defined Table addresses which written first cycle should same addresses which written second cycle. X=Any valid address within device. IA=Identifier codes address (See Table QA=Query codes address. Refer Appendix LHF00LXX series details. BA=Address within block being erased, set/cleared block lock block lock-down bit. WA=Address memory location Program command. OA=Address block read programmed (See Figure ID=Data read from identifier codes. (See Table QD=Data read from query database. Refer Appendix LHF00LXX series details. SRD=Data read from status register. Table description status register bits. WD=Data programmed location Data latched rising edge (whichever goes high first) during command write cycles. OD=Data within block. Data latched rising edge (whichever goes high first) during command write cycles. Following Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code data within block (See Table Read Query command available reading (Common Flash Interface) information. Block erase, full chip erase program cannot executed when selected block locked. Unlocked block erased programmed when RST# VIH. Either recognized (Command User Interface) program setup. program operation erase operation both suspended, suspended program operation will resumed first. Full chip erase program operations suspended. Program command accepted while block erase operation being suspended.
Rev. 2.45
LHF00L28
Following Clear Block Lock command, block which locked-down unlocked when WP#/ACC VIL. When WP#/ACC VIH, lock-down disabled selected block unlocked regardless lock-down configuration. Commands other than those shown above reserved SHARP future device implementations should used.
Rev. 2.45
LHF00L28
Table Functions Block Lock(5) Block Lock-Down Current State State [000] [001](3) [011] [100] [101](3) [110](4) [111] WP#/ACC DQ1(1) DQ0(1) State Name Unlocked Locked Locked-down Unlocked Locked Lock-down Disable Lock-down Disable Erase/Program Allowed
NOTES: DQ0=1: block locked; DQ0=0: block unlocked. DQ1=1: block locked-down; DQ1=0: block locked-down. Erase program general terms, respectively, express: block erase, full chip erase program operations. power-up device reset, blocks default locked state locked-down, that [001] (WP#/ACC=0) [101] (WP#/ACC=1), regardless states before power-off reset operation. When WP#/ACC driven [110] state, state changes [011] blocks automatically locked. (One Time Program) block lock function which different from those described above.
Table Block Locking State Transitions upon Command Write(4) Current State State [000] [001] [011] [100] [101] [110] [111] WP#/ACC Result after Lock Command Written (Next State) Lock(1) [001] Change(3) Change [101] Change [111] Change Clear Lock(1) Change [000] Change Change [100] Change [110] Lock-down(1) [011](2) [011] Change [111](2) [111] [111](2) Change
NOTES: "Set Lock" means Block Lock command, "Clear Lock" means Clear Block Lock command "Set Lock-down" means Block Lock-Down command. When Block Lock-Down command written unlocked block (DQ0=0), corresponding block locked-down automatically locked same time. Change" means that state remains unchanged after command written. this state transitions table, assumes that WP#/ACC changed fixed VIH.
Rev. 2.45
LHF00L28
Table Block Locking State Transitions upon WP#/ACC Transition(4) Current State Previous State State [110](2) Other than [110](2) [100] [101] [110] [111] [000] [001] [011] WP#/ACC Result after WP#/ACC Transition (Next State) WP#/ACC=01(1) [100] [101] [110] [111] WP#/ACC=10(1) [000] [001] [011](3) [011]
NOTES: "WP#/ACC=01" means that WP#/ACC driven "WP#/ACC=10" means that WP#/ACC driven VIL. State transition from current state [011] next state depends previous state. When WP#/ACC driven [110] state, state changes [011] blocks automatically locked. this state transitions table, assumes that lock configuration commands written previous, current next state.
Rev. 2.45
LHF00L28
Table Status Register Definition WSMS BESS BEFCES POPS WPACCS NOTES:
SR.15 SR.8 RESERVED FUTURE ENHANCEMENTS SR.7 WRITE STATE MACHINE STATUS (WSMS) Ready Busy SR.6 BLOCK ERASE SUSPEND STATUS (BESS) Block Erase Suspended Block Erase Progress/Completed SR.5 BLOCK ERASE FULL CHIP ERASE STATUS (BEFCES) Error Block Erase Full Chip Erase Successful Block Erase Full Chip Erase SR.4 PROGRAM PROGRAM STATUS (POPS) Error Program Program Successful Program Program SR.3 WP#/ACC STATUS (WPACCS) VCC+0.4V WP#/ACC 11.7V Detect, Operation Abort WP#/ACC SR.2 PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SR.1 DEVICE PROTECT STATUS (DPS) Erase Program Attempted Locked Block, Operation Abort Unlocked SR.0 RESERVED FUTURE ENHANCEMENTS
Status Register indicates status (Write State Machine). Check SR.7 RY/BY# determine block erase, full chip erase, program program completion. SR.6 SR.1 invalid while SR.7="0". both SR.5 SR.4 "1"s after block erase, full chip erase, program, set/clear block lock bit, block lock-down attempt, improper command sequence entered. SR.3 does provide continuous indication WP#/ACC level. interrogates indicates WP#/ACC level only after Block Erase, Full Chip Erase, Program Program command sequences. SR.3 guaranteed report accurate feedback when WP#/ACCVACCH. SR.1 does provide continuous indication block lock bit. interrogates block lock only after Block Erase, Full Chip Erase, Program Program command sequences. informs system, depending attempted operation, block lock set. Reading block lock configuration codes after writing Read Identifier Codes/ command indicates block lock status. SR.15 SR.8 SR.0 reserved future should masked when polling status register.
Rev. 2.45
LHF00L28
Electrical Specifications Absolute Maximum Ratings*
Operating Temperature During Read, Erase Program .-40°C +85°C Storage Temperature During under Bias. -40°C +85°C During Bias. -65°C +125°C Voltage (except WP#/ACC) -0.5V VCC+0.5V Supply Voltage -0.2V +3.9V WP#/ACC Supply Voltage -0.2V +12.6V Output Short Circuit Current 100mA
*WARNING: Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability. NOTES: Operating temperature extended temperature product defined this specification. specified voltages with respect GND. Minimum voltage -0.5V input/output pins -0.2V WP#/ACC pins. During transitions, this level undershoot -2.0V periods <20ns. Maximum voltage input/output pins VCC+0.5V which, during transitions, overshoot VCC+2.0V periods <20ns. Maximum voltage WP#/ACC overshoot +13.0V periods <20ns. WP#/ACC erase/program voltage normally 2.7V3.6V. Applying 11.7V-12.3V WP#/ACC during erase/program done maximum 1,000 cycles each block. WP#/ACC connected 11.7V-12.3V total hours maximum. Output shorted more than second. more than output shorted time.
Operating Conditions
Parameter Operating Temperature Supply Voltage WP#/ACC Voltage when Used Logic Control WP#/ACC Supply Voltage Block Erase Cycling: WP#/ACC=VIL Block Erase Cycling: WP#/ACC=VACCH, hrs. Maximum WP#/ACC hours VACCH VACCH 11.7 100,000 1,000 12.0 Symbol Min. -0.2 Typ. Max. 12.3 Unit Cycles Cycles Hours Notes
NOTES: Characteristics tables voltage range-specific specification. Applying WP#/ACC=11.7V-12.3V during erase program done maximum 1,000 cycles each block. permanent connection WP#/ACC=11.7V-12.3V allowed cause damage device.
Rev. 2.45
LHF00L28
1.2.1 Capacitance (TA=+25°C, f=1MHz)
Parameter Input Capacitance WP#/ACC Input Capacitance Output Capacitance NOTE: Sampled, 100% tested. Symbol COUT Condition VIN=0.0V VIN=0.0V VOUT=0.0V Min. Typ. Max. Unit
1.2.2 Input/Output Test Conditions
INPUT test inputs driven VCC(min) Logic 0.0V Logic "0". Input timing begins, output timing ends VCC/2. Input rise fall times (10% 90%) 5ns. Worst case speed conditions when VCC=VCC(min). VCC/2 TEST POINTS VCC/2 OUTPUT
Figure Transient Input/Output Reference Waveform VCC=2.7V-3.6V
Table Test Configuration Capacitance Loading Value
VCC(min)/2
1N914
Test Configuration VCC=2.7V-3.6V
(pF)
RL=3.3K DEVICE UNDER TEST Includes Capacitances.
Figure Transient Equivalent Testing Load Circuit
Rev. 2.45
LHF00L28
1.2.3 Characteristics
VCC=2.7V-3.6V Symbol Parameter Input Load Current Output Leakage Current Notes Min. -1.0 -1.0 Typ. Max. +1.0 +1.0 Unit Test Conditions VCC=VCCMax., VIN/VOUT=VCC VCC=VCCMax., CE#=RST#= VCC±0.2V, WP#/ACC=VCC VCC=VCCMax., CE#=GND±0.2V, WP#/ACC=VCC RST#=GND±0.2V VCC=VCCMax., CE#=VIL, OE#=VIH, f=5MHz WP#/ACC=VIL WP#/ACC=VACCH WP#/ACC=VIL WP#/ACC=VACCH CE#=VIH WP#/ACCVCC WP#/ACC=VIL WP#/ACC=VACCH WP#/ACC=VIL WP#/ACC=VACCH WP#/ACC=VIL WP#/ACC=VACCH WP#/ACC=VIL WP#/ACC=VACCH
ICCS
Standby Current
1,6,7
ICCAS
Automatic Current Reset Current
Power
Savings
1,3,6
ICCD
ICCR
Read Current
ICCW ICCE ICCWS ICCES IACCS IACCR IACCW IACCE IACCWS IACCES
Program Current Block Erase, Full Chip Erase Current Program Block Erase Suspend Current WP#/ACC Standby Read Current WP#/ACC Program Current WP#/ACC Block Erase, Full Chip Erase Current WP#/ACC Program Suspend Current WP#/ACC Current Block Erase Suspend
1,4,6 1,4,6 1,4,6 1,4,6 1,2,6 1,5,6 1,4,5,6 1,4,5,6 1,4,5,6 1,4,5,6 1,5,6 1,5,6 1,5,6 1,5,6
Rev. 2.45
LHF00L28
Characteristics (Continued) VCC=2.7V-3.6V Symbol VACCH VLKO Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage WP#/ACC during Block Erase, Full Chip Erase, Program Program Operations Lockout Voltage Notes -0.2 11.7 12.0 12.3 Min. -0.4 Typ. Max. Unit VCC=VCCMin., IOL=100µA VCC=VCCMin., IOH=-100µA Test Conditions
NOTES: currents unless otherwise noted. Typical values reference values VCC=3.0V TA=+25°C unless specified. ICCWS ICCES specified with device de-selected. read program executed while block erase suspend mode, device's current draw ICCES ICCR ICCW. read executed while program suspend mode, device's current draw ICCWS ICCR. Automatic Power Savings (APS) feature automatically places device power save mode after read cycle completion. Standard address access timings (tAVQV) provide data when addresses changed. Sampled, 100% tested. Applying 12.0V±0.3V WP#/ACC provides fast erasing fast programming mode. this mode, WP#/ACC power supply supplies memory cell current block erasing programming. similar power supply trace widths layout considerations given power bus. Applying 12.0V±0.3V WP#/ACC during erase/program only done maximum 1,000 cycles each block. WP#/ACC connected 12.0V±0.3V total hours maximum. pins other than those shown test conditions, input level GND. Includes RY/BY#.
Rev. 2.45
LHF00L28
1.2.4 Characteristics Read-Only Operations(1)
VCC=2.7V-3.6V, TA=-40°C +85°C Symbol tAVAV tAVQV tELQV tGLQV tPHQV tEHQZ, tGHQZ tELQX tGLQX Read Cycle Time Address Output Delay Output Delay Output Delay RST# High Output Delay Output High Whichever Occurs First Output Output Output Hold from First Occurring Address, change Parameter Notes Min. Max. Unit
NOTES: input/output reference waveform timing measurements maximum allowable input slew rate. Sampled, 100% tested. delayed tELQV tGLQV after falling edge without impact tELQV.
Rev. 2.45
LHF00L28
A19-0 A20-0
VALID ADDRESS tAVAV tAVQV tEHQZ tGHQZ
tELQV
tGLQV tGLQX tELQX VALID OUTPUT tPHQV
DQ15-0 (D/Q)
High
RST#
Figure Waveform Read Operations
Rev. 2.45
LHF00L28
1.2.5 Characteristics Write Operations(1),
VCC=2.7V-3.6V, TA=-40°C +85°C Symbol tAVAV tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tSHWH (tSHEH) tWHGL (tEHGL) tQVSL tWHR0 (tEHR0) tWHRL (tEHRL) Write Cycle Time RST# High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High (CE#) Pulse Width High WP#/ACC High Setup (CE#) WP#/ACC=VIH Going High WP#/ACC=VACCH Write Recovery before Read WP#/ACC High Hold from Valid SRD, RY/BY# High (CE#) High SR.7 Going (CE#) High RY/BY# Going Parameter Notes Min. tAVQV Max. Unit
NOTES: timing characteristics reading status register during block erase, full chip erase, program program operations same during read-only operations. Refer Characteristics read-only operations. write operation initiated terminated with either WE#. Sampled, 100% tested. Write pulse width (tWP) defined from falling edge (whichever goes last) rising edge (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. Write pulse width high (tWPH) defined from rising edge (whichever goes high first) falling edge (whichever goes last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. tWHR0 (tEHR0) after Read Query Read Identifier Codes/OTP command=tAVQV+100ns. Refer Table valid address data block erase, full chip erase, program, program lock configuration.
Rev. 2.45
LHF00L28
NOTE A19-0 20-0
NOTE
VALID ADDRESS tAVAV
NOTE
VALID ADDRESS tAVWH (tAVEH)
NOTE
VALID ADDRESS
NOTE
tELWL (tWLEL) tWHEH (tEHWH)
tWHAX (tEHAX)
NOTES
tWHGL (tEHGL)
tPHWL (tPHEL) tWLWH (tELEH tWHWL (tEHEL)
NOTES
tWHQV1,2,3,4 (tEHQV1,2,3,4) tWHDX (tEHDX) tDVWH (tDVEH)
DQ15-0 (D/Q)
DATA DATA tWHRL (tEHRL) (tWHR0 (tEHR0))
VALID
High
RY/BY# ("1") (SR.7)
("0")
RST#
tSHWH (tSHEH) tQVSL
WP#/ACC
VACCH
NOTES: power-up standby. Write each first cycle command. Write each second cycle command valid address data. Automated erase program delay. Read status register data. read operation, must driven active, de-asserted.
Figure Waveform Write Operations
Rev. 2.45
LHF00L28
1.2.6 Reset Operations
tPHQV RST#
High
tPLPH
VALID OUTPUT
DQ15-0 (D/Q)
Reset during Read Array Mode
ABORT COMPLETE
SR.7="1"
tPLRH RST#
tPHQV
High
tPLPH
VALID OUTPUT
DQ15-0 (D/Q) VCC(min)
Reset during Erase Program Mode
tVHQV t2VPH tPHQV
RST#
High
VALID OUTPUT
DQ15-0 (D/Q)
RST# rising timing
Figure Waveform Reset Operations Reset Specifications (VCC=2.7V-3.6V, TA=-40°C +85°C)
Symbol tPLPH tPLRH t2VPH tVHQV
Parameter RST# Reset during Read (RST# should during power-up.) RST# Reset during Erase Program 2.7V RST# High 2.7V Output Delay
Notes
Min.
Max.
Unit
NOTES: reset time, tPHQV, required from later SR.7 (RY/BY#) going (High RST# going high until outputs valid. Refer Characteristics Read-Only Operations tPHQV. tPLPH <100ns device still reset this guaranteed. Sampled, 100% tested. RST# asserted while block erase, full chip erase, program program operation executing, reset will complete within 100ns. When device power-up, holding RST# minimum 100ns required after been predefined range also been stable there.
Rev. 2.45
LHF00L28
1.2.7 Block Erase, Full Chip Erase, Program Program Performance(3)
VCC=2.7V-3.6V, TA=-40°C +85°C WP#/ACC=VIL WP#/ACC=VACCH System) Manufacturing) Notes Min. Typ.(1) Max.(2) Min. Typ.(1) Max.(2) 0.05 0.34 0.68 0.26 0.51 0.82 0.04 0.31 0.62 16.5 0.12
Symbol
Parameter 4-Kword Parameter Block Program Time 32-Kword Block Program Time 64-Kword Block Program Time Word Program Time Program Time 4-Kword Parameter Block Erase Time 32-Kword Block Erase Time 64-Kword Block Erase Time Full Chip Erase Time
Unit
tWPB tWMB1 tWMB2 tWHQV1/ tEHQV1 tWHOV1/ tEHOV1 tWHQV2/ tEHQV2 tWHQV3/ tEHQV3 tWHQV4/ tEHQV4 tWHRH1/ tEHRH1 tWHRH2/ tEHRH2 tERES
Program Suspend Latency Time Read Block Erase Suspend Latency Time Read Latency Time from Block Erase Resume Command Block Erase Suspend Command
NOTES: Typical values measured VCC=3.0V, WP#/ACC=3.0V 12.0V, TA=+25°C. Assumes corresponding lock bits set. Subject change based device characterization. Excludes external system-level overhead. Sampled, 100% tested. latency time required from writing suspend command (WE# going high) until SR.7 going RY/BY# going High interval time from Block Erase Resume command subsequent Block Erase Suspend command shorter than tERES sequence repeated, block erase operation finished.
Rev. 2.45
LHF00L28 Related Document Information(1)
Document FUM03802 NOTE: International customers should contact their local SHARP distribution sales offices. Document Name LHF00LXX series Appendix
Rev. 2.45
RECOMMENDED OPERATING CONDITIONS A-1.1 Device Power-Up
timing illustrated Figure recommended supply voltages control signals device power-up. timing figure ignored, device operate correctly.
VCC(min) (RST#) ADDRESS
t2VPH
tPHQV
tAVQV Valid Address tELQV
tGLQV
DATA High Valid Output
(D/Q)
Figure A-1. Timing Device Power-Up specifications tVR, figure, refer next page. "ELECTRICAL SPECIFICATIONS" described specifications supply voltage range, operating temperature specifications shown next page.
Rev. 1.10
A-1.1.1 Rise Fall Time
Symbol Rise Time
Parameter
Notes
Min.
Max. 30000
Unit µs/V µs/V µs/V
Input Signal Rise Time Input Signal Fall Time
NOTES: Sampled, 100% tested. This specification applied only device power-up also normal operations.
Rev. 1.10
A-1.2 Glitch Noises
input glitch noises which below (Min.) above (Max.) address, data, reset, control signals, shown Figure (b). acceptable glitch noises illustrated Figure (a).
Input Signal (Min.)
Input Signal (Min.)
(Max.)
(Max.)
Input Signal
Input Signal
Acceptable Glitch Noises
Acceptable Glitch Noises
Figure A-2. Waveform Glitch Noises
CHARACTERISTICS" described specifications (Min.) (Max.).
Rev. 1.10
RELATED DOCUMENT INFORMATION(1)
Document AP-001-SD-E AP-006-PT-E AP-007-SW-E
Document Name Flash Memory Family Software Drivers Data Protection Method SHARP Flash Memory RP#, Electric Potential Switching Circuit
NOTE: International customers should contact their local SHARP distribution sales office.
Rev. 1.10
SPECIFICATIONS SUBJECT CHANGE WITHOUT NOTICE.
Suggested applications any) standard use; Important Restrictions limitations special applications. Limited Warranty SHARP's product warranty. Limited Warranty lieu, exclusive other warranties, express implied. EXPRESS IMPLIED WARRANTIES, INCLUDING WARRANTIES MERCHANTABILITY, FITNESS FITNESS PARTICULAR PURPOSE, SPECIFICALLY EXCLUDED. event will SHARP liable, responsible, incidental consequential economic property damage.
NORTH AMERICA
EUROPE
JAPAN
SHARP Microelectronics Americas 5700 Pacific Blvd. Camas, 98607, U.S.A. Phone: 360-834-2500 Fax: 360-834-8903 Fast Info: 800-833-9437 www.sharpsma.com
SHARP Microelectronics Europe Division Sharp Electronics (Europe) GmbH Sonninstrasse 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com
SINGAPORE
SHARP Corporation Electronic Components Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com
TAIWAN
KOREA
SHARP Electronic Components (Taiwan) Corporation 8F-A, Sec. Nanking Taipei, Taiwan, Republic China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328
SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855
SHARP Electronic Components (Korea) Corporation Geosung B/D, Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 Fax: (82) 2-711-5819
CHINA
HONG KONG
SHARP Microelectronics China (Shanghai) Co., Ltd. Qiao Road King Tower Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: 360, Bashen Road, Development Bldg. Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd. Business Division, 17/F, Admiralty Centre, Tower Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower Electronics Science Technology Building Shen Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735

Flash Memory (1Mb (Model Number: LHF00L28) Spec. Issue Date:

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