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Section HardCopy Device Family Data Sheet
This section provides designers with data sheet specifications HardCopy® devices. These chapters contain feature definitions internal architecture, configuration JTAG boundary-scan testing information, operating conditions, timing parameters, reference power consumption, ordering information HardCopy devices. This section contains following:
Chapter Introduction HardCopy Devices Chapter Description, Architecture Features Chapter Boundary-Scan Support Chapter Operating Conditions Chapter Quartus Support Hardcopy Devices Chapter Script-Based Design HardCopy Devices Chapter Hardcopy Timing constraints Chapter Migrating Stratix Device Resources HardCopy Devices
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Section Preliminary
HardCopy Device Family Data Sheet
HardCopy Series Handbook, Volume
Revision History
table below shows revision history Chapters through Chapter(s)
Chapter
Date Version
March 2006, v2.3 October 2005, v2.2. July 2005, v2.2. 2005, v2.0
Changes Made
Updated Table Table 1-3. Minor edits clarifications throughout.
Updated graphics Updated graphics
Updated Table 1-1. Updated migration process time. Updated "Features" section.
January 2005 v1.0 Chapter March 2006, v2.2
Added document HardCopy Series Handbook.
Updated Table 2-1, Table 2-9, Table 2-13. Updated Figure Figure 2-5.
October 2005, v2.1 2005, v2.0
Updated graphics.
Added Table 2-1. Updated HCell information functions Functional Description section. Updated Table 2-9. Updated Figures 2-4, 2-5, 2-6.
January 2005 v1.0 Chapter October 2005, v2.1 2005, v2.0 January 2005 v1.0 Chapter October 2005, v2.1 2005, v2.0 January 2005 v1.0
Added document HardCopy Series Handbook. Updated graphics. Updated Table 3-2. Added document HardCopy Series Handbook. Updated graphics. Updated various tables throughout chapter. Added document HardCopy Series Handbook.
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HardCopy Device Family Data Sheet
Chapter(s)
Chapter
Date Version
change. October 2005 v2.1
Changes Made
Formerly chapter content change. Moved Chapter Quartus Support HardCopy Devices Chapter Hardcopy Series Device Handbook 3.2. Updated Graphics. Updated technical content Quartus support HardCopy devices.
2005 v2.0 January 2005 v1.0 Chapter change.
Added information support HardCopy devices version Quartus software. Added document HardCopy Series Handbook. Formerly chapter content change.
October 2005 v1.0 Initial release Script-Based Design Hardcopy Devices. Chapter Chapter March 2006, v1.0 change. Added document HardCopy Series Handbook. Formerly chapter content change.
October 2005 v1.1 Minor edits 2005 v1.0 Added document HardCopy Series Handbook.
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HardCopy Device Family Data Sheet
HardCopy Series Handbook, Volume
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Introduction HardCopy Devices
H51015-2.3
Introduction
HardCopy devices low-cost, high-performance structured ASICs with outs, densities, architecture that complement Stratix® FPGAs. HardCopy device features, such PLLs, memory, elements (IOEs), functionally electrically equivalent Stratix FPGA features. combination Stratix FPGAs in-system prototype design verification, HardCopy devices high volume production, Quartus® design software, provide complete, low-risk structured ASIC solution. Altera® HardCopy devices same base arrays across multiple designs given device density customized using only metal layers. Designers Quartus software design with Stratix FPGAs before migrating their design corresponding HardCopy device. typical designs, HardCopy devices offer over 350-MHz system performance, more than power reduction (dynamic static), cost reduction compared Stratix FPGA prototypes. Quartus software provides complete tools designing HardCopy devices. Additionally, HardCopy devices also supported through other front-end design tools, such tools from Synopsys, Synplicity, Mentor Graphics. Stratix FPGA designs seamlessly quickly migrated HardCopy devices, low-cost ASIC alternative. HardCopy devices improve successful proven methodology previous generations HardCopy series devices. migration process fully automated takes approximately weeks from design submission receipt fully tested HardCopy prototypes.
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HardCopy Series Handbook, Volume
HardCopy device family consists five devices. Table summarizes features available HardCopy devices.
Table 1-1. HardCopy Device Family Features Feature
ASIC gates Additional gates digital signal processing (DSP) block blocks Kbits plus parity) M-RAM blocks (512 Kbits plus parity) Total bits (including parity bits) Enhanced PLLs Fast PLLs Maximum user pins (5), Notes Table 1-1:
HC210W devices wire-bond package. other HardCopy devices Stratix FPGAs flip-chip package. Devices wire-bond package offer different performance signal integrity characteristics compared devices flip-chip package. This number ASIC gates available HardCopy base array both logic functions that implemented Stratix FPGA prototype. This number includes additional ASIC gates available Stratix functions. Total number usable blocks 768, which allows migration compatibility when prototyping with EP2S180 device. This different from Quartus software total physical count HC240. counts include dedicated input pins, which used clock signals data inputs. Quartus counts include additional (PLLENA), which available general-purpose pin. PLLENA only used enable PLLs.
HC210W
1,000,000
HC210
1,000,000
HC220
1,600,000 300,000
HC230
2,200,000 700,000
HC240
2,200,000 1,400,000
875,520
875,520
3,059,712
6,368,256
8,847,360
HardCopy devices offer pin-to-pin compatibility Stratix prototype, which makes them drop-in replacements FPGAs. Therefore, same system board software developed prototyping field trials retained, enabling fastest time-tomarket high-volume production. When migrating specific Stratix
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Features
FPGA HardCopy device, there number FPGA prototype choices, shown Table 1-2. Depending design resource needs, designers choose appropriate HardCopy device.
Table 1-2. HardCopy Options Stratix Device HardCopy Device EP2S30
HC210W 484-pin FineLine BGA®
EP2S60
EP2S90
EP2S130
EP2S180
HC210 484-pin FineLine HC220 672-pin FineLine HC220 780-pin FineLine HC230 1,020-pin FineLine HC240 1,020-pin FineLine HC240 1,508-pin FineLine Note Table 1-2:
HC210W device uses wire-bond package while Stratix FPGA prototype device uses pin-compatible flip-chip package.
more information migration path from Stratix FPGAs HardCopy devices, refer Prototyping Strategy HardCopy Devices chapter HardCopy Series Handbook. HardCopy structured ASICs manufactured all-layer-copper metal fabrication process nine layers metal). HardCopy devices offer following features:
Features
Fine-grained architecture resulting low-cost, high-performance, low-power structured ASIC Customized using only metal layers fast turn-around times non-recurring expenses (NRE) Preserves design functionality Stratix FPGA prototype Pin-compatible with Stratix FPGA prototypes Typical system performance more than Over power reduction (dynamic static) typical designs compared Stratix FPGA prototypes 1,000,000 3,600,00 usable gates both logic functions 9,068,544 bits available, including parity bits user pins available Memory blocks implement true dual-port memory first-in-first-out (FIFO) buffers
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HardCopy Series Handbook, Volume
global clocks with clocking resources device region Clock control block supports dynamic clock network enable/disable dynamic global clock network source selection PLLs (four enhanced PLLs eight fast PLLs) device which provide identical features FPGA counterparts, including spread spectrum, programmable bandwidth, clock switchover, real-time reconfiguration, advanced multiplication, phase shifting Support numerous single-ended differential standards such LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL, LVDS High-speed differential support channels with dynamic phase alignment (DPA) circuitry 1-Gigabits-per-second (Gbps) performance Support high-speed networking communications standards including Parallel RapidIO, SPI-4 Phase (POS-PHY Level HyperTransporttechnology, SFI-4 Support high-speed external memory, including DDR2 SDRAM, RLDRAM QDRII SRAM, SDRAM Support multiple intellectual property (IP) megafunctions from Altera MegaCore® functions, Altera Megafunction Partners Program (AMPPSM) megafunctions HardCopy devices available wire-bond flip-chip space-saving FineLine packages (Tables 1-4) Support instant instant after power-up modes
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Features
actual performance power consumption improvements mentioned this data sheet design-dependent.
Table 1-3. HardCopy Package Options Counts Device
HC210W HC210 HC220
Notes (1), 780-Pin FineLine 1,020-Pin FineLine 1,508-Pin FineLine
484-Pin FineLine
484-Pin FineLine
672-Pin FineLine
HC230 HC240
Notes Table 1-3:
Quartus counts include additional (PLLENA) which available general-purpose pin. PLLENA only used enable PLLs. counts include dedicated input pins, which used clock signals data inputs. This wire-bond package. This flip-chip package.
Table 1-4. HardCopy FineLine Package Sizes Dimension
Pitch (mm) Area (mm2)
1.00
1.00
1.00
1,020
1.00 1,089
1,508
1.00 1,600
Length width Note Table 1-4:
EP2S90 FPGA prototype uses 484-pin hybrid FineLine package. more information, refer Stratix FPGA Handbook.
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HardCopy Series Handbook, Volume
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Description, Architecture Features
H51016-2.2
Introduction
Altera® HardCopy devices feature architecture that provides high density, high performance, power consumption suitable variety applications. HardCopy devices low-cost structured ASICs with pin-outs, densities, architecture that complement Stratix FPGAs. HardCopy devices make optimal area core resources while offering features that functionally equivalent Stratix FPGA. combination Stratix FPGAs in-system prototype design verification, HardCopy devices high volume production, Quartus® design software, provide complete, seamless path from prototype volume production. Table provides overview HardCopy device features.
Table 2-1. Hardcopy Family Overview (Part Feature
ASIC gates Additional gates digital signal processing (DSP) blocks blocks bits plus parity) M-RAM blocks (512k bits plus parity) Total bits (including parity bits) Enhanced PLLs Fast PLLs Package (maximum user pins) (5),
HC210W
1,000,000
HC210
1,000,000
HC220
1,600,000 300,000
HC230
2,200,000 700,000
HC240
2,200,000 1,400,000
875,520
875,520 484-pin FineLine (334)
3,059,712 672-pin FineLine (492) 780-pin FineLine (494)
6,368,256 1,020-pin FineLine (698)
8,847,360 1,020-pin FineLine (742) 1,508-pin FineLine (951)
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HardCopy Series Handbook, Volume
Table 2-1. Hardcopy Family Overview (Part Feature
FPGA prototype options Notes Table 2-1:
HC210W devices wire-bond package. other HardCopy devices Stratix FPGAs flip-chip package. Devices wire-bond package offer different performance signal integrity characteristics compared devices flip-chip package. This number ASIC gates available HardCopy base array both logic functions that implemented Stratix FPGA prototype. This number includes additional ASIC gates available Stratix functions. Total number usable blocks 768, which allows migration compatibility when prototyping with EP2S180 device. This different from Quartus software total physical count HC240. counts include dedicated clock input pins, which used clock signals data inputs. Quartus counts include additional (PLLENA), which available general-purpose pin. PLLENA only used enable PLLs.
HC210W
EP2S30 EP2S60 EP2S90
HC210
EP2S30 EP2S60 EP2S90
HC220
EP2S60 EP2S90 EP2S130
HC230
EP2S90 EP2S130 EP2S180
HC240
EP2S180
Functional Description
Hardcopy device family provides greater flexibility design with FPGA prototypes before moving structured ASICs production. Before seamlessly migrating HardCopy structured ASIC, designer prototype test their design functionality using Stratix FPGA. There multiple options prototype FPGA, allowing designers choose right HardCopy device volume production maximum cost savings. Quartus design software includes features such Device Resource Guide, help select optimal HardCopy device based design requirements. more information Device Resource Guide, refer Quartus Support HardCopy Devices chapter HardCopy Series Handbook. HardCopy devices require minimal involvement from designer device migration process. Additionally, unlike ASICs, designer required generate test benches, test vectors, timing functional simulations since prototyping performed using FPGA.
more information migration path from Stratix FPGAs HardCopy devices, refer Prototyping Strategy HardCopy Using Stratix FPGA chapter HardCopy Series Handbook. HardCopy devices consist base arrays that common designs particular device density, with design-specific customization done using metal layers. reprogrammable FPGA logic, routing, memory, FPGA configuration-related logic stripped from
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Functional Description
HardCopy devices. Removing programmable configuration resources replacing them with direct metal connections results considerable size reduction cost savings. fine-grain architecture consisting array HCells extends reduction cost savings, which results low-cost structured ASICs with high performance power suitable wide variety applications. SRAM configuration cells Stratix FPGAs replaced HardCopy devices with metal connections, which define function logic, memory, phase-locked loop (PLL), elements (IOEs) device. These resources interconnected using metallization layers. Once HardCopy device manufactured, functionality device fixed. HardCopy devices manufactured using same process technology operate using same core voltage (1.2 Stratix FPGAs. Additionally, almost architectural features HardCopy devices functionally equivalent features found Stratix FPGA architecture. HardCopy devices feature HCells, memory blocks, PLLs, IOEs (Figure 2-1).
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HardCopy Series Handbook, Volume
Figure 2-1. Example Block Diagram HC230 Device
Blocks Array HCells Blocks
Note
IOEs
Array HCells Enhanced
Fast
Array HCells
M-RAM Block
Fast Array HCells Array HCells Array HCells
Note Figure 2-1:
Figure shows graphical representation device floor plan. detailed floor plan available Quartus software.
HardCopy Stratix Similarities Differences
HardCopy devices preserve functionality Stratix FPGAs. Implementation these architectural features HardCopy structured ASICs matches Stratix FPGA implementation, with exceptions. Table shows qualitative comparison HardCopy device feature
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HardCopy Stratix Similarities Differences
implementation versus Stratix FPGA feature implementation. Other sections within this chapter provide details similarities differences particular HardCopy feature.
Table 2-2. HardCopy Device Stratix FPGA Feature Implementation Feature
Logic blocks blocks Memory Clock networks PLLs features Configuration Note Table 2-2:
HardCopy structured ASICs need configured upon power-up.
Equivalent
Different
major similarities differences between Stratix FPGAs HardCopy devices highlighted below:
HardCopy devices consume less than power equivalent Stratix FPGAs operating same frequency. Power consumption design dependent direct result design performance resource utilization. HardCopy devices offer 100% performance improvement when compared Stratix FPGA prototypes. performance improvement achieved efficient logic blocks, metal interconnect optimization, size reduction, customized signal buffering. Logic blocks, known HCells, basic building block core logic HardCopy devices replace Stratix adaptive logic modules (ALMs). HCells implement logic functions. block functions implemented using HCells, instead dedicated blocks. M-RAM memory blocks implement various types memory (the same Stratix FPGAs), with without parity, including true dual-port, simple dual-port, single-port RAM, ROM, first-in first-out (FIFO) buffers. Unlike Stratix FPGAs, HardCopy block contents cannot pre-loaded with Memory Initialization File (.mif) when used RAM. When used ROM, HardCopy blocks initialized contents.
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HardCopy Series Handbook, Volume
When used RAM, HardCopy M-RAM blocks power with outputs unknown. Stratix FPGAs, blocks power with outputs cleared, while M-RAM blocks power with outputs unknown. HardCopy clock network features same Stratix FPGAs. Enhanced fast implementations HardCopy devices same Stratix FPGAs. Stratix features supported standards offered HardCopy devices. Joint Test Action Group (JTAG) boundary scan order length HardCopy devices different than that Stratix FPGA. HardCopy boundary-scan description language (BSDL) file that describes re-ordered shortened boundary scan chain. Unlike Stratix devices, HardCopy devices customized using metal layers. Therefore, configuration circuitry required. FPGA configuration emulation other configuration modes, including remote system upgrades design security using configuration bitstream encryption, supported HardCopy devices. Only supplementary information highlight HardCopy similarities differences compared Stratix FPGA architecture functionality provided this chapter. Refer Stratix Device Handbook detailed explanations architectural features functions.
HCells
HardCopy devices built using array fine-grained architecture blocks called HCells. HCells collection logic transistors based process technology, similar Stratix devices. construction logic using HCells allows flexible functionality such that when HCells combined, viable logic combinations Stratix functionality replicated. These HCells constitute array HCells area Figure 2-1. Only HCells needed implement customer design assembled together, which optimizes HCell utilization. unused area HCell logic fabric powered down, resulting significant power savings compared with Stratix FPGA prototype. Quartus software uses library pre-characterized HCell macros place Stratix configurations into HardCopy HCell-based logic fabric. HCell macro defines group HCells connected together within array. HCell macros construct combinations combinational logic, adder, register functions that implemented Stratix ALM. HCells used configurations used implement block functions.
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HCells
Based design requirements, Quartus software will chose appropriate HCell macros implement design functionality. example, Stratix ALMs offer flexible look-up table (LUT) blocks, registers, arithmetic blocks, LAB-wide control signals. HardCopy devices, user's design requires these architectural elements, Quartus synthesis tool will design appropriate HCells, resulting improved design performance compared Stratix FPGA prototype. Stratix FPGAs have dedicated blocks implement various functions. Stratix blocks consist multiplier block, adder/subtractor/accumulator block, summation block, input output interfaces, input output registers. HardCopy devices, HCell macros implement Stratix block functionality with area efficiency performance with dedicated blocks Stratix FPGAs. There eight HCell macros which implement eight supported modes operation Stratix block:
multiplier two-multiplier adder complex multiply) four-multiplier adder multiplier two-multiplier adder complex multiply) four-multiplier adder 52-bit multiplier-accumulator multiplier
Only HCells that required implement design's functions enabled. HCells needed functions used configurations, which results efficient logic usage. addition area management, placement these HCell macros allows optimized routing performance. example efficient logic area usage seen when comparing multiplier implementation Stratix FPGAs using dedicated block versus implementation HardCopy devices using HCells. Stratix function only calls multiplier, other three multipliers block's adder output block used (Figure 2-2). HardCopy devices, HCell-based logic fabric that used functions used implement other combinational logic, adder, register functions.
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HardCopy Series Handbook, Volume
Figure 2-2. Stratix Block HardCopy HCell 18-Bit Multiplier Implementation
Stratix Block Input Registers Output Registers HardCopy HCell-Based Logic Fabric Input Registers Output Registers
Multiplier
Multiplier
Multiplier
These elements implemented using HCell macros. Adder/ Subtractor/ Accumulator Block
Input Registers
Multiplier
Output Registers
Multiplier
Unused logic area used perform other logic functions.
Used portions block Unused portions block
HardCopy devices support Stratix configurations multipliers) Stratix block features, such dynamic sign controls, dynamic addition/subtraction, saturation, rounding, dynamic input shift registers, except dynamic mode switching. Dynamic mode switching allows designer each Stratix block dynamically switch between following three modes:
four 18-bit independent multipliers 8-bit multiplier-accumulators 36-bit multiplier
Each half Stratix block separate mode control signals. Since block functions implemented HardCopy devices using HCells, HardCopy devices support dynamic mode switching. this feature used, Quartus software flags implementation does allow migrate design. fitter reports that HardCopy devices compatible with design. migrate your Stratix design HardCopy companion device, disable dynamic switching blocks.
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Embedded Memory
more information Stratix operational modes, refer Stratix Device Handbook. HardCopy memory blocks implement various types memory with without parity, including true dual-port, simple dual-port, single-port RAM, ROM, FIFO buffers. HardCopy devices support same memory functions features Stratix FPGAs. Functionally, memory both devices identical. However, number available memory blocks differs based density (Table 2-3).
Embedded Memory
Table 2-3. Hardcopy Embedded Memory Resources Feature
blocks Kbits) M-RAM blocks (512 Kbits) Total bits (bits)
HC210W
875,520
HC210
875,520
HC220
3,059,712
HC230
6,368,256
HC240
8,847,360
Since device functionality fixed HardCopy devices, block contents cannot preloaded initialized with when they configured RAM. When blocks used ROM, they will initialize design's contents. Unlike Stratix FPGA, Hardcopy memory block power-up conditions behave like M-RAM blocks. This means that output registers memory blocks will have unknown output conditions. designer must take this into consideration when designing logic that might evaluate initial power-up values memory block. HardCopy embedded memory consists M-RAM memory blocks have one-to-one mapping from Stratix M-RAM resources. Table shows size features different blocks.
more information Stratix memory block features, refer Stratix Device Handbook. Both HardCopy enhanced fast PLLs feature rich, supporting advanced capabilities such clock switchover, reconfigurable phase shift, reconfiguration, reconfigurable bandwidth. PLLs used general-purpose clock management, supporting multiplication, division, phase shifting, programmable duty cycle. addition,
PLLs Clock Networks
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HardCopy Series Handbook, Volume
Table 2-4. HardCopy Embedded Memory Features Feature
Maximum performance Total bits (including parity bits) Configurations
Blocks
4,608
M-RAM Blocks
589,824
Parity bits Byte enable Pack mode Address clock enable Single-port memory Simple dual-port memory True dual-port memory Embedded shift register FIFO buffer Simple dual-port mixed width support True dual-port mixed width support Memory initialization file (.mif) Mixed-clock mode Power-up condition Register clears Same-port read-during-write
Outputs unknown Output registers only data available positive clock edge
Outputs unknown Output registers only data available positive clock edge
Mixed-port read-during-write Note Table 2-4:
Outputs Unknown output unknown data
Maximum performance information preliminary until device characterization.
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PLLs Clock Networks
enhanced PLLs support external clock feedback mode, spread-spectrum clocking, counter cascading. Fast PLLs offer high speed outputs manage high-speed differential interfaces. Stratix features supported HardCopy PLLs.
Similar Stratix FPGAs, HardCopy devices also support powerdown mode where unused clock networks disabled. HardCopy Stratix clock control blocks support dynamic selection input clock from four possible sources, giving designer flexibility choose from multiple four) clock sources.
Enhanced Fast PLLs
number PLLs available differs based density (Table 2-5).
Table 2-5. HardCopy PLLs Feature
Enhanced PLLs Fast PLLs
HC210W
HC210
HC220
HC230
HC240
target HardCopy device support same number enhanced PLLs prototyping Stratix FPGA. However, since HardCopy enhanced PLLs fast PLLs offer similar feature (Table page 2-14), fast could used place enhanced PLL. type used design should chosen using Quartus software accommodate resources available HardCopy device. Table shows which PLLs available each device density. Figure shows location each PLL. During prototyping stage using FPGA, must select appropriate number enhanced fast PLLs that will used your HardCopy device. Table ensure that FPGA prototyping design uses same resources available HardCopy device.
Table 2-6. HardCopy PLLs Available Device
HC210W HC210
Note Enhanced PLLs
Fast PLLs
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HardCopy Series Handbook, Volume
Table 2-6. HardCopy PLLs Available Device
HC220 HC230 HC240
Note Enhanced PLLs
Fast PLLs
Note Table 2-6:
performance HC210W device differ from Stratix FPGA prototype.
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PLLs Clock Networks
Figure 2-3. HardCopy Locations
Notes (1),
CLK[15.12]
FPLL7CLK
FPLL10CLK
CLK[3.0]
CLK[8.11]
PLLs
FPLL8CLK
FPLL9CLK
CLK[7.4]
Notes Figure 2-3:
PLLs located periphery core device. This die-level view device only graphical representation locations.
functionality HardCopy devices remains same Stratix FPGA PLLs. Therefore, Hardcopy PLLs support reconfiguration (the dynamically configured user mode).
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2-13 Preliminary
HardCopy Series Handbook, Volume
HardCopy enhanced fast PLLs support one-to-one mapping from Stratix resources. Table shows features different PLLs. more information Stratix features, refer Stratix Device Handbook.
Table 2-7. HardCopy Features Feature
Clock multiplication division Phase shift Clock switchover reconfiguration Reconfigurable bandwidth Spread-spectrum clocking Programmable duty cycle Number clock outputs
Enhanced
m/(n post-scale counter) Down 125-ps increments
Fast
m/(n post-scale counter) Down 125-ps increments
Number dedicated external clock outputs Three differential singledper ended Number feedback clock inputs Notes Table 2-7:
enhanced PLLs, range from post-scale counters range from with duty cycle. non-50% duty-cycle clock outputs, post-scale counters range from 256. fast PLLs, range from post-scale counters range from non-50% duty-cycle clock outputs, post-scale counters range from smallest phase shift determined voltage controlled oscillator (VCO) period divided eight. supported phase shift range from HardCopy devices shift output frequencies increments least Smaller degree increments possible depending frequency divide parameters. non-50% duty cycle clock outputs post-scale counters range from 256. HardCopy fast PLLs only support manual clock switchover. clock outputs driven internal clock networks pin. clock outputs fast PLLs drive used external clock output. highspeed differential pins, device uses data channel generate transmitter output clock (txclkout). design uses external feedback input pins, will lose two, fBIN differential) dedicated external clock output pin.
Clock Networks
There clock pins (CLK[15.0]) HardCopy devices that drive either global- regional-clock networks. pins drive clock ports data inputs. HardCopy devices provide dedicated global-clock networks regional-clock networks; same Stratix FPGAs. These clocks organized provide unique clock sources device quadrant
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Structure Features
with skew delay. This clocking scheme provides unique clock domains within entire HardCopy device. Table lists clock resources features available HardCopy devices.
Table 2-8. Clock Network Resources Features Available HardCopy Devices Resources Features
Number global clock networks Number regional clock networks Global clock input sources Regional clock input sources Number unique clock sources quadrant Number unique clock sources entire device Power-down mode Clocking regions high fan-out applications Clock input pins, outputs, logic array Clock input pins, outputs, logic array global clocks regional clocks) global clocks regional clocks) Global- regional-clock networks, dual-regional-clock region Quadrant region, dual-regional, entire device globalor regional-clock networks
Availability
Hardcopy devices also support same features Stratix clock control block, which available each global- regional-clock network. control block functions:
Clock source selection (dynamic selection global clocks): user either dynamically select between outputs, between clock pins (CLKp CLKn), combination clock pins outputs. Clock power-down (dynamic clock enable disable): HardCopy devices, user dynamically turn clock user-mode.
Structure Features
structure features HardCopy remains same Stratix feature implemented Stratix IOEs migrated Hardcopy IOEs. feature HardCopy devices classified three categories:
General purpose IOEs-The most commonly used type designs. Memory Interface IOEs-Includes features interface with common external memory standards. High-speed IOEs-Supports high-speed data transmission reception.
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HardCopy Series Handbook, Volume
pins Stratix FPGAs support general-purpose standards, which includes LVTTL LVCMOS standards. Stratix FPGAs, clamping diode memory interfaces supported bottom pins, while high-speed interfaces supported left right side pins device. general purpose IOEs HardCopy devices cost saving area efficient advantage. complex memory interface high-speed circuitry removed save area while still offering more commonly-used features. memory interface supports features available general purpose IOE. high-speed also supports same features standards general purpose IOE, except clamping diode (supported bottom general purpose IOEs HC210 HC220 devices). order increase area efficiency HardCopy devices, features available given depends location. Table shows which standards supported different types.
Table 2-9. Hardcopy Supported Standards (Part VCCIO Level Standard
LVTTL/ LVCMOS LVTTL/ LVCMOS LVTTL/ LVCMOS LVCMOS SSTL-2 class SSTL-2 class SSTL-18 class SSTL-18 class HSTL class
Type Input
Single-ended Single-ended Single-ended Single-ended Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced 3.3/2.5 3.3/2.5 1.8/1.5 1.8/1.5
Output
Memory Interface IOEs
General Purpose IOEs
High-Speed IOEs
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Structure Features
Table 2-9. Hardcopy Supported Standards (Part VCCIO Level Standard
HSTL class HSTL Class HSTL Class PCI/PCI-X Differential SSTL-2 class input Differential SSTL-2 class output Differential SSTL-18 class input Differential SSTL-18 class output differential HSTL class input differential HSTL class output differential HSTL class input differential HSTL class output LVDS HyperTransporttechnology
Type Input
Voltage referenced Voltage referenced Voltage referenced Single-ended Pseudo differential Pseudo differential Pseudo differential Pseudo differential Pseudo differential Pseudo Differential Pseudo differential Pseudo Differential Differential Differential 3.3/2.5/ 1.8/1.5 3.3/2.5/ 1.8/1.5 3.3/2.5/ 1.8/1.5 3.3/2.5/ 1.8/1.5
Output
Memory Interface IOEs
General Purpose IOEs
High-Speed IOEs
(4), (4),
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Table 2-9. Hardcopy Supported Standards (Part VCCIO Level Standard
LVPECL Notes Table 2-9:
Pseudo-differential HSTL SSTL inputs only positive-polarity input speed path. negative input connected internally. Pseudo-differential HSTL SSTL outputs single-ended outputs with second output programmed inverted. This similar Stratix device implementation. clamping diode only supported pins bottom sides device. This standard only supported DQS, PLL_FB input pins PLL_OUT output pins. This standard only supported bottom PLL_FB input pins bottom PLL_OUT output pins. This standard only supported PLL_FB input pins PLL_OUT output pins. Also supported CLK9 CLK11 pins. This standard only supported PLL_FB input pins. LVPECL input standard supported bottom PLL_FB input pins. LVPECL output standard supported bottom PLL_OUT output pins. LVPECL support similar Stratix devices.
Type Input
Differential 3.3/2.5/ 1.8/1.5
Output
Memory Interface IOEs
General Purpose IOEs
High-Speed IOEs
three types IOEs located different areas device described following sections. HardCopy devices have eight banks, just Stratix FPGAs. Figures through show which type each bank supports.
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Structure Features
Figure 2-4. Type Support HC210 HC220 Devices
Bank Memory Interface IOEs Bank
Notes (1),
Bank Memory Interface IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank General-Purpose IOEs
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS &1.5-V LVCMOS
Bank High-Speed IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS PCI/PCI-X standards. CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL.
Bank General-Purpose IOEs
Bank General Purpose IOEs
Bank
Bank General Purpose IOEs
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Figure 2-5. Type Support HC230 Devices
Bank Memory Interface IOEs
Notes (1),
Bank Memory Interface IOEs
Bank Bank
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank General-Purpose IOEs
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS &1.5-V LVCMOS
Bank High-Speed IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards.
Bank General-Purpose IOEs
Bank Memory Interface IOEs
Bank Bank
Bank Memory Interface IOEs
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Structure Features
Figure 2-6. Type Support HC240 Devices
Bank Memory Interface IOEs
Notes (1),
Bank Bank Bank Memory Interface IOEs
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank High-Speed IOEs
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
Banks Support 3.3-, 2.5- 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, LVDS HyperTransport Technology
banks support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL PCI/PCI-X standards. Bank High-Speed IOEs CLK, PLL_FB input pins PLL_OUT output pins support differential SSTL, differential HSTL, LVDS HyperTransport technology. PLL_FB pins support LVPECL. input pins support differential SSTL differential HSTL standards. Bank High-Speed IOEs
Bank Memory Interface IOEs
Bank Bank
Bank Memory Interface IOEs
Notes Figures through 2-6:
addition supporting external memory interfaces, memory interface IOEs have same features general purpose IOEs. addition supporting high-speed interfaces, high-speed IOEs have same features general purpose IOEs, except clamping diode LVPECL clock input support. This view silicon which corresponds reverse view flip-chip packages. graphical representation only.
When planning placement designs targeting HardCopy devices, care should taken ensure same standards supported same HardCopy banks Stratix banks.
General Purpose
general purpose IOEs HC210 HC220 devices located right side bottom device. general purpose IOEs HC230 devices located right side device. (Directions
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HardCopy Series Handbook, Volume
based view silicon die.) HC240 devices have general purpose IOEs. general purpose functionality supported memory interface IOEs these devices. high-speed IOEs also provide same features general purpose IOEs except clamping diode. Stratix FPGAs, IOEs support general purpose features except diode, which only supported bottom pins. general purpose many features including:
Dedicated single-ended buffers 64-bit, compliance 64-bit, PCI-X compliance JTAG boundary-scan test (BST) support On-chip driver series termination (non-calibrated) Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs clamping diode (supported bottom pins only) Double data rate (DDR) registers
General purpose IOEs support following standards:
LVTTL/LVCMOS LVTTL/LVCMOS LVTTL/LVCMOS LVCMOS PCI-X mode
general purpose PLL_FB input pins PLL_OUT output pins support following standards:
LVDS HyperTransport technology LVPECL input clocks PLL_OUT only)
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Structure Features
programmable drive strengths available vary depending standard being used listed Table 2-10.
Table 2-10. Programmable Drive Strength Support General-Purpose IOEs Standard
LVTTL LVCMOS LVTTL/LVCMOS LVTTL/LVCMOS LVCMOS
Programmable Drive Strength Options (mA)
General purpose IOEs support non-calibrated on-chip series termination. on-chip series termination available standards. on-chip series termination available standards (pending characterization).
Memory Interface
Memory interface IOEs HC210 HC220 devices located device. Memory interface IOEs HC230 HC240 devices located bottom device. Stratix FPGAs, bottom IOEs support memory interface features. memory interface many features including:
Dedicated single-ended buffers 64-bit, compliance 64-bit, PCI-X compliance JTAG support On-chip driver series termination VREF pins Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs clamping diode pins Double data rate (DDR) registers
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HardCopy Series Handbook, Volume
following standards supported when using memory interface IOEs used interface external memory, including DDR2 SDRAM, QDRII, RLDRAM SRAM:
LVTTL/LVCMOS LVTTL/LVCMOS LVTTL/LVCMOS LVCMOS PCI-X mode SSTL-2 class SSTL-18 class HSTL class HSTL class
memory interface DQS, CLK, PLL_FB input pins PLL_OUT output pins support following standards:
LVTTL/LVCMOS SSTL-2 class SSTL-18 class HSTL class HSTL class Differential SSTL-2 class Differential SSTL-18 class differential HSTL class differential HSTL class LVDS (not supported pins) HyperTransport technology (not supported pins) LVPECL input clocks PLL_OUT only (not supported pins)
Pseudo-differential HSTL SSTL inputs supported clock pins, while outputs supported dedicated PLL_OUT pins. Pseudo-differential HSTL SSTL standards single-ended outputs with second output programmed inverted. Pseudo-differential HSTL SSTL inputs treat differential inputs single-ended HSTL SSTL inputs only decode them. This support same Stratix FPGAs.
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Structure Features
functionality circuitry HardCopy devices same Stratix FPGAs. Table 2-11 shows number DQS/DQ groups supported each HardCopy device density package.
Table 2-11. Mode Support Device
HC210 HC220
Package
484-pin FineLine 672-pin FineLine 780-pin FineLine
Number Number Number Number Groups Groups Groups Groups
HC230 HC240
1,020-pin FineLine 1,020-pin FineLine 1,508-pin FineLine
programmable drive strengths available vary depending standard used. options listed Table 2-12.
Table 2-12. Programmable Drive Strength Support Memory Interface IOEs Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS SSTL-2 class SSTL-2 class SSTL-18 class SSTL-18 class 1.8-V HSTL class 1.8-V HSTL class 1.5-V HSTL class 1.5-V HSTL class
Programmable Drive Strength Options (mA)
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HardCopy Series Handbook, Volume
Memory interface IOEs support both non-calibrated calibrated onchip series termination. on-chip series termination available 3.3, 2.5, standards. on-chip series termination available standards (pending characterization). on-chip series termination enabled, programmable drive strength support available.
High-Speed
High-speed IOEs HC210, HC220, HC230 devices located left side device. High-speed IOEs HC240 devices located left right sides device. (Directions based view silicon die.) Unlike Stratix left right side pins, Hardcopy left right side pins support SSTL HSTL standards clamping diode. Stratix FPGAs, right left IOEs support high-speed features. high-speed many features including:
Dedicated single-ended buffers Differential buffer JTAG support On-chip driver series termination (non-calibrated) On-chip termination differential standards Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs Transmit serializer Receive deserializer Dynamic phase alignment (DPA) Double data rate (DDR) registers
following standards supported when using high-speed IOEs:
LVTTL/LVCMOS LVTTL/LVCMOS LVTTL/LVCMOS 1.5- LVCMOS LVDS HyperTransport technology
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Structure Features
SERDES circuitry functionality same Hardcopy devices Stratix FPGAs. HardCopy devices support differential standards rates Gbps when using DPA, rates Mbps when using DPA. Table 2-13 provides number differential channels HardCopy device.
Table 2-13. Number Differential Channels HardCopy Devices HC210W Channel 484-Pin FineLine (WireBond)
Notes (1), HC230 HC240 1,020-Pin FineLine
HC210 484-Pin FineLine
HC220 672-Pin FineLine
780-Pin FineLine
1,020-Pin FineLine
1,508-Pin FineLine
Transmitter channels Receiver channels
Notes Table 2-13:
count does include dedicated input output pins. total number receiver channels includes non-dedicated clock channels that optionally used data channels.
Hardcopy high-speed IOEs, which left and/or right sides device, support fewer programmable drive strengths than Stratix side IOEs. programmable drive strengths available vary depending standard being used. options listed Table 2-14.
Table 2-14. Programmable Drive Strength Support High-Speed IOEs Standard
LVTTL LVCMOS LVTTL/LVCMOS LVTTL/LVCMOS LVCMOS
Programmable Drive Strength Options (mA)
High-speed IOEs support non-calibrated on-chip series termination differential termination receiver channels. on-chip series termination available standards. on-chip series termination available 1.8- standards (pending characterization).
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HardCopy Series Handbook, Volume
Power-Up Modes
functionality structured ASICs determined before they produced. Therefore, they require programmability. HardCopy structured ASICs follow same principle, enabling traditional ASIClike power Although prototyping FPGAs require configuration upon power HardCopy structured ASICs need configured. HardCopy devices support configuration designers should take this into account prototyping production development process. HardCopy device does require configuration device, must ensure that that nCONFIG nSTATUS pins high after power HardCopy devices support FPGA configuration emulation, other configuration modes, including remote system upgrades design security using configuration bitstream encryption.
HardCopy devices support both instant instant after power-up modes. instant power-up mode, HardCopy device available shortly after device powers safe operating voltage. on-chip power-on reset (POR) circuit will reset registers. nCE, nCONFIG, nSTATUS signals must appropriate logic levels CONF_DONE output tristated once elapsed. This option similar ASIC's functionality upon power most likely scenario production. instant after power-up mode, HardCopy device behaves similarly instant mode, except that there additional delay during which time device will held reset. CONF_DONE output pulled during this time, then tri-stated after have elapsed.
more information about which power-up modes HardCopy devices support, refer Power-Up Modes Configuration Emulation HardCopy Series Devices chapter HardCopy Series Handbook.
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Boundary-Scan Support
H51017-2.1
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
HardCopy® structured ASICs provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with IEEE Std. 1149.1-1990 specification. architecture offers capability efficiently test components printed circuit boards (PCBs) with tight lead spacing testing connections, without using physical test probes, capturing functional data while device normal operation. Boundary-scan cells device force signals onto pins, capture data from core logic signals. Forced test data serially shifted into boundary-scan cells. Captured data serially shifted externally compared expected results. device using JTAG interface uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. internal weak pull-down resistor, while TDI, TMS, TRST pins have weak internal pull-up resistors. output powered VCCIO HardCopy devices support JTAG instructions shown Table 3-1.
Table 3-1. HardCopy JTAG Instructions (Part JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
0000 0101
Description
Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Allows external circuitry board-level interconnects tested forcing test pattern output pins capturing test results input pins. Places 1-bit BYPASS register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation.
EXTEST
0000 1111
BYPASS
1111 1111
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Table 3-1. HardCopy JTAG Instructions (Part JTAG Instruction
USERCODE
Instruction Code
0000 0111
Description
Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. Places 1-bit BYPASS register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation, while tristating pins. Places 1-bit BYPASS register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation while holding pins state defined data boundary-scan register.
IDCODE
0000 0110
HIGHZ
0000 1011
CLAMP
0000 1010
Note Table 3-1:
hold weak pull-up resistor features override high-impedance state HIGHZ, CLAMP, EXTEST.
BSDL files HardCopy devices different from corresponding Stratix® FPGAs. Contact Altera Applications HardCopy BSDL files. HardCopy device instruction register length bits USERCODE register length bits. USERCODE registers reprogrammable mask-programmed. designer choose appropriate sequence which will programmed into USERCODE registers.
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Tables show boundary-scan register length device IDCODE information HardCopy devices.
Table 3-2. HardCopy Boundary-Scan Register Length Device
HC210W HC210 HC220 HC230 HC240 Notes Table 3-2:
These values preliminary. Contact Altera Applications more information.
Note
Boundary-Scan Register Length
1050 1530 2154 2910
Table 3-3. HardCopy Device IDCODE IDCODE Bits) Device
HC210W HC210 HC220 HC230 HC240 Notes Table 3-3:
most significant (MSB) left. least significant (LSB) IDCODE always
Version Bits)
0000 0000 0000 0000 0000
Part Number Bits)
0010 0000 0000 0011 0010 0000 0000 0100 0010 0000 0000 0101 0010 0000 0000 0110 0010 0000 0000 0111
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110 0110 1110
Bit)
Figure shows timing requirements JTAG signals.
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HardCopy Series Handbook, Volume
Figure 3-1. HardCopy JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows JTAG timing parameters values HardCopy devices.
Table 3-4. HardCopy JTAG Timing Parameters Values (Part Symbol
Parameter
clock period clock high time clock time
JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output
Unit
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 3-4. HardCopy JTAG Timing Parameters Values (Part Symbol
Parameter
Update register high impedance valid output Update register valid output high impedance
Unit
more information JTAG boundary-scan testing, refer IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices. Stratix FPGAs support SignalTap® embedded logic analyzer, which monitors design operation over period time through JTAG interface. SignalTap logic analyzer useful feature during FPGA prototyping phase, should removed needed once design been migrated HardCopy device.
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HardCopy Series Handbook, Volume
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Operating Conditions
H51018-2.1
Introduction
This chapter provides preliminary information absolute maximum ratings, recommended operating conditions, electrical characteristics, other specifications HardCopy® devices. Table contains absolute maximum ratings HardCopy device family.
Absolute Maximum Ratings
Table 4-1. HardCopy Device Absolute Maximum Ratings Symbol
Notes (1), (2), Minimum
-0.5 -0.5 -0.5
Parameter
Supply voltage Supply voltage Supply voltage input voltage output current, Storage temperature Junction temperature bias
Conditions
With respect ground With respect ground With respect ground
Maximum
Unit
Ball-grid array (BGA) packages under bias
Notes Table 4-1:
Refer Operating Requirements Altera Devices Data Sheet more information. Conditions beyond those listed Table cause permanent damage device. Additionally, device operation absolute maximum ratings extended periods time have adverse affects device. Supply voltage specifications apply voltage readings taken device pins, power supply. During transitions, inputs overshoot voltage shown Table based upon input duty cycle. case equivalent 100% duty cycle. During transitions, inputs undershoot -2.0 input currents less than periods shorter than
Table 4-2. Maximum Duty Cycles Voltage Transitions (Part
Maximum Duty Cycles
100%
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Preliminary
HardCopy Series Handbook, Volume
Table 4-2. Maximum Duty Cycles Voltage Transitions (Part
Maximum Duty Cycles
Recommended Operating Conditions
Table contains HardCopy device family recommended operating conditions.
Table 4-3. HardCopy Device Recommended Operating Conditions (Part Symbol
Note Maximum
1.25 3.60 2.625 1.89 1.575 3.465
Parameter
Supply voltage internal logic input buffers Supply voltage output buffers, 3.3-V operation Supply voltage output buffers, 2.5-V operation Supply voltage output buffers, 1.8-V operation Supply voltage output buffers, 1.5-V operation
Conditions
Maximum rise time Maximum rise time Maximum rise time Maximum rise time Maximum rise time
Minimum
1.15 3.00 2.375 1.71 1.425 3.135
Unit
rise time Supply voltage pre-drivers well configuration JTAG buffers. Input voltage (4),
-0.5
Preliminary
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Electrical Characteristics
Table 4-3. HardCopy Device Recommended Operating Conditions (Part Symbol
Note Maximum
Parameter
Output voltage Operating junction temperature
Conditions
Minimum
Unit
commercial industrial
Notes Table 4-3:
Supply voltage specifications apply voltage readings taken device pins, power supply. Maximum rise time must rise monotonically. VCCPD must ramp-up from within VCCPD ramped within this specified time, HardCopy device will power successfully. During transitions, inputs overshoot voltage shown Table based upon input duty cycle. case equivalent 100% duty cycle. During transitions, inputs undershoot -2.0 input currents less than periods shorter than pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT, VCCPD, VCCIO powered.
Electrical Characteristics
Table shows HardCopy device family electrical characteristics.
Table 4-4. HardCopy Device Operating Conditions Symbol
Note Typical Maximum
Parameter
Input leakage current Tri-stated leakage current
Conditions
Minimum
Unit
supply current ground, (standby) (all load, toggling memory blocks inputs power-down mode) Value pull-up resistor before during configuration 2.375 1.71
Notes Table 4-4:
Typical values VCCINT VCCIO 1.5, 1.8, 2.5, This value specified normal device operation. value vary during power-up. This applies VCCIO settings (3.3, 2.5, 1.8, This specification pending device characterization. pull-up resistance values will lower external source drives higher than VCCIO.
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Preliminary
HardCopy Series Handbook, Volume
Standard Specifications
Tables through 4-26 show HardCopy device family standard specifications.
Table 4-5. LVTTL Specifications Symbol
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.135 -0.3
Maximum
3.465
Unit
(2), (2),
0.45
Notes Table 4-5:
HardCopy devices comply narrow range supply voltage specified EIA/JEDEC Standard, JESD8-B. Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-6. LVCMOS Specifications Symbol
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.135 -0.3
Maximum
3.465
Unit
3.0, -0.1 (2), 3.0, (2),
Notes Table 4-6:
HardCopy devices comply narrow range supply voltage specified EIA/JEDEC Standard, JESD8-B. Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-7. Specifications (Part Symbol
Parameter
Output-supply voltage High-level input voltage
Conditions
Minimum
2.375
Maximum
2.625
Unit
Preliminary
Altera Corporation October 2005
Standard Specifications
Table 4-7. Specifications (Part Symbol
Parameter
Low-level input voltage High-level output voltage Low-level output voltage
Conditions
(2), (2),
Minimum
-0.3
Maximum
Unit
Notes Table 4-7:
HardCopy devices voltage-level support 2.5± narrower than defined normal range EIA/JEDEC Standard. Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-8. Specifications Symbol
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.65 -0.3
Maximum
1.89 2.25 0.35
Unit
(2), (2),
0.45 0.45
Notes Table 4-8:
HardCopy devices voltage-level support 1.8± narrower than defined normal range EIA/JEDEC Standard. Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, Volume more information.
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Preliminary
HardCopy Series Handbook, Volume
Table 4-9. 1.5-V Specifications Symbol
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.425 0.65 -0.3
Maximum
1.575 0.35
Unit
(2), (2),
0.75 0.25
Notes Table 4-9:
HardCopy devices voltage-level support 1.5± narrower than defined normal range EIA/JEDEC Standard. Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Figures show receiver input transmitter output waveforms, respectively, differential standards (LVDS, LVPECL, HyperTransport technology). Figure 4-1. Receiver Input Waveforms Differential Standards
Single-Ended Waveform Positive Channel Negative Channel Ground
Differential Waveform
p-n=0V (Peak-to-peak)
Preliminary
Altera Corporation October 2005
Standard Specifications
Figure 4-2. Transmitter Output Waveforms Differential Standards
Single-Ended Waveform Positive Channel Negative Channel Ground
Differential Waveform
p-n=0V
Table 4-10. 2.5-V LVDS Specifications (Part Symbol
Parameter
supply voltage banks that support high-speed IOEs (1), Output feedback pins banks
Conditions
Minimum
2.375
Typical
Maximum
2.625
Unit
3.135 1.125
3.465 1,000 1,800
(peakto-peak)
Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change between high Output common mode voltage Change between high
1.25
1.375
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Preliminary
HardCopy Series Handbook, Volume
Table 4-10. 2.5-V LVDS Specifications (Part Symbol
Parameter
Receiver differential input discrete resistor (external HardCopy devices)
Conditions
Minimum
Typical
Maximum
Unit
Notes Table 4-10:
IOEs elements. information which banks support high-speed IOEs, refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume bottom clock input differential buffers banks powered clock output feedback differential buffers powered VCC_PLLOUT. differential clock output feedback operation, connect VCC_PLLOUT 3.3V.
Table 4-11. LVPECL Specifications Symbol
(peakto-peak)
Parameter
supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input resistor
Conditions
Minimum
3.135
Typical
Maximum
3.465 1,000
Unit
Note Table 4-11:
bottom clock input differential buffers banks powered clock output feedback differential buffers powered VCC_PLLOUT. differential clock output feedback operation, connect VCC_PLLOUT
Table 4-12. HyperTransport Technology Specifications (Part Symbol
Parameter
supply voltage banks that support high-speed IOEs Output feedback pins banks
Conditions
Minimum
2.375 3.135
Typical
Maximum
2.625 3.465
Unit
(peakto-peak)
Input differential voltage swing (single-ended) Input common mode voltage
Preliminary
Altera Corporation October 2005
Standard Specifications
Table 4-12. HyperTransport Technology Specifications (Part Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
Output differential voltage (single- ended) Change between high Output common mode voltage Change between high Receiver differential input resistor
Notes Table 4-12:
information which banks support high-speed IOEs, refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume bottom clock input differential buffers banks powered clock output feedback differential buffers powered VCC_PLLOUT. differential clock output feedback operation, connect VCC_PLLOUT 3.3V.
Table 4-13. 3.3-V Specifications Symbol
Parameter
Output-supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Typical
Maximum
Unit
-500 1,500
Table 4-14. PCI-X Mode Specifications Symbol
Parameter
Output-supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Typical
Maximum
0.35
Unit
-500 1,500
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Preliminary
HardCopy Series Handbook, Volume
Table 4-15. SSTL-18 Class Specifications Symbol
Parameter
Output-supply voltage Reference voltage Termination voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.855 0.04 0.125
Typical
Maximum
1.89 0.945 0.04
Unit
0.125 0.25 0.25 -6.7 (1), (1), 0.475 0.475
Notes Table 4-15:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
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Standard Specifications
Table 4-16. SSTL-18 Class Specifications Symbol
Parameter
Output-supply voltage Reference voltage Termination voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.855 0.04 0.125
Typical
Maximum
1.89 0.945 0.04
Unit
0.125 0.25 0.25 -13.4 (1), 13.4 (1), 0.28 0.28
Notes Table 4-16:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-17. SSTL-18 Differential Specifications Symbol
Parameter
Output-supply voltage
Conditions
Minimum
1.71 0.25 0.175
Typical
Maximum
1.89
Unit
differential input voltage differential input cross point voltage
0.175
differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation differential cross point voltage
±200 0.125 0.125
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HardCopy Series Handbook, Volume
Table 4-18. SSTL-2 Class Specifications Symbol
Parameter
Output-supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 0.04 1.188 0.18 -0.3
Typical
1.25
Maximum
2.625 0.04 1.313 0.18
Unit
-8.1 (1), (1),
0.57 0.57
Notes Table 4-18:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-19. SSTL-2 Class Specifications Symbol
VREF
Parameter
Output-supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.188 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.313 VREF 0.18
Unit
-16.4 (1), 16.4 (1),
0.76 0.76
Notes Table 4-19:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-20. SSTL-2 Differential Specifications (Part Symbol
Parameter
Output-supply voltage
Conditions
Minimum
2.375 0.36
Typical
Maximum
2.625
Unit
differential input voltage
4-12 Preliminary
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Standard Specifications
Table 4-20. SSTL-2 Differential Specifications (Part Symbol
Parameter
differential input cross point voltage
Conditions
Minimum
Typical
Maximum
Unit
differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation differential output cross point voltage
±200
Table 4-21. 1.5-V HSTL Class Specifications Symbol
VREF
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.425 0.713 0.713 VREF -0.3 VREF
Typical
0.75 0.75
Maximum
1.575 0.788 0.788
Unit
VREF
VREF (1), (1),
Notes Table 4-21:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-22. 1.5-V HSTL Class Specifications (Part Symbol
VREF
Parameter
Output-supply voltage Input reference voltage Termination voltage
Conditions
Minimum
1.425 0.713 0.713
Typical
1.50 0.75 0.75
Maximum
1.575 0.788 0.788
Unit
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Table 4-22. 1.5-V HSTL Class Specifications (Part Symbol
Parameter
high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF -0.3 VREF
Typical
Maximum
Unit
VREF
VREF (1), (1),
Notes Table 4-22:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-23. 1.5-V Differential HSTL Specifications Symbol
Parameter
supply voltage input differential voltage common mode input voltage differential input voltage differential cross point voltage
Conditions
Minimum
1.425 0.68 0.68
Typical
Maximum
1.575
Unit
Table 4-24. 1.8-V HSTL Class Specifications (Part Symbol
VREF
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage
Conditions
Minimum
1.71 0.85 0.85 VREF -0.3
Typical
1.80 0.90 0.90
Maximum
1.89 0.95 0.95
Unit
VREF
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Standard Specifications
Table 4-24. 1.8-V HSTL Class Specifications (Part Symbol
Parameter
high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF
Typical
Maximum
Unit
VREF (1), (1),
Notes Table 4-24:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
Table 4-25. 1.8-V HSTL Class Specifications Symbol
VREF
Parameter
Output-supply voltage Input reference voltage Termination voltage high-level input voltage low-level input voltage high-level input voltage low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.85 0.85 VREF -0.3 VREF
Typical
1.80 0.90 0.90
Maximum
1.89 0.95 0.95
Unit
VREF
VREF (1), (1),
Notes Table 4-25:
Drive strength programmable according values Tables 2-10, 2-12, 2-14. Drive strength varies based location. Refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume more information.
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Table 4-26. 1.8-V Differential HSTL Specifications Symbol
Parameter
supply voltage input differential voltage common mode input voltage differential input voltage differential cross point voltage
Conditions
Minimum
1.71 0.68 0.68
Typical
1.80
Maximum
1.89
Unit
Hold Specifications
Table 4-27 shows HardCopy device family hold specifications.
Table 4-27. Hold Parameters Level Parameter Conditions
sustaining current High sustaining current overdrive current High overdrive current Note Table 4-27:
This specification pending device characterization.
-200
-300
-500
Unit
(maximum) (minimum)
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On-Chip Termination Specifications
On-Chip Termination Specifications
Tables 4-28 4-29 define specification internal termination resistance tolerance when using series differential on-chip termination.
Table 4-28. Series On-Chip Termination Specification Banks Supporting Memory Interface IOEs Note Resistance Tolerance Symbol
3.3/2.5
Description
Internal series termination with calibration setting) Internal series termination without calibration setting)
Conditions
3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5
Commercial
Industrial
Unit
3.3/2.5
Internal series termination with calibration setting) Internal series termination without calibration setting)
Internal series termination with calibration setting) Internal series termination without calibration setting)
Internal series termination with calibration setting) Internal series termination without calibration setting)
Internal series termination with calibration setting) Internal series termination without calibration setting)
Internal series termination with calibration setting) Internal series termination without calibration setting)
Notes Table 4-28:
information which banks support memory interface IOEs, refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume This specification pending device characterization.
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Table 4-29. Series Differential On-Chip Termination Specification Banks Supporting High-Speed General Purpose IOEs Note Resistance Tolerance Symbol
3.3/2.5 3.3/2.5/1.8
Description
Internal series termination without calibration setting) Internal series termination without calibration setting) Internal series termination without calibration setting) Internal differential termination LVDS HyperTransport technology
Conditions
3.3/2.5 3.3/2.5/1.8
Commercial Industrial
Unit
Notes Table 4-29:
information which banks support high-speed IOEs, refer Description, Architecture Features chapter HardCopy Device Family Data Sheet section HardCopy Series Handbook, volume This specification pending device characterization. only supported high-speed IOEs.
Capacitance
Table 4-30 shows HardCopy device family capacitance.
Table 4-30. HardCopy Device Capacitance (Part Symbol
Parameter
Input capacitance pins banks supporting general-purpose IOEs. Input capacitance pins banks supporting memory interface IOEs. Input capacitance pins banks supporting high-speed IOEs. Input capacitance top/bottom clock input pins CLK[4.7] CLK[12.15]. Input capacitance left/right clock inputs CLK0, CLK2, CLK8, CLK10. Input capacitance left/right clock inputs
Minimum
Typical
Maximum
Unit
CLK1, CLK3, CLK9, CLK11.
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Maximum Input Output Clock Rates
Table 4-30. HardCopy Device Capacitance (Part Symbol
Parameter
Input capacitance dual-purpose clock output/feedback pins banks
Minimum
Typical
Maximum
Unit
Note Table 4-30:
This specification pending device characterization.
Maximum Input Output Clock Rates
Refer Tables 4-31 through 4-35 maximum clock rates.
Table 4-31. HardCopy Maximum Input Clock Rate Memory Interface IOEs (Part Standard
LVTTL LVCMOS SSTL-2 class SSTL-2 class SSTL-18 class SSTL-18 class 1.5-V HSTL class 1.5-V HSTL class 1.8-V HSTL class 1.8-V HSTL class PCI-X Differential SSTL-2 class Differential SSTL-2 class Differential SSTL-18 class Differential SSTL-18 class differential HSTL class differential HSTL class differential HSTL class
Performance
Unit
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Table 4-31. HardCopy Maximum Input Clock Rate Memory Interface IOEs (Part Standard
differential HSTL class Notes Table 4-31:
clamping diode only supported bottom pins. This standard only supported DQS, CLK, PLL_FB input pins.
Performance
Unit
Table 4-32. HardCopy Maximum Input Clock Rate General-Purpose IOEs Standard
LVTTL LVCMOS PCI-X Differential SSTL-2 class Differential SSTL-2 class Differential SSTL-18 class Differential SSTL-18 class differential HSTL class differential HSTL class differential HSTL class 1.5- differential HSTL class LVDS HyperTransport Notes Table 4-32:
clamping diode only supported bottom pins. This standard only supported bottom PLL_FB input pins.
Performance
Unit
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Maximum Input Output Clock Rates
Table 4-33. HardCopy Maximum Input Clock Rate High-Speed IOEs Standard
LVTTL LVCMOS LVDS HyperTransport
Performance
Unit
Table 4-34. HardCopy Maximum Output Clock Rate Memory Interface IOEs (Part Standard
LVTTL
Drive Strength
Performance
Unit
LVCMOS
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Table 4-34. HardCopy Maximum Output Clock Rate Memory Interface IOEs (Part Standard
Drive Strength
Performance
Unit
SSTL-2 class
SSTL-2 class
SSTL-18 class
SSTL-18 class
1.8-V HSTL class
1.8-V HSTL class
1.5-V HSTL class
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Maximum Input Output Clock Rates
Table 4-34. HardCopy Maximum Output Clock Rate Memory Interface IOEs (Part Standard
1.5-V HSTL class
Drive Strength
Performance
Unit
PCI-X Differential SSTL-2 class Differential SSTL-2 class Differential SSTL-18 class Differential SSTL-18 class differential HSTL class differential HSTL class differential HSTL class
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Table 4-34. HardCopy Maximum Output Clock Rate Memory Interface IOEs (Part Standard
differential HSTL class
Drive Strength
Performance
Unit
Notes Table 4-34:
This default setting Quartus software supported location. clamping diode only supported bottom pins. This standard only supported PLL_OUT pins.
Table 4-35. HardCopy Maximum Output Clock Rate General-Purpose IOEs (Part Standard
LVTTL
Drive Strength
Performance
Unit
LVCMOS
PCI-X Differential SSTL-2 class Differential SSTL-2 class
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Maximum Input Output Clock Rates
Table 4-35. HardCopy Maximum Output Clock Rate General-Purpose IOEs (Part Standard
Differential SSTL-18 class
Drive Strength
Performance
Unit
LVDS HyperTransport Notes Table 4-35:
This default setting Quartus software supported location. clamping diode only supported bottom pins. This standard only supported bottom PLL_OUT output pins.
Table 4-36. HardCopy Maximum Output Clock Rate High-Speed IOEs Standard
LVTTL
Drive Strength
Performance
Unit
LVCMOS
LVDS HyperTransport
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Quartus Support HardCopy Devices
H51022-2.1
Introduction
Altera® HardCopy® devices feature process technology provide structured ASIC alternative increasingly expensive multi-million gate ASIC designs. HardCopy design methodology offers fast time-to-market schedule, providing ASIC designers with solution long ASIC development cycles. Using Quartus® version software, leverage Stratix® FPGA prototype seamlessly migrate your design HardCopy device production. This document discusses following topics:
HardCopy design development flow companion devices HardCopy Device Resource Guide Recommended Quartus software settings HardCopy Utilities menu options functions
more information HardCopy HardCopy Stratix, HardCopy APEXdevices, refer respective device data sheets HardCopy Series Handbook.
HardCopy Design Benefits
Designing with HardCopy structured ASICs offers substantial benefits over other structured ASIC offerings:
Prototyping using Stratix FPGA functional verification system development reduces total project development time Seamless migration from Stratix FPGA prototype HardCopy device reduces time market risk Unified design methodology Stratix FPGA design HardCopy design reduces need ASIC development software up-front development cost HardCopy devices reduces financial risk your project
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Quartus Features HardCopy Planning
With Quartus version software design HardCopy device using Stratix device prototype. Quartus version software contains following expanded features HardCopy device planning:
HardCopy Companion Device Assignment-Identifies compatible HardCopy devices migration with Stratix device currently selected
This feature constrains pins your Stratix FPGA prototype making compatible with your HardCopy device. also constrains correct resources available HardCopy device making sure that your Stratix FPGA design does become incompatible.
HardCopy Utilities-The HardCopy Utilities' functions create overwrites HardCopy companion revisions, change revisions use, compare revisions equivalency HardCopy Advisor-The HardCopy Advisor helps follow necessary steps successfully submit HardCopy design Altera's HardCopy Design Center
HardCopy Advisor Similar Resource Optimization Advisor Timing Optimization Advisor. Advisor provides guidelines follow during development. reports tasks completed well task that still need complete during HardCopy designing.
HardCopy Floorplan-The Quartus software show preliminary floorplan view your HardCopy design's Fitter placement results HardCopy Design Archiving-The Quartus software archives HardCopy design project's files needed handoff design HardCopy Design Center
This feature similar Quartus software's HardCopy Files Wizard used HardCopy Stratix HardCopy APEX families.
HardCopy Device Preliminary Timing-The Quartus version software perform timing analysis HardCopy devices based preliminary timing models Fitter placements
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HardCopy Development Flow
HardCopy Handoff Report-The Quartus software generates handoff report containing information about HardCopy design used HardCopy Design Center design review process Formal Verification-Cadence Encounter Conformal software perform formal verifications
HardCopy Development Flow
Quartus version software, have methods designing your Stratix FPGA HardCopy companion device together Quartus project.
Design HardCopy device first, create Stratix FPGA companion device second build your prototype in-system verification Design traditional HardCopy design flow, whereby design Stratix FPGA first create HardCopy companion device second
Both these possible flows illustrated high level Figure 5-1. added features HardCopy Utilities menu assist completing your HardCopy design submission Altera's HardCopy Design Center back-end implementation.
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Figure 5-1. HardCopy Flow Quartus Version
Prepare Design
Design Stratix First
Design Stratix Second
Select Stratix Device HardCopy Companion Device
Design Stratix First?
Select HardCopy Device Stratix Companion Device
Complete Stratix First Flow In-System Verification Stratix FPGA Design
Complete HardCopy First Flow
Compare Stratix HardCopy Design Revisions
Generate HardCopy Archive
Handoff Design Archive Back-End Migration
Notes Figure 5-1:
complete Stratix First Flow, refer Figure expanded description this process. complete HardCopy First Flow, refer Figure expanded description this process.
Designing Stratix FPGA First
HardCopy development flow beginning with Stratix FPGA prototype very similar traditional Stratix FPGA design flow, requires additional tasks performed migrate design HardCopy companion device. design your HardCopy device using Stratix FPGA prototype, need following tasks:
Specify HardCopy device migration Create compile HardCopy companion revision Compare HardCopy companion revision compilation Stratix device compilation
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HardCopy Development Flow
flowchart Figure provides overview highlighting development process designing with Stratix FPGA first creating HardCopy companion device second. Prototype your HardCopy design selecting then compiling Stratix device Quartus software. Once compile Stratix design successfully, view HardCopy Device Resource Guide Quartus software Fitter report, evaluate which HardCopy devices meet your design's resource requirements. When satisfied with compilation results choice Stratix HardCopy devices, select HardCopy companion device Device page Settings dialog (Assignments menu). After select your HardCopy companion device, following:
Review HardCopy Advisor required recommended tasks perform Enable Design Assistant during compilation timing location assignments Compile your Stratix design Create your HardCopy companion revision Compile your design HardCopy companion device HardCopy Utilities Quartus software compare HardCopy companion device compilation with Stratix FPGA revision Generate HardCopy Handoff Report using HardCopy Utilities Generate HardCopy Handoff Archive using HardCopy Utilities Arrange submission your HardCopy handoff archive Altera's HardCopy Design Center back-end implementation
design flow continues similarly Stratix design, with timing analysis optimization design, simulation verification design, programming configuring Stratix FPGA. complete HardCopy development process, archive your final design handoff Altera's HardCopy Design Center. more information overall design flow using Quartus software, refer Introduction Quartus manual Altera site (www.altera.com).
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HardCopy Series Handbook, Volume
Figure 5-2. Designing Stratix Device First Flow
Stratix Prototype Device Development Phase Prepare Stratix Design
Select HardCopy Companion Device
Review HardCopy Advisor
Apply Design Constraints
In-System Verification
Compile Stratix Design
Violations?
Violations
Create Overwrite HardCopy Companion Revision HardCopy Companion Device Development Phase
Compile HardCopy Companion Revision
Compare Stratix HardCopy Revisions
Violations? Design Submission Back-End Implementation Phase
Generate Handoff Report
Archive Project Handoff
Designing HardCopy Device First
HardCopy presents option designing that unavailable previous HardCopy families. design your HardCopy device first create your Stratix FPGA prototype second Quartus software. This allows what your maximum performance HardCopy device immediately during development, create slower performing FPGA prototype design in-system verification. This design process very similar traditional HardCopy design flow where build FPGA first, instead, merely change starting device family. remaining tasks complete your design both Stratix HardCopy devices
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HardCopy Development Flow
roughly follow same process (Figure 5-3). HardCopy Advisor adjusts list tasks based which device family start with, Stratix HardCopy that complete process seamlessly. Figure 5-3. Designing HardCopy Device First Flow
HardCopy Device Development Phase Prepare HardCopy Design
Select Stratix Companion Device
Review HardCopy Advisor
Apply Design Constraints
Compile HardCopy Design
Violations?
Violations
Create Overwrite Stratix Companion Revision Stratix Companion Device Development Phase
In-System Verification
Compile Stratix Companion Revision
Compare HardCopy Stratix Revisions
Violations? Design Submission Back-End Implementation Phase
Generate Handoff Report
Generate HardCopy Archive Handoff
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HardCopy Device Resource Guide
HardCopy Device Resource Guide compares resources required successfully compile design with resources available various HardCopy devices. report rates each HardCopy device each device resource well fits design. Quartus software generates HardCopy Device Resource Guide designs successfully compiled Stratix devices, found Fitter folder Compilation Report. Figure shows example HardCopy Device Resource Guide. color code explained Table 5-1.
Figure 5-4. HardCopy Device Resource Guide
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HardCopy Device Resource Guide
Table 5-1. HardCopy Device Resource Guide Color Legend Color Green (High) Package Resource
design migrate Hardcopy package design been with target device migration enabled HardCopy Companion Device dialog box.
Device Resources
resource quantity within range HardCopy device design likely migrate other resources also fit. resource quantity within range HardCopy device. However, resource risk exceeding range HardCopy package. Consult your Product Field Applications Engineer recommended course action. resource quantity exceeds range HardCopy device. design cannot migrate this HardCopy device.
design migrate Hardcopy package. However, design been Orange with target device migration enabled (Medium) HardCopy Companion Device dialog box. design cannot migrate Hardcopy package.
(None)
Note Table 5-1:
package resource constrained Stratix FPGA that design compiled for. Only vertical migration devices within same package able migrate HardCopy devices.
this report determine which HardCopy device potential candidate migration your Stratix design. HardCopy device package must compatible with Stratix device package. logic resource usage greater than 100% ratio greater than category indicates that design does that particular HardCopy device. HardCopy architecture consists array fine-grained HCells, which used build logic equivalent Stratix adaptive logic modules (ALMs) digital signal processing (DSP) blocks. blocks HardCopy devices match functionality Stratix blocks, though timing these blocks will different than FPGA since they constructed HCell Macros. M-RAM memory blocks HardCopy devices equivalent Stratix memory blocks. Preliminary timing reports HardCopy device available version Quartus software
more information HardCopy device resources, refer Introduction HardCopy Devices Description, Architecture Features chapters HardCopy Device Family Data Sheet HardCopy Series Handbook. report example Figure shows resource comparisons design compiled Stratix EP2S130F1020 device. Based report, HC230F1020 device 1,020-pin FineLine BGA® package appropriate HardCopy device migrate HC230F1020 device specified migration target during compilation,
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HardCopy Series Handbook, Volume
package migration compatibility would rated orange Medium. migration compatibility other HardCopy devices rated red, None, because package types incompatible with Stratix device. 1,020-pin FineLine HC240 device rated because only compatible with Stratix EP2S180F1020 device. Figure shows report after (unchanged) design recompiled with HardCopy HC230F1020 device specified migration target. HC230F1020 device's package migration compatibility rated green High. Figure 5-5. HardCopy Device Resource Guide with Target Migration Enabled
HardCopy Companion Device Selection
Quartus version software, select HardCopy companion device help structure your design migration from Stratix device HardCopy device. make your HardCopy companion device selection Device page (Figure 5-6) Settings dialog (Assignments Menu). Selecting HardCopy Companion device with your Stratix prototype constrains memory blocks, blocks, assignments, that your Stratix HardCopy devices migration compatible. assignments constrained Stratix design revision that HardCopy device selected compatible. Quartus software also constrains Stratix design revision does M512 memory blocks exceed number M-RAM blocks HardCopy companion device.
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HardCopy Companion Device Selection
Figure 5-6. Quartus Settings Dialog
also specify your HardCopy companion device using following command: set_global_assignment -name <HardCopy Device Part Number> example, select HC230F1020 device your HardCopy companion device EP2S130F1020C4 Stratix FPGA, command set_global_assignment -name HC230F1020
Migration Compatibility Filtering
Migration Devices dialog displays which devices vertically migratable within same package family Altera devices. When designing HardCopy devices with Stratix prototype device, Migration Devices dialog filters compatible devices between Stratix devices HardCopy devices within same package.
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When select Stratix device Device settings page Settings dialog (Assignments Menu) HardCopy companion device <None>, Migration Devices dialog shows Stratix devices that vertically migratable current Stratix device selected. Figure shows example selected Stratix EP2S130F1020C4 device. Figure 5-7. Available Migration Devices Without Selecting HardCopy Device
Without HardCopy companion device constraints, Stratix devices 1,020-pin FineLine package available vertical migration. Selecting HardCopy companion device Device page, shown Figure 5-8, filters list migration devices only those Stratix devices that vertically migratable within same package usable HardCopy prototype devices. Figure 5-8. Setting HardCopy Companion Device
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HardCopy Recommended Settings Quartus Software
example, select HC230F1020 device companion device, Migration Devices dialog shows EP2S90F1020C4 EP2S180F1020C4 devices possible companion devices EP2S130F1020C4 device currently selected (Figure 5-9). However, EP2S60F1020C4 device compatible device HC230F1020 device, even though same package, listed Migration Devices dialog box. Figure 5-9. Available Migration Devices After Selecting HardCopy Device
HardCopy Recommended Settings Quartus Software
HardCopy development flow involves additional planning preparation Quartus software compared standard FPGA design. This because developing your design implemented devices: prototype your design Stratix prototype FPGA, companion revision HardCopy device production. need additional settings constraints make Stratix design compatible with HardCopy device and, some cases, must remove certain settings design. This section explains additional settings constraints necessary your design successful both Stratix FPGA HardCopy structured ASIC devices.
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Limit HardCopy Device Resources
Limit Hardcopy device resources setting turned default (Figure 5-10). this default setting turn Assignments menu, click Settings view Settings dialog box. Category list, select Device list, select Stratix Under Companion device, Limit Hardcopy device resources turned default. This maintains compatibility between Stratix HardCopy devices ensuring your design does resources Stratix device that available selected HardCopy device. require additional memory blocks blocks debugging purposes using SignalTap® temporarily turn this setting compile verify your design your test environment. However, your final Stratix HardCopy designs submitted Altera back-end migration must compiled with this setting turned
Figure 5-10. Limit HardCopy Device Resources Check
Enable Design Assistant During Compile
must Quartus Design Assistant check HardCopy series designs design rule violations before submitting designs Altera HardCopy Design Center. Additionally, must critical high-level errors. Altera recommends turning Design Assistant automatically during each compile, that during development, violations must fix.
more information Design Assistant rules uses, refer Design Guidelines HardCopy Series Devices chapter HardCopy Series Handbook.
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HardCopy Recommended Settings Quartus Software
enable Design Assistant during compilation, Assignment menu, click Settings. Category list select Design Assistant turn Design Assistant during compilation (Figure 5-11) entering following command Console: set_global_assignment -name ENABLE_DRC_SETTINGS Figure 5-11. Enabling Design Assistant
Timing Settings
More Timing Settings dialog box, specify optional timing settings, some which crucial HardCopy development. specify these options, click More Settings Timing Requirements Options page Settings dialog (Assignments menu). Stratix HardCopy co-development, Altera recommends that turn following settings, shown Figure 5-12: Enable Clock Latency Enable Recovery/Removal analysis Enable Timing Constraint Check
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HardCopy Series Handbook, Volume
Report Combined Fast/Slow Timing Report Paths Separately
Figure 5-12. Timing Settings
Enable Clock Latency
Turning Enable Clock Latency option enables support clock latency Timing Analyzer. Latency clock delay clock path affects clock skew. This different from offset, which instead alters setup relationship between clocks. When enable clock latency, design adjusts early late clock latency assignments. PLL's compensation delay analyzed latency does affect offset. clock settings where have specified offset, design automatically treats computed offset latency. using latency these automatically calculated clock offsets, setup relationship registers driven these clocks does vary
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HardCopy Recommended Settings Quartus Software
with routing. This potentially remove need multicycle assignments, well improve results ensuring that timing results more consistent each Fitter iteration. Once enabled, might need add, modify, remove multicycle assignments output clocks because potential change setup relationship these clocks. command enable clock latency set_global_assignment -name ENABLE_CLOCK_LATENCY
Enable Recovery/Removal Analysis
This setting allows Quartus Timing Analysis tool calculate recovery removal times control reset signals. recovery time minimum length time that asynchronous control input must stable before clock active edge. removal time minimum length time that asynchronous control input must stable after clock active edge. Altera recommends turning Timing Analysis tool setting during development because gives more complete timing analysis logic paths your design. However, your design does have timing requirement reset logic, turn this timing analysis off.
command enable recovery removal analysis set_global_assignment -name
Enable Timing Constraint Check
This setting enables Timing Analysis tool review your timing constraints complete minimum maximum timing coverage inputs, outputs, bidirectional pins, well clock settings clock sources. Asynchronous pins such resets static control signals also checked minimum maximum delay constraints. must perform this check review results before handoff design HardCopy Design Center. command enable Timing Constraint Check set_global_assignment -name
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Report Combined Fast/Slow Timing
Quartus software perform separate timing analysis worst-case best-case conditions independent reports. Report Combined Fast/Slow Timing setting allows Quartus software report slow corner delay case fast corner delay case timing combined report. This setting provides better timing report your design allowing hold-time issues well setup issues report. This report required HardCopy device development. Turning Report Combined Fast/Slow Timing setting requires Quartus software Timing Analyzer twice, once fast corner delay model once slow corner delay model. command enable Report Combined Fast/Slow Timing setting set_global_assignment -name DO_COMBINED_ANALYSIS
Report Paths Separately
Turning Report Paths Separately setting creates separate report panels paths constrained INPUT_MAX_DELAY, INPUT_MIN_DELAY, OUTPUT_MAX_DELAY, OUTPUT_MIN_DELAY parameters. specify these constraints Assignment Editor (Assignments menu). default, paths reported Clock Setup Clock Hold sections Timing Analyzer compilation report. Altera recommends turning Report Paths Separately setting make easier view timing analysis reports each device pin. This optional FPGA designs, helpful HardCopy development because timing requirements specify must both Stratix timing HardCopy timing results. This setting helps guarantee drop-in compatibility between your Stratix FPGA prototype your HardCopy structured ASIC.
command enable Report Paths Separately setting set_global_assignment -name REPORT_IO_PATHS_SEPARATELY
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HardCopy Recommended Settings Quartus Software
Quartus Version Features Supported HardCopy Designs
Quartus version software, supports Stratix optimization features HardCopy prototype development:
Physical Synthesis Optimization LogicLock Regions
Physical Synthesis Optimization
Physical Synthesis Optimizations Fitter settings dialog (Assignments Menu) enabled Stratix FPGA revision design. These optimizations migrated into HardCopy companion revision placement timing closure.
LogicLock Regions
LogicLock Regions Stratix FPGA allowed designs migrating HardCopy However, LogicLock Regions passed into HardCopy Companion Revision. LogicLock HardCopy design must create LogicLock Regions HardCopy companion revision. information using LogicLock Regions, refer LogicLock Design Methodology, chapter volume Quartus Handbook Altera website
Quartus Features Presently Supported HardCopy Designs
Because HardCopy devices new, Quartus version software does support advanced design features available other Altera devices. many these features scheduled subsequent releases Quartus software. Quartus software version does supports following features HardCopy prototype development using Stratix FPGA:
Incremental compilation (Synthesis Fitter) Physical Synthesis Fitter Optimizations HardCopy devices Virtual assignments Maximum fan-out assignments
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Chip Editor HardCopy Devices
When using Quartus Chip Editor your HardCopy design, Chip Editor changes done following ways:
Chip Editor change applied compiled Stratix design revision HardCopy Companion Revision created afterwards, incorporating Chip Editor modifications. Chip Editor change performed separately compiled, existing Stratix HardCopy design revisions. companion revisions created.
want Quartus Chip Editor Stratix design want migrate HardCopy device, best start with compiled Stratix project HardCopy Companion Revision created overwritten using HardCopy Utilities. Using Chip Editor compiled HardCopy design revision, requires that manually complete changes both HardCopy Stratix revisions, then HardCopy Companion Comparison Utility third-party formal verification software determine they equivalent. Chip Editor HardCopy following enabled features:
Add/Modify/Remove HCell Macro Combinational Function, Register, Adder/Subtractor connect wires them Create wires design Edit Cell properties such drive strength programmable delay values Edit settings such counter settings phase shift derived clocks
more information using Quartus Chip Editor, refer Design Analysis Engineering Change Management with Chip Editor chapter volume Quartus Handbook. Third party formal verification software available your HardCopy design. Cadence Encounter Conformal verification software used Stratix HardCopy families, well several other Altera product families. order Conformal software with Quartus software project your Stratix HardCopy design revisions, must enable Netlist Writer. necessary turn Netlist Writer generate necessary netlists command files needed
Formal Verification Stratix HardCopy Revisions
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HardCopy Utilities Menu
Conformal software. automatically Netlist Writer during compile your Stratix HardCopy design revisions, perform following steps: Select Tool Settings (Assignment Editor). Select Conformal (Formal Verification). Compile your Stratix Hardcopy design revisions, with both Tool Settings Conformal turned Netlist Writer automatically runs.
Quartus Netlist Writer produces netlist Stratix when that revision, generates second netlist when runs HardCopy revision. then Cadence Encounter Conformal software perform formal verification between your Stratix HardCopy netlists.
more information using Cadence Encounter Conformal verification software, refer Cadence Encounter Conformal Support chapter volume Quartus Handbook. HardCopy Utilities menu shown Quartus software (Figure 5-13). HardCopy Utilities (Project menu) contains main functions develop your HardCopy design Stratix FPGA prototype companion revision. From HardCopy Utilities menu, can:
HardCopy Utilities Menu
Create update HardCopy companion revisions which HardCopy companion revision current revision Generate HardCopy Handoff Report design reviews Archive HardCopy Handoff Files submission HardCopy Design Center Compare companion revisions functional equivalence Track your design progress using HardCopy Advisor
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Figure 5-13. HardCopy Utilities Menu
Each features within HardCopy Utilities (Project menu) summarized Table 5-2. process using each these features explained following sections.
Table 5-2. HardCopy Utilities Menu Options (Part Menu
Create/Overwrite HardCopy Companion Revision Current HardCopy Companion Revision Compare HardCopy Companion Revisions
Description
Create companion revision update existing companion revision your Stratix HardCopy design. Specify which companion revision associate with current design revision.
Applicable Design Revision
Stratix prototype design HardCopy Companion Revision Stratix prototype design HardCopy Companion Revision Stratix prototype design HardCopy Companion Revision
Restrictions
Must disable Auto Device selection Must Stratix device HardCopy companion device
Companion Revision must already exist
Compares Stratix design revision with HardCopy companion design revision generates report.
Compilation both revisions must complete
17-22
Alte
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