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Hitachi SuperH
RISC engine
SH7760
HD6417760BP200D
Hardware Manual
ADE-602-291 Rev. 02/28/03 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Rev. 1.0, 02/03, page xlviii
General Precautions Handling Product
Treatment Pins Note: connect anything pins. (not connected) pins either connected internal circuitry they used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, passthrough current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition Access Undefined Reserved Addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
Rev. 1.0, 02/03, page xlviii
Configuration This Manual
This manual comprises following items: General Precautions Handling Product Configuration This Manual Preface Contents Overview Description Functional Modules System-Control Modules On-Chip Peripheral Modules configuration functional description each module differs according module. However, generic style includes following items: Feature Input/Output iii) Register Description Operation Usage Note When designing application system that includes this LSI, take notes into account. Each section includes notes relation descriptions given, usage notes given, required, final part each section. List Registers Main Revisions Additions this Edition (only revised versions) list revisions summary points that have been revised added earlier versions. This does include revised contents. details, actual locations this manual.
Rev. 1.0, 02/03, page xlviii
Preface
SH7760 RISC (Reduced Instruction Computer) microcomputer includes Hitachioriginal RISC core, peripheral functions required configure system. Target Users: This manual written users will using this design application systems. Users this manual expected understand fundamentals electrical circuits, logical circuits, microcomputers. Objective: This manual written explain hardware functions electrical characteristics this above users.
Notes reading this manual: Product names following products covered this manual.
Product Classifications Abbreviations Basic Classification SH7760 (256-pin LBGA) Product Code HD6417760BP200D
order understand overall functions chip Read manual according contents. This manual roughly categorized into parts CPU, system control functions, peripheral functions. Rules: order: Signal notation: Related Manuals: left right. overbar added low-active signal: xxxx
Number notation: Binary B'xxxx, hexadecimal H'xxxx, decimal xxxx.
latest versions related manuals available from site. Please ensure have latest versions documents require.
Rev. 1.0, 02/03, page xlviii
Contents
Section Overview
Features. Block Diagram Arrangement Description. Function
Section Programming Model.29
Data Formats. Register Descriptions 2.2.1 Privileged Mode Banks 2.2.2 General Registers 2.2.3 Control Registers 2.2.4 System Registers. 2.2.5 Registers Memory-Mapped Registers. Data Formats. 2.4.1 Data Format Registers 2.4.2 Data Formats Memory Processing States. Processing Modes
Section Floating-Point Unit (FPU).41
Features. Data Formats. 3.2.1 Floating-Point Format. 3.2.2 Non-Numbers (NaN) 3.2.3 Denormalized Numbers Register Descriptions 3.3.1 Floating-Point Registers. 3.3.2 Floating-Point Status/Control Register (FPSCR). 3.3.3 Floating-Point Communication Register (FPUL) Rounding. Floating-Point Exceptions. 3.5.1 General Disable Exceptions Slot Disable Exceptions. 3.5.2 Exception Sources 3.5.3 Exception Handling Graphics Support Functions. 3.6.1 Geometric Operation Instructions.
Rev. 1.0, 02/03, page xlviii
3.6.2 Pair Single-Precision Data Transfer.53 Notes programming.53
Section Instruction
Execution Environment.55 Addressing Modes.57 Instruction
Section Pipelining
Pipelines.73 Parallel-Executability.80 Execution Cycles Pipeline Stalling
Section Memory Management Unit (MMU)
Overview MMU.99 6.1.1 Address Spaces .101 Register Descriptions .108 6.2.1 Page Table Entry High Register (PTEH) .109 6.2.2 Page Table Entry Register (PTEL) .110 6.2.3 Page Table Entry Assistance Register (PTEA) .111 6.2.4 Translation Table Base Register (TTB) .111 6.2.5 Exception Address Register (TEA) .112 6.2.6 Control Register (MMUCR) .112 Functions .115 6.3.1 Unified (UTLB) Configuration .115 6.3.2 Instruction (ITLB) Configuration.118 6.3.3 Address Translation Method.119 Functions.121 6.4.1 Hardware Management .121 6.4.2 Software Management .121 6.4.3 Instruction (LDTLB).121 6.4.4 Hardware ITLB Miss Handling .122 6.4.5 Avoiding Synonym Problems .123 Exceptions.124 6.5.1 Instruction Multiple Exception.124 6.5.2 Instruction Miss Exception.125 6.5.3 Instruction Protection Violation Exception .126 6.5.4 Data Multiple Exception.127 6.5.5 Data Miss Exception.127 6.5.6 Data Protection Violation Exception .128 6.5.7 Initial Page Write Exception .129 Memory-Mapped Configuration.130
Rev. 1.0, 02/03, page xlviii
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6
ITLB Address Array ITLB Data Array ITLB Data Array UTLB Address Array. UTLB Data Array UTLB Data Array
Section Caches.137
Features. Register Descriptions 7.2.1 Cache Control Register (CCR) 7.2.2 Queue Address Control Register (QACR0) 7.2.3 Queue Address Control Register (QACR1) Operand Cache Operation. 7.3.1 Read Operation 7.3.2 Write Operation 7.3.3 Write-Back Buffer 7.3.4 Write-Through Buffer. 7.3.5 Mode 7.3.6 Index Mode 7.3.7 Coherency between Cache External Memory 7.3.8 Prefetch Operation Instruction Cache Operation 7.4.1 Read Operation 7.4.2 Index Mode Memory-Mapped Cache Configuration (Cache Direct Mapping Mode) 7.5.1 Address Array 7.5.2 Data Array. 7.5.3 Address Array 7.5.4 Data Array Memory-Mapped Cache Configuration (Double-Size Cache Mode). 7.6.1 Address Array 7.6.2 Data Array. 7.6.3 Address Array 7.6.4 Data Array 7.6.5 Summary Memory-Mapping Store Queues 7.7.1 Configuration. 7.7.2 Writing 7.7.3 Transfer External Memory. 7.7.4 Determination Access Exception. 7.7.5 Reading from
Rev. 1.0, 02/03, page viii xlviii
Section Exceptions.
Exception Handling Functions.165 8.1.1 Exception Handling Flow .165 8.1.2 Exception Handling Vector Addresses .166 Exception Types Priorities .167 Exception Flow .171 8.3.1 Exception Flow .171 8.3.2 Exception Source Acceptance.172 8.3.3 Exception Requests .173 8.3.4 Return from Exception Handling .173 Register Descriptions .174 8.4.1 Exception Event Register (EXPEVT) .175 8.4.2 Interrupt Event Register (INTEVT) .175 8.4.3 TRAPA Exception Register (TRA) .176 Operation.177 8.5.1 Resets .177 8.5.2 General Exceptions .182 8.5.3 Interrupts.196 8.5.4 Priority Order with Multiple Exceptions.200 Usage Notes .201 Restrictions .202 8.7.1 Restrictions First Instruction Exception Handling Routine .202
Section Interrupt Controller (INTC)
Features .203 Input/Output Pins .205 Register Descriptions .205 9.3.1 Interrupt Priority Level Setting Registers (IPRA IPRD).207 9.3.2 Interrupt Priority Level Setting Registers (INTPRI00 INTPRI0C).208 9.3.3 Interrupt Control Register (ICR).209 9.3.4 Interrupt Source Registers (INTREQ00, INTREQ04) .211 9.3.5 Interrupt Mask Registers (INTMSK00, INTMSK04) .213 9.3.6 Interrupt Mask Clear Registers (INTMSKCLR00, INTMSKCLR04) .216 Interrupt Sources .217 9.4.1 Interrupt.217 9.4.2 Interrupts .217 9.4.3 Interrupts.217 9.4.4 Peripheral Module Interrupts .219 9.4.5 Interrupt Exception Handling Priority.220 Operation.225 9.5.1 Interrupt Operation Sequence .225 9.5.2 Multiple Interrupts .227
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9.5.3 Interrupt Masking with Bit. Interrupt Response Time.
Section State Controller (BSC) .229
10.1 10.2 10.3 10.4 10.5 Features. Input/Output Pins Overview Areas PCMCIA Support. Register Descriptions 10.5.1 Control Register (BCR1) 10.5.2 Control Register (BCR2) 10.5.3 Control Register (BCR3) 10.5.4 Control Register (BCR4) 10.5.5 Wait Control Register (WCR1). 10.5.6 Wait Control Register (WCR2). 10.5.7 Wait Control Register (WCR3). 10.5.8 Wait Control Register (WCR4). 10.5.9 Memory Control Register (MCR). 10.5.10 PCMCIA Control Register (PCR). 10.5.11 Synchronous DRAM Mode Register (SDMR) 10.5.12 Refresh Timer Control/Status Register (RTCSR) 10.5.13 Refresh Timer Counter (RTCNT). 10.5.14 Refresh Time Constant Register (RTCOR) 10.5.15 Refresh Count Register (RFCR) 10.5.16 Accessing Refresh Control Related Registers. 10.6 Operation 10.6.1 Endian/Access Size Data Alignment. 10.6.2 Areas 10.6.3 SRAM Interface. 10.6.4 Synchronous DRAM Interface. 10.6.5 Burst Interface. 10.6.6 PCMCIA Interface. 10.6.7 Interface. 10.6.8 Byte Control SRAM Interface 10.6.9 Waits between Access Cycles. 10.6.10 Arbitration 10.6.11 Release Acquire Sequences 10.7 Usage Notes 10.7.1 Refresh 10.7.2 Arbitration
Rev. 1.0, 02/03, page xlviii
Section Direct Memory Access Controller (DMAC)
11.1 Features .361 11.2 Input/Output Pins .364 11.3 Register Descriptions .365 11.3.1 Source Address Register (SAR).371 11.3.2 Destination Address Register (DAR).371 11.3.3 Transfer Count Register (DMATCR) .372 11.3.4 Channel Control Register (CHCR) .373 11.3.5 Operation Register (DMAOR).382 11.3.6 Request Resource Selection Registers (DMARSRA, DMARSRB) .384 11.3.7 Control Register (DMAPCR) .388 11.3.8 Request Control Register (DMARCR) .388 11.3.9 Control Register (DMABRGCR) .391 11.3.10 Audio Source Address Register (DMAATXSAR) .395 11.3.11 Audio Destination Address Register (DMAARXDAR) .395 11.3.12 Audio Transmit Transfer Count Register (DMAATXTCR).396 11.3.13 Audio Receive Transfer Count Register (DMAARXTCR) .396 11.3.14 Audio Control Register (DMAACR).397 11.3.15 Audio Transmit Transfer Counter (DMAATXTCNT) .400 11.3.16 Audio Receive Transfer Counter (DMAARXTCNT).400 11.3.17 Source Address Register (DMAUSAR).401 11.3.18 Destination Address Register (DMAUDAR).401 11.3.19 Size Register (DMAURWSZ) .402 11.3.20 Control Register (DMAUCR) .403 11.4 Operation.404 11.4.1 Transfer Procedure.404 11.4.2 Transfer Requests .406 11.4.3 Channel Priorities.408 11.4.4 Types Transfer.411 11.4.5 Number Cycles DREQ Sampling Timing .420 11.4.6 Ending Transfer .441 11.4.7 Interrupt-Request Codes .444 11.5 Examples .445 11.5.1 Examples Transfer between External Memory External Device with DACK .445 11.6 DMABRG Operation .447 11.6.1 DMABRG Request .447 11.6.2 DMABRG Reset .447 11.6.3 Transfer Operating Mode .448 11.6.4 Audio Receive Operation.450 11.6.5 Audio Transmit Operation .450 11.6.6 Auto Reload Function .453
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11.6.7 Forced Termination Audio Transfer. 11.6.8 Double Buffer Control Audio Data 11.6.9 HAC/SSI Endian Conversion Function 11.6.10 Switching Data Left Right Channels 11.6.11 LCDC Transfer 11.6.12 Transfer. 11.6.13 Endian Conversion Function. 11.6.14 DMABRG Interrupts 11.7 Usage Notes
Section Clock Pulse Generator (CPG) .465
12.1 12.2 12.3 12.4 Features. Input/Output Pins Clock Operating Modes Register Descriptions 12.4.1 Frequency Control Register (FRQCR) 12.4.2 Clock Division Register (DCKDR) 12.4.3 Module Clock Control Register (MCKCR) 12.5 Frequency Changing Method. 12.5.1 Switching between Circuit On/Off (When Circuit Off) 12.5.2 Switching between Circuit On/Off (When Circuit On). 12.5.3 Changing Clock Frequency Division Ratio (When Circuit On). 12.5.4 Changing Clock Frequency Division Ratio (When Circuit Off). 12.5.5 Changing Frequency Division Ratio Clock Peripheral Clock 12.5.6 Switching between Circuit On/Off 12.5.7 Changing Output Clock Division Ratio. 12.5.8 Controlling Output Clock 12.5.9 Controlling CKIO Output Clock. 12.6 Usage Notes
Section Watchdog Timer (WDT) .481
13.1 Features. 13.2 Register Descriptions 13.2.1 Watchdog Timer Counter (WTCNT). 13.2.2 Watchdog Timer Control/Status Register (WTCSR). 13.2.3 Notes Register Access. 13.3 Operation 13.3.1 Standby Clearing Procedure 13.3.2 Frequency Changing Procedure 13.3.3 Using Watchdog Timer Mode. 13.3.4 Using Interval Timer Mode
Rev. 1.0, 02/03, page xlviii
Section Power-Down Modes
14.1 Input/Output Pins .491 14.2 Register Descriptions .491 14.2.1 Standby Control Register (STBCR).492 14.2.2 Standby Control Register (STBCR2).493 14.2.3 Clock Stop Register (CLKSTP00) .495 14.2.4 Clock Stop Clear Register (CLKSTPCLR00).496 14.3 Operation.496 14.3.1 Sleep Mode .496 14.3.2 Deep Sleep Mode.497 14.3.3 Software Standby Mode.497 14.3.4 Module Standby Function.498 14.3.5 Hardware Standby Mode .499 14.3.6 STATUS Change Timing .499 14.3.7 Hardware Standby Mode Timing.506
Section Timer Unit (TMU)
15.1 Features .509 15.2 Input/Output Pins .510 15.3 Register Descriptions .511 15.3.1 Timer Start Register (TSTR).512 15.3.2 Timer Constant Register (TCORn) .513 15.3.3 Timer Counter (TCNTn) .513 15.3.4 Timer Control Registers (TCRn) 2).514 15.3.5 Input Capture Register (TCPR2).516 15.4 Operation.517 15.4.1 Counter Operation.517 15.4.2 Input Capture Function .519 15.5 Interrupts .520 15.6 Usage Notes .521 15.6.1 Register Writes.521 15.6.2 Reading from TCNT .521 15.6.3 External Clock Frequency.521
Section Timer/Counter (CMT)
16.1 Features .523 16.2 Input/Output Pins .524 16.3 Register Descriptions .524 16.3.1 Configuration Register (CMTCFG) .526 16.3.2 Free-Running Timer (CMTFRT) .530 16.3.3 Control Register (CMTCTL) .530 16.3.4 Status Register (CMTIRQS) .533
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16.3.5 Channels Time Registers (CMTCH0T CMTCH3T). 16.3.6 Channels Stop Time Registers (CMTCH0ST CMTCH3ST). 16.3.7 Channels Counters (CMTCH0C CMTCH3C) 16.4 Operation 16.4.1 Edge Detection. 16.4.2 32-Bit Timer: Input Capture 16.4.3 32-Bit Timer: Output Compare. 16.4.4 16-Bit Timer: Input Capture 16.4.5 16-Bit Timer: Output Compare. 16.4.6 Counter: Up-/Updown-Counter 16.4.7 Counter: Up-Counter with Capture. 16.4.8 Interrupts. 16.4.9 Rotary Mode 16.4.10 Timer Frequency. 16.4.11 Standby Mode
Section Serial Communication Interface with FIFO (SCIF).543
17.1 Features. 17.2 Input/Output Pins 17.3 Register Descriptions 17.3.1 Receive Shift Register (SCRSR). 17.3.2 Receive FIFO Data Register (SCFRDR) 17.3.3 Transmit Shift Register (SCTSR) 17.3.4 Transmit FIFO Data Register (SCFTDR) 17.3.5 Serial Mode Register (SCSMR). 17.3.6 Serial Control Register (SCSCR). 17.3.7 Serial Status Register (SCFSR). 17.3.8 Rate Register (SCBRR) 17.3.9 FIFO Control Register (SCFCR) 17.3.10 Transmit FIFO Data Count Register (SCTFDR) 17.3.11 Receive FIFO Data Count Register (SCRFDR). 17.3.12 Serial Port Register (SCSPTR) 17.3.13 Line Status Register (SCLSR) 17.3.14 Serial Error Register (SCRER) 17.4 Operation 17.4.1 Overview. 17.4.2 Operation Asynchronous Mode 17.4.3 Operation Synchronous Mode 17.5 SCIF Interrupt Sources DMAC 17.6 Usage Notes
Rev. 1.0, 02/03, page xlviii
Section Card Module (SIM)
18.1 Features .601 18.2 Input/Output Pins .602 18.3 Register Descriptions .603 18.3.1 Serial Mode Register (SISMR) .605 18.3.2 Rate Register (SIBRR) .606 18.3.3 Serial Control Register (SISCR) .606 18.3.4 Transmit Shift Register (SITSR).609 18.3.5 Transmit Data Register (SITDR) .609 18.3.6 Serial Status Register (SISSR) .610 18.3.7 Receive Shift Register (SIRSR) .616 18.3.8 Receive Data Register (SIRDR).616 18.3.9 Smart Card Mode Register (SISCMR).617 18.3.10 Serial Control Register (SISC2R) .619 18.3.11 Guard Extension Register (SIGRD).619 18.3.12 Wait Time Register (SIWAIT) .620 18.3.13 Sampling Register (SISMPL) .621 18.4 Operation.621 18.4.1 Data Format .621 18.4.2 Register Settings .623 18.4.3 Clocks .625 18.4.4 Data Transmission/Reception Operation .626 18.5 Usage Notes .630 18.5.1 Receive data Timing .630 18.5.2 Repetition when Smart Card Interface Receiver Mode 0).631 18.5.3 Repetition when Smart Card Interface Transmitter Mode .631 18.5.4 Transmit Interrupt.633 18.5.5 Standby Mode Switching .633 18.5.6 Power-On Clock Output.634 18.5.7 Connections .634
Section Hitachi Interface.
19.1 Features .637 19.2 Input/Output Pins .638 19.3 Register Descriptions .638 19.3.1 Slave Control Register (ICSCR) .641 19.3.2 Slave Status Register (ICSSR) .642 19.3.3 Slave Interrupt Enable Register (ICSIER) .645 19.3.4 Slave Address Register (ICSAR) .646 19.3.5 Master Control Register (ICMCR).646 19.3.6 Master Status Register (ICMSR) .649 19.3.7 Master Interrupt Enable Register (ICMIER).651
Rev. 1.0, 02/03, page xlviii
19.4
19.5
19.6
19.7
19.3.8 Master Address Register (ICMAR) 19.3.9 Clock Control Register (ICCCR) 19.3.10 Receive/Transmit Data Registers (ICRXD/ICTXD). 19.3.11 FIFO Control Register (ICFCR) 19.3.12 FIFO Status Register (ICFSR) 19.3.13 FIFO Interrupt Enable Register (ICFIER) 19.3.14 Receive FIFO Data Count Register (ICRFDR) 19.3.15 Transmit FIFO Data Count Register (ICTFDR) Operation 19.4.1 Data Clock Filters 19.4.2 Clock Generator. 19.4.3 Master Slave Interfaces 19.4.4 Software Status Interlocking. 19.4.5 Data Format 19.4.6 7-Bit Address Format. 19.4.7 10-Bit Address Format. 19.4.8 Master Transmit Operation (Single Buffer Mode). 19.4.9 Master Receiver Operation (Single Buffer Mode). 19.4.10 Standby Mode FIFO Mode Operation. 19.5.1 Master Transmitter Operation (FIFO Buffer Mode) 19.5.2 Master Receiver Operation (FIFO Buffer Mode) Programming Examples. 19.6.1 Master Transmitter (Single Buffer Mode) 19.6.2 Master Receiver (Single Buffer Mode). 19.6.3 Master Transmitter-Restart-Master Receiver (Single Buffer Mode) 19.6.4 Master Transmitter (FIFO Buffer Mode). 19.6.5 Master Receiver (FIFO Buffer Mode) Usage Notes 19.7.1 Restriction 19.7.2 Restriction
Section Serial Sound Interface (SSI) Module .681
20.1 Features. 20.2 Input/Output Pins 20.3 Register Descriptions 20.3.1 Control Register (SSICR) 20.3.2 Status Register (SSISR) 20.3.3 Transmit Data Register (SSITDR) 20.3.4 Receive Data Register (SSIRDR) 20.4 Operation 20.4.1 Format.
Rev. 1.0, 02/03, page xlviii
20.4.2 Non-Compressed Modes.696 20.4.3 Compressed Modes.705 20.4.4 Operation Modes.707 20.4.5 Transmit Operation .708 20.4.6 Receive Operation.711 20.4.7 Serial Clock Control .714 20.5 Usage Note.714 20.5.1 Restrictions when Overflow Occurs during Receive Operation .714
Section Host Module (USB)
21.1 Features .715 21.2 Input/Output Pins .717 21.3 Register Descriptions .717 21.3.1 Host Controller Interface Revision Register (HcRevision).720 21.3.2 Control Register (HcControl).720 21.3.3 Command Status Register (HcCommandStatus) .724 21.3.4 Interrupt Status Register (HcInterruptStatus).726 21.3.5 Interrupt Enable Register (HcInterruptEnable) .728 21.3.6 Interrupt Disable Register (HcInterruptDisable).730 21.3.7 Host Controller Communication Area Pointer Register (HcHCCA) .732 21.3.8 Period Current Pointer Register (HcPeriodCurrentED).732 21.3.9 Control Head Pointer Register (HcControlHeadED).733 21.3.10 Control Current Pointer Register (HcControlCurrentED) .733 21.3.11 Bulk Head Pointer Register (HcBulkHeadED).734 21.3.12 Bulk Current Pointer Register (HcBulkCurrentED) .734 21.3.13 Done Queue Head Pointer Register (HcDoneHead) .735 21.3.14 Frame Interval Register (HcFmInterval).736 21.3.15 Frame Remaining Register (HcFmRemaining).737 21.3.16 Frame Number Register (HcFmNumber) .737 21.3.17 Periodic Start Register (HcPeriodicStart) .738 21.3.18 Speed Threshold Register (HcLSThreshold) .739 21.3.19 Root Descriptor Register (HcRhDescriptorA) .740 21.3.20 Root Descriptor Register (HcRhDescriptorB) .742 21.3.21 Root Status Register (HcRhStatus) .744 21.3.22 Root Port Status Register (HcRhPortStatus1) .746 21.4 Memory.754 21.5 Data Storage Format Host Controller .755 21.5.1 Storage Format Transfer Data.755 21.5.2 Storage Format Descriptor.756 21.6 Restrictions HcRhDescriptorA.756
Rev. 1.0, 02/03, page xvii xlviii
Section Hitachi Controller Area Network (HCAN2) .757
22.1 Features. 22.2 Architecture 22.2.1 Block diagram. 22.2.2 Block Function. 22.3 Input/Output Pins 22.4 Programming model overview. 22.4.1 Memory map. 22.4.2 Mail box. 22.5 HCAN2 Control Registers 22.5.1 Master Control Register (CANMCR) 22.5.2 General Status Register (CANGSR) 22.5.3 Configuration Registers (CANBCR1, CANBCR0) 22.5.4 Interrupt Request Register (CANIRR). 22.5.5 Interrupt Mask Register (CANIMR). 22.5.6 Transmit Error Counter Receive Error Counter (CANTECREC) 22.5.7 Transmit Pending Request Registers (CANTXPR1, CANTXPR0) 22.5.8 Transmit Cancel Registers (CANTXCR1, CANTXCR0) 22.5.9 Transmit Acknowledge Registers (CANTXACK1, CANTXACK0). 22.5.10 Abort Acknowledge Registers (CANABACK1, CANABACK0) 22.5.11 Receive Data Frame Pending Registers (CANRXPR1, CANRXPR0) 22.5.12 Remote Frame Request Pending Registers (CANRFPR1, CANRFPR0) 22.5.13 Mailbox Interrupt Mask Registers (CANMBIMR1, CANMBIMR0) 22.5.14 Unread Message Status Registers (CANUMSR1, CANUMSR0). 22.5.15 Timer Counter Register (CANTCNTR). 22.5.16 Timer Control Register (CANTCR) 22.5.17 Timer Compare Match Registers (CANTCMR). 22.6 Operation 22.6.1 Test Mode Settings 22.6.2 HCAN2 Settings 22.6.3 Message Transmission Sequence. 22.6.4 Message Reception Sequence 22.6.5 Reconfiguration Mailbox. 22.6.6 Standby Mode
Section Hitachi Serial Protocol Interface (HSPI).823
23.1 Features. 23.2 Input/Output Pins 23.3 Register Descriptions 23.3.1 Control Register (SPCR).
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23.3.2 Status Register (SPSR).828 23.3.3 System Control Register (SPSCR).831 23.3.4 Transmit Buffer Register (SPTBR).834 23.3.5 Receive Buffer Register (SPRBR) .835 23.4 Operation.836 23.4.1 Operation Overview without (FIFO Mode Disabled).836 23.4.2 Operation Overview with DMA.837 23.4.3 Operation with FIFO Mode Enabled.837 23.4.4 Timing Diagrams .838 23.4.5 HSPI Software Reset.839 23.4.6 Clock Polarity Transmit Control .839 23.4.7 Transmit Receive Routines .839 23.5 Power Saving Clocking Strategy.840
Section Function Controller (PFC).
24.1 Features .841 24.2 Register Descriptions .844 24.2.1 Port Control Register (PACR).847 24.2.2 Port Control Register (PBCR) .848 24.2.3 Port Control Register (PCCR) .849 24.2.4 Port Control Register (PDCR).850 24.2.5 Port Control Register (PECR) .852 24.2.6 Port Control Register (PFCR).853 24.2.7 Port Control Register (PGCR).854 24.2.8 Port Control Register (PHCR).855 24.2.9 Port Control Register (PJCR) .857 24.2.10 Port Control Register (PKCR).858 24.2.11 Port Data Register (PADR) .859 24.2.12 Port Data Register (PBDR) .860 24.2.13 Port Data Register (PCDR) .861 24.2.14 Port Data Register (PDDR) .861 24.2.15 Port Data Register (PEDR).862 24.2.16 Port Data Register (PFDR) .862 24.2.17 Port Data Register (PGDR) .863 24.2.18 Port Data Register (PHDR) .863 24.2.19 Port Data Register (PJDR).864 24.2.20 Port Data Register (PKDR) .864 24.2.21 GPIO Interrupt Control Register (GPIOIC) .865 24.2.22 Port Pull-Up Control Register (PAPUPR) .867 24.2.23 Port Pull-Up Control Register (PBPUPR).867 24.2.24 Port Pull-Up Control Register (PCPUPR).868 24.2.25 Port Pull-Up Control Register (PDPUPR) .869
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24.2.26 Port Pull-Up Control Register (PEPUPR) 24.2.27 Port Pull-Up Control Register (PFPUPR). 24.2.28 Port Pull-Up Control Register (PGPUPR) 24.2.29 Port Pull-Up Control Register (PHPUPR) 24.2.30 Port Pull-Up Control Register (PJPUPR) 24.2.31 Port Pull-Up Control Register (PKPUPR) 24.2.32 Mode-Pin Pull-Up Control Register (MDPUPR). 24.2.33 Input-Pin Pull-Up Control Register (INPUPA) 24.2.34 Control Register (DMAPCR) 24.2.35 Peripheral Module Select Register (IPSELR). 24.2.36 SCIF.Hi-z Control Register (SCIHZR). 24.2.37 Mode Select Register (MODSELR)
Section Hitachi Audio Codec Interface (HAC).881
25.1 Features. 25.2 Input/Output Pins 25.3 Register Descriptions 25.3.1 Control Status Register (HACCR) 25.3.2 Command/Status Address Register (HACCSAR) 25.3.3 Command/Status Data Register (HACCSDR). 25.3.4 Left Channel Register (HACPCML) 25.3.5 Right Channel Register (HACPCMR). 25.3.6 Interrupt Enable Register (HACTIER) 25.3.7 Status Register (HACTSR). 25.3.8 Interrupt Enable Register (HACRIER). 25.3.9 Status Register (HACRSR) 25.3.10 Control Register (HACACR) 25.4 Frame Slot Structure. 25.5 Operation 25.5.1 Receiver 25.5.2 Transmitter. 25.5.3 25.5.4 Interrupts. 25.5.5 Restrictions Related HACTCR.CMDAMT 25.5.6 Initialization Sequence. 25.5.7 Power-Down Mode. 25.5.8 Notes 25.5.9 Reference
Section Multimedia Card Interface (MMCIF) .909
26.1 Features. 26.2 Input/Output Pins
Rev. 1.0, 02/03, page xlviii
26.3 Register Descriptions .911 26.3.1 Mode Register (MODER) .914 26.3.2 Command Type Register (CMDTYR).915 26.3.3 Response Type Register (RSPTYR) .916 26.3.4 Transfer Byte Number Count Register (TBCR) .919 26.3.5 Command Registers (CMDR0 CMDR5) .920 26.3.6 Response Registers (RSPR0 RSPR16) .921 26.3.7 Command Start Register (CMDSTRT).923 26.3.8 Operation Control Register (OPCR) .924 26.3.9 Command Timeout Control Register (CTOCR) .926 26.3.10 Data Timeout Register (DTOUTR) .927 26.3.11 Card Status Register (CSTR) .928 26.3.12 Interrupt Control Registers (INTCR0 INTCR2) .930 26.3.13 Interrupt Status Registers (INTSTR0 INTSTR2).932 26.3.14 Transfer Clock Control Register (CLKON).937 26.3.15 Data Register (DR) .938 26.3.16 FIFO Pointer Clear Register (FIFOCLR).939 26.3.17 Control Register (DMACR).940 26.3.18 Receive Data Timing Select Register (RDTIMSEL) .941 26.4 Operation.941 26.4.1 Operations Mode.941 26.5 MMCIF Interrupt Sources.964 26.6 Operations when Using DMA.965 26.6.1 Operation Read Sequence .965 26.6.2 Operation Write Sequence .965 26.7 Register Accesses with Little Endian Specification.968
Section Multifunctional Interface (MFI)
27.1 Features .969 27.2 Input/Output Pins .971 27.3 Register Descriptions .972 27.3.1 Index Register (MFIIDX) .974 27.3.2 General Status Register (MFIGSR) .975 27.3.3 Status/Control Register (MFISCR) .976 27.3.4 Memory Control Register (MFIMCR).978 27.3.5 Internal Interrupt Control Register (MFIIICR) .980 27.3.6 External Interrupt Control Register (MFIEICR) .981 27.3.7 Address Register (MFIADR) .982 27.3.8 Data Register (MFIDATA).983 27.4 Operation.984 27.4.1 Overview.984 27.4.2 Connections .985
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27.4.3 Memory 27.5 Interface (Basic). 27.5.1 68-Series 8-Bit Parallel Interface. 27.5.2 80-Series 8-Bit Parallel Interface. 27.6 Interface (Details) 27.6.1 Writing MFIIDX/Reading from MFIGSR. 27.6.2 Reading from/Writing Register 27.6.3 Continuous Data Writing MFRAM 27.6.4 Continuous Reading from MFRAM
Section Hitachi User Debug Interface (H-UDI) .991
28.1 Input/Output Pins 28.2 Boundary Scan Controllers (EXTEST, SAMPLE/PRELOAD, BYPASS). 28.2.1 Boundary Scan Register (SDBSR) 28.3 Register Descriptions 1005 28.3.1 Instruction Register (SDIR) 1007 28.3.2 Data Register (SDDRH, SDDRL) 1007 28.3.3 Interrupt Source Register (SDINT). 1008 28.4 Operation 1009 28.4.1 Control. 1009 28.4.2 H-UDI Reset 1010 28.4.3 H-UDI Interrupt 1010 28.5 Usage Notes 1011
Section Converter (ADC) .1013
29.1 Features. 1013 29.2 Input/Output Pins 1015 29.3 Register Descriptions 1016 29.3.1 Conversion Data Registers (ADDRA ADDRD) 1017 29.3.2 Control/Status Register (ADCSR) 1018 29.4 Operation 1021 29.4.1 Single Mode. 1021 29.4.2 Multi Mode 1023 29.4.3 Scan Mode 1025 29.4.4 Conversion Time. 1028 29.4.5 External Trigger Input Timing. 1029 29.5 Interrupts. 1030 29.6 Definitions Conversion Accuracy. 1030 29.7 Usage Notes 1031 29.7.1 Setting Analog Input Voltage 1031 29.7.2 Processing Analog Input Pins. 1032 29.7.3 Clock Division Ratio Settings 1033
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29.7.4 Notes Standby Modes 1033
Section Controller (LCDC). 1035
30.1 Features 1035 30.2 Input/Output Pins 1036 30.3 Register Configuration 1037 30.3.1 LCDC Input Clock Register (LDICKR) 1039 30.3.2 LCDC Module Type Register (LDMTR). 1040 30.3.3 LCDC Data Format Register (LDDFR) 1043 30.3.4 LCDC Scan Mode Register (LDSMR) 1045 30.3.5 LCDC Display Start Address Register Upper (LDSARU) 1046 30.3.6 LCDC Display Start Address Register Lower (LDSARL) 1047 30.3.7 LCDC Display Line Address Offset Register (LDLAOR) 1048 30.3.8 LCDC Palette Control Register (LDPALCR) 1049 30.3.9 Palette Data Registers (LDPR00 LDPRFF) 1050 30.3.10 LCDC Horizontal Character Number Register (LDHCNR) 1051 30.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) 1051 30.3.12 LCDC Vertical Display Line Number Register (LDVDLNR). 1053 30.3.13 LCDC Vertical Total Line Number Register (LDVTLNR) 1054 30.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) 1055 30.3.15 LCDC Modulation Signal Toggle Line Number Register (LDACLNR). 1056 30.3.16 LCDC Interrupt Control Register (LDINTR) 1056 30.3.17 LCDC Power Management Mode Register (LDPMMR). 1058 30.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) 1060 30.3.19 LCDC Control Register (LDCNTR) 1061 30.4 Operation. 1063 30.4.1 Size Modules Which Displayed with this LCDC. 1063 30.4.2 Limits Resolution Rotated Displays 1064 30.4.3 Color Palette Specification. 1064 30.4.4 Data Format 1066 30.4.5 Setting Display Resolution. 1069 30.4.6 Power Supply Control Sequence Processing 1069 30.4.7 Operation Hardware Rotation. 1074 30.5 Clock Data Signal Examples 1077
Section User Break Controller (UBC) 1089
31.1 Features 1089 31.2 Register Descriptions 1091 31.2.1 Break Address Register (BARA, BARB). 1093 31.2.2 Break ASID Register (BASRA, BASRB) 1094 31.2.3 Break Address Mask Register (BAMRA). 1095 31.2.4 Break Address Mask Register (BAMRB) 1096
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31.3
31.4 31.5 31.6 31.7
31.2.5 Break Cycle Register (BBRA). 1097 31.2.6 Break Cycle Register (BBRB) 1098 31.2.7 Break Data Register (BDRB) 1099 31.2.8 Break Data Mask Register (BDMRB). 1099 31.2.9 Break Control Register (BRCR) 1100 Operation 1102 31.3.1 Explanation Terms Relating Access. 1102 31.3.2 Explanation Terms Instruction Intervals. 1103 31.3.3 User Break Operation Sequence 1103 31.3.4 Instruction Access Cycle Break 1104 31.3.5 Operand Access Cycle Break. 1105 31.3.6 Condition Match Flag Setting 1106 31.3.7 Program Counter (PC) Value Saved 1106 31.3.8 Contiguous Settings Sequential Conditions 1107 Usage Notes 1108 User Break Debug Support Function 1109 Examples 1111 User Break Controller Stop Function. 1113 31.7.1 Transition User Break Controller Stopped State. 1113 31.7.2 Cancelling User Break Controller Stopped State 1113 31.7.3 Examples Stopping Restarting User Break Controller. 1114
Section List Registers.1115
32.1 Register Addresses functional module, order corresponding section numbers). 1116 32.2 Register Bits. 1133 32.3 Register States Each Operating Mode. 1177
Section Electrical Characteristics .1195
33.1 Absolute Maximum Ratings 1195 33.2 Characteristics 1196 33.3 Characteristics 1198 33.3.1 Clock Control Signal Timing 1199 33.3.2 Control Signal Timing 1206 33.3.3 Timing 1208 33.3.4 INTC Module Signal Timing. 1241 33.3.5 DMAC Module Signal Timing 1241 33.3.6 Module Signal Timing 1242 33.3.7 SCIF Module Signal Timing. 1243 33.3.8 H-UDI Module Signal Timing. 1244 33.3.9 Module Signal Timing 1246 33.3.10 HCAN2 Module Signal Timing. 1247
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33.3.11 GPIO Signal Timing 1247 33.3.12 Electrical Characteristics. 1248 33.3.13 HSPI Module Signal Timing. 1251 33.3.14 Electrical Characteristics. 1252 33.3.15 Electrical Characteristics. 1254 33.3.16 Module Signal Timing 1258 33.3.17 MMCIF Module Signal Timing 1258 33.3.18 LCDC Module Signal Timing. 1260 33.3.19 Interface Module Signal Timing. 1261 33.3.20 Interface Module Signal Timing 1262 33.4 Converter Characteristics 1264 33.5 Characteristic Test Conditions. 1265 33.6 Change Delay Time Based Load Capacitance 1266
Appendix
1267
Package Dimensions 1267 Mode Settings 1268 Functions 1270 States. 1270 Handling Unused Pins 1279 Synchronous DRAM Address Multiplexing Tables. 1280 Instruction Prefetching Side Effects 1291 Power-On Power-Off Procedures. 1292 Version registers 1293
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Figures
Section Overview Figure SH7760 Block Diagram Figure SH7760 Arrangement.11 Section Figure Figure Figure Figure Figure Section Figure Figure Figure Figure Section Figure Figure Figure Programming Model Data Formats Register Configuration Each Processing Mode General Registers Data Formats Memory.38 Processing State Transitions.39 Floating-Point Unit (FPU) Format Single-Precision Floating-Point Number.41 Format Double-Precision Floating-Point Number Single-Precision Pattern Floating-Point Registers Pipelining Basic Pipelines Instruction Execution Patterns.75 Examples Pipelined Execution.86
Section Memory Management Unit (MMU) Figure Role .101 Figure Physical Address Space MMUCR) .102 Figure Area.103 Figure External Memory Space .104 Figure Virtual Address Space MMUCR).106 Figure UTLB Configuration .115 Figure Relationship between Page Size Address Format.116 Figure ITLB Configuration.118 Figure Flowchart Memory Access Using UTLB.119 Figure 6.10 Flowchart Memory Access Using ITLB .120 Figure 6.11 Operation LDTLB Instruction.122 Figure 6.12 Memory-Mapped ITLB Address Array.131 Figure 6.13 Memory-Mapped ITLB Data Array .132 Figure 6.14 Memory-Mapped ITLB Data Array .133 Figure 6.15 Memory-Mapped UTLB Address Array .134 Figure 6.16 Memory-Mapped UTLB Data Array 1.135 Figure 6.17 Memory-Mapped UTLB Data Array 2.136 Section Caches Figure Configuration Operand Cache.139
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Figure Configuration Instruction Cache .140 Figure Configuration Write-Back Buffer .148 Figure Configuration Write-Through Buffer Figure Memory-Mapped Address Array.152 Figure Memory-Mapped Data Array .153 Figure Memory-Mapped Address Array .154 Figure Memory-Mapped Data Array.155 Figure Memory-Mapped Address Array.157 Figure 7.10 Memory-Mapped Data Array .158 Figure 7.11 Memory-Mapped Address Array .159 Figure 7.12 Memory-Mapped Data Array.160 Figure 7.13 Store Queue Configuration.161 Section Exceptions Figure Instruction Execution Exception Handling .171 Figure Example General Exception Acceptance Order .172 Section Figure Figure Figure Interrupt Controller (INTC) Block Diagram INTC.204 Example Interrupt Connection.218 Interrupt Operation Flowchart .226
Section State Controller (BSC) Figure 10.1 Block Diagram BSC.231 Figure 10.2 Correspondence between Virtual Address Space Off-chip Memory Space.234 Figure 10.3 Off-chip Memory Space Allocation .236 Figure 10.4 Example Sampling Timing .253 Figure 10.5 Write RTCSR, RTCNT, RTCOR, RFCR.279 Figure 10.6 Basic Timing SRAM Interface.292 Figure 10.7 Example 32-Bit Data Width SRAM Connection .293 Figure 10.8 Example 16-Bit Data Width SRAM Connection .294 Figure 10.9 Example 8-Bit Data Width SRAM Connection .294 Figure 10.10 SRAM Interface Wait Timing (Software Wait Only).295 Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion Signal) .296 Figure 10.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting; 011, 10).297 Figure 10.13 DCK, BS2, Timing when Reading SRAM Interface (DCKDR H'0002, A1RDH A1H[1:0] WCR3, CSH[1:0] WCR4 Three Wait Cycles) .298 Figure 10.14 DCK, BS2, Timing when Writing SRAM Interface (DCKDR H'0002, A1RDH A1H[1:0] WCR3, CSH[1:0] WCR4 Three Wait Cycles) .299 Figure 10.15 Connection Example Synchronous DRAM with 32-Bit Data Width (Area 3).301
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Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26
Basic Timing Synchronous DRAM Burst Read .304 Basic Timing Synchronous DRAM Single Read.305 Basic Timing Synchronous DRAM Burst Write .306 Basic Timing Synchronous DRAM Single Write .308 Burst Read Timing .310 Burst Read Timing (RAS Down, Same Address) .311 Burst Read Timing (RAS Down, Different Addresses) .312 Burst Write Timing.313 Burst Write Timing (Same Address).314 Burst Write Timing (Different Addresses).315 Burst Read Cycle Different Bank Address From Preceding Burst Read Cycle .316 Figure 10.27 Auto-Refresh Operation .318 Figure 10.28 Synchronous DRAM Auto-Refresh Timing .318 Figure 10.29 Synchronous DRAM Self-Refresh Timing .320 Figure 10.30(1) Synchronous DRAM Mode Write Timing (PALL) .322 Figure 10.30(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) .323 Figure 10.31 Basic Timing Burst Read from Synchronous DRAM (Burst Length 8).325 Figure 10.32 Basic Timing Burst Write Synchronous DRAM .326 Figure 10.33 Burst Basic Access Timing .328 Figure 10.34 Burst Wait Access Timing.329 Figure 10.35 Burst Wait Access Timing.330 Figure 10.36 Example PCMCIA Interface .334 Figure 10.37 Basic Timing PCMCIA Memory Card Interface .335 Figure 10.38 Wait Timing PCMCIA Memory Card Interface .336 Figure 10.39 PCMCIA Space Allocation .337 Figure 10.40 Basic Timing PCMCIA Card Interface .338 Figure 10.41 Wait Timing PCMCIA Card Interface.339 Figure 10.42 Dynamic Sizing Timing PCMCIA Card Interface .340 Figure 10.43 Example 32-Bit Data Width Connection .341 Figure 10.44 Interface Timing (Single Read Cycle, External Wait).342 Figure 10.45 Interface Timing (Single Read, External Wait Inserted) .343 Figure 10.46 Interface Timing (Single Write Cycle, External Wait).344 Figure 10.47 Interface Timing (Single Write, External Wait Inserted) Figure 10.48 Interface Timing (Burst Read Cycle, External Wait, 32-Bit Width, 32-Byte Data Transfer).346 Figure 10.49 Interface Timing (Burst Read Cycle, External Wait Control, 32-Bit Width, 32-Byte Data Transfer).346 Figure 10.50 Interface Timing (Burst Write Cycle, External Wait, 32-Bit Width, 32-Byte Data Transfer).347 Figure 10.51 Interface Timing (Burst Write Cycle, External Wait Control, 32-Bit Width, 32-Byte Data Transfer).347
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Figure 10.52 Interface Timing (Burst Read Cycle, External Wait, 32-Bit Width, 64-Bit Data Transfer) .348 Figure 10.53 Interface Timing (Burst Read Cycle, External Wait Inserted, 32-Bit Width, 64-Bit Data Transfer).349 Figure 10.54 Interface Timing (Burst Write Cycle, External Wait, 32-Bit Width, 64-Bit Data Transfer) .350 Figure 10.55 Interface Timing (Burst Write Cycle, External Wait Inserted, 32-Bit Width, 64-Bit Data Transfer).351 Figure 10.56 Example 32-Bit Data Width Byte Control SRAM Figure 10.57 Byte Control SRAM Basic Read Cycle Wait).353 Figure 10.58 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) .354 Figure 10.59 Byte Control SRAM Basic Read Cycle (One Internal Wait External Wait).355 Figure 10.60 Wait Cycles between Access Cycles .357 Figure 10.61 Arbitration Sequence .359 Section Direct Memory Access Controller (DMAC) Figure 11.1 DMAC Block Diagram.362 Figure 11.2 DMABRG Block Diagram .363 Figure 11.3 DMAC Transfer Flowchart .405 Figure 11.4 Round Robin Mode .409 Figure 11.5 Example Changes Priority Order Round Robin Mode.411 Figure 11.6 Data Flow Single Address Mode.412 Figure 11.7 Transfer Timing Single Address Mode .413 Figure 11.8 Operation Dual Address Mode .414 Figure 11.9 Example Transfer Timing Dual Address Mode .415 Figure 11.10 Example Transfer Cycle Steal Mode .416 Figure 11.11 Example Transfer Burst Mode.416 Figure 11.12 Handling with DMAC Channels Operating .420 Figure 11.13 Dual Address Mode/Cycle Steal Mode External Request 2-Channel Mode External External Bus/DREQ (Level Detection), DACK (Read Cycle).423 Figure 11.14 Dual Address Mode/Cycle Steal Mode DMABRG Mode External External Bus/DREQ (Level Detection), DACK (Read Cycle).424 Figure 11.15 Dual Address Mode/Cycle Steal Mode External Request 2-Channel Mode External External Bus/DREQ (Edge Detection), DACK (Read Cycle).425 Figure 11.16 Dual Address Mode/Cycle Steal Mode DMABRG Mode External External Bus/DREQ (Edge Detection), DACK (Read Cycle) .426 Figure 11.17 Dual Address Mode/Burst Mode External Request 2-Channel Mode External External Device/DREQ (Level Detection), DACK (Read Cycle).427 Figure 11.18 Dual Address Mode/Burst Modes DMABRG Mode External External Bus/ DREQ (Level Detection), DACK (Read Cycle).428
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Figure 11.19 Dual Address Mode/Burst Mode External Request 2-Channel Mode External External Bus/DREQ (Edge Detection), DACK (Read Cycle) .429 Figure 11.20 Dual Address Mode/Burst Modes DMABRG Mode External External Bus/DREQ (Edge Detection), DACK (Read Cycle) .430 Figure 11.21 Single Address Mode/Cycle Steal Mode External Request 2-Channel Mode External External Device/ DREQ (Level Detection).431 Figure 11.22 Single Address Mode/Cycle Steal Mode External Request 2-Channel Mode External External Device/ DREQ (Level Detection).432 Figure 11.23 Single Address Mode/Cycle Steal Mode External Request 2-Channel Mode External External Device/ DREQ (Edge Detection).433 Figure 11.24 Single Address Mode/Cycle Steal Mode DMABRG Mode External External Device/ DREQ (Edge Detection).434 Figure 11.25 Single Address Mode/Burst Mode External Request 2-Channel Mode External External Device/ DREQ (Level Detection).435 Figure 11.26 Single Address Mode/Burst Mode DMABRG Mode External External Device/ DREQ (Level Detection) .436 Figure 11.27 Single Address Mode/Burst Mode External Request 2-Channel Mode External External Device/ DREQ (Edge Detection).437 Figure 11.28 Single Address Mode/Burst Mode DMABRG Mode External External Device/ DREQ (Edge Detection).438 Figure 11.29 Single Address Mode/Burst Mode External Request 2-Channel Mode External Device External Bus/ DREQ (Level Detection)/32 Byte Block Transfer (Bus Width: bits, SDRAM: write) .439 Figure 11.30 Single Address Mode/Burst Mode DMABRG Mode External Device External Bus/ DREQ (Level Detection)/32 Byte Block Transfer (Bus Width: bits, SDRAM: write) .440 Figure 11.31 Configuration HAC/SSI .449 Figure 11.32 Example Transfer Operation Flow .451 Figure 11.33 Example Transfer Operation Flow .452 Figure 11.34 Forced Termination Resume Procedures Audio Transfer .454 Figure 11.35 HAC/SSI Transfer Operation Flow Using Interrupt.455 Figure 11.36 8-Bit Data Transfer .457 Figure 11.37 16-Bit Data Transfer HAC/SSI .457 Figure 11.38 Example LCDC Data Transfer Flow.458 Figure 11.39 Transfer Flow Shared Memory Synchronous DRAM.459 Figure 11.40 Arrangement Data Alignment.460 Section Figure 12.1 Figure 12.2 Figure 12.3 Clock Pulse Generator (CPG) Block Diagram .466 Points Attention when Using Crystal Resonator.479 Points Attention when Using Oscillation Circuit.480
Section Watchdog Timer (WDT) Figure 13.1 Block Diagram .481
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Figure 13.2 Writing WTCNT WTCSR.485 Section Power-Down Modes Figure 14.1 STATUS Output Power-On Reset.500 Figure 14.2 STATUS Output Manual Reset.500 Figure 14.3 STATUS Output Sequence Software Standby Interrupt .501 Figure 14.4 STATUS Output Sequence Software Standby Power-On Reset .501 Figure 14.5 STATUS Output Sequence Software Standby Manual Reset .502 Figure 14.6 STATUS Output Sequence Sleep Interrupt.502 Figure 14.7 STATUS Output Sequence Sleep Power-On Reset .503 Figure 14.8 STATUS Output Sequence Sleep Manual Reset.503 Figure 14.9 STATUS Output Sequence Deep Sleep Interrupt .504 Figure 14.10 STATUS Output Sequence Deep Sleep Power-On Reset .504 Figure 14.11 STATUS Output Sequence Deep Sleep Manual Reset .505 Figure 14.12 Hardware Standby Mode Timing (When Normal Operation) .506 Figure 14.13 Hardware Standby Mode Timing (When Operation) .507 Figure 14.14 Timing when Power .507 Section Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Timer Unit (TMU) Block Diagram .510 Example Count Operation Setting Procedure.517 TCNT Auto-Reload Operation .518 Count Timing when Operating Internal Clock .518 Count Timing when Operating External Clock .519 Operation Timing when Using Input Capture Function .520
Section Timer/Counter (CMT) Figure 16.1 Block Diagram CMT.523 Figure 16.2 Edge Detection .536 Figure 16.3 32-Bit Timer Mode: Input Capture.536 Figure 16.4 Output Assertion Period .537 Figure 16.5 32-Bit Timer Mode: Output Compare .537 Figure 16.6 16-Bit Timer Mode: Input Capture.538 Figure 16.7 16-Bit Timer Mode: Output Compare .539 Figure 16.8 Updown-Counter Mode.540 Figure 16.9 Up-Counter Mode.540 Figure 16.10 Up-Counter with Capture Mode .541 Figure 16.11 Rotary Mode.542 Section Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Serial Communication Interface with FIFO (SCIF) Block Diagram SCIF.545 SCIF_RTS (Only Channels 2).546 SCIF_CTS (Only Channels 2).546 SCIF_CLK .547 SCIF_TXD .547
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Figure 17.6 SCIF_RXD Pin.548 Figure 17.7 Data Format Asynchronous Communication (Example with 8-Bit Data, Parity, Stop Bits) .578 Figure 17.8 Sample SCIF Initialization Flowchart .581 Figure 17.9 Sample Serial Transmission Flowchart .582 Figure 17.10 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, Stop Bit) .583 Figure 17.11 Sample Operation Using Modem Control (SCIF_CTS) (Only Channels 2).584 Figure 17.12 Sample Serial Reception Flowchart .585 Figure 17.12 Sample Serial Reception Flowchart .586 Figure 17.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, Stop Bit) .587 Figure 17.14 Sample Operation Using Modem Control (SCIF_RTS) (Only Channels 2).588 Figure 17.15 Data Format Clocked Synchronous Communication .588 Figure 17.16 Sample SCIF Initialization Flowchart .590 Figure 17.17 Sample Serial Transmission Flowchart .591 Figure 17.18 Sample SCIF Transmission Operation Clocked Synchronous Mode .592 Figure 17.19 Sample Serial Reception Flowchart .593 Figure 17.19 Sample Serial Reception Flowchart .594 Figure 17.20 Sample SCIF Reception Operation Clocked Synchronous Mode .594 Figure 17.21 Sample Simultaneous Serial Transmission Reception Flowchart.595 Figure 17.22 Receive Data Sampling Timing Asynchronous Mode .599 Figure 17.23 Example Synchronization Clock Transfer DMAC.600 Section Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Card Module (SIM) Block Diagram .602 Data Format Used Smart Card Interface.622 Examples Initial Character Waveforms .624 Example Initialization Flow .626 Example Transmission Processing.627 Example Reception Processing .628 Received Data Sampling Timing Smart Card Mode .631 Retransmission Smart Card Interface Reception Mode.632 Retransmission Standby Mode (clock stopped) when Smart Card Interface Transmission Mode.632 Figure 18.10 TEIE Timing .633 Figure 18.11 Procedure Stopping Clock Restarting.634 Figure 18.12 Example Smart Card Interface Connections .635 Section Hitachi Interface Figure 19.1 Interface Block Diagram .638 Figure 19.2 Timing.663
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Figure 19.3 Master Data Transmit format .664 Figure 19.4 Master Data Receive format .664 Figure 19.5 Combination Transfer Format Master Transfer .665 Figure 19.6 10-Bit Address Data Transfer Format .665 Figure 19.7 10-Bit Address Data Receive Format .666 Figure 19.8 10-Bit Address Transmit/Receive Combination Format .666 Figure 19.9 Data Transfer Mode Timing Chart .668 Figure 19.10 Data Receive Mode Timing Chart.669 Figure 19.11 Operational Example One-byte Data Transmission .676 Figure 19.12 Operational Example Two-byte Data Transmission .677 Figure 19.13 Operational Example Three-byte Data Transmission .678 Figure 19.14 Operation Example Four More Byte Data Transmission.678 Section Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Figure 20.8 Serial Sound Interface (SSI) Module Block Diagram Module .682 Philips Format (with Padding).697 Philips Format (with Padding).698 Sony Format (with Serial Data First, Followed Padding Bits) .698 Matsushita Format (with Padding Bits First, Followed Serial Data) .699 Multichannel Format Channels, Padding) .701 Multichannel Format Channels with High Padding).701 Multichannel Format Channels, with Padding Bits First, Followed Serial Data, with Padding) .702 Figure 20.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length).702 Figure 20.10 Inverted Clock .703 Figure 20.11 Inverted Word Select.703 Figure 20.12 Inverted Padding Polarity .703 Figure 20.13 Padding Bits First, Followed Serial Data, with Delay .704 Figure 20.14 Padding Bits First, Followed Serial Data, without Delay .704 Figure 20.15 Serial Data First, Followed Padding Bits, without Delay.704 Figure 20.16 Parallel Right Aligned with Delay.705 Figure 20.17 Mute Enabled .705 Figure 20.18 Compressed Data Format, Slave Transmitter, Burst Mode Disabled .706 Figure 20.19 Compressed Data Format, Slave Transmitter, Burst Mode Enabled .706 Figure 20.20 Transition Diagram between Operation Modes.708 Figure 20.21 Transmission Using Controller .709 Figure 20.22 Transmission using Interrupt Data Flow Control .710 Figure 20.23 Reception using Controller.712 Figure 20.24 Reception using Interrupt Data Flow Control.713 Section Host Module (USB) Figure 21.1 Block Diagram Host Module.716 Figure 21.2 Memory Shared Memory .754
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Figure 21.3 Read Operation .755 Figure 21.4 Example Transfer Failure.755 Figure 21.5 Example RHSC interrupt handling.756 Section Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 Figure 22.8 Figure 22.9 Section Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Section Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Figure 25.5 Figure 25.6 Figure 25.7 Section Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Figure 26.5 Figure 26.6 Figure 26.7 Figure 26.8 Hitachi Controller Area Network (HCAN2) Block Diagram HCAN2 Module.758 HCAN2 Memory Map.761 Mailbox Structure .764 Acceptance Filter.769 Reset Sequence.813 Transmission Request.814 Internal Arbitration Transmission.815 Message Receive Sequence .817 Changing Receive Changing Receive Transmit .820 Hitachi Serial Protocol Interface (HSPI) Block Diagram HSPI.824 Operational Flowchart .836 Timing Conditions when 0.838 Timing Conditions when 1.839 Hitachi Audio Codec Interface (HAC) Block Diagram .882 AC97 Frame Slot Structure .898 Initialization Sequence .902 Sample Flowchart Off-Chip Codec Register Write .903 Sample Flowchart Off-Chip Codec Register Read .904 Sample Flowchart Off-Chip Codec Register Read (cont).905 Sample Flowchart Off-Chip Codec Register Read (cont).906 Multimedia Card Interface (MMCIF) Block Diagram MMCIF .910 Access Example .939 Example Command Sequence Commands Requiring Command Response.943 Example Operational Flow Commands Requiring Command Response.944 Example Command Sequence Commands without Data Transfer Data Busy State).945 Example Command Sequence Commands without Data Transfer (with Data Busy State) .946 Example Operational Flow Commands without Data Transfer.947 Example Command Sequence Commands with Read Data (Block Size FIFO Size) .949
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Figure 26.9 Example Command Sequence Commands with Read Data (Block Size FIFO Size) .950 Figure 26.10 Example Command Sequence Commands with Read Data (Multiblock Transfer) .951 Figure 26.11 Example Command Sequence Commands with Read Data (Stream Transfer).952 Figure 26.12 Example Operational Flow Commands with Read Data (Single Block Transfer) .953 Figure 26.13 Example Operational Flow Commands with Read Data (Multiblock Transfer) .954 Figure 26.14 Example Operational Flow Commands with Read Data (Stream Transfer).955 Figure 26.15 Example Command Sequence Commands with Write Data (Block Size FIFO Size) .957 Figure 26.16 Example Command Sequence Commands with Write Data (Block Size FIFO Size) .958 Figure 26.17 Example Command Sequence Commands with Write Data (Multiblock Transfer) .959 Figure 26.18 Example Command Sequence Commands with Write Data (Stream Transfer).960 Figure 26.19 Example Operational Flow Commands with Write Data (Single Block Transfer) .961 Figure 26.20 Example Operational Flow Commands with Write Data (Multiblock Transfer) .962 Figure 26.21 Example Operational Flow Commands with Write Data (Stream Transfer).963 Figure 26.22 Example Read Sequence Flow .966 Figure 26.23 Example Write Sequence Flow .967 Section Multifunctional Interface (MFI) Figure 27.1 block diagram .970 Figure 27.2 Differences Settings .977 Figure 27.3 Example Connections.985 Figure 27.4 Basic Timing 68-Series Interface.986 Figure 27.5 Basic Timing 80-Series Interface .987 Figure 27.6 Writing MFIIDX Reading from MFIGSR.988 Figure 27.7 Register Settings.988 Figure 27.8 Continuous Data Writing MFRAM (8-Bit Width, MFISCR.SCRMD2 .989 Figure 27.9 Continuous Data Reading from MFRAM (8-Bit Width, MFISCR.SCRMD2 .989 Section Hitachi User Debug Interface (H-UDI) Figure 28.1 H-UDI Block Diagram .992
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Figure 28.2 Controller State Transitions .1009 Figure 28.3 H-UDI Reset.1010 Section Figure 29.1 Figure 29.2 Figure 29.3 Figure 29.4 Figure 29.5 Figure 29.6 Figure 29.7 Figure 29.8 Figure 29.9 Converter (ADC) Converter Block Diagram.1014 Example Converter Operation (Single Mode, Channel Selected) .1022 Example Converter Operation (Multi Mode, Three Channels Selected) .1024 Example Converter Operation (Scan Mode, Three Channels Selected) .1026 Timing Data Write when Four Channels Selected Multi Mode.1027 External Trigger Input Timing .1029 Definitions Conversion Accuracy .1031 Example Analog Input Protection Circuit.1032 Analog Input Equivalent Circuit .1032
Section Controller (LCDC) Figure 30.1 LCDC Block Diagram.1036 Figure 30.2 Valid Display Retrace Period.1063 Figure 30.3 Color-Palette Data Format.1065 Figure 30.4 Power-Supply Control Sequence States Module .1070 Figure 30.5 Power-Supply Control Sequence States Module .1070 Figure 30.6 Power-Supply Control Sequence States Module .1071 Figure 30.7 Power-Supply Control Sequence States Module .1071 Figure 30.8 Clock Data Signal Example .1077 Figure 30.9 Clock Data Signal Example .1077 Figure 30.10 Clock Data Signal Example .1078 Figure 30.11 Clock Data Signal Example .1078 Figure 30.12 Clock Data Signal Example .1079 Figure 30.13 Clock Data Signal Example .1080 Figure 30.14 Clock Data Signal Example .1080 Figure 30.15 Clock Data Signal Example .1081 Figure 30.16 Clock Data Signal Example .1081 Figure 30.17 Clock Data Signal Example .1082 Figure 30.18 Clock Data Signal Example .1083 Figure 30.19 Clock Data Signal Example .1084 Figure 30.20 Clock Data Signal Example .1085 Figure 30.21 Clock Data Signal Example .1086 Figure 30.22 Clock Data Signal Example .1087 Section User Break Controller (UBC) Figure 31.1 Block Diagram .1090 Figure 31.2 User Break Debug Support Function Flowchart.1110
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Section Electrical Characteristics Figure 33.1 EXTAL Clock Input Timing .1200 Figure 33.2 CKIO Clock Output Timing .1201 Figure 33.3 CKIO Clock Output Timing .1201 Figure 33.4 Clock Output Timing (1).1201 Figure 33.5 Clock Output Timing (2).1201 Figure 33.6 Power-On Oscillation Settling Time (1).1202 Figure 33.7 Standby Return Oscillation Settling Time (Return RESET MRESET) (1).1202 Figure 33.8 Power-On Oscillation Settling Time (2).1203 Figure 33.9 Standby Return Oscillation Settling Time (Return RESET MRESET) (2).1203 Figure 33.10 Standby Return Oscillation Settling Time (Return NMI).1204 Figure 33.11 Standby Return Oscillation Settling Time (Return IRL3 IRL0).1204 Figure 33.12 Synchronization Settling Time Case RESET, MRESET Interrupt .1204 Figure 33.13 Synchronization Settling Time Case Interrupt.1205 Figure 33.14 pins Setup/Hold Timing .1205 Figure 33.15 Control Signal Timing .1206 Figure 33.16 Drive Timing Standby Mode .1207 Figure 33.17 SRAM Cycle: Basic Cycle Wait).1209 Figure 33.18 SRAM Cycle: Basic Cycle (One Internal Wait).1210 Figure 33.19 SRAM Cycle: Basic Cycle (One Internal Wait External Wait).1211 Figure 33.20 SRAM Cycle: Basic Cycle Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .1212 Figure 33.21 Burst Cycle Wait).1213 Figure 33.22 Burst Cycle (1st Data: Internal Wait External Wait 2nd/3rd/4th Data: Internal Wait).1214 Figure 33.23 Burst Cycle Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .1215 Figure 33.24 Burst Cycle (One Internal Wait External Wait) .1216 Figure 33.25 Synchronous DRAN Auto-Precharge Read Cycle: Single (RCD[1:0]=01, Latency=3, TPC[2:0]=011) .1217 Figure 33.26 Synchronous DRAM Auto-Precharge Read Cycle: Burst (RCD[1:0]=01, Latency=3, TPC[2:0]=011) .1218 Figure 33.27 Synchronous DRAM Normal Read Cycle: READ Commands, Burst (RCD[1:0]=01, Latency=3) .1219 Figure 33.28 Synchronous DRAM Normal Read Cycle: READ Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, Latency=3) .1220 Figure 33.29 Synchronous DRAM Normal Read Cycle: READ Command, Burst (CAS Latency=3).1221 Figure 33.30 Synchronous DRAM Auto-Precharge Write Cycle: Single (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) .1222
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Figure 33.31 Synchronous DRAM Auto-Precharge Write Cycle: Burst (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) .1223 Figure 33.32 Synchronous DRAM Normal Write Cycle: ACT+WRITE Commands, Burst (RCD[1:0]=01, TRWL[2:0]=010).1224 Figure 33.33 Synchronous DRAM Normal Write Cycle: PRE+ACT+WRITE Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) .1225 Figure 33.34 Synchronous DRAM Normal Write Cycle: WRITE Command, Burst (TRWL[2:0]=010).1226 Figure 33.35 Synchronous DRAM Cycle: Precharge Command (TPC[2:0]=001) .1227 Figure 33.36 Synchronous DRAM Cycle: Auto-Refresh (TRAS=1, TRC[2:0]=001) .1228 Figure 33.37 Synchronous DRAM Cycle: Self-Refresh (TRC[2:0]=001) .1229 Figure 33.38 Synchronous DRAM Cycle: Mode Register Setting (PALL) .1230 Figure 33.39 Synchronous DRAM Cycle: Mode Register Setting (SET) .1231 Figure 33.40 PCMCIA Memory Cycle.1232 Figure 33.41 PCMCIA Cycle .1233 Figure 33.42 PCMCIA Cycle (TED=1, TEH=1, Internal Wait, Sizing).1234 Figure 33.43 Basic Cycle: Read.1235 Figure 33.44 Basic Cycle: Write.1236 Figure 33.45 Cycle: Burst Read .1237 Figure 33.46 Cycle: Burst Write .1238 Figure 33.47 Memory Byte Control SRAM Cycle .1239 Figure 33.48 Memory Byte Control SRAM Cycle: Basic Read Cycle Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .1240 Figure 33.49 Input Timing .1241 Figure 33.50 DREQ/DRAK Timing .1242 Figure 33.51 TCLK Input Timing .1242 Figure 33.52 SCIFn_CLK Input Clock Timing .1243 Figure 33.53 SCIF Synchronous Mode Clock Timing .1243 Figure 33.54 Input Timing.1244 Figure 33.55 RESET Hold Timing .1244 Figure 33.56 H-UDI Data Transfer Timing .1245 Figure 33.57 Break Timing .1245 Figure 33.58 Timing .1246 Figure 33.59 Timing .1246 Figure 33.60 HCAN2 Timing .1247 Figure 33.61 GPIO Timing .1247 Figure 33.62 Block Diagram Buffer .1248 Figure 33.63 Interface Module Signal Timing .1250 Figure 33.64 HSPI Data Output/Input Timing.1251 Figure 33.65 Input Voltage (VIH, VIL) .1252 Figure 33.66 Output (VOH, VOL) .1252
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Figure 33.67 Differential Input Sensitivity (VDI), Differential common mode range (VCM) .1252 Figure 33.68 Load Condition Characteristics (Full speed) .1253 Figure 33.69 Load Condition Characteristics (Low speed) .1254 Figure 33.70 .1254 Figure 33.71 VCRS .1254 Figure 33.72 Characteristics Series Bus.1255 Figure 33.73 Characteristics Series (Read).1256 Figure 33.74 Characteristics Series (Write) .1257 Figure 33.75 Module Signal Timing.1258 Figure 33.76 MMCIF Transmit Timing.1259 Figure 33.77 MMCIF Receive Timing (rising edge sampling) .1259 Figure 33.78 MMCIF Receive Timing (falling edge sampling) .1259 Figure 33.79 LCDC Module Signal Timing .1260 Figure 33.80 Cold Reset Timing .1261 Figure 33.81 Cold Reset Timing .1261 Figure 33.82 Clock Input Timing .1261 Figure 33.83 Interface Module Signal Timing .1262 Figure 33.84 Clock Input/Output Timing .1262 Figure 33.85 Transmit Timing (1).1263 Figure 33.86 Transmit Timing .1263 Figure 33.87 Receive Timing .1263 Figure 33.88 Receive Timing .1263 Figure 33.89 Output Load Circuit.1265 Figure 33.90 Load Capacitance-Delay Time .1266 Appendix Figure Instruction Prefetch .1261 Figure Power-On Power-Off Procedures .1262
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Tables
Section Overview Table Configuration.12 Table Functions Table Functions (1).22 Table Functions (2).23 Table Functions (3).24 Table Functions Section Programming Model Table Initial Register Values.31 Section Floating-Point Unit (FPU) Table Floating-Point Number Formats Parameters Table Floating-Point Ranges.43 Table Allocation Exception Handling Section Table Table Table Table Table Table Table Table Table Table 4.10 Table 4.11 Table 4.12 Instruction Addressing Modes Effective Addresses Notation Used Instruction List Fixed-Point Transfer Instructions Arithmetic Operation Instructions.63 Logic Operation Instructions.65 Shift Instructions Branch Instructions System Control Instructions.68 Floating-Point Single-Precision Instructions Floating-Point Double-Precision Instructions Floating-Point Control Instructions.71 Floating-Point Graphics Acceleration Instructions
Section Pipelining Table Instruction Groups.80 Table Parallel-Executability.83 Table Execution Cycles Section Memory Management Unit (MMU) Table Register Configuration .108 Table Register Configuration .109 Section Caches Table Cache Features (EMODE .137 Table Cache Features (EMODE .137 Table Store Queue Features .138
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Table Table
Register Configuration .141 Register Configuration .141
Section Exceptions Table Exception Sources Priorities .167 Table Register Configuration .174 Table Register Configuration .174 Section Interrupt Controller (INTC) Table Configuration.205 Table Register Configuration .205 Table Register Configuration .206 Table Interrupt Request Sources IPRA IPRD .208 Table Interrupt Request Sources INTPRI00 INTPRI0C*1 .209 Table Interrupt Request Sources Assignments Each Register .212 Table Interrupt Request Sources Assignments Each Register .213 Table IRL3 IRL0 Pins Interrupt Levels.218 Table Interrupt Exception Handling Sources Priority Order .221 Table Interrupt Response Time .228 Section State Controller (BSC) Table 10.1 Configuration.232 Table 10.2 Off-chip Memory Space .235 Table 10.3 Correspondence between Off-chip Pins (MD4 MD3) Width .236 Table 10.4 PCMCIA Interface Features.237 Table 10.5 PCMCIA Support Interfaces .238 Table 10.6 Register Configuration .241 Table 10.6 Register Configuration .242 Table 10.7 Idle Insertion between Accesses .256 Table 10.8 Interface Setting .263 Table 10.9 32-Bit Off-chip Device/Big-Endian Access Data Alignment.281 Table 10.10 16-Bit Off-chip Device/Big-Endian Access Data Alignment.282 Table 10.11 8-Bit Off-chip Device/Big-Endian Access Data Alignment.283 Table 10.12 32-Bit Off-Chip Device/Little-Endian Access Data Alignment.284 Table 10.13 16-Bit Off-Chip Device/Little-Endian Access Data Alignment.285 Table 10.14 8-Bit Off-Chip Device/Little-Endian Access Data Alignment.286 Table 10.15 Example Correspondence between This Synchronous DRAM Address Pins (32-Bit Width, AMX2 AMX0 000, AMXEXT 0).302 Table 10.16 Availability Pipelined Access Cycles .317 Table 10.17 Relationship between Address When Using PCMCIA Interface .332 Section Direct Memory Access Controller (DMAC) Table 11.1 Configuration.364 Table 11.2 Register Configuration .365
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Table 11.2 Register Configuration .368 Table 11.3 External Request 2-Channel Mode (DMS[1:0] DMAOR .380 Table 11.4 DMABRG Mode (DMS[1:0] DMAOR 11).381 Table 11.5 Data Alignment Receive Slot Data External .400 Table 11.5 Data Alignment Transmit Slot Data External Bus.400 Table 11.6 Selecting External Request Mode with Bits.406 Table 11.7 Supported Transfers.412 Table 11.8 Relationship between Transfer Type, Request Mode, Mode .417 Table 11.9 External Request Transfer Sources Destinations External Request 2-Channel Mode .418 Table 11.9 External Request Transfer Sources Destinations DMABRG Mode.419 Table 11.10 DMAC Interrupt-Request Codes.444 Table 11.11 Conditions Transfer between External Memory External Device with DACK, Corresponding Register Settings .445 Table 11.11 Conditions Transfer between External Memory External Device with DACK, Corresponding Register Settings .446 Table 11.12 Data Alignment between Peripheral Bridge Bus.461 Table 11.13 Data Alignment between External Bridge Bus.462 Section Clock Pulse Generator (CPG) Table 12.1 Configuration Function Oscillation Circuit.468 Table 12.2 Clock Operating Modes .469 Table 12.3 FRQCR Settings Clock Frequencies.470 Table 12.4 Register Configuration .471 Table 12.4 Register Configuration .471 Section Watchdog Timer (WDT) Table 13.1 Register Configuration .482 Table 13.1 Register Configuration .482 Section Power-Down Modes Table 14.1 Status Power-Down Modes.490 Table 14.2 Configuration.491 Table 14.3 Register Configuration .491 Table 14.3 Register Configuration .492 Table 14.4 Assignment CLKSTP00 CLKSTPCLR00 .495 Section Timer Unit (TMU) Table 15.1 Configuration.510 Table 15.2 Register Configuration .511 Table 15.2 Register Configuration .512 Table 15.3 Interrupt Sources .520 Section Timer/Counter (CMT) Table 16.1 Configuration.524
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Table 16.2 Table 16.2
Register Configuration .524 Register Configuration .525
Section Serial Communication Interface with FIFO (SCIF) Table 17.1 Configuration.548 Table 17.2 Register Configuration .549 Table 17.2 Register Configuration .550 Table 17.3 SCSMR Settings .567 Table 17.4 SCSMR Settings Serial Transfer Format Selection.577 Table 17.5 SCSMR SCSCR Settings SCIF Clock Source Selection .577 Table 17.6 Serial Transfer Formats (Asynchronous Mode).579 Table 17.7 SCIF Interrupt Sources.597 Section Card Module (SIM) Table 18.1 Configuration.602 Table 18.2 Register Configuration .603 Table 18.2 Register Configuration .604 Table 18.3 Register Settings Smart Card Interface.623 Table 18.4 Example Rates (bits/s) SIBRR Settings (Pck 33.3 MHz, SISMPL 371).625 Table 18.5 Smart Card Interface Interrupt Sources.629 Section Hitachi Interface Table 19.1 Interface.638 Table 19.2 Register Configuration .639 Table 19.2 Register Configuration .640 Table 19.3 SCGD Recommended Values.653 Table 19.4 Legend Data Format .664 Section Serial Sound Interface (SSI) Module Table 20.1 Configuration.682 Table 20.2 Register Configuration .683 Table 20.2 Register Configuration .683 Table 20.3 Formats Module.696 Table 20.4 Number Padding Bits Each Valid Configuration .700 Section Host Module (USB) Table 21.1 Configuration.717 Table 21.2 Register Configuration .718 Table 21.2 Register Configuration .719 Section Hitachi Controller Area Network (HCAN2) Table 22.1 Configuration.760 Table 22.2 Address map.763 Table 22.3 Settings Mailbox Functions .768
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Table 22.4 Table 22.4 Table 22.5
Register Configuration .770 Register Configuration .774 TSEG1 TSEG2 Settings .789
Section Hitachi Serial Protocol Interface (HSPI) Table 23.1 Configuration.824 Table 23.2 Register Configuration .825 Table 23.2 Register Configuration .825 Section Function Controller (PFC) Table 24.1 Multiplexed Pins Controlled Port Control Registers.841 Table 24.2 Register Configuration .844 Table 24.2 Register Configuration .845 Section Hitachi Audio Codec Interface (HAC) Table 25.1 Configuration.882 Table 25.2 Register Configuration .883 Table 25.2 Register Configuration .884 Table 25.3 AC97 Transmit Frame Structure.898 Table 25.4 AC97 Receive Frame Structure .899 Section Multimedia Card Interface (MMCIF) Table 26.1 Configuration.910 Table 26.2 Register Configuration .911 Table 26.2 Register Configuration .912 Table 26.3 Correspondence between Commands Settings CMDTYR RSPTYR.917 Table 26.4 CMDR Configuration .920 Table 26.5 Correspondence between Command Response Byte Number RSPR.922 Table 26.6 Card States which Command Sequence Halted.925 Table 26.7 MMCIF Interrupt Sources.964 Section Multifunctional Interface (MFI) Table 27.1 Configuration.971 Table 27.2 Register Configuration .972 Table 27.2 Register Configuration .973 Table 27.3 Operations .984 Table 27.4 Access MFIIDX MFIGSR .984 Table 27.5 Memory .985 Section Hitachi User Debug Interface (H-UDI) Table 28.1 Configuration.993 Table 28.2 Commands Supported Boundary-Scan Controller.996 Table 28.3 SDBSR Configuration.997 Table 28.3 SDBSR Configuration.998 Table 28.3 SDBSR Configuration.999
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Table 28.3 SDBSR Configuration.1000 Table 28.3 SDBSR Configuration.1001 Table 28.3 SDBSR Configuration.1002 Table 28.3 SDBSR Configuration.1003 Table 28.3 SDBSR Configuration.1004 Table 28.3 SDBSR Configuration.1005 Table 28.4 Register Configuration .1005 Table 28.4 Register Configuration .1006 Table 28.4 Register Configuration .1006 Section Converter (ADC) Table 29.1 Configuration.1015 Table 29.2 Register Configuration .1016 Table 29.2 Register Configuration .1016 Table 29.3 Analog Input Channels Corresponding Data Registers .1017 Table 29.4 Conversion Time .1028 Table 29.5 Relationship between Clock Division Ratio Usable Input Clock Frequency.1033 Section Controller (LCDC) Table 30.1 Configuration.1036 Table 30.2 Register Configuration .1037 Table 30.2 Register Configuration .1038 Table 30.3 Clock Frequency Clock Division Ratio .1040 Table 30.4 Display Resolutions when Using Display Rotation .1064 Table 30.5 Available Power-Supply Control-Sequence Periods Typical Frame Rates.1072 Table 30.6 LCDC Operating Modes .1073 Table 30.7 Module Power-Supply States .1073 Section User Break Controller (UBC) Table 31.1 Register Configuration .1091 Table 31.1 Register Configuration .1092 Section Electrical Characteristics Table 33.1 Absolute Maximum Ratings .1195 Table 33.2 Characteristics (Ta=-40 85°C) .1196 Table 33.3 Permissible Output Currents .1198 Table 33.4 Clock Timing .1198 Table 33.5 Clock Control Signal Timing .1199 Table 33.6 Control Signal Timing .1206 Table 33.7 Timing.1208 Table 33.8 INTC Module Signal Timing .1241 Table 33.9 DMAC Module Signal Timing .1241 Table 33.10 Module Signal Timing .1242
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Table 33.11 Table 33.12 Table 33.13 Table 33.14 Table 33.15 Table 33.16 Table 33.17 Table 33.18 Table 33.19 Table 33.20 Table 33.21 Table 33.22 Table 33.23 Table 33.24 Table 33.25 Table 33.26 Table 33.27 Table 33.28 Table 33.29 Table 33.30 Appendix Table Table Table Table Table Table Table
SCIF Module Signal Timing.1243 H-UDI Module Signal Timing .1244 Module Signal Timing.1246 HCAN2 Module Signal Timing .1247 GPIO Signal Timing .1247 Truth Table Buffer .1248 Characteristics .1248 Interface Module Signal Timing.1249 Schmitt characteristics .1249 HSPI Module Signal Timing.1251 characteristics .1252 characteristics .1253 Characteristics Series .1255 Characteristics Series .1256 Module Signal Timing .1258 MMCIF Module Signal Timing .1258 LCDC Module Signal Timing.1260 Interface Module Signal Timing.1261 Interface Module Signal Timing .1262 Converter Characteristics .1264 Clock Operating Modes (SH7760).1238 Area Memory Width .1238 Endian .1239 Mode/LCD Mode.1239 Clock Input.1239 States Reset, Power-Down State, Bus-Released State .1240 Register Configuration .1263
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Section Overview
This microcomputer, featuring controller, host, other peripheral functions. SuperH RISC engine Hitachi-original 32-bit RISC (Reduced Instruction Computer) microcomputer. SuperH RISC engine employs fixed-length 16-bit instruction set, allowing approximately reduction program size over 32-bit instruction set. This features SH-4 CPU, which object code level upwardly compatible with SH-1, SH-2, SH-3 microcomputers. This instruction cache, operand cache that switched between copy-back write-through modes, 4-entry full-associative instruction (translation look aside buffer), (memory management unit) with 64entry full-associative shared TLB. sizes instruction cache operand cache kbytes kbytes. This also features state controller (BSC) that connect synchronous DRAM. Also, because on-chip functions, such controller, host, timers, serial communication functions, required multimedia equipment, this enables dramatic reduction system costs. Note: SuperH
trademark Hitachi, Ltd.
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Item
Features
Features Operating frequency: Performance: 360MIPS, GFLOPS Voltage: (internal), (I/O) Superscalar architecture: Parallel execution instructions Packages: 256-pin (Size: pitch: External buses: Separate 26-bit address 32-bit data buses External frequency: 67MHz Choice mode mode: mode: 8-/16-bit parallel interface (supports 68-/80-family interface) mode: controller/data output
Original Hitachi SuperH architecture 32-bit internal data General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers
RISC-type instruction (upward-compatible with SuperH Series) Fixed 16-bit instruction length improved code efficiency Load-store architecture Delayed branch instructions Conditional execution C-based instruction
Superscalar architecture (providing simultaneous execution instructions) including Instruction execution time: Maximum instructions/cycle Virtual address space: Gbytes (448-Mbyte external memory space) Space identifier ASIDs: bits, virtual address spaces On-chip multiplier 5-stage pipeline
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Item
Features On-chip floating-point coprocessor Supports single-precision bits) double-precision bits) Supports IEEE754-compliant data types exceptions rounding modes: Round Nearest Round Zero Handling denormalized numbers: Truncation zero interrupt generation compliance with IEEE754 Floating-point registers: bits words banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution times: Latency (FMAC/FADD/FSUB/FMUL): cycles (single-precision), cycles (double-precision) Pitch (FMAC/FADD/FSUB/FMUL): cycle (single-precision), cycles (double-precision) Note: FMAC supported single-precision only. graphics instructions (single-precision only): 4-dimensional vector conversion matrix operations (FTRV): cycles (pitch), cycles (latency) 4-dimensional vector inner product (FIPR): cycle (pitch), cycles (latency) 5-stage pipeline
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Item Clock pulse generator (CPG)
Features Choice main clock: times EXTAL Clock modes: frequency: 1/2, 1/3, 1/4, 1/6, times main clock frequency: 1/2, 1/3, 1/4, 1/6, times main clock Peripheral frequency: 1/2, 1/3, 1/4, 1/6, times main clock Power-down modes: Sleep mode Deep sleep mode Standby mode Hardware standby mode Module standby mode Single-channel watchdog timer 4-Gbyte address space, address space identifiers (8-bit ASIDs) Single virtual mode multiple virtual memory mode Supports multiple page sizes: kbyte, kbytes, kbytes, Mbyte 4-entry fully-associative instructions 64-entry fully-associative instructions operands Supports software-controlled replacement random-counter replacement algorithm contents accessed directly address mapping
Memory management unit (MMU)
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Item Cache memory
Features Instruction cache (IC) 16-kbyte, 2-way associative (LRU) entries, 32-byte block length Cache-double-mode (16-kbyte cache) Index mode Operand cache (OC) 32-kbyte, 2-way associative (LRU) entries, 32-byte block length Cache-double-mode (32-kbyte cache) Index mode mode (16-kbyte cache 16-kbyte RAM) Choice write method (copy-back write-through) Single-stage copy-back buffer, single-stage write-through buffer Cache memory contents accessed directly address mapping (usable on-chip memory) Store queue bytes entries) Nine independent external interrupts: NMI, IRL3 IRL0, IRQ7 IRQ4 15-level signed external interrupts: IRL3 IRL0 On-chip peripheral module interrupts: Priority level each module Supports debugging means user break interrupts break channels Address, data value, access type, data size break conditions Supports sequential break function
Interrupt controller (INTC)
User break controller (UBC)
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Item state controller (BSC)
Features Supports external memory access External memory space divided into seven areas, each Mbytes, with following parameters settable each area: size bits) Number wait cycles (hardware wait function also supported) SRAM, synchronous DRAM, burst Supports PCMCIA interface (only little endian mode) Synchronous DRAM refresh functions: Programmable refresh interval Supports auto refresh mode self-refresh mode Synchronous DRAM burst access function endian little endian mode 8-channel physical address controller Transfer data size: bits, bytes Address modes: 1-bus-cycle single address mode 2-bus-cycle dual address mode Transfer requests: External, peripheral module, auto-requests Choice DACK DRAK (four external pins) modes: Cycle-steal burst mode Supports on-chip FIFO bridge (16-stage 32-bit FIFO achieve high-speed transfer HAC/SSI, LCDC 3-channel auto-reload 32-bit timer Input-capture function (only channel Choice types counter input clocks (external peripheral clocks) 4-channel auto-reload 32-bit timers Choice bits Choice 1-shot free-running operation Choice interrupt source transfer request from compare match overflow
Direct memory access controller (DMAC)
Timer unit (TMU)
Compare match timer (CMT)
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Item Serial communication interface (SCIF)
Features Three full-duplex communications channels On-chip 128-byte FIFOs channels Choice asynchronous mode synchronous mode select rate generated on-chip baud-rate generator On-chip modem control function (SCIF_RTS SCIF_CTS) channel Digital interface audio codec Supports transfer slot slot Choice 20-bit transfer Supports various sampling rates adjusting slot data Generates interrupt: data ready, data request, overflow, underrun 2-channel bi-directional transfer (maximum) Support multi-channel compressed-data transfer Selectable frame size channels (maximum) Master/slave 16-byte FIFO Supports high-speed mode (400 kbits/sec) Supports version Supports mode maximum rate Mbps peripheral clock Interface with MCCLK output transfer clock output, MCCMD command output/response input, MCDAT (data I/O) Four interrupt sources Supports ISO/IEC7816-3 (Identification card) Asynchronous half-duplex transfer bits) select rate generated on-chip baud-rate generator Generates checks parity Four interrupt sources
Hitachi audio codec interface (HAC) Serial sound interface (SSI) interface
Multimedia card interface (MMCIF)
Smart card interface (SIM)
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Item Hitachi controller area network (HCAN2)
Features channels (maximum) Supports specification 2.0A 2.0B Standard data remote frame (11-bit Extended data remote frame (29-bit independent message buffers using standard (11-bit) extended (29-bit) format Mailboxes used transmission reception Mailbox used only reception Message reception filtering IDs: Standard message Extended message Local reception filter reception-only Mailbox (standard extended message specified Power-down sleep mode maximum 1-Mbit/s data transfer rate specified Transmit message queue having internal priority sorting mechanism which handle priority-inversion issue real time applications Data buffer access without hand-shaking channel Master/slave mode Selectable rate generated on-chip baud-rate generator 2-kbyte internal memory read from written 32-bit units 8-/16-/32-bit units. Choice 16-bit parallel interface Supports 68-/80-family interface (can switched during reset) Endians switched channel Supports version OHCI Supports data transfer rate Mbps 12Mbps On-chip 8-kbyte SRAM shared memory defined OHCI specification
Serial peripheral interface (HSPI)
Multifunctional interface (MFI)
host
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Item controller (LCDC)
Features Supports 1024 1024 dots bpp: maximum dots, bpp: maximum dots) Supports color modes Supports grayscale modes. Supports TFT/DSTN/STN display Selectable signal polarities 24-bit color palette memory bits bits valid: 5/G: 6/B: Unified graphics memory architecture 10-bit resolution 4-channel input Three types conversion modes Single mode: 1-channel conversion Multi mode: 4-channel conversion Scan mode: 4-channel conversion Conversion time: channel (maximum) Absolute error 4LSB general port output)
converter (ADC)
General (GPIO)
Rev. 1.0, 02/03, page 1294
Block Diagram
32-bit address (instruction) 32-bit address (instruction)
32-bit address (store)
32-bit address (road)
32-bit address (data)
Lower 32-bit data
64-bit data (store) Upper 32-bit data
cache
ITLB
Cache controller
UTLB
cache
HCAN2 SCIF
29-bit address
32-bit data
Peripheral data
HSPI/SIM/ MMCIF
Peripheral address Peripheral data
INTC
GPIO MFRAM(2kB)
Peripheral address
DMAC
External (SH) interface
26-bit address 32-bit data
Address
H-UDI
32-bit data
RAM(8kB) HAC/SSI LCDC
Legend: DMAC ITLB UTLB INTC H-UDI SCIF state controller Direct memory access controller Floating-point unit User break controller Instruction translation lookaside buffer Unit translation lookaside buffer Clock pulse generator Interrupt controller Timer unit Hitachi user debug interface Compare match timer Serial communication interface with FIFO HSPI MMCIF HCAN2 LCDC GPIO Hitachi audio codec interface Serial sound interface interface Hitachi serial peripheral interface Smart card interface Multimedia card interface Hitachi controller area network Multifunctional interface host controller converter General port
Figure SH7760 Block Diagram
Rev. 1.0, 02/03, page 1294
EXTAL RESET
VCPWC/ IRQ4 XTAL
Arrangement
SSI0_SCK/ HAC_SD_IN0/
DACK0
VDD-PLL3 UCLK
VDD-CPG VDD-PLL1
HSPI_TX/ HSPI_CLK/ SIM_CLK/ SIM_D/ MD4/ MCCLK CMT_CTR1 CMT_CTR3 SCIF2_CLK SCIF2_TXD SCIF2_RXD SCIF2_CTS SCIF2_RTS SCIF0_CLK SCIF0_TXD CE2B MCDAT
HSPI_CS/ SIM_RST/ CMT_CTR0/
TCLK
VSS-CPG VDD-PLL2 VSS-PLL1 HAC_ BIT_CLK0 VSS-PLL2 HAC_RES
SSI1_SCK/ SSI1_WS/ HAC_ HAC_ SD_IN1 SYNC1
SSI0_WS/ HAC_SYNC0
HSPI_RX MCCMD
CMT_CTR2
SCIF1_CLK SCIF1_TXD SCIF1_RXD SCIF1_CTS SCIF1_RTS SCIF0_RXD CE2A
MD3/
VSS-PLL3 USB_DM
VDDQ
SSI0_SDATA/ SSI1_SDATA/ HAC_ HAC_ SD_OUT0 SD_OUT1
ASEBRK/ BRKACK VDDQ
VDDQ
VDDQ
DRAK0
USB_PENC VSSQ
USB_DP
HAC_ BIT_CLK1 MRESET STATUS0 BREQ BACK
STATUS1 VSSQ
TRST
VSSQ
VSSQ
VSSQ
DRAK1
DACK1
USB_OVC
VEPWC/ IRQ5
VSSQ
VDDQ
DREQ0
DREQ1
MFI-D8/ MFI-D0/ LCD_DATA8 LCD_DATA0 MFI-D1/ MFI-D9/ LCD_DATA9 LCD_DATA1
MFI-D2/ MFI-D10/ LCD_DATA2/ LCD_DATA10 IRQ6 MFI-D3/ MFI-D11/ LCD_DATA3/ LCD_DATA11 IRQ7 MFI-D4/ MFI-D12/ LCD_DATA4/ LCD_DATA12 DREQ2 MFI-D5/ MFI-D13/ LCD_DATA5/ LCD_DATA13 DRAK2/DACK2 MFI-D6/ MFI-D14/ LCD_DATA6/ LCD_DATA14 DREQ3
I2C1_SCL I2C1_SDA I2C0_SCL I2C0_SDA MD6/ IOIS16
Reserved/ AUDCK Reserved/ AUDATA[2]
Reserved/ AUDSYNC Reserved/ AUDATA[3] Reserved/ AUDATA[1]
VDDQ
VSSQ
VSSQ
VDDQ
VDDQ
VSSQ
P-LBGA 2121-256
ADTRG/ AVss_ADC AVcc_ADC AUDATA[0]
VDDQ
VSSQ
VSSQ
VDDQ
IRL3 IRL1
CAN0_ NERR/ AUDCK
IRL2 IRL0
CAN1_ NERR/ AUDSYNC
MFI-D7/ MFI-D15/ LCD_DATA7/ LCD_DATA15 DRAK3/DACK3
VSSQ
VDDQ
MFI-INT/ MFI-CS/ LCD_CLK LCD_DON MFI-E/ MFI-MD/
LCD_CL1 LCD_CL2
MFI-RW/ MFI-RS/ LCD_M_DISP LCD_FLM
CAN0_RX/ CAN1_RX/ AUDATA[2] AUDATA[3] CAN0_TX/ CAN1_TX/ AUDATA[0] AUDATA[1]
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VSSQ
RD/WR CASS/ FRAME
WE0/ DQM0/ WE1/ DQM1
VDDQ
VDDQ
VDDQ
VDDQ
CKIO
WE2/ DQM2/ ICIORD WE3/ DQM3/ ICIOWR
VDDQ
VDDQ
VSSQ
Figure SH7760 Arrangement
Rev. 1.0, 02/03, page 1294
Description
Table lists configuration this LSI. column, indicate input, output, input/output, respectively. GPIO column, indicates which also functions general port. Table
Configuration
Name
EXTAL XTAL VDD-CPG VDD-PLL1 SSI0_SCK/HAC_SD_IN0/BS2 HSPI_TX/SIM_D/MCDAT HSPI_CLK/SIM_CLK/MCCLK CMT_CTR1 CMT_CTR3 SCIF2_CLK SCIF2_TXD SCIF2_RXD SCIF2_CTS SCIF2_RTS SCIF0_CLK SCIF0_TXD MD4/CE2B DACK0 VDD-PLL3 UCLK RESET VSS-CPG VDD-PLL2 VSS-PLL1 SSI0_WS/HAC_SYNC0
IO/I/O O/IO/IO IO/O/O IO/O
Function
External input clock/crystal resonator Crystal resonator PLL1 serial clock input/HAC serial data/bus start HSPI transmit data/SIM data transfer/MMCIF data HSPI serial clock/SIM clock/MMCIF clock counter counter SCIF serial clock SCIF transmit data SCIF receive data SCIF modem control SCIF modem control SCIF serial clock SCIF transmit data Mode control 4/PCMCIA-CE DMAC0 acknowledge PLL3 operation clock Reset PLL2 PLL1 word selection/HAC from sync output
GPIO
Rev. 1.0, 02/03, page 1294
Name
HSPI_RX HSPI_CS/SIM_RST/MCCMD
IO/O/IO
Function
HSPI receive data input HSPI chip selection/SIM reset/MMCIF command/response
GPIO
CMT_CTR0/TCLK CMT_CTR2 SCIF1_CLK SCIF1_TXD SCIF1_RXD SCIF1_CTS SCIF1_RTS SCIF0_RXD MD3/CE2A VSS-PLL3 USB_DM VDDQ HAC_BIT_CLK0 VSS-PLL2 HAC_RES SSI0_SDATA/HAC_SD_OUT0 SSI1_SDATA/HAC-SD_OUT1 ASEBRK/BRKACK VDDQ VDDQ VDDQ DRAK0 USB_PENC
IO/I IO/O IO/O
counter/TMU clock counter Non-maskerable interrupt SCIF serial clock SCIF transmit data SCIF receive data SCIF modem control SCIF modem control SCIF receive data Mode control 3/PCMCIA-CE PLL3 D-transceiver analog ready serial data clock/SSI divider input clock PLL2 reset serial data/HAC serial data serial data/HAC serial data Internal H-UDI emulator H-UDI mode H_UDI data Internal H-UDI clock Mode control DMAC request acknowledgement power-on enable control
Rev. 1.0, 02/03, page 1294
Name
VSSQ USB_DP SSI1_SCK/HAC_SD_IN1 SSI1_WS/HAC_SYNC1 HAC_BIT_CLK1 MRESET STATUS0 STATUS1 VSSQ TRST VSSQ VSSQ VSSQ DRAK1 DACK1 USB_OVC VCPWC/IRQ4
IO/I IO/O
Function
analog transceiver Clock clock/HAC serial data word selection/HAC frame sync output serial data clock/SSI divider input clock Manual reset Status Internal Status H-UDI reset H-UDI data Internal Mode control Mode control DMAC request acknowledgement DMAC acknowledgement overcurrent detection LCDC panel power supply control (VCC)/external interrupt request
GPIO
VEPWC/IRQ5
LCDC panel power supply control (VEE)/external interrupt request
BREQ VSSQ VDDQ DREQ0 DREQ1 MFI-D8/LCD_DATA8 MFI-D0/LCD_DATA0
IO/O IO/O
Chip active request DMAC request DMAC request data/LCDC panel data data/LCDC panel data
Rev. 1.0, 02/03, page 1294
Name
BACK I2C1_SCL I2C1_SDA I2C0_SCL I2C0_SDA MFI-D9/LCD_DATA9 MFI-D1/LCD_DATA1 MD6/IOIS16 MFI-D10/LCD_DATA10 MFI-D2/LCD_DATA2/IRQ6
IO/O IO/O IO/O IO/O/I
Function
Chip select acknowledgement serial clock serial data serial clock serial data data/LCDC panel data data/LCDC panel data Internal Internal Internal Internal Mode control 6/IOIS16 (PCMCIA) Mode control data/LCDC panel data data/LCDC panel data/external interrupt request
GPIO
VDDQ VSSQ Reserved/AUDCK Reserved/AUDSYNC MFI-D11/LCD_DATA11 MFI-D3/LCD_DATA3/IRQ7
IO/O IO/O/I
Mode control Mode control Reserved/H-UDI emulator Reserved/H-UDI emulator data/LCDC panel data data/LCDC panel data/external interrupt request
VSSQ VDDQ Reserved/AUDATA[2] Reserved/AUDATA[3] MFI-D12/LCD_DATA12 MFI-D4/LCD_DATA4/DREQ2
IO/O IO/O/I
Chip select Chip select Reserved/H-UDI emulator Reserved/H-UDI emulator data/LCDC panel data data/LCDC panel data/DMAC2 request
Rev. 1.0, 02/03, page 1294
Name
VDDQ VSSQ AVss_ADC AVcc_ADC ADTRG/AUDATA[0] Reserved/AUDATA[1] MFI-D13/LCD_DATA13 MFI-D5/LCD_DATA5/DRAK2/DACK2
IO/O
Function
analog analog external trigger/H-UDI emulator Reserved/H-UDI emulator data/LCDC panel data
GPIO
IO/O/O/O data/LCDC panel data/DMAC2 request acknowledgement/DMAC2 acknowledgement
MFI-D14/LCD_DATA14 MFI-D6/LCD_DATA6/DREQ3 VDDQ VSSQ VSSQ VDDQ IRL3 IRL2 MFI-D15/LCD_DATA15 MFI-D7/LCD_DATA7/DRAK3/DACK3
IO/O IO/O/I IO/O
Chip select Address analog input analog input analog input analog input data/LCDC panel data data/LCDC panel data/DMAC3 request interrupt request interrupt request data/LCDC panel data
IO/O/O/O data/LCDC panel data/DMAC3 request acknowledgement/DMAC3 acknowledgement
VSSQ VDDQ IRL1 IRL0 MFI-INT/LCD_CLK MFI-CS/LCD_DON
Chip select Address interrupt request interrupt request interrupt/LCDC clock chip selection/LCDC display-on signal
Rev. 1.0, 02/03, page 1294
Name
CAN0_NERR/AUDCK CAN1_NERR/AUDSYNC MFI-E/LCD_CL1 MFI-MD/LCD_CL2 CAN0_RX/AUDATA[2] CAN1_RX/AUDATA[3] MFI-RS/LCD_M_DISP
Function
Internal Internal Internal Internal HCAN0 error signal/H-UDI emulator HCAN1 error signal/H-UDI emulator enable/ LCDC shift clock mode/LCDC shift clock Chip select Address Address Address HCAN0 data receive signal/H-UDI emulator HCAN1 data receive signal/H-UDI emulator register select/LCDC current-alternating signal/DISP signal
GPIO
MFI-RW/LCD_FLM CAN0_TX/AUDATA[0] CAN1_TX/AUDATA[1] VSSQ VSSQ VSSQ
read-write/read/LCDC first line marker start Address Address Address HCAN0 data transmit signal/H-UDI emulator HCAN1 data transmit signal/H-UDI emulator Data Data Data Data Clock output enable Internal Address
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Name
VSSQ VSSQ VSSQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ
Function
Address Internal Address Data Data Data Data Data Data Data Address Internal Address Address Internal Address Data Data Data Data Data
GPIO
Rev. 1.0, 02/03, page 1294
Name
RD/WR WE0/DQM0/REG WE2/DQM2/ICIORD VSSQ RD/CASS/FRAME WE1/DQM1 CKIO WE3/DQM3/ICIOWR
O/O/O
Function
Data Data Read/write Selection signal D0/REG Address Address Address Address Address Address Selection signal D16/ICIORD Data Data Data Data Data Data Data Data Data Read/CAS/FRAME Selection signal Address Address Clock output Address Address Address Selection signal D24/ICIOWR Chip select
GPIO
Rev. 1.0, 02/03, page 1294
Name
Function
Data Data Data Data Data
GPIO
column, indicate input, output, input/output, direction, respectively. Notes: used GPIO interrupt pin. used GPIO interrupt pin. When interrupt occurs, this exits standby mode. Only outputs. Legend:
Rev. 1.0, 02/03, page 1294
mode (MD7=0) Function Name Function Name GPIO GPIO Setting Selection PTE7 PECR[15:14] PTE6 PECR[13:12] PTE5 PECR[11:10] PTE4 PECR[9:8] PTE3 PECR[7:6] PTE2 PECR[5:4] PTC7 PCCR[15:14] PTC6 PCCR[13:12] INTC IRQ7 DMAC DRAK2/ DACK2 LCD_DATA6 LCD_DATA7 DACK3 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 VCPWC PTD7 PDCR[15:14] PTD6 PDCR[13:12] PTD5 PDCR[11:10] PTD4 PDCR[9:8] PTD3 PDCR[7:6] PTD2 PDCR[5:4] PTD1 PDCR[3:2] PTD0 PDCR[1:0] PTE1 PECR[3:2] PTE0 PECR[1:0] DRAK3/ DREQ3 PTC1 PCCR[3:2] PTC0 PCCR[1:0] DREQ2 IRQ6 PTC5 PCCR[11:10] PTC4 PCCR[9:8] PTC3 PCCR[7:6] MODSELR[7] MODSELR[6] MODSELR[5] MODSELR[4] DMARCR[22]*1 MODSELR[3] MODSELR[2] DMARCR[23]*2 IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] LCD_CLK LCD_DON LCD_CL1 LCD_CL2 LCD_M_DISP LCD_FLM LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCDC
LCDC mode (MD7=1)
Other modes
Register
Function
Name
Table
MFI-INT
MFI-CS
MFI-E
MFI-MD
MFI-RS
MFI-RW
Function
MFI-D0
Functions
MFI-D1
MFI-D2
MFI-D3
MFI-D4
MFI-D5
PTC2 PCCR[5:4]
MFI-D6
MFI-D7
MFI-D8
MFI-D9
MFI-D10
MFI-D11
MFI-D12
MFI-D13
MFI-D14
MFI-D15
INTC
IRQ4
Rev. 1.0, 02/03, page 1294
IRQ5 VEPWC Notes: DRAK2/DACK2 selected only DMABRG mode DRAK3/DACK3 selected only DMABRG mode
Register Function Name Name GPIO GPIO Setting Selection Function PTF2 PFCR[5:4] PFCR[7:6] PFCR[3:2] PFCR[1:0] IPSELR[15:14] IPSELR[15:14] IPSELR[15:14] IPSELR[13] IPSELR[13] IPSELR[13] PTA4 PACR[9:8] PTA3 PACR[7:6] PTA2 PACR[5:4] PTK7 PKCR[15:14] PTK6 PKCR[13:12] PTK5 PKCR[11:10] PTK4 PKCR[9:8] PTK3 PKCR[7:6] PTK2 PKCR[5:4] IPSELR[13] IPSELR[13] IPSELR[13] IPSELR[12] IPSELR[12] IPSELR[12] IPSELR[12] IPSELR[12] IPSELR[12] SIM_D MMCIF MCCLK MCCMD PTF0 PTF1 MCDAT PTF3 SIM_CLK SIM_RST AUDCK AUDATA[2] AUDATA[0] AUDSYNC AUDATA[3] AUDATA[1] AUDATA[3] AUDATA[2] AUDATA[1] AUDCK AUDSYNC AUDATA[0] HAC_SD_IN0 HAC_SYNC0 BS*1 PTB7 PBCR[15:14] PTB6 PBCR[13:12] PTB5 PBCR[11:10] IPSELR[11:10] IPSELR[11:10] IPSELR[11:10]
Function Name
Table
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
HSPI
HSPI_RX
HSPI_TX
HSPI_CLK
Functions
HSPI_CS
Rev. 1.0, 02/03, page 1294
PTA7 PACR[15:14] PTA6 PACR[13:12] PTA5 PACR[11:10]
HCAN2
CAN0_NERR
CAN0_RX
CAN0_TX
HCAN2
CAN1_NERR
CAN1_RX
CAN1_TX
Reserved*2
Reserved*2
Reserved*2
Reserved*2
Reserved*2
ADTRG
SSI_SCK
SSI0_WS
SSI0_SDATA HAC_SD_OUT0 Notes: details settings, MODSELR[1]. Refer section Function Controller(PFC) processing Reserved terminal.
Register Function Name Name PTJ7 PJCR[15:14] PJCR[13:12] PJCR[11:10] PJCR[9:8] PJCR[7:6] PJCR[5:4] IPSELR[11:10] IPSELR[11:10] IPSELR[11:10] PTJ6 HAC_SYNC1 PTJ5 PTJ4 PTJ3 PTJ2 PTB4 PBCR[9:8] PTB3 PBCR[7:6] PTB2 PBCR[5:4] PTB1 PBCR[3:2] PTG7 PGCR[15:14] PTG6 PGCR[13:12] PTG5 PGCR[11:10] PTG4 PGCR[9:8] PTG3 PGCR[7:6] PTG2 PGCR[5:4] PTG1 PGCR[3:2] PTG0 PGCR[1:0] PTH7 PHCR[15:14] PTH6 PFCR[13:12] PTH5 PHCR[11:10] PTH4 PHCR[9:8] PTH3 PHCR[7:6] PTH2 PHCR[5:4] PTH1 PHCR[3:2] PTH0 PHCR[1:0] HAC_SD_IN1 HAC_SD_OUT HAC_BIT_CLK1 TCLK GPIO GPIO Setting Selection HAC_BIT_CLK0 Function
Function Name
Table
HAC_BIT_CLK0
(0/1)
HAC_RES
SSI1_WS
SSI1_SCK
SSI1_DATA
HAC_BIT_CLK1
CMT_CTR0
CMT_CTR1
Functions
CMT_CTR2
CMT_CTR3
SCIF
SCIF0_CLK
SCIF0_RXD
SCIF0_TXD
SCIF
SCIF1_CLK
SCIF1_CTS
SCIF1_RTS
SCIF1_RXD
SCIF1_TXD
SCIF
SCIF2_CLK
SCIF2_CTS
SCIF2_RTS
SCIF2_RXD
SCIF2_TXD
UCLK
USB_PENC
USB_OVC
USB_DP
Rev. 1.0, 02/03, page 1294
USB_DM
Register Function Name Function Name GPIO GPIO Setting Selection PTJ1 PJCR[3] H-UDI BRKACK
Function Name
Table
H-UDI
TRST
ASEBRK
INTC
Functions
IRL0
Rev. 1.0, 02/03, page 1294
IRL1
IRL2
IRL3
DMAC
DACK0
DACK1
DRAK0
DRAK1
DREQ0
DREQ1
Table
Data
Functions
Memory Interface
Function
Address
Name
SRAM
SDRAM
PCMCIA
Remarks
Rev. 1.0, 02/03, page 1294
Memory Interface Function
Data
Name
SRAM
SDRAM
PCMCIA
Remarks
ACCSIZE0 ACCSIZE1 ACCSIZE2
Chip select
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Memory Interface Function
Chip select
Name
SRAM
RD/WR
SDRAM
PCMCIA
CE1A CE1B
RD/WR
Remarks
Read/Write Read/CAS/FRAME Selection signal D0/REG
RD/WR
RD/WR
RD/CASS/FRAME WE0/DQM0/REG
DQM0
FRAME
Selection signal WE1/DQM1 Selection signal D16/ICIORD
DQM1 DQM2
ICIORD
WE2/DQM2/ICIORD
Selection signal D24/ICIOWR
WE3/DQM3/ICIOWR
DQM3
ICIOWR
Clock output Clock output enable Mode Mode Mode Mode/PCMCIA-CE Mode/PCMCIA-CE Mode Mode/IOIS16 Mode Mode Reset Manual reset ready start request acknowledgement Chip active Status Status
CKIO MD3/CE2A MD4/CE2B MD6/IOIS16 RESET MRESET BREQ BACK STATUS0 STATUS1
(BS)
CKIO
CKIO
Reset; Reset; Reset;
CE2A CE2B
Reset; Reset; Reset;
IOIS16
Reset; Reset; Reset;
RESET
(BS) (BS)
(BS)
Rev. 1.0, 02/03, page 1294
Memory Interface Function
External input clock/crystal resonator
Name
EXTAL
SRAM
SDRAM
PCMCIA
Remarks
Crystal resonator
XTAL
Rev. 1.0, 02/03, page 1294
Section Programming Model
Data Formats
data formats supported this shown figure 2.1.
Byte bits) Word bits) Longword bits) fraction fraction
Single-precision floating-point bits)
Double-precision floating-point bits)
Figure Data Formats
Rev. 0.1, 02/03, page 1294
2.2.1
Register Descriptions
Privileged Mode Banks
Processor Modes: This processor modes, user mode privileged mode. This normally operates user mode, switches privileged mode when exception occurs interrupt accepted. There four kinds registers-general registers, system registers, control registers, floating-point registers-and registers that accessed differ processor modes. General Registers: There general registers, designated R15. General registers banked registers which switched processor mode change. privileged mode, register bank (RB) status register (SR) defines which banked register accessed general registers, which accessed only through load control register (LDC) store control register (STC) instructions. When (that when bank selected), registers comprising bank general registers R0_BANK1 R7_BANK1 non-banked general registers accessed general registers R15. this case, eight registers comprising bank general registers R0_BANK0 R7_BANK0 accessed LDC/STC instructions. When (that when bank selected), registers comprising bank general registers R0_BANK0 R7_BANK0 non-banked general registers accessed general registers R15. this case, eight registers comprising bank general registers R0_BANK1 R7_BANK1 accessed LDC/STC instructions. user mode, registers comprising bank general registers R0_BANK0 R7_BANK0 non-banked general registers accessed general registers R15. eight registers comprising bank general registers R0_BANK1 R7_BANK1 cannot accessed. Control Registers: Control registers comprise global base register (GBR) status register (SR), which accessed both processor modes, saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register (SGR), debug base register (DBR), which only accessed privileged mode. Some bits status register (such bit) only accessed privileged mode. System Registers: System registers comprise multiply-and-accumulate registers (MACH/MACL), procedure register (PR), program counter (PC), floating-point status/control register (FPSCR), floating-point communication register (FPUL). Access these registers does depend processor mode.
Rev. 1.0, 02/03, page 1294
Floating-Point Registers: There thirty-two floating-point registers, FR0-FR15 XF0- XF15. FR0-FR15 XF0-XF15 assigned either banks (FPR0_BANK0- FPR15_BANK0 FPR0_BANK1-FPR15_BANK1). FR0-FR15 used eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, pair registers) four registers FV0/4/8/12 (register vectors), while XF0- XF15 used eight registers XD0/2/4/6/8/10/12/14 (register pairs) register matrix XMTRX. Register values after reset shown table 2.1. Table
Type
Initial Register Values
Registers Initial Value* Undefined
General registers R0_BANK0 R7_BANK0, R0_BANK1 R7_BANK1, Control registers
bits 1111 (H'F), reserved bits others undefined
GBR, SSR, SPC, SGR, Undefined System registers MACH, MACL, FPUL FPSCR Floating-point registers Note: FR15, XF15 H'0000 0000 Undefined H'A000 0000 H'0004 0001 Undefined
Initialized power-on reset manual reset.
register configuration each processing mode shown figure 2.2. User mode privileged mode switched processing mode (MD) status register.
Rev. 0.1, 02/03, page 1294
R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2
R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 MACH MACL
R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 MACH MACL
MACH MACL
Register configuration user mode
R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 Register configuration privileged mode
R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 Register configuration privileged mode
Notes: used index register indexed register-indirect addressing mode indexed indirect addressing mode. Banked registers Banked registers Accessed general registers when Accessed only LDC/STC instructions when cleared Banked registers Accessed general registers when cleared Accessed only LDC/STC instructions when
Figure Register Configuration Each Processing Mode
Rev. 1.0, 02/03, page 1294
2.2.2
General Registers
Figure shows relationship between processing modes general registers. This twenty-four 32-bit general registers (R0_BANK0 R7_BANK0, R0_BANK1 R7_BANK1, R15). However, only these accessed general registers processing mode. This processing modes, user mode privileged mode. R0_BANK0 R7_BANK0 Allocated user mode (SR.MD Allocated when SR.RB privileged mode (SR.MD R0_BANK1 R7_BANK1 Cannot accessed user mode. Allocated when SR.RB privileged mode.
SR.MD (SR.MD SR.RB R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1
R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1
(SR.MD SR.RB R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0
Note user's R0-R7 assigned R0_BANK0-R7_BANK0, after exception interrupt R0-R7 assigned R0_BANK1-R7_BANK1, necessary interrupt handler save restore user's R0-R7 (R0_BANK0-R7_BANK0). After reset, values R0_BANK0-R7_BANK0, R0_BANK1-R7_BANK1, R8-R15 undefined.
Figure General Registers
Rev. 0.1, 02/03, page 1294
2.2.3
Control Registers
control registers bits long. They consist status register (SR), global base register (GBR), saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register (SGR), debug base register (DBR). accessed both processing modes, SSR, SPC, VBR, SGR, only accessed privileged mode. Status Register (SR):
Bit: Initial value: R/W: Bit: Initial value: R/W:
IMASK3 IMASK2 IMASK1 IMASK0
Name Initial Value
Description Reserved This always read write value should always Processing Mode Selects processing mode. User mode (Some instructions cannot executed some resources cannot accessed.) Privileged mode
Privileged Mode General Register Bank Soecification This exception interrupt. R0_BANK0 R7_BANK0 accessed general registers R0_BANK1 R7_BANK1 accessed using LDC/STC instructions R0_BANK1 R7_BANK1 accessed general accessed using LDC/STC instructions
Exception/Interrupt Block This reset, exception, interrupt. While this interrupt request masked. this case, this processor enters reset state when general exception other than user break occurs.
Rev. 1.0, 02/03, page 1294
Name Initial Value
Description Reserved These bits always read write value should always Disable reset clears this When this instruction delay slot, general disable exception occurs. When this instruction delay slot, slot disable exception occurs. (FPU instructions: H'F*** instructions (.L)/STS(.L) instructions using FPUL/FPSCR)
Reserved These bits always read write value should always Used DIV0S, DIV0U, DIV1 instructions. Interrupt Mask Level Bits interrupt whose priority equal less than value IMASK bits masked. These bits modified interrupt. Reserved These bits always read write value should always Used instruction. Indicates true/false carry/borrow.
IMASK3 IMASK2 IMASK1 IMASK0
Saved Status Register (SSR): contents saved event exception interrupt. Saved Program Counter (SPC): address instruction which interrupt exception occurs saved SPC. Global Base Register (GB
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