Silicon Anomaly List ADuC7019/ADuC702x This anomaly list des

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Silicon Anomaly List ADuC7019/ADuC702x This anomaly list des

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Precision Analog Microcontroller 12-Bit ADCs DACs, ARM7TDMI® Core
Silicon Anomaly List
ADuC7019/ADuC702x
This anomaly list describes known bugs, anomalies, workarounds ADuC7019/ADuC702x MicroConverter®. anomalies listed apply ADuC7019/702x packaged material branded follows:
First Line Third Line ADuC7019 ADuC702x (where: (revision identifier)
Analog Devices, Inc. committed, through future silicon revisions, continuously improve silicon functionality. Analog Devices tries ensure that these future silicon revisions remain compatible with your present software/systems implementing recommended workarounds outlined here.
ADuC7019/ADuC702x FUNCTIONALITY ISSUES
Silicon Revision Identifier Kernel Revision Identifier Chip Marking silicon branded Silicon Status Release Anomaly Sheet Rev. Reported Anomalies
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. rights reserved.
ADuC7019/ADuC702x
ANOMALIES
ADuC7019/ADuC702x Functionality Issues
Conversion Start Mode [er017]:
Background: ADCCON [2:0] allow user select conversion start modes operation, namely: External (P2.0) triggered conversion Timer1 overflow Timer0 overflow Single software conversion Continuous software conversion
triggered conversion
Issue: active-low, external (P2.0) triggered conversion always active, even selected ADCCON [2:0]. This case function P2.0 configured CONVSTART input P2.0 configured other function, example, SOUT, PLAO[5], GPIO. This means that falling edge seen P2.0, single conversion triggered ADCCON enabled. conversion cycle already progress, this conversion stops conversion cycle begins response falling edge P2.0. Pending. ADCCON [7], enable conversion mode bit, fully functional, allowing user disable active conversion modes except continuous conversion (see data sheet).
Workaround: Related Issues:
Default Values [er018]:
Background: on-chip factory firmware allows downloading ADuC7019/ADuC702x parts through UART I2C® interfaces. After kernel execution, normal mode after downloading jumping user code, default values should described datasheet (see data sheet). When downloading occurs these interfaces software command sent described AN-724 AN-806), following MMRs modified factory firmware: UART loader (standard parts) loader models) COMTX I2C0SRX COMRX I2C0STX COMDIV0 I2C0CFG COMCON0 I2C0ID0/1/2/3 COMDIV2 I2C0STA GP1CON GP1CON FEEADR FEEADR GP1CON needs configured P1.0 P1.1 GPIO. COMDIV2 must cleared UART without fractional divider standard parts. MMRs modified result running user code from power cycle, toggling reset pin, software reset.
Issue:
Workaround: Related Issues:
On-Chip Loader's Protection Command [er019]:
Background: on-chip factory firmware residing Flash/EE memory allows downloading user code user space Flash/EE serial port (either UART I2C, depending model). After downloading code, also allows protection Flash/EE user space through 32-bit key. protection 32-bit value that should entered FEEADR FEEDAT during protection sequence. loader ignores writes only both FEEADR FEEDAT. None. This does affect writing keys JTAG user code.
Issue: Workaround: Related Issues:
Rev. Page
ADuC7019/ADuC702x
On-Chip Loader's Write/Verify Commands [er020]:
Background: on-chip factory firmware residing Flash/EE memory allows downloading user code from Intel files user space Flash/EE memory serial port (either UART I2C, depending model). After downloading, also allows verification that Flash/EE memory been programmed properly. Both write command verify command, described AN-724 AN-806, cause issues with addresses: address first byte data packet programmed odd, data previous address becomes corrupted. address last byte data packet programmed even, this byte written into Flash/EE memory. ARMWSD Version higher ensures that data starts terminates half word boundaries. Dummy bytes (0xFF) added data packets that start/stop half word boundaries. Users employing their software downloading should also take this precaution. None.
Issue:
Workaround:
Related Issues:
Slave Releasing [er021]:
Background: Issue: Workaround: During read from master slave, slave's FIFO empty, slave generates NACK response master's request. Then releases bus, allowing master generate STOP condition. Following generation acknowledge, ADuC7019/ADuC702x release generation FIFO transmit empty interrupt. Following generation transmit FIFO empty interrupt, released following: Placing valid data transmit FIFO Placing dummy data transmit FIFO, followed transmit FIFO flush Resetting slave interface disabling/enabling slave None.
Related Issues:
Rev. Page
ADuC7019/ADuC702x
SECTION ADuC7019/ADuC702X FUNCTIONALITY ISSUES
Reference Number er001 er002 er003 er004 er005 er006 er007 er008 er009 er010 er011 er012 er013 er014 er015 er016 er017 er018 er019 er020 er021 Description External reference wrap around Flash/EE controller Code execution, boundary issue Clocking system Wake-up timer operation transmit FIFO flush operation master mode Block interconnection peripheral Baud rate generation Temperature sensor operation clock source pins power-up time sync interrupt Watchdog timer operation External memory operation conversion start mode default values On-chip loader's protection command On-chip loader's write/verify commands slave releasing Status Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Feature Fixed Fixed Fixed Open Open Open Open Open
SECTION ADuC7019/ADuC702x PERFORMANCE RELATED ISSUES
Reference Number pr001 pr002 pr003 pr004 Description linearity gain error Execution speed Flash retention specification Status Fixed Fixed Fixed Fixed
SECTION ADuC7019/ADuC702x SILICON FUTURE ENHANCEMENTS
Reference Number fe001 fe002 fe003 Description address matching start stop condition identification External clock input Status Fixed Fixed Fixed
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. S05883-0-3/06(B)
Rev. Page

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