WirelessUSBLP 2.4GHz Radio Features Applications 2.4-GH
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CYRF6936
WirelessUSBLP 2.4GHz Radio
Features
Applications
2.4-GHz Direct Sequence Spread Spectrum (DSSS) radio transceiver. Operates unlicensed worldwide Industrial, Scientific Medical (ISM) band (2.400 GHz-2.483 GHz). Highly integrated, very external component count (see Figure 8-1) 21mA operating current (Transmit dBm) Transmit power Receive sensitivity DSSS data rates kbps GFSK data rate Mbps Operating range: 10m+ Auto Transaction Sequencer (ATS) Framing, CRC, Auto Power Management Unit (PMU) MCU/Sensor Sleep Current Fast Startup Fast Channel Changes Receive Signal Strength Indication (RSSI) Automatic Gain Control (AGC) 4-MHz microcontroller interface access while sleep mode Supports coin-cell operated applications Operating voltage from 1.8V 3.6V Operating temperature from 70°C Space saving 40-pin package
Wireless Keyboards Mice Wireless Gamepads Remote Controls Toys VOIP Wireless Headsets White Goods Consumer Electronics Home Automation Automatic Meter Readers Personal Health Entertainment
Applications Support
www.cypress.com development tools, reference designs, application notes.
Functional Description
CYRF6936 WirelessUSBLP radio second generation member Cypress's WirelessUSB Radio System-OnChip (SoC) family. CYRF6936 interoperable with first generation CYWUSB69xx devices. CYRF6936 adds range enhanced features, including increased operating voltage range, reduced supply current operating modes, higher data rate options, reduced crystal start-up, synthesizer settling link turn-around times.
VBAT
VREG
PACTL GFSK Modulator RFBIAS
Power Management
MISO MOSI
Data Interface Sequencer RSSI Xtal
DSSS Baseband Framer GFSK Demodulator
Synthesizer Block Diagram
XTAL XOUT
Figure 4-1. CYRF6936 Simplified Block Diagram Cypress Semiconductor Corporation Document 38-16015 Rev. Champion Court Jose, 95134-1709 408-943-2600 Revised December 2005
EPAD
CYRF6936
Descriptions
Name RFBIAS PACTL XTAL XOUT MISO MOSI VREG VBAT RESV Type Default Description Differential signal to/from antenna Differential signal to/from antenna 1.8V reference voltage Control signal external switch, GPIO 12-MHz crystal external clock connection Buffered 0.75, 1.5, clock, GPIO clock data output pin, GPIO data input pin, SDAT enable Interrupt output, GPIO Device reset. Internal 10k-ohm pull-down resistor. Active HIGH, connect 0.1-µF capacitor VBAT inductor/diode connection boosted output voltage feedback Decoupling 1.8V logic regulator, connect 0.47-µF capacitor VBAT 1.8V 3.6V. Main supply. 2.4V 3.6V. Typically connected VREG interface voltage, 1.8-3.6V Must connected Recommend connect Ground Ground
CYRF6936 View*
VREG XTAL VBAT VBAT RFBIAS RESV VBAT
PACTL GPIO XOUT GPIO MISO GPIO MOSI SDAT
CYRF6936 40-lead
GPIO
E-PAD BOTTOM SIDE
Figure 5-1. CYRF6936, View Document 38-16015 Rev. Page
Functional Overview
CYRF6936 provides complete WirelessUSB antenna wireless MODEM. designed implement wireless device links operating worldwide 2.4-GHz frequency band. intended systems compliant with world-wide regulations covered ETSI 489-1 V1.41, ETSI 328-1 V1.3.1 (Europe), Part (USA Industry Canada) TELEC ARIB_T66_March, 2003 (Japan). contains 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), Automatic Gain Control (AGC) interface data transfer device configuration. radio supports discrete 1-MHz channels (regulations limit some these channels certain jurisdictions). DSSS modes baseband performs DSSS spreading/despreading, while GFSK Mode Mb/s GFSK) baseband performs Start Frame (SOF), Frame (EOF) detection generation checking. baseband also configured automatically transmit Acknowledge (ACK) handshake packets whenever valid packet received. When receive mode, with packet framing enabled, device always ready receive data transmitted supported rates, enabling implementation mixed-rate systems which different devices different data rates. This also enables implementation dynamic data rate systems, which high data rates shorter distances and/or low-moderate interference environment, change lower data rates longer distances and/or high interference environments. addition, CYRF6936 Power Management Unit (PMU) which allows direct connection device battery voltage range 1.8V 3.6V. conditions battery voltage provide supply voltages required device, supply external devices.
CYRF6936
mode, 1-byte bits) encoded each code symbol transmitted. mode, 2-bits encoded each code symbol transmitted. CYWUSB6934 mode). mode, single encoded each code symbol transmitted. CYWUSB6934 standard modes.) Both 64-chip 32-chip Data codes supported. four data transmission modes modes apply data after SOP. particular length, data, sent same mode.
Link Layer Modes
CYRF6936 device supports following data packet framing features: Packets begin with 2-symbol Start Packet (SOP) marker. This required GFSK modes, optional modes; framing disabled then inferred whenever successive correlations detected. code used different from that used "body" packet, desired different length. There options detecting packet. enabled, then packet length field enabled. This first 8-bits after symbol, transmitted payload data rate. enabled, Packet (EOP) condition inferred after reception number bytes defined length field, plus bytes enabled-see below). alternative using length field infer condition from configurable number successive non-correlations; this option available GFSK mode. device configured append 16-bit each packet. polynomial with added programmability seed. enabled, receiver will verify calculated payload data against received value field. starting value calculation configurable, transmitted calculated using either loaded "seed" value zero seed; received data will checked against both configured zero seeds. Figure shows example packet with SOP, lengths fields enabled, Figure shows standard packet.
Data Transmission Modes
supports four different data transmission modes: GFSK mode, data transmitted Mbps, without DSSS.
Preamble 16us
Framing Symbol*
Framing Symbol*
Length
Packet length Byte Period
Payload Data
*Note:32 64us
Figure 6-1. Example Default Packet Format
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Preamble 16us Framing Symbol*
CYRF6936
Framing Symbol*
field from received packet. Byte periods
*Note:32 64us
Figure 6-2. Default Packet Format
Packet Buffers
data transmission reception utilizes 16-byte packet buffers-one transmission reception. transmit buffer allows complete packet 16-bytes payload data loaded burst transaction, then transmitted with further intervention. Similarly, receive buffer allows entire packet payload data bytes received with firmware intervention required until packet reception complete. CYRF6936 supports packet length bytes; interrupts provided allow transmit receive buffers FIFOs. When transmitting packet longer than bytes, load 16-bytes initially, further bytes transmit buffer transmission data creates space buffer. Similarly, when receiving packets longer than bytes, must fetch received data from FIFO periodically during packet reception prevent from overflowing.
supported selecting 32-chip codes, mode, disabling SOP, length, fields. Similarly, 15.675-kHz mode supported selecting 64-chip codes mode. this way, suitably configured CYRF6936 device transmit data and/or receive data from first generation device.
Data Rates
Auto Transaction Sequencer (ATS)
combining code lengths data transmission modes described above, CYRF6936 supports following data rates: 1000-kbps (GFSK) 250-kbps (32-chip 8DR) 125-kbps (64-chip 8DR) 62.5-kbps (32-chip DDR) 31.25-kbps (64-chip DDR) 15.625-kbps (64-chip SDR) Lower data rates typically provide longer range and/or more robust link.
CYRF6936 provides automated support transmission reception acknowledged data packets. When transmitting data packet, device automatically starts crystal synthesizer, enters transmit mode, transmits packet transmit buffer, then automatically switches receive mode waits handshake packet-and then automatically reverts sleep mode idle mode when either packet received, timeout period expires. Similarly, when receiving transaction mode, device waits receive mode valid packet received, then automatically transitions transmit mode, transmits packet, switches back receive mode await next packet. contents packet buffers affected transmission reception packets. each case, entire packet transaction takes place without need firmware action; transmit data simply needs load data packet transmitted bit. Similarly, when receiving packets transaction mode, firmware simply needs retrieve fully received packet response interrupt request indicating reception valid packet-invalid error packets simply ignored.
Functional Block Overview
2.4-GHz Radio
radio transceiver dual conversion architecture optimized power range/robustness. radio employs channel-matched filters achieve high performance presence interference. integrated Power Amplifier (PA) provides transmit power, with output power control range steps. supply current device reduced output power reduced. Table 7-1. Internal Output Power Step Table Setting Typical Output Power (dBm)
Backward Compatibility
CYRF6936 fully interoperable with main modes first generation devices. 62.5-kbps mode Document 38-16015 Rev.
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Frequency Synthesizer
Before transmission reception commence, necessary frequency synthesizer settle. settling time varies depending channel; fast channels provided with maximum settling time 100-µs. frequencies link turn-around time (from transmit receive receive transmit) less than 30-µs. "fast channels" (<100-µs settling time) every frequency, starting 2400 including 2472 (i.e., 0,3,6,9.69 72).
CYRF6936
application initiate data transfer multi-byte transaction. first byte Command/Address byte, following bytes data bytes shown Figure through Figure 7-4. communications interface burst mechanism, where command byte followed many data bytes desired. burst transaction terminated deasserting slave select communications interface single read burst read sequences shown Figure Figure 7-3, respectively. communications interface single write burst write sequences shown Figure Figure 7-5, respectively. This interface optionally operated 3-wire mode with MISO MOSI functions combined single bidirectional data (SDAT). When using 3-wire mode, user firmware should ensure that MOSI high-impedance state except when MOSI actively transmitting data. device registers written read from byte time, several sequential register locations written/read single transaction using incrementing burst mode. addition single byte configuration registers, device includes register files; register files FIFOs written read from using non-incrementing burst transactions. function optionally multiplexed onto MOSI pin; when this option enabled function available while low. When using this configuration, user firmware should ensure that MOSI high impedance state whenever high. interface dependent internal 12-MHz clock, registers therefore read from written while device sleep mode, 12-MHz oscillator disabled. interface pins have separate voltage reference (VIO), enabling device interface directly MCUs operating voltages above below CYRF6936 supply voltage.
Baseband Framer
baseband framer blocks provide DSSS encoding decoding, generation reception generation checking, well detection length field.
Packet Buffers Radio Configuration Registers
Packet data configuration registers accessed through interface. configuration registers directly addressed through address field packet CYWUSB6934). Configuration registers provided allow configuration DSSS codes, data rate, operating mode, interrupt masks, interrupt status, etc.
Interface
CYRF6936 4-wire communication interface between application more slave devices. interface supports single-byte multi-byte serial transfers. 4-wire communications interface consists Master Out-Slave (MOSI), Master In-Slave (MISO), Serial Clock (SCK), Slave Select (SS). receives from application pin. Data from application shifted MOSI pin. Data application shifted MISO pin. active-low Slave Select (SS) must asserted initiate transfer.
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Byte Name [5:0] Address Byte [7:0] Data
CYRF6936
Figure 7-1. Transaction Format
MOSI
addr
Figure 7-2. Single Read Sequence
MOSI MISO
addr
data
data
Figure 7-3. Incrementing Burst Read Sequence
Figure 7-4. Single Write Sequence
addr
data from
MOSI
from
Figure 7-5. Incrementing Burst Write Sequence
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Interrupts
device provides interrupt (IRQ) output, which configurable indicate occurrence various different events. programmed either active high active low, either CMOS open drain output. full description available interrupts found Section 9.0. CYRF6936 features three sets interrupts: transmit, receive, system interrupts. These interrupts share single (IRQ), independently enabled/disabled. transmit mode, receive interrupts automatically disabled, receive mode transmit interrupts automatically disabled. However, contents enable registers preserved when switching between transmit receive modes. more than interrupt enabled time, necessary read relevant status register determine which event caused assert. Even when given interrupt source disabled, status condition that would otherwise cause interrupt determined reading appropriate status register. therefore possible devices without making polling status register(s) wait event, rather than using pin.
7.6.1 Transmit Interrupts Section 7.6.2 Receive Interrupts Section 7.6.3 System Interrupts Section
CYRF6936
fully static sleep mode writing FRC_END=1 END_STATE=000 bits XACT_CFG_ADR register over interface. device will enter sleep mode within after signal goes high this transaction. Alternatively, device configured automatically enter sleep mode after completing packet transmission reception. When sleep mode, on-chip oscillator stopped, interface remains functional. device will wake from sleep mode automatically when device commanded enter transmit receive mode. When resuming from sleep mode, there short delay while oscillator restarts. device configured assert when oscillator stabilized. output voltage (VREG) Power Management Unit (PMU) configurable several minimum values between 2.4V 2.7V. VREG used provide external devices. possible disable PMU, provide externally regulated supply voltage device range 2.4V 3.6V. also provides regulated 1.8V supply logic. been designed provide excellent boost efficiency (~85%) when using Schottky diode power inductor, eliminating need external boost converter many systems where other components require boosted voltage. However, reasonable efficiencies (~75%) achieved when using very cost components such signal diodes and/or inductors. also provides configurable battery detection function which read over interface. seven thresholds between 1.8V 2.7V selected. interrupt configured assert when voltage VBAT falls below configured threshold.
Automatic Gain Control Received Signal Strength Indication (RSSI)
Clocks
12-MHz crystal (30-ppm better) directly connected between XTAL without need external capacitors. digital clock function provided, with selectable output frequencies 0.75-, 1.5-, 12-MHz. This output used clock external microcontroller (MCU) ASIC. This output enabled default, disabled. Below requirements crystal directly connected XTAL GND: Nominal Frequency: Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: Series Resistance: ohms Load Capacitance: Drive Level: µW-100
receiver features Automatic Gain Control (AGC) circuit that allows accurate reception very strong received signals (for example when operating receiver very close transmitter) switching Noise Amplifier (LNA). Alternatively, gain receiver controlled directly disabling (bit writing RX_CFG_ADR register. When cleared, receiver gain reduced approximately additional receiver attenuation added setting Attenuation (ATT) bit; this allows data reception limited devices very short ranges. RSSI register returns relative signal strength onchannel signal power. When receiving, device configured automatically measure store strength signal being received 5-bit value. When enabled, RSSI reading taken read through interface. RSSI reading taken automatically when start packet detected. addition, RSSI reading taken every time previous reading read from RSSI register, allowing background energy level given channel easily measured when RSSI read when signal being received.
Power Management
operating voltage device 1.8V 3.6V which applied VBAT pin. device shutdown
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Application Example
CYRF6936
Matrix
XOut MOSI RFbias PACtl
MISO Reset
WirelessUSB
Vreg
Vbat
Xtal
2.4V Bind
Figure 8-1. CYRF6936 Keyboard
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Register Descriptions
CYRF6936
registers read writable, except where noted. Registers written read from either individually sequential groups. single-byte read write reads writes from addressed register. Incrementing burst read write sequence that begins with address, then reads writes to/from each register address order long clocking continues. possible repeatedly read (poll) single register using non-incrementing burst read.
Table 9-1. Register Summary
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Mnemonic CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR RX_CFG_ADR Used RXOW Used SOPDET IRQEN SOFDET TXB15 IRQEN DATA CODE LENGTH TXB15 RXB16 IRQEN RXB16 Used Channel Length TXB8 IRQEN TXB0 IRQEN TXBERR IRQEN IRQEN SETTING TXBERR RXBERR IRQEN Used RXBERR Code IRQEN RXOW IRQEN IRQEN Default[1] -1001000 00000000 00000011 -000101 10111000 00000111 10010-10 00000000 00001-00000000 00000000 Used PACTL PACTL GPIO XOUT STATE Used TH64 RSSI SEED SEED STRIM Used RSVD Used RSVD RXTX Used RXACK RSVD Used AWAKE RXDR TXACK CRC0 OVRD STRIM Used RXCRC TXCRC Used RSVD Used TH32 MISO OUTV FREQ 3PIN PACTL GPIO 10100000 000-100 00000000 0000-1-000000 10101001 -0100 -01010 0-100000 10100100 00000000 00000000 -11111111 11111111 00000000 -0000 00000-0 000000000000000 Access[1] -bbbbbbb bbbbbbbb bbbbbbbb -bbbbbb rrrrrrrr bbbbbbbb bbbbb-bb brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb-bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb -bbbb -bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb -bbbb wwwww-w bbbbbbbbbbbbbbb
DATA MODE TXB8 RXB8 IRQEN HILO RXB8 CRC0 TXB0 RXB1 IRQEN FAST TURN RXB1
0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR
Data Mode
Count Length LVIRQ XSIRQ MISO PACTL Used Used HINT Used Used XOUT
XOUT XOUT Used Used MISO Used Used Used Used
Register Files 0x20 0x21 0x22 0x23 0x24 0x25 TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR Buffer File Buffer File Code File Data Code File Preamble File File -Note Note Note wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
Notes: read/write, read only, write only, used, default value undefined. SOP_CODE_ADR default 0x17FF9E213690C782. DATA_CODE_ADR default PREAMBLE_ADR default 0x333302.
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Mnemonic Default Read/Write Function Bits 6:0: Used CHANNEL_ADR Channel
CYRF6936
Address 0x00
This field selects channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 valid. default channel fast channel above frequency typically used non-overlapping WiFi systems. write this register will impact time take synthesizer settle.
Mnemonic Default Read/Write Function Bits 7:0:
TX_LENGTH_ADR Length
Address
0x01
This register sets length packet transmitted. length zero valid, will transmit packet with SOP, length fields enabled), data field. Packet lengths more than bytes will require that some data bytes written after transmission packet begun. Typically, length updated prior setting maximum length packets which framing determined 60-ppm delta smaller delta allows longer time) between transmitter receiver crystals. However, when using 15.625 kbps (64-chip SDR) data rate maximum packet length bytes.
Mnemonic Default Read/Write Function
TX_CTRL_ADR TXB15 IRQEN TXB8 IRQEN TXB0 IRQEN TXBERR IRQEN
Address IRQEN
0x02
IRQEN
Start Transmission. Setting this triggers transmission packet. Writing this flag effect. This cleared automatically packet transmission. buffer loaded either before after setting this bit. data loaded after setting this bit, length time available load buffer depends starting state (sleep, idle synth), length code packet data rate. example, starting from idle mode fast channel mode with chip codes time available (synth start) (SOP length) (length byte) there bytes buffer transmission length field, TXBERR will occur. Writing this flag effect. This cleared automatically packet transmission. Clear Buffer. Writing this register clears buffer. Writing this effect. previous packet retransmitted setting setting this bit. transmit packet loaded transmitted without setting this after packet loaded buffer. TX_BUFFER_ADR loaded after been set, then this should before loading transmit packet buffer before set. This should during same write cycle that set. Buffer Full Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. TX_IRQ_STATUS_ADR description. Transmission Complete Interrupt Enable. TX_IRQ_STATUS_ADR description. Typically, IRQEN IRQEN together. Transmit Error Interrupt Enable. TX_IRQ_STATUS_ADR description. Typically, IRQEN IRQEN together.
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Mnemonic Default Read/Write Function Used Used TX_CFG_ADR Data Code Length Data Mode
CYRF6936
Address Setting 0x03
Bits 4:3: Bits 2:0:
Data Code Length. This selects length codes (DATA_CODE_ADR) data portion packet. This ignored when data mode GFSK. chip codes. chip codes. Data Mode. This field sets data transmission mode. 1-Mbps GFSK. Mode. Mode. Mode. Setting. This field sets transmit signal strength. dBm, dBm, dBm, dBm, dBm, dBm, dBm, dBm.
Mnemonic Default Read/Write Function
TX_IRQ_STATUS_ADR TXB15 TXB8 TXB0 TXBERR
Address
0x04
state Status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Oscillator Stable Status. This when internal crystal oscillator stabilized within final value. Voltage Interrupt Status. This when voltage VBAT below threshold (see PWR_CTL_ADR). Buffer Full Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Half Empty Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Empty Interrupt Status. This time that transmit buffer empty. Buffer Error Interrupt Status. This triggered either events: When transmit buffer (TX_BUFFER_ADR) empty number bytes remaining transmitted greater than zero. When byte written transmit buffer buffer already full. This cleared setting TX_CTRL_ADR. Transmission Complete Interrupt Status. This triggered when transmission complete. transaction mode enabled, this interrupt triggered only when correctly received. transaction mode enabled then this interrupt triggered immediately after transmission last CRC. Reading this register clears this bit. Transmit Error Interrupt Status. This triggered when there error transmission. This interrupt only applicable transaction mode. triggered whenever valid packet received within timeout period. Reading this register clears this bit.
Mnemonic Default Read/Write Function SOPDET IRQEN
RX_CTRL_ADR RXB16 IRQEN RXB8 IRQEN RXB1 IRQEN RXBERR IRQEN
Address IRQEN
0x05
IRQEN
Start Receive. Setting this causes device transition receive mode. necessary, crystal oscillator synthesizer will start automatically after this set. Clearing this effect. This must until after self clears. correct exit receive mode force state. XACT_CFG_ADR description. Start Packet Detect Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Full Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. RX_IRQ_STATUS_ADR description. Packet Reception Complete Interrupt Enable. RX_IRQ_STATUS_ADR description. Receive Error Interrupt Enable. RX_IRQ_STATUS_ADR description.
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Mnemonic Default Read/Write Function RX_CFG_ADR HILO FAST TURN Used
CYRF6936
Address 0x06
RXOW
Automatic Gain Control (AGC) Enable. When this set, enabled, controlled circuit. When this cleared controlled manually using bit. Noise Amplifier (LNA) Manual Control. When (Bit cleared, this controls state receiver LNA; when set, this effect. Setting this enables LNA; clearing this disables LNA. Device current receive mode slightly lower when disabled. Receive Attenuator Enable. Setting this enables receiver attenuator. receiver attenuator used de-sensitize receiver that only very strong signals received. This should only when disabled manually disabled. HILO. When FAST TURN set, this used select whether device will high frequency channel selected, frequency. When FAST TURN enabled this also controls highlow receiver should left default value high side receive injection. Typically, this cleared during initialization. Fast Turn Mode Enable. When this set, HILO determines whether device receives data transmitted 1MHz above Synthesizer frequency below receiver synthesizer frequency. this mode allows very fast turn-around, because same synthesizer frequency used both transmit receive, thus eliminating synthesizer re-settling period between transmit receive. Note that when this set, HILO cleared, received data bits automatically inverted compensate inversion data received "image" frequency. Typically, this during initialization. Overwrite Enable. When this set, detected while receive buffer empty, then existing contents receive buffer lost, packet loaded into receive buffer. When this set, RXOW enabled. this cleared, then receive buffer over-written packet, whenever receive buffer empty conditions ignored, possible receive data until previously received packet been completely read from receive buffer. Valid Flag Enable. When this set, receive buffer store only bytes data. other half buffer used store valid flags. RX_BUFFER_ADR more detail.
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Mnemonic Default Read/Write Function RXOW RX_IRQ_STATUS_ADR SOFDET RXB16 RXB8 RXB1 RXBERR
CYRF6936
Address 0x07
state Status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Receive Overwrite Interrupt Status. This triggered when receive buffer over-written packet being received before previous packet been read from buffer. This cleared writing value this register. This condition only possible when RXOW RX_CFG_ADR set. This must written firmware before packet read from receive buffer. Start Packet Detect Interrupt Status. This when condition detected. This cleared when this register read. Receive Buffer Full Interrupt Status. This whenever receive buffer full, cleared otherwise. Receive Buffer Half Full Interrupt Status. This whenever there more bytes remaining receive buffer. Receive Buffer Empty Interrupt Status. This time that there more bytes receive buffer., cleared when receive buffer empty. Receive Buffer Error Interrupt Status. This triggered ways: When receive buffer empty there attempt read data. When receive buffer full more data received. This flag cleared when received. Packet Receive Complete Interrupt Status. This triggered when packet been received. transaction mode enabled, then this until after transmission ACK. transaction mode enabled then this soon valid packet received. This cleared when this register read. There cases when this triggered when EN=1 there error reception. Therefore, firmware should examine IRQ, IRQ, determine receive status. Receive Error Interrupt Status. This triggered when there error reception. triggered whenever packet received with CRC, unexpected detected, packet type (data ACK) mismatch, packet dropped because receive buffer still empty when next packet starts. exact cause error determined reading RX_IRQ_STATUS_ADR. This cleared when this register read.
Mnemonic Default Read/Write Function
RX_STATUS_ADR CRC0 Code
Address Data Mode
0x08
Bits
Packet Type. This when received packet packet, cleared when received packet standard packet. Receive Packet Type Error. This when packet type received what expected cleared when packet type received expected. example, data packet expected received, this will set. Unexpected EOP. This when detected before expected data length fields have been received. This cleared when pattern next packet been received. This includes case where there invalid bits detected length field length field forced Zero-seed CRC. This whenever last received packet zero seed. CRC. This when last received packet incorrect. Receive Code Length. This indicates code (DATA_CODE_ADR) length used last correctly received packet. 64-chip code, 32-chip code. Receive Data Mode. This indicates data mode last correctly received packet. 1-Mbps GFSK. Mode. Mode. Mode.
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Mnemonic Default Read/Write Function Bits 7:0: RX_COUNT_ADR Count
CYRF6936
Address 0x09
This register contains total number payload bytes received during reception current packet. After packet reception complete, this register will match value RX_LENGTH_ADR unless there packet error. This register reset 0x00 when RX_LENGTH_ADR loaded. this register read without set, then firmware should read this register until same value read twice.
Mnemonic Default Read/Write Function Bits 7:0:
RX_LENGTH_ADR Length
Address
0x0A
This register contains length field which updated with reception length field (shortly after SOFDET IRQ). there error received length field, 0x00 loaded instead error flagged.
Mnemonic Default Read/Write Function
PWR_CTRL_ADR Used
Address OUTV
0x0B
LVIRQ
Bits Bits
Power Management Unit (PMU) Enable. Setting this enables PMU. When disabled, enabled VBAT voltage above value Bits this register, VREG internally connected VBAT pin. enabled VBAT voltage below value OUTV, then will boost VREG voltage less than value PMUOP. Voltage Interrupt Enable. Setting this enables interrupt. When this interrupt enabled, VBAT voltage falls below threshold then voltage interrupt will generated. available when device sleep mode. Sleep Mode Enable. this set, will continue operate normally when device sleep mode. this set, then disabled when device sleep mode. this case, VBAT below OUTV voltage set, when device enters sleep mode VREG voltage fall VBAT voltage VREG capacitors discharge. Voltage Interrupt Threshold. This field sets voltage VBAT which triggered. 1.8V; 2.0V; 2.2V; OUTV voltage. Output Voltage. This field sets minimum output voltage PMU. 2.4V; 2.5V; 2.6V; 2.7V. When active, voltage output VREG will never less this voltage provided that total load VREG less than specified maximum value, voltage VBAT greater than specified minimum value.
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Mnemonic Default Read/Write Function Bits XOUT XTAL_CTRL_ADR XSIRQ Used Used
CYRF6936
Address FREQ 0x0C
Bits 2:0:
XOUT Function. This field selects between different functions XOUT pin. Clock frequency XOUT FREQ; Active Control; Radio data serial stream. this option selected configured 3-wire mode then MISO will output serial clock associated with this data stream; GPIO. disable this output, GPIO mode, GPIO state IO_CFG_ADR. Crystal Stable Interrupt Enable. This enables interrupt. When enabled, this interrupt generates event when crystal stabilized after device woken from sleep mode. This event cleared writing zero this bit. XOUT Frequency. This field sets frequency output XOUT when XOUT MHz; MHz, MHz, MHz, 0.75 MHz; other values defined.
Mnemonic Default Read/Write Function
IO_CFG_ADR MISO XOUT PACTL PACTL GPIO
Address 3PIN
0x0D
GPIO
Drive Strength. Setting this configures open drain output. Clearing this configures standard CMOS output, with output drive voltage being equal voltage. Polarity. Setting this configures signal polarity active high. Clearing this configures signal polarity active low. MISO Drive Strength. Setting this configures MISO open drain output. Clearing this configures MISO standard CMOS output, with output drive voltage being equal voltage. XOUT Drive Strength. Setting this configures XOUT open drain output. Clearing this configures XOUT standard CMOS output, with output drive voltage being equal voltage. PACTL Drive Strength. Setting this configures PACTL open drain output. Clearing this configures PACTL standard CMOS output, with output drive voltage being equal voltage. PACTL Function. When this PACTL available GPIO. Mode. When this cleared, interface acts standard 4-wire Slave interface. When this set, interface operates "3-Wire Mode" combining MISO MOSI same (SDAT), MISO available GPIO pin. Function. When this cleared, asserted when active; polarity this signal configurable POL. When this set, available GPIO pin, function multiplexed onto MOSI pin. this case signal state presented MOSI whenever signal inactive (HIGH).
Mnemonic Default Read/Write Function XOUT
GPIO_CTRL_ADR PACTL XOUT MISO
Address PACTL
0x0E
MISO
When using GPIO input, output mode should open drain, written corresponding output register bit. XOUT Output. When XOUT configured GPIO, state this sets output state XOUT pin. MISO Output. When MISO configured GPIO, state this sets output state MISO pin. PACTL Output. When PACTL configured GPIO, state this sets output state PACTL pin. Output. When configured GPIO, state this sets output state pin. XOUT Input. When XOUT configured GPIO, state this reflects voltage XOUT pin. MISO Input. When MISO configured GPIO, state this reflects voltage MISO pin. PACTL Input. When PACTL configured GPIO, state this reflects voltage PACTL pin. Input. When configured GPIO, state this reflects voltage pin.
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Mnemonic Default Read/Write Function Used XACT_CFG_ADR STATE
CYRF6936
Address 0x0F
Bits 4:2:
Bits 1:0:
Acknowledge Enable. When this set, packet automatically transmitted whenever valid packet received; this case device considered transaction mode. After transmission packet, device automatically transitions STATE. When this cleared, device transitions directly STATE immediately after packet transmission. When this cleared device transitions STATE immediately after transmission packet. Force State. Setting this forces transition state STATE. setting desired STATE same time setting this device forced immediately transition from current state other state. This automatically cleared upon completion. Transaction State. This field defines mode which device transitions after receiving transmitting packet. Sleep Mode; Idle Mode; Synth Mode (TX); Synth Mode (RX); Mode. normal use, this field will typically when device transmitting packets, when device receiving packets. Note that when device transitions receive mode STATE, receiver must still armed setting before device begin receiving data. Timeout. When device configured transaction mode, this field sets timeout period after transmission packet during which must correctly received order prevent transmit error condition from being detected. This timeout period expressed terms number SOP_CODE_ADR Code lengths; set, then timeout period this value multiplied cleared then timeout this value multiplied 12x; SOP_CODE_ADR Code length.
Mnemonic Default Read/Write Function
FRAMING_CFG_ADR
Address
0x10
Bits
Enable. When this set, each transmitted packet begins with field, only packets beginning with valid field will received. this cleared, field will generated when packet transmitted, packet reception will begin whenever successive correlations against DATA_CODE_ADR code detected. Code Length. When this SOP_CODE_ADR Code length chips. When this cleared SOP_CODE_ADR Code length chips. Packet Length Enable. When this 8-bit value contained TX_LENGTH_ADR transmitted immediately after field. receive mode, bits immediately following field interpreted length packet. When this cleared packet length field transmitted. Correlator Threshold. This receive data correlator threshold used when attempting detect symbol. There threshold SOP_CODE_ADR Code. This (single) threshold applied independently each SOP1 SOP2 fields. There then thresholds each 64-chip DATA_CODE_ADR Codes chip DATA_CODE_ADR Codes. When set, bits this field used. When cleared, most significant disregarded.
Mnemonic Default Read/Write Function Bits 3:0: Used
DATA32_THOLD_ADR Used Used Used TH32
Address
0x11
Chip Data Code Correlator Threshold. This register sets correlator threshold used DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR)
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Mnemonic Default Read/Write Function Bits 4:0: Used DATA64_THOLD_ADR Used Used TH64
CYRF6936
Address 0x12
Chip Data Code Correlator Threshold. This register sets correlator threshold used DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR)
Mnemonic Default Read/Write Function Used
RSSI_ADR RSSI
Address
0x13
Received Signal Strength Indicator (RSSI) reading taken automatically when symbol detected. addition, RSSI reading taken whenever RSSI_ADR read. contents this register valid after device configured receive mode until either symbol detected, register read. desired measure background signal strength channel before packet been received then should perform "dummy" read this register, results which should discarded. This "dummy" read will cause RSSI measurement taken, therefore subsequent readings register will yield valid data. RSSI Reading. When set, this indicates that reading RSSI field taken when symbol detected. When cleared, this indicates that reading stored RSSI field triggered previous read this register. State. This indicates state when RSSI reading taken. When cleared, this indicates that disabled when RSSI reading taken; this indicates that enabled when RSSI reading taken. RSSI Reading. This field indicates instantaneous strength signal being received time that RSSI reading taken. larger value indicates stronger signal. signal strength measured signal configured channel, measured after stage.
Bits 4:0:
Mnemonic Default Read/Write Function
EOP_CTRL_ADR HINT
Address
0x14
set, then contents this register have effect. cleared, then this register used configure (end packet) condition detected. Hint Enable. When set, this will cause detected correlations have been detected number symbol periods HINT field last received bytes match calculated previously received bytes. this mode reduces chance non-correlations middle packet from being detected condition. Hint Symbol Count. minimum number symbols consecutive non-correlations which last bytes checked against calculated detect condition. Symbol Count. condition deemed exist when number consecutive non-correlations detected.
Bits Bits 4:0:
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Mnemonic Default Read/Write Function CRC_SEED_LSB_ADR
CYRF6936
Address 0x15
SEED
seed allows different devices generate recognize different CRCs same payload data. transmitter receiver randomly selected seed, probability correctly receiving data intended different receiver 1/65535, even other transmitter/receiver using same SOP_CODE_ADR Codes channel. Bits 7:0: Seed Least Significant Byte. starting value calculation.
Mnemonic Default Read/Write Function Bits 7:0:
CRC_SEED_MSB_ADR
Address
0x16
SEED Seed Most Significant Byte. starting value calculation.
Mnemonic Default Read/Write Function Bits 7:0:
TX_CRC_LSB_ADR
Address
0x17
Calculated LSB. that calculated last transmitted packet. This value only valid after packet transmission complete.
Mnemonic Default Read/Write Function Bits 7:0:
TX_CRC_MSB_ADR
Address
0x18
Calculated MSB. that calculated last transmitted packet. This value only valid after packet transmission complete.
Mnemonic Default Read/Write Function Bits 7:0:
RX_CRC_LSB_ADR
Address
0x19
Received LSB. field from last received packet. This value valid whether field matched calculated received packet.
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Mnemonic Default Read/Write Function Bits 7:0: RX_CRC_MSB_ADR
CYRF6936
Address 0x1A
Received MSB. field from last received packet. This value valid whether field matched calculated received packet.
Mnemonic Default Read/Write Function
TX_OFFSET_LSB_ADR STRIM
Address
0x1B
Bits least significant bits synthesizer offset value. This 12-bit complement signed number which used offset transmit frequency device ±1.5MHz. positive value increases transmit frequency, negative value reduces transmit frequency. value increases transmit frequency 732.6Hz; value decreases transmit frequency 732.6Hz. value 0x0555 increases transmit frequency 1MHz; value 0xAAB decreases transmit frequency MHz. Typically, this register loaded with 0x55 during initialization. Synthesizer offset effect receive frequency.
Mnemonic Default Read/Write Function Bits 3:0: Used
TX_OFFSET_MSB_ADR Used Used Used
Address STRIM
0x1C
most significant bits synthesizer trim value. Typically, this register loaded with 0x05 during initialization.
Mnemonic Default Read/Write Function RSVD
MODE_OVERRIDE_ADR RSVD AWAKE Used
Address Used
0x1D
Typically, user firmware only uses this register. Bits Bits Bits Bits Bits Reserved. User firmware should this bit. Reserved. User firmware should this bit. Manually Initiate Synthesizer. Setting this forces synthesizer start. Clearing this effect. this operate correctly, oscillator must running before this set. Force Awake. Force device sleep mode. Setting both bits this field forces oscillator keep running times regardless STATE setting. Clearing both these bits disables this function. Reset. Setting this forces full reset device. Clearing this effect.
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Mnemonic Default Read/Write Function RX_OVERRIDE_ADR RXTX RXACK RXDR CRC0 RXCRC
CYRF6936
Address Used 0x1E
This register provides ability over-ride some automatic features device. Bits Bits Bits Bits Bits Bits Bits When this set, device uses transmit synthesizer frequency rather than receive synthesizer frequency given channel when automatically entering receive mode. When this enabled, transmission packet delayed Force Expected Packet Type. When this set, device receive mode, device configured receive packet data rate defined TX_CFG_ADR. Force Receive Data Rate. When this set, receiver will ignore data rate encoded symbol, will receive data data rate defined TX_CFG_ADR. Reject packets with zero-seed CRC. Setting this causes receiver reject packets with zero-seed, accept only packets with that matches seed CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR. checker disabled. packets with enabled received, will treated payload data stored receive buffer. Accept CRC. Setting this causes receiver accept packets with that match seed CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR. sent regardless condition received CRC.
Mnemonic Default Read/Write Function
TX_OVERRIDE_ADR RSVD TXACK OVRD TXCRC
Address RSVD
0x1F
This register provides ability over-ride some automatic features device. Bits Bits Bits Bits Bits Bits Bits Bits When this set, device uses receive synthesizer frequency rather than transmit synthesizer frequency given channel when automatically entering transmit mode. Force Preamble. When this set, device will transmit continuous repetition preamble pattern (see PREAMBLE_ADR) after set. This mode useful some regulatory approval procedures. Reserved. write this bit. Transmit Packet. When this set, device sends packet when set. Override. TX_CFG_ADR determine data rate used when transmitting packet. Disable Transmit CRC. When set, field present transmitted packets. Reserved. write this bit. Data Invert. When this transmit bitstream inverted.
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Register Files
CYRF6936
Files written read from using non-incrementing burst read write transactions. most cases reading file destructive; file must completely read, otherwise contents altered.
Mnemonic Length Default TX_BUFFER_ADR Bytes Address 0x20
transmit buffer FIFO. Writing this file adds byte packet being sent. Writing more bytes this file than packet length TX_LENGTH_ADR will have effect, these bytes will lost after successful packet transmission. possible load two-eight byte packets into this register, then transmit them sequentially enabling twice; this would have effect sending first eight bytes twice.
Mnemonic Length Default
RX_BUFFER_ADR Bytes
Address
0x21
receive buffer FIFO. Received byte read from this file register time that empty, when reading from this file register before packet been completely received care must taken ensure that error packets (for example with CRCs) handled correctly. When receive buffer configured overwritten packets (the alternative packets discarded receive buffer empty), similar care must taken verify after packet been read from buffer that part overwritten newly received packet while this file register being read. When RX_CFG_ADR set, bytes this file register alternate-the first byte read data, second byte valid flags each first byte, third byte data, fourth byte valid flags, etc. modes valid flag correlation coefficient exceeded correlator threshold, cleared not. mode, valid flags byte indicates whether correlation coefficient corresponding received symbol exceeded threshold. seven LSBs contain height correlation peak.
Mnemonic Length Default
SOP_CODE_ADR Bytes
0x17FF9E213690C782
Address
0x22
When using chip Codes, only first four bytes this register used; order complete file write process, these four bytes must followed four bytes "dummy" data. However, class codes known "multiplicative codes" used; there chip codes with good auto-correlation cross-correlation properties where least significant chips themselves have good autocorrelation cross-correlation properties when used 32-chip codes. this case same eight-byte value loaded into this file used both chip chip symbols. When reading this file, eight bytes must read; fewer than eight bytes read from file, contents file will have been rotated number bytes read. This applies writes, well.
Mnemonic Length Default
DATA_CODE_ADR Bytes
Address
0x23
This file ignored when using device 1-Mbps GFSK mode. chip mode, only first eight bytes used; order complete file write process, these eight bytes must followed eight bytes "dummy" data. 32-chip mode, only four bytes used, chip mode only eight bytes used. 64-chip modes, sixteen bytes used. Certain sixteen-byte sequences have been calculated that provide excellent auto-correlation cross-correlation properties, recommended that such sequences used; default value this register such sequence. some applications, devices same DATA_CODE_ADR codes, devices systems addressed using different SOP_CODE_ADR codes; such cases never necessary change contents this register from default value. When reading this file, sixteen bytes must read; fewer than sixteen bytes read from file, contents file will have been rotated number bytes read. This applies writes, well.
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Mnemonic Length Default PREAMBLE_ADR Bytes 0x333302
CYRF6936
Address 0x24
byte number repetitions preamble sequence that transmitted. preamble disabled writing 0x00 this byte. byte Least significant eight chips preamble sequence byte Most significant eight chips preamble sequence using chip communicate with CYWUSB69xx devices, number repetitions four optimum performance When reading this file, three bytes must read; fewer than three bytes read from file, contents file will have been rotated number bytes read. This applies writes, well.
Mnemonic Length Default
MFG_ID_ADR Bytes
Address
0x25
byte: bits version bits vendor high bits Year through bytes: Manufacturing device. minimize current consumption (default), execute "dummy" single-byte write this address with zero data stage after contents have been read.
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10.0 Absolute Maximum Ratings
CYRF6936
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage power supply relative .-0.3V +3.9V Voltage Logic Inputs[5] -0.3V +0.3V Voltage applied Outputs High-Z State -0.3V +0.3V
Static Discharge Voltage (Digital)[6]. 1500V Static Discharge Voltage (RF)[6] 1100V Latch-up Current .+200 -200
11.0
Operating Conditions
.2.4V 3.6V VIO.1.8V 3.6V VBAT .1.8V 3.6V (Ambient Temperature Under Bias). +70°C Ground Voltage FOSC (Oscillator Crystal Frequency)
12.0 Characteristics
Parameter Description Conditions Min. Typ. Max. Unit
VBAT
Battery Voltage output voltage output voltage Voltage Voltage Output High Voltage condition Output High Voltage condition Output Voltage Input High Voltage Input Voltage Input Leakage Current Input Capacitance
0-70°C 2.4V mode 2.7V mode 0-70°C -100.0 -2.0
0.7VIO -0.3 2.45 2.75
VREG[7] VREG[7] VOH1 VOH2 IDLE Isynth (Avg)[8]
0.3VIO
except XTAL, RFN, RFP, RFBIAS 2-way, 4-bytes/8 VBAT 2.4V VBAT 2.4V VBAT 2.4V VBAT 2.4V, dBm) VBAT 2.4V, dBm) VBAT 2.4V, dBm) VBAT 2.4V VBAT 2.4V
0.26
Average Sleep Mode Radio off, XTAL active during Synth start during Transmit during Transmit during Transmit during Receive during Receive
Notes: permissible connect voltages above inputs through series resistor limiting input current 1mA. This can't done during sleep mode. timing guaranteed. Human Body Model (HBM). VREG depends battery input voltage. This average current drawn from battery device when transmitting 4-byte packet once every 8ms, including current drawn while starting crystal, starting synthesizer, transmitting packet (including CRC), changing receive mode, receiving handshake, when using 1-Mbps GSFK data rate. device sleep except during this transaction.
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13.0 Characteristics
Parameter Description Min. Typ. Table 13-1. Interface[10]
CYRF6936
Max.
Unit
tSCK_CYC tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tSS_SU tSS_HLD
Clock Period Clock High Time Clock Time Input Data Set-up Time Input Data Hold Time Output Data Valid Time Slave Select Set-up Time before first positive edge SCK[11] Slave Select Hold Time after last negative edge
238.1
MOSI
tSCK_LO
tSS_SU tDAT_SU
tDAT_H
tSS_HLD
tDAT_VAL
Figure 13-1. Timing Diagram
Notes: values guaranteed voltage exceed VCC. FOSC ppm, 3.3V 25°C. must start low, otherwise success transactions guaranteed.
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14.0 Characteristics
Table 14-1. Radio Parameters Parameter Description Conditions Min. Typ.
CYRF6936
Max.
Unit
Frequency Range Note Radio Receiver 25°C, 3.0V, fosc ppm, XOUT off, Threshold 10-3) Sensitivity GFSK 1E-3 Sensitivity Sensitivity Maximum Received Signal Maximum Received Signal RSSI value PWRin RSSI value PWRin RSSI value PWRin
Interference Performance
2.400
2.497
1E-3 (250-kbps)
Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Image Frequency Interference, Image Adjacent MHz) interference in-band image frequency, image MHz-2399 MHz, except (FO/N FO/N±1 MHz)[13] 2498 -12.75 GHz, Intermodulation
Spurious Emission
[13] except (FO*N FO*N±1 MHz)
Out-of-Band Blocking Interference Signal Frequency
dBm, 5,10
MHz-1 GHz-12.75
Radio Transmitter 25°C, 3.0V, fosc ppm)
Maximum Transmit Power Maximum Transmit Power Power Control Range Power Range Control Step Size
Frequency Deviation Frequency Deviation
seven steps, monotonic Code Pattern 10101010 Code Pattern 11110000 100-kHz ResBW,
Error Vector Magnitude (FSK error) Occupied Bandwidth Initial Frequency Offset
In-band Spurious
%rms
Second Channel Power MHz) Third Channel Power MHz)
Non-Harmonically Related Spurs
MHz-12.75
Notes: Subject regulation. Tuned Frequency, Integer.
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Table 14-1. Radio Parameters (continued) Parameter Description Harmonic Spurs Conditions Min. Typ.
CYRF6936
Max. Unit
Second Harmonic Third Harmonic Fourth Greater Harmonics GFSK data rate Synth Settle Synth Settle Link turn-around time Worst case channels Fast channels When FAST TURN
Mbps
15.0 Test Loads Waveforms Digital Pins Test Loads
OUTPUT INCLUDING SCOPE OUTPUT
Test Load
OUTPUT
INCLUDING Typical SCOPE INPUT PULSES
Parameter
1071 3.00
Unit
Rise time: V/ns Equivalent
Fall time: V/ns
EQUIVALENT OUTPUT
Figure 15-1. Test Loads Waveforms Digital Pins
16.0
Ordering Information
Radio Transceiver Package Name Package Type Quad Flat Package Leads Lead-Free Operating Range Commercial
Table 16-1. Ordering Information Part Number CYRF6936-40LFXC
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17.0 Package Description
VIEW SIDE VIEW BOTTOM VIEW
CYRF6936
0.08[0.003] 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] 0.60[0.024] DIA. 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF.
0.18[0.007] 0.28[0.011] PIN1 0.20[0.008] 0.45[0.018]
5.70[0.224] 5.80[0.228]
5.90[0.232] 6.10[0.240]
0.30[0.012] 0.50[0.020]
(PAD SIZE VARY DEVICE TYPE)
0°-12°
0.50[0.020] 4.45[0.175] 4.55[0.179]
0.24[0.009] 0.60[0.024]
(4X)
SEATING PLANE
51-85190-**
Figure 17-1. 40-pin Lead-Free LY40
recommended dimension size EPAD underneath (width length). This document subject change, found contain errors omission changes parameters. feedback technical support regarding Cypress WirelessUSB products please contact Cypress www.cypress.com. WirelessUSB, PSoC, enCoRe trademarks Cypress Semiconductor. product company names mentioned this document trademarks their respective holders.
Document 38-16015 Rev.
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Cypress Semiconductor Corporation, 2005. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges.
4.45[0.175] 4.55[0.179]
E-PAD
Document History Page
Description Title: CYRF6936 WirelessUSBLP 2.4GHz Radio Document Number: 38-16015 REV. Issue Date Orig. Change Description Change
CYRF6936
307437 377574
data sheet Preliminary release- updated Section Features updated Section Applications added Section Applications Support updated Section Functional Descriptions updated Section Description added Figure updated Section Functional Overview added Section Functional Block Overview added Section Register Descriptions updated Section 10.0 Absolute Maximum Ratings updated Section 11.0 Operating Conditions updated Section 12.0 Characteristics updated Section 13.0 Characteristics updated Section 14.0 Characteristics added Section 16.0 Ordering Information ES-10 update- changed part updated Section Register Descriptions updated Section 12.0 Characteristics updated Section 14.0 Characteristics ES-10 update- updated Section Functional Descriptions updated Section Descriptions updated Section Functional Overview updated Section Functional Block Overview updated Section Register Descriptions updated Section 10.0 Absolute Maximum Ratings updated Section 11.0 Operating Conditions updated Section 14.0 Characteristics
398756
412778
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