AX07CF192 Product Summary Preliminary Data Sheet August, 2003
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AX07CF192 Product Summary
Preliminary Data Sheet August, 2003
www.aeroflex.com/ARM7
ARM7® Microcontroller with Embedded Flash
FEATURES ARM7TDMI Core 192K Flash SRAM 10-bit, 5-channel Power Management Unit (PMU) 2-channel UART 8-bit Watchdog Timer 16-bit, 6-channel Timers/PWM Ports External Interrupt pins Internal Interrupts 50MHz Maximum Operating Frequency 3.3V Operation* 100-pin TQFP package 0.35u CMOS 430mW power (@50MHz) -40o 85oC Operating Temperature additional supply required programming flash memory. in-circuit programming required this supply required. Factory programming available.
General Description
This 32-bit with embedded flash memory based ARM7TDMI core. AX07CF192 contains following functions: 192Kbytes Flash memory, bytes SRAM, channel 16-bit Timer, Watch Timer, 2-channel UART, Programmable Priority Interrupt Controller, bits PIO, Controller including Chip select logic. These functions implemented using AMBA On-Chip Modular Architecture. major functional blocks described more detail following pages. complete Users Manual downloaded from website www.aeroflex.com/ARM7.
AVDD AVREF AN0/P70 AN0/P71 AN0/P72 AN0/P73 AN0/P74 TIOCA5/nIRQ6/P76 TIOCB5/nIRQ7/P77 nIRQ0/P80 nCS3/nIRQ1/P81 nCS2/nIRQ2/P82 nCS1/nIRQ3/P83 nCS0/P84 TCLKA/PA0 TCLKB/PA1 TCLKC/TCIOA0/PA2 TCLKD/TCIOB0/PA3 A23/TIOCA1/PA4 A22/TIOCB1/PA5 A21/TIOCA2/PA6 A20/TIOCB2/PA7
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nCS7/TIOCA3/PB0 nCS6/TIOCB3/PB1 nCS5/TIOCA4/PB2 nCS4/TIOCB4/PB3 TMS/PB4 TDO/PB5 TDI/PB6 TCK/PB7 XFVPPD/XP96 TxD0/P90 RxD0/P91 TxD1/P92 RxD1/P93 nIRQ4/P94 nIRQ5/P95 D0/P40 D1/P41 D3/P43 D4/P44 D5/P45 D6/P46
A14/P26 A15/P27 A16/P50 A17/P51 A18/P52 A19/P53 nWAIT/P60 nBREQ/P61 nBACK/P62 CLKO/P67 nSTBY nRES nTRST/P97 XTALOUT XTALIN nAS/P63 nRD/P64 nHWR/P65 nLWR/P66 MODE0 MODE1 MODE2
AX07CF192
(Rev.
2001.02
A13/P25 A12/P24 A11/P23 A10/P22 A9/P21 A8/P20 A7/P17 A6/P16 A5/P15 A4/P14 A3/P13 A2/P12 A1/P11 A0/P10 D15/P37 D14/P36 D13/P35 D12/P34 D11/P33 D10/P32 D9/P31 D8/P30 D7/P47
3-AX07CF192-8/03
Block Diagram
Crystal
Arbiter
CONTROLLER
ARM7TDMI
TIC*
INTC SRAM 4kbyte Flash Memory 192kbyte TIMER
UART Multi-Function
Operation Modes
AX07CF192 operation modes shown Table external functionality changed setting external Mode and/or configuring on-chip registers. Modes enabling external data buses will have corresponding reduction pins available general purpose ports. When changing modes memory remapped
*TIC: Test Interface Controller
accordingly. usual mode operation Flash-boot mode (modes when device will boot from on-chip flash. Boot mode (modes when user program UART available, such first time on-board programming performed, user program mode accidentally erased.
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2-AX07CF192-6/03
Table Mode Description MODE
MODE DESCRIPTION
Reserved Test Boot from external 8-bit data with 16MBytes Address Range Boot from external 16-bit data with 16MBytes Address Range Flash-boot mode with 16-bit data Flash-boot mode (microcomputer mode) UART-boot mode with 16-bit data UART-boot mode (microcomputer mode) Utilizes ARM7TDMI embedded processor High performance 32-bit RISC architecture High density instruction (THUMB code) Fully static operation: 50MHz 3-stage pipeline architecture (Fetch, decode, execution stages) Enhanced software toolkit THUMB code able provide code size ARM, 160% performance equivalent processor connected 16-bit memory system.
Flash memory reprogrammed mode, however modes control program program/erase operations must first transferred executed from RAM, since flash memory itself cannot read while being programmed erased. Mode pins also determine only on-chip memory used (microcomputer mode, modes external memory also available (modes (Modes bypass on-board flash completely, external memory program storage).
ARM7 TDMI Core
ARM7 TDMI member family generalpurpose 32-bit microprocessors, which offer high performance very power consumption. This processor employs unique architectural strategy known THUMB, which makes ideally suited high volume applications with memory restrictions applications where code density issue. idea behind THUMB super reduced instruction set. Essentially, ARM7TDMI instruction sets, standard 32-bit 16-bit THUMB set. THUMB set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because THUMB code operates same 32-bit register code. 32bit RISC architecture power consumption ARM7TDMI core with: On-chip ICEbreaker debug support 32-bit hardware multiplier Thumb decompressor
Controller
AX07CF192 on-chip controller that manages external address space divided into eight areas, which consist SRAM, ROM, Flash-memory off-chip peripheral devices. specifications, such width number access states, independently each area, enabling multiple memories connected easily. 8-bit access 16-bit access selected each area THUMB mode, only 16-bit accessing external code memory allowed) Active-low chip select signals (nCS0 nCS7) output areas specifications independently each area Support Little-Endian Memory Format Variable wait states waits) transfers extended using nWAIT signal. nWAIT signal active-low Each area 16MB (when SM='0' PMU), (when SM='1' PMU) size programmed individually.
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3-AX07CF192-8/03
Power Management Unit
block used optimize device power dissipation. consists clock controller reset controller. user control internal clocks embedded peripherals main clock setting registers. four reset sources: external power-on reset, soft-reset PMU, soft-reset overflow reset WDT. status registers that hold reset value status.To improve power management, support power-saving mode included whereby clocks disabled dropped lower frequency). Interrupt Controller Asynchronous interrupt controller external interrupt sources internal interrupt sources interrupt latency Selectable level- edge-trigger interrupt source inputs Each interrupt source output signal maskable Selectable output paths (IRQ FIQ) each interrupt source Watchdog Timers Watchdog timer mode interval timer mode Generates interrupt signal interrupt controller either mode Outputs reset signals (Power Management Unit) Eight counter clock sources Selection whether reset chip internally types reset signal: power-on reset manual reset AX07CF192 one-channel watchdog timer (WDT) monitoring system operations. system locks timer counter overflows without being rewritten correctly CPU, reset signal output PMU. When this watchdog function needed, used interval timer. interval timer mode, interval timer interrupt generated each counter overflow. clock generator that produces eight counter clock sources. clock signals obtained dividing down frequency system clock. Users select eight internal clock sources input counter. General Purpose Timer Unit channels with 16-bit counters different pulse inputs different pulse outputs Independent functionality with general registers Compare match waveform output function
Input capture function Counter-clearing function compare match input capture mode Synchronizing mode mode interrupt sources Selectable internal clock sources external clock sources AX07CF192 general-purpose timer unit (GPTU) with channels 16-bit timers. There counter operation modes: free-running mode periodic mode. Each channel independent operating modes. There common functions each channel: counter operation, input capture, compare match, PWM, synchronized clear write.
UARTs
UART module functionally identical 16550. UART into alternate mode (FIFO mode) relieve excessive software overhead. this mode internal FIFOs activated allowing bytes plus bits error data byte RCVR FIFO, stored both receive transmit modes. logic chip minimize system overhead maximize system efficiency. UART performs serial-to-parallel conversion data characters received from peripheral device parallel-to-serial conversion data characters received from CPU. read complete status UART time during operation. Status information includes type condition transfer operations performed UART, well error conditions (parity, overrun, framing, break interrupt). UART includes programmable baud rate generator that capable dividing timing reference clock input divisors 65535 producing clock driving internal transmitter logic. Provisions also included this clock drive receiver logic. addition baud rate generation, UART also includes clock divider which divides input system clock setting 8-bit divider register. UART processor interrupt system. Interrupts programmed user's requirements, minimizing computing required handle communications link. standard 16450/16550 UART features modem control signals which duplicated internally, concealed from outside.
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2-AX07CF192-6/03
Capable running existing 16550 software. After reset, registers identical 16450 register set. FIFO mode transmitter receiver each buffered with 16-byte FIFO's reduce number interrupts presented CPU. Adds deletes standard asynchronous communication bits (start, stop, parity) from serial data. Hold shift registers 16450 mode eliminate need precise synchronization between serial data. Independently controlled transmit, receive, line status data interrupts. Programmable baud generator divides input clock 65535 generates clock Input clock divider setting 8-bit divider register. Independent receiver clock input. Fully programmable serial-interface characteristics: 8-bit characters Even, odd, no-parity generation detection 1.5- 2-stop generation detection Baud generation 256k baud) False start detection. Complete status reporting capabilities. Line break generation detection. Internal diagnostic capabilities. Loopback controls communications link fault isolation Full prioritized interrupt system controls.
Data read from on-chip SRAM, data written SRAM single clock cycle through bus. SRAM implemented single module with 32-bit data control lines. single cycle access makes SRAM ideal program area, stack area, data area, which requires high-speed access. contents on-chip SRAM retained both standby power-down modes. Since on-chip connected internal 32-bit data bus, written read word access. also written read half-word byte access.
On-chip Flash Memory
AX07CF192 192-Kbytes on-chip flash memory. flash memory connected 16-bit data bus. accesses both half-word word data several states depending wait register value. Memory organization (1.5Mbit) Operating Voltage 3.0V 3.6V (Vcc) Programming Voltage: 4.5~5.5V (FTVPPD) Random access time 90nsec Program time typ. 100usec/word Erase block size 32KB 24KB Block erase time typ. 1.5sec/32KB (pre program erase) Multiple block erase command support (maximum blocks) Endurance Min. cycles Both on-chip (user/boot mode) on-board (PROM mode) program/erase support Bi-directional Data Operating current Standby mode 10uA Read/Program/Erase mode max. 20mA Flash memory programmed either externally (UART boot mode) from user program (Flash boot mode). latter case control program erase/program must first transferred executed from RAM.
General Purpose Ports
GPIO peripheral which provides bits programmable input /output divided into ports; port port port port port port port port port port port Each configurable either input output. system reset, ports default inputs ports outputs. Each port data register data direction register. data direction register defines whether each individual input output. data register used read value GPIO pins, both input output, well values pins that configured outputs. input pins tolerant.
Analog-to-Digital Converter
AX07CF192 10-bit successive-approximation converter with five analog input channels. input channels multiplexed into converter. serial output configured interface with standard shift registers. differential analog voltage input allows common-mode rejection offset analog zero input voltage value. voltage reference input adjusted effectively scale input voltage span while retaining full bits resolution.
On-chip SRAM
AX07CF192 4-kbytes high-speed static onchip. connected 32-bit (Advanced System Bus) bus. accesses byte data, half-word data, word data cycle, making useful rapid data transfer.
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3-AX07CF192-8/03
10-bit resolution input channels Reference voltage input (AVREF) scale analog input range High-speed conversion: minimum channel (with 8MHz clock) Analog input range: AVREF Five 10-bit data registers conversion results transferred individual data registers each channel. Sample-and-hold function Optional Interrupt
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Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex) reserves right make changes products services herein time without notice. Consult Aeroflex authorized sales representative verify that information this data sheet current before using this product. Aeroflex does assume responsibility liability arising application product service described herein, except expressly agreed writing Aeroflex; does purchase, lease, product service from Aeroflex convey license under patent rights, copyrights, trademark rights, other intellectual rights Aeroflex third parties.
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