Communication Edition 2005-09-13 Published Infineon Technologies

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AMD8513
Communication
Edition 2005-09-13 Published Infineon Technologies St.-Martin-Strasse 81669 Germany Infineon Technologies 2005. Rights Reserved. Attention please! information herein given describe certain components shall considered guarantee characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
USB-to-10/100 Mbps Ethernet Controller Revision History: 2005-09-13, Rev. 1.21 Previous Version: Page/Date 2001-12 2002-01 2002-06 Subjects (major changes since last revision) Rev. 0.1: Preliminary Rev. 1.0: Rearrange Rev. 1.1: 1.VAARef power pin, input 2.GNDRef power pin, input 3.Modify Assignment Diagram 4.Make small correction P10, P13, P17, P19, P35, P37, 1.2: 1.Remove power consumption mode 2.Change power consumption P.33 3.Add layout guide Appendix
2002-06
2005-09-13 1.21: when changed Infineon format
Trademarks ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®, 10BaseV®, 10BaseVX® registered trademarks Infineon Technologies 10BaseSTM, EasyPortTM, VDSLiteare trademarks Infineon Technologies Microsoft® registered trademark Microsoft Corporation, Linux® Linus Torvalds, Visio® Visio Corporation, FrameMaker® Adobe Systems Incorporated.
Template: template_A4_3.0.fm 2005-01-17
ADM8513 Data Sheet
Table Contents
Table Contents
Table Contents List Figures List Tables 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 3.1.1 3.1.2 4.2.1 4.2.2 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.1.12 5.1.13 5.1.14 5.1.15 Product Overview Package Information Features Interface Description Assignment Diagram Description Function Host Interface Physical Interface Interface EEPROM Interface Miscellaneous POWER POWER Block Diagram Function Description Interface Command Decoder FIFO Controller FIFO FIFO 10/100M Ethernet Device Endpoint Operation Endpoint Endpoint Bulk Endpoint Bulk Endpoint Interrupt Commands Command Register (Vendor Specific) Single/Burst Read Register (Vendor Specific) Burst Write Status (Device) Status (Interface) Status (EP0) Status (EP1) Bulk Status (EP2) Bulk Status (EP3) Interrupt Descriptor (Device) Total 18-byte Descriptor (Configuration) Total 39-byte Descriptor (String) Index LanguageID Code Descriptor (String) Index Manufacture Descriptor (String) Index Product Descriptor (String) Index Serial Configuration
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Table Contents 5.1.16 5.1.17 5.1.18 5.1.19 5.1.20 6.1.1 6.2.1 7.3.1 10.1 Interface Clear Feature (Device) Remote Wakeup Feature (Device) Remote Wakeup Clear Feature Halt Feature Halt Registers Description System Registers System Registers Registers Description Registers Electrical Characteristics Absolute Maximum Ratings Operating Condition Specifications Interface Specification
EEPROM Interface Specification Recommended Operating Conditions GPIO Interface Specification Timing Reset Timing Interface Timing EEPROM Interface Timing
EEPROM Interface Example Example Package Appendix Layout Guide References Terminology
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
List Figures
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Diagram Block Diagram Packet Form when Receive Packet Form when Transmit EEPROM Interface Timing Package Placement Placement Trace Routing Trace Routing Trace Routing Power Ground Power Ground Power Ground
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
List Tables
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Data Sheet Abbreviations Type Abbreviations Buffer Type Host Interface Physical Interface Interface Mapping between action EEPROM 0B[7:6] setting EEPROM Interface Miscellaneous Power Power Received Status Packet Format Interrupt Packet Form Interrupt Packet Form Setup Stage Data Stage Setup Stage Data Stage Setup Stage Setup Stage Transfer Transfer Transfer Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage: wLength Field Specifies Total byte Count Return Data Stage: wLength Field Specifies Total byte Count Return Data Stage: wLength Field Specifies Total byte Count Return Setup Stage Configuration Descriptor Configuration Descriptor Interface Descriptor Descriptor Descriptor Descriptor Setup Stage Data Stage Setup Stage Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Data Stage Setup Stage Setup Stage Setup Stage Setup Stage Registers Address Space Registers Overview Register Access Types Registers Clock DomainsRegisters Clock Domains Reserved Registers Wakeup Frame Mask Registers Wakeup Frame Mask Registers Wakeup Frame Mask Registers Registers Address SpaceRegisters Address Space Registers Overview Register Access Types Registers Clock DomainsRegisters Clock Domains Absolute Maximum Rating Operating Condition Interface Specification EEPROM Interface Specification GPIO Interface Specification GPIO Interface Specification EEPROM Interface Timing EEPROM Interface EEPROM Example Dimensions LQFP Package
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Product Overview
Product Overview
Package Information
Product Name ADM8513 ADM8513X
Product Type ADM8513-AD-T-1 ADM8513X-AD-T-1
Package P-LQFP-48-5 PG-LQFP-48-5
Ordering Number Q67801H 62A101 Q67801H 98A101
stands Infineon packing variants, such "Tape&reel, drypacked".
Features
Main features: Industrial Standard IEEE 802.3/802.3u 10Base-T/100Base-Tx compliant. Supports IEEE 802.3x flow control Supports Auto-Negotiation 10BASE-T 100BASE-TX specification compliant Interface specification compliant Full-Speed Device Supports configuration interface Supports standard commands Supports vendor specific commands Supports Suspend/Resume detection logic Supports endpoints: control endpoint with maximum 8-byte packet, bulk endpoint with maximum 64-byte packet, bulk endpoint with maximum 64-byte packet interrupt endpoint with maximum 8-byte packet MAC/PHY Integrates using address Supports configurable threshold PAUSE frame. Supports Auto-Negotiation Provides transmit wave-shaper, receive filter, adapter equalizer. Provides MLT-3 transceiver with restoration Base-Line wander. Supports external transmit/receive transformer with turn ration 1:1. EEPROM Interface Provides serial interface access 93C46 EEPROM Automatically load device vendor from EEPROM after power-on reset FIFO Synchronous SRAM. Internal 2K-byte port asynchronous SRAM. Interface operation modes LED0: speed indication 10Mbps 100Mbps. LED1: link indication. LED2: full duplex indication. Support Power Save Function suspend mode Mode Resume remote wakeup host when goes into standby Rev. 1.21, 2005-09-13
Data Sheet
ADM8513 Data Sheet
Product Overview Mode Resume host when goes into standby. Miscellaneous Supports GPIO pins Provides 48-pin LQFP package power supply with V/3.3 tolerance Support Driver Win98/ME/2000/XP Linux driver, WinCE 3.0&4.0 driver Manufacturing test utilities: EEPROM Burn-in program testing program
Data Sheet
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ADM8513 Data Sheet
Interface Description
Interface Description
Assignment Diagram
Diagram ADM8513.
VDD33 EECS EESK EEDI EEDO VDD33 GPIO1 GPIO0 POREN# RXIP RXIN VAAR LED0 LED1 LED2 VDD33 GPIO5 GPIO4 GPIO3
VDD33 RST# CLK48_O CLK48_I UVss UVDD33 VDD33 GPIO2
Figure
Diagram
Description Function
Table AI/O
Abbreviations Type Description Standard input-only pin. Digital levels. Output. Digital levels. bidirectional input/output signal. Input. Analog levels. Output. Analog levels. Input Output. Analog levels. Power Ground Must connected (JEDEC Standard) Must connected High (JEDEC Standard)
Abbreviations
Data Sheet
VAAT TXON TXOP GNDT CLK25_I CLK25_O VAARef RIBB GNDRef TSTB TSTA GNDR
ADM8513
rev. 1.0a
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Interface Description Table Table Abbreviations Type (cont'd) Description Usable (JEDEC Standard) Connected (JEDEC Standard) Abbreviations Buffer Type Description High impedance Pull Pull down, Pull down, Tristate capability: corresponding operational states: Low, high highimpedance. Open Drain. corresponding operational states, active tristate, allows multiple devices share wire-OR. external pull-up required sustain inactive state until another agent drives must provided central resource. Open Collector Push-Pull. corresponding operational states: Active-low active-high (identical output with type attribute). Open-Drain Push-Pull. corresponding configured either output with attribute output with attribute. Schmitt-Trigger characteristics characteristics
Abbreviations
Abbreviations
OD/PP
2.2.1
Host Interface
Table Ball
Host Interface Name CLK48_I CLK48_O RST# Type Buffer Type Function Input Clock clock input from crystal oscillator. Output Crystal External Hardware Reset Input Schmitt-trigger, internal pull high. Data Minus Data Plus
2.2.2
Physical Interface
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Interface Description
Table Ball
Physical Interface Name RXIP, RXIN TXOP, TXON CLK25_I CLK25_O RIBB TSTA, TSTB Type Buffer Type Function Input Output Crystal Input 25MHz Crystal Output 25MHz Reference Bias Resistor, tied external 10K(1%) resistor ground Test Output
2.2.3
Interface
Table Ball
Interface Name LED0 Type Buffer Type Function display 100M speed. Active indicates 100Base-TX, active high indicates BaseT. display link activity status. Active when link established. display Full Duplex Collision status. Active indicates full duplex, high indicates collision half duplex.
LED1 LED2
Note: interface EEPROM-programmable, EEPROM control bit, Address 0B[7:6] EEPROM, used select mode, default setting are: LED0: 100Mbps(on, drive '0') 10Mbps(off, drive '1') LED1: link (keeps when link activity (blinks with 10Hz when Pegasus receiving transmitting colliding LED2: full duplex (keeps when full duplex mode) collision (blinks with 20Hz when colliding) pins will tri-state when using external (offset with bit[4:2] 001B) Mapping between action EEPROM 0B[7:6] setting Table Mapping between action EEPROM 0B[7:6] setting Action LED0 (OFF/ON) LED1 LINK ACTIVITY (ON/FLASH) LED2 FULL (ON/FLASH) LED0 ACTIVITY when LINK (FLASH) LED1 LINK 10(ON) LED2 LINK 100(ON)
EEPROM 0B[7:6]
Data Sheet
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ADM8513 Data Sheet
Interface Description
2.2.4
EEPROM Interface
Table Ball
EEPROM Interface Name EECS Type Buffer Type Function EEPROM Chip Select This enables EEPROM during loading Ethernet configuration data. CMOS with tolerant, EEPROM Data will this serially write opcodes, addresses data into serial EEPROM. CMOS with tolerant, EEPROM Data Out, internal pull will read contents EEPROM serially through this pin. Input, pull down, tolerant EEPROM Clock After reset, configured, will read contents EEPROM using EESK, EEDO, EEDI. This provides clock EEPROM. CMOS with tolerant,
EEDI
EEDO
EESK
2.2.5
Miscellaneous
Table Ball
Miscellaneous Name GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 POREN# Test Pins Test Pins Type Buffer Type Function General Purpose Input/Output Pins These pins used general purpose Input/Output pins offset 0A[1] EEPROM. Default internal pull-low
2.2.6
POWER
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Interface Description
Table Ball
Power Name UVDD UVSS Type Buffer Type Function 3.3V power supply transceiver Ground transceiver
2.2.7
POWER
Table Ball
Power Name Type Buffer Type Function 3.3V Power Supply. Ground +3.3V Power Supply PHY. +3.3V Power Ground +3.3V Transmitter Transmitter +3.3V Receiver Receiver
VAARef GNDRed VAAT GNDT VAAR GNDR
Block Diagram
Command Decoder
SRAM 10/100 Ethernet RJ45
FIFO Controller
10/100M Ethernet
FIFO
Figure
Block Diagram
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Function Description
Function Description
Interface
likely solution time want computer communication with devices outside computer. interface suitable one-of-kind small-scale designs well mass-produced, standard peripheral. benefits easy use, fast reliable data transfers, flexibility, cost power conservation.
3.1.1
(Serial Interface Engine) control communications check protocol, then transfer protocol decoder. transceivers, which provide hardware interface cable, together comprise engine.
3.1.2
Command Decoder
detail description "USB Command".
FIFO Controller
FIFO Controller receive path charge Stores received Ethernet packets SRAM multiple packets stored SRAM. more than maximum packet counts received total packet size more than size SRAM, subsequent coming Ethernet packet will discarded. FIFO controller will load data from SRAM internal FIFO then inform Decoder that 64-byte data packet ready FIFO. Before FIFO controller informs about this, access bulk endpoint will return NAK. This maintain data transfer bulk transfer which continuous, thus 64-byte internal FIFO needed. Ethernet packet being received loading into SRAM while FIFO Controller moving data from SRAM internal FIFO, writing Ethernet packet SRAM will higher priority.
FIFO FIFO
FIFO one-port 64-byte FIFO FIFO two-port 2K-byte FIFO.
10/100M Ethernet
Ethernet compliant IEEE 802.3u 100BASE-TX IEEE802.3 10BASE-T. provides whole physical layer functions both 100M Ethernet speed.
Device Endpoint Operation
Endpoint
Endpoint charge response standard commands vendor specific commands. Internal register settings also this endpoint. response each command described section
Data Sheet
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ADM8513 Data Sheet
Device Endpoint Operation
Endpoint Bulk
Endpoint charge sending received Ethernet packet host. Ethernet packet will split multiple bytes packets USB. Ethernet packet indicated less then 64-byte length data transfer this pipe. Ethernet received status optionally reported packet. While accessing this endpoint, RXFIFO either full packet inside, data RXFIFO returned data stage. received from host, data RXFIFO flushed. response received from host, content RXFIFO will re-transmitted. RXFIFO isn't ready transmission, returned host.
Packet
Ethernet Packet Multiple Packet
1/10/100 Layer 1514 bytes)
Ethernet Packet
Figure
Packet Form when Receive
Received Status Reported Follows: Table Offset Offset0 Offset1 Offset2 Received Status Offset3 Field rx_bytecnt_lo rx_bytecnt_hi reserved multicast_frame long_pkt runt_pkt crc_err dribble_bit reserved reserved Indicates received multicast frame. Indicates received packet length 1518 bytes. Indicates received packet length bytes. Indicates check error. Indicates packet length integer multiple 8bit. Description received byte count[7:0]. received byte count[11:8].
4.2.1
Endpoint Bulk
Endpoint charge sending packet Ethernet. Ethernet packet concatenated multiple bytes packets USB. first bytes every first concatenated packet indicate length Ethernet packet. Ethernet packet indicated less then 64-byte length data transfer this pipe. Ethernet transmit status reported transmit status register. When accessing this endpoint, data data stage transferred TXFIFO, TXFIFO free returned. TXFIFO isn't free, returned.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table Field Content
Packet Format Byte Packet len[7:0]: byte Ethernet packet length Byte Packet {reserved[4:0], len[10:8]} Following Packets Ethernet packet
Packet
Multiple Packet Ethernet Packet
1/10/100 Layer 1514 bytes)
Ethernet Packet
Figure
Packet Form when Transmit
4.2.2
Endpoint Interrupt
Endpoint charge returning current Ethernet transfer status every polling interval. When accessing this endpoint, bytes data returned host. 8-byte packet contains Table Offset0 tx_status(Reg2BH) Table Offset5 wakeup_status(Reg7AH) Interrupt Packet Form Offset1 tx_status(Reg2CH) Offset2 rx_status(Reg2DH) Offset3 rx_lostpkt(Reg2EH) Offset4 rx_lostpkt(Reg2FH)
Interrupt Packet Form Offset6(1B) Packet number FIFO (Reg82H) Offset7(1B) 7'b00, length error
Commands
Command
5.1.1
Register (Vendor Specific) Single/Burst Read
Table bmReq
Setup Stage bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B) RegIndex[7:0] Length Length High
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table Offset0(1B) {RegIndex}
Data Stage Offset1(1B) {RegIndex+1) Offset2(1B) {RegIndex+2)
returned total number registers depends length field.
5.1.2
Register (Vendor Specific) Burst Write
Table bmReq Table Offset0(1B) {RegIndex}
Setup Stage bReq Data Stage Offset1(1B) {RegIndex+1} Offset2(1B) {RegIndex+2} Offset3(1B) {RegIndex+3} wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B) RegIndex[7:0] Length Length High
Write RegIndex 05H, transfer will Table bmReq Setup Stage bReq wValue L(1B) wValue H(1B) wIndexLow wIndexHigh wLength (1B) (1B) L(1B) wLength H(1B)
wLength more than register accessed (burst write) mask supported DataStage 8-byte transfer appears Burst write registers from RegIndex data from Setup Stage Setup Stage bReq Data Stage Transfer Offset1(1B) Offset2(1B) Offset3(1B) Offset4(1B) Offset5(1B) Offset6(1B) Offset7(1B) wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B) 0000
Table bmReq
Table Offset0(1B) Table Offset0(1B)
Transfer Offset1(1B) Offset2(1B) Offset3(1B) Offset4(1B) Offset5(1B) Offset6(1B) Offset7(1B)
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table Offset0(1B)
Transfer Offset1(1B) Offset2(1B)
5.1.3
Status (Device)
Table bmReq Table D[15:2]
Setup Stage bReq Data Stage D[1]: Remote Wakeup Register remote_wakeup D[0]:Self Powered wValue(2B) wIndex(2B) wLength L(1B) wLength H(1B)
5.1.4
Status (Interface)
Table bmReq Table D[15:0]
Setup Stage bReq Data Stage wValue(2B) wIndex(2B) wLength L(1B) wLength H(1B)
5.1.5
Status (EP0)
Table bmReq Table D[15:1]
Setup Stage bReq Data Stage D[0]: Halt Register ep0_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength L(1B) wLength H(1B)
5.1.6
Status (EP1) Bulk
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table bmReq Table D[15:1]
Setup Stage bReq Data Stage D[0]: Halt Register ep1_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength L(1B) wLength H(1B)
5.1.7
Status (EP2) Bulk
Table bmReq Table D[15:1]
Setup Stage bReq Data Stage D[0]: Halt register ep2_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength L(1B) WLength H(1B)
5.1.8
Status (EP3) Interrupt
Table bmReq Table D[15:1]
Setup Stage bReq Data Stage D[0]: Halt register ep3_halt wValue(2B) wIndex L(1B) wIndex H(1B) wLength L(1B) wLength H(1B)
5.1.9
Descriptor (Device) Total 18-byte
Table bmReq
Setup Stage bReq wValue L(1B) wValue H(1B) wIndex(2B) wLength L(1B) Length wLength H(1B) Length high
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table
Data Stage: wLength Field Specifies Total byte Count Return Offset (USB Offset (USB Offset Offset (Sub Offset release release (Class code) Class Code) (Protocol) 10(1B) 01(1B) FF(1B) 00(1B) ff(1B) Offset (EP0 MaxPktSize) 8(1B)
Offset Offset (type) 12(1B) Table 01(1B)
Data Stage: wLength Field Specifies Total byte Count Return Offset (productID) High (1B) Offset (releaseID Low) 01(1B)
Offset (vendor Offset 9(vendor Offset High (productID) (1B) Table (1B) (1B)
Data Stage: wLength Field Specifies Total byte Count Return Offset (Product) Offset (serial no.) 02(1B) 03(1B) Offset (no. config) 01(1B)
Offset (releaseID Offset High) (manufacture) 01(1B) 01(1B)
5.1.10
Descriptor (Configuration) Total 39-byte
Table BmReq
Setup Stage bReq wValue L(1B) wValue H(1B) wIndex(2B) wLength L(1B) Length wLength H(1B) Length high
Data Stage Configuration Descriptor Offset (DscrType) Offset (TotalLength) 02(1B) Configuration Descriptor Offset (StringIndex) 00(1B) Interface Descriptor Offset Offset (AltInterfa (NumEP) 00(1B) 03(1B) Offset Offset Offset (IntfClass) (IntfSubCl (IntfProto ass) col) FF(1B) E0(1B) FF(1B) Offset (StringInd 00(1B) Offset (Attribute) E0(1B) Offset 8(MaxPower) max_pwr(1B) 27(1B) Offset (TotalLength) High 00(1B) Offset (NumInterface) 01(1B)
Table
Offset (Length) 09(1B) Table 00(1B) Table
Offset (ConfgValue)
Offset Offset Offset (Length) (DscrType) (Interface Num) 09(1B) 04(1B) 00(1B)
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table
Descriptor Offset (EPAddr) 81(1B) Offset (Attribute) 02(1B) bulk Offset (MaxPktSize) 64(1B) Offset (MaxPktSize) High 00(1B) Offset (Interval) 00(1B)
Offset Offset (Length) (DscrType) 07(1B) Table 05(1B)
Descriptor Offset (EPAddr) 02(1B) Offset (Attribute) 02(1B) bulk Offset (MaxPktSize) 64(1B) Offset (MaxPktSize) High 00(1B) Offset (Interval) 00(1B)
Offset Offset (Length) (DscrType) 07(1B) Table 05(1B)
Descriptor Offset (EPAddr) 83(1B) Offset (Attribute) Offset (MaxPktSize) Offset (MaxPktSize) High 00(1B) Offset (Interval) ep3_interval(1B)
Offset Offset (Length) (DscrType) 07(1B) 05(1B)
03(1B) interrupt 08(1B)
5.1.11
Descriptor (String) Index LanguageID Code
Table BmReq Table 04(1B)
Setup Stage bReq Data Stage Offset1 (DscrType) 03(1B) Offset2 (LanguageID) 09(1B) Offset3 (LanguageID) 04(1B) wValue L(1B) wValue H(1B) wIndex(2B) 0000 wLength Low(1B) Length wLength High(1B) Length High
Offset0 (Length)
5.1.12
Descriptor (String) Index Manufacture
Table BmReq Table length(1B)
Setup Stage bReq Data Stage Offset1 (DscrType) 03(1B) String wValue L(1B) wValue H(1B) wIndex (2B) 0904 wLength Low(1B) Length wLength High(1B) Length High
Offset0 (Length)
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
5.1.13
Descriptor (String) Index Product
Table BmReq Table length(1B)
Setup Stage bReq Data Stage Offset (DscrType) 03(1B) String wValue L(1B) wValue H(1B) wIndex (2B) 0904 wLength Low(1B) Length wLength High(1B) Length High
Offset (Length)
5.1.14
Descriptor (String) Index Serial
Table BmReq Table Length(1B)
Setup Stage bReq Data Stage Offset (DscrType) 03(1B) String wValue L(1B) wValue H(1B) wIndex (2B) 0904 wLength Low(1B) Length wLength High(1B) Length High
Offset (Length)
5.1.15
Configuration
Table BmReq Table
Setup Stage bReq Data Stage wValue(2B) wIndex(2B) wLength Low(1B) wLength High(1B)
Offset (ConfgValue)(1B)
5.1.16
Interface
Table BmReq
Setup Stage bReq wValue(2B) wIndex(2B) wLength Low(1B) wLength High(1B)
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Commands
Table
Data Stage
Offset0 (AltIntf) (1B)
5.1.17
Clear Feature (Device) Remote Wakeup
Table BmReq
Setup Stage bReq wValue L(1B) WValue H(1B) wIndex(2B) wLength(2B)
5.1.18
Feature (Device) Remote Wakeup
Table BmReq
Setup Stage bReq wValue L(1B) WValue H(1B) wIndex(2B) wLength(2B)
5.1.19
Clear Feature Halt
Table BmReq
Setup Stage bReq wValue(2B) 0000 WIndex L(1B) wIndex L(2B) WLength(2B)
5.1.20
Feature Halt
Table BmReq
Setup Stage bReq wValue(2B) 0000 WIndex H(1B) wIndex H(2B) WLength(2B)
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Registers Description
System Registers
Table Module
Registers Address Space Base Address 0000 0000H Address 0000 0081H Note
System Registers Table
Registers Overview Register Long Name Reserved 30~Reserved Ethernet Control Ethernet Control Ethernet Control Reserved Reserved Reserved Reserved Reserved Multicast Address Multicast Address Multicast Address Multicast Address Multicast Address Multicast Address Multicast Address Multicast Address Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet Reserved Reserved Pause Timer Receive Packet Number Based Flow Control Occupied Receive FIFO Based Flow Control Control Reserved Offset Address 82~FFH Page Number
Register Short Name Res30_Res155 Res0 Res1 Res2 Res3 Res4 EID0 EID1 EID2 EID3 EID4 EID5 Res5 Res6 RPNBFC ORFBFC EP1C Res7
Data Sheet
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ADM8513 Data Sheet
Registers Description Table Res8 Res9 Res10 EEPROMO EEPROMDL EEPROMDH EEPROMAC Res11 PHYA PHYDL PHYDH PHYAC Res12 USBBS RLPCH RLPCL WUF0M_0 WUF0M_1 WUF0M_2 WUF0M_3 WUF0M_4 WUF0M_5 WUF0M_6 WUF0M_7 WUF0M_8 WUF0M_9 WUF0M_10 WUF0M_11 WUF0M_12 WUF0M_13 WUF0M_14 WUF0M_15 WUF0O_0 WUF0CRCL WUF0CRCH Res13 Res14 Res15 Data Sheet Registers Overview (cont'd) Register Long Name Reserved Reserved Reserved EEPROM Offset EEPROM Data EEPROM Data High EEPROM Access Control Reserved Address Data Data High Access Control Reserved Status Transmit Status Transmit Status Receive Status Receive Lost Packet Count High Receive Lost Packet Count Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Offset Wakeup Frame Wakeup Frame High Reserved Reserved Reserved Offset Address Page Number Rev. 1.21, 2005-09-13
Register Short Name
ADM8513 Data Sheet
Registers Description Table Res16 Res17 WUF1M_0 WUF1M_1 WUF1M_2 WUF1M_3 WUF1M_4 WUF1M_5 WUF1M_6 WUF1M_7 WUF1M_8 WUF1M_9 WUF1M_10 WUF1M_12 WUF1M_13 WUF1M_11 WUF1M_14 WUF1M_15 WUF1O WUF1CRCL WUF1CRCH Res18 Res19 Res20 Res21 Res22 WUF2M WUF2M_1 WUF2M_2 WUF2M_3 WUF2M_4 WUF2M_5 WUF2M_6 WUF2M_7 WUF2M_8 WUF2M_9 WUF2M_10 WUF2M_11 WUF2M_12 WUF2M_13 WUF2M_14 Data Sheet Registers Overview (cont'd) Register Long Name Reserved Reserved Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Offset Wakeup Frame Wakeup Frame High Reserved Reserved Reserved Reserved Reserved Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Offset Address Page Number Rev. 1.21, 2005-09-13
Register Short Name
ADM8513 Data Sheet
Registers Description Table WUF2M_15 WUF2O WUF2CRCL WUF2CRCH Res23 Res24 Res25 Res26 Res27 Res28 IPHYC GPIO54C Res29 GPIO10C GPIO32C Test Registers Overview (cont'd) Register Long Name Wakeup Frame Mask Wakeup Frame Offset Wakeup Frame Wakeup Frame High Reserved Reserved Reserved Reserved Reserved Wakeup Control Reserved Wakeup Status Internal Control GPIO[5:4] Control Reserved GPIO[1:0] Control GPIO[3:2] Control TEST Test Mode Offset Address Page Number
Register Short Name
register addressed wordwise. Table Mode read/write read Register Access Types Symbol Description Register used input Description Register readable writable
Register written (register Value written software ignored between input output cycle hardware; that software write delay) value this field without affecting hardware behavior Target development.) Register (register between only read this register input output cycle delay) Physically, there register, only read this register input signal connected directly address multiplexer. Latch high signal high level, clear read register read Latch high signal low-level, clear read register read Latch high signal high level, register read register, with write mask cleared with written mask register cleared clears) Latch high signal low-level, register cleared read read register, with write mask register cleared clears)
Read only Read virtual
Latch high, self clearing Latch low, self clearing Latch high, mask clearing Latch low, mask clearing
lhsc llsc lhmk llmk
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Table Mode Interrupt high, self clearing Interrupt low, self clearing Interrupt high, mask clearing Interrupt low, mask clearing Register Access Types (cont'd) Symbol Description ihsc ilsc ihmk ilmk Differentiates input signal (low>high) register cleared read Differentiates input signal (high>low) register cleared read Description read register read register
Differentiates input signal (highSW read register, with write mask >low) register cleared with written mask register cleared Differentiates input signal (low>high) register cleared with written mask Enables interrupt source interrupt generation register, value latched after first clock cycle after reset read register, with write mask register cleared read write this register Register readable writable
Interrupt enable register latch_on_reset Read/write self clearing rwsc
Register used input Writing register generates strobe register will cleared signal clock cycle) mechanism. Register readable writable
Table
Registers Clock DomainsRegisters Clock Domains Description
Clock Short Name
6.1.1
System Registers
Ethernet Control
Ethernet Control
Offset
Reset Value
Field RXFCE RXSA
Bits
Type
Description Ethernet Transmission Enable Ethernet Receive Enable Receive Pause Frame Enable Wake-on-LAN Mode Enable Status Append Received Packet Enable
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Field Bits Type Description Stop Back CNOT, Back-off counter isn't affected carrier CST, Back-off counter stops when carrier active resumes when carrier drops Receive Multicast Packet Include Receive Packet
RXMA RXCS
Ethernet Control
Ethernet Control
Offset
Reset Value
Field
Bits
Type
Description Reserved Full Dublex HDM, Half-duplex mode FDM, Full-duplex mode 10mode 10Base, 10Base-T mode 100Base, 100Base-T mode Reset After write will clear this after reset. Mode MIIM, mode Reserved
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Ethernet Control
Ethernet Control
Offset
Reset Value
Field MEPL
Bits
Type
Description Ethernet Packet Length 1528B, 1528 bytes 1638B, 1638 bytes, Default Reserved Load EEPROM Start When this written with will start load EEPROM. EEPROM Write Enable/disable WEDC, EEPROM writes enable/disable command EEPROM writes command Loop Back Mode Enable Promiscuous RPP, Receives packets which pass address filter RAP, Receives packet Receive Packets FABP, Filters packet RBPP, Receives packets which pass address filter Read Cleared AEP3, Access EP3, effect those registers. OEP3, Once accessed, those registers (2B-2F, will cleared.
LEEPRS EEPRW
PROM
RXBP
EP3RC
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Reserved
Res0 Reserved
Offset
Reset Value
Field
Bits
Type
Description Reserved
Similar Registers Table Res1 Res2 Res3 Res4 Res5 Res6 Res7 Res8 Res9 Res10 Res11 Res12 Res13 Res14 Res15 Res16 Res17 Res18 Res19 Res20 Res21 Res22 Res23 Res24 Res25 Data Sheet Reserved Registers Register Long Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Offset Address Rev. 1.21, 2005-09-13 Page Number
Register Short Name
ADM8513 Data Sheet
Registers Description Table Res26 Res27 Res28 Res29 Res30_Res155 Multicast Address Reserved Registers (cont'd) Register Long Name Reserved Reserved Reserved Reserved Reserved 30~Reserved Offset Address 82~FFH Page Number
Register Short Name
Multicast Address
Offset
Reset Value
Field MAB0
Bits
Type
Description Multicast Multicast address byte [7:0]
Multicast Address
Multicast Address
Offset
Reset Value
Field MAB1
Bits
Type
Description Multicast Multicast address byte [15:8]
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Multicast Address
Multicast Address
Offset
Reset Value
Field MAB2
Bits
Type
Description Multicast Multicast address byte [23:16]
Multicast Address
Multicast Address
Offset
Reset Value
Field MAB3
Bits
Type
Description Multicast Multicast address byte [31:24]
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Multicast Address
Multicast Address
Offset
Reset Value
Field MAB4
Bits
Type
Description Multicast Multicast address byte [39:32]
Multicast Address
Multicast Address
Offset
Reset Value
Field MAB5
Bits
Type
Description Multicast Multicast address byte [47:40]
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Multicast Address
Multicast Address
Offset
Reset Value
Field MAB6
Bits
Type
Description Multicast Multicast address byte [55:48]
Multicast Address
Multicast Address
Offset
Reset Value
Field MAB7
Bits
Type
Description Multicast Multicast address byte [63:56]
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Ethernet
EID0 Ethernet
Offset
Reset Value
Field EID0
Bits
Type
Description Ethernet byte Ethernet automatically loaded from EEPROM after reset.
Ethernet
EID1 Ethernet
Offset
Reset Value
Field EID1
Bits
Type
Description Ethernet byte Ethernet
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Ethernet
EID2 Ethernet
Offset
Reset Value
Field EID2
Bits
Type
Description Ethernet byte Ethernet
Ethernet
EID3 Ethernet
Offset
Reset Value
Field EID3
Bits
Type
Description Ethernet byte Ethernet
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Ethernet
EID4 Ethernet
Offset
Reset Value
Field EID4
Bits
Type
Description Ethernet byte Ethernet
Ethernet
EID5 Ethernet
Offset
Reset Value
Field EID5
Bits
Type
Description Ethernet byte Ethernet
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Pause Timer
Pause Timer
Offset
Reset Value
Field
Bits
Type
Description Pause Timer [11:4] pause time PAUSE frame.
Receive Packet Number Based Flow Control
RPNBFC Receive Packet Number Based Flow Control
Offset
Reset Value
Field
Bits
Type
Description Packet Number This field specifies threshold transmitting PAUSE frame. received packet number more than equal this field, PAUSE frame sent automatically Flow Control Packet RPN, Enables pause frame transmission based received packet number
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Occupied Receive FIFO Based Flow Control
ORFBFC Occupied Receive FIFO Based Flow Control
Offset
Reset Value
Field
Bits
Type
Description Size This field specifies Kbyte threshold transmitting PAUSE frame. received FIFO occupied than equal this field, PAUSE frame sent automatically this field receive FIFO occupied more than equal Kbyte, PAUSE frame transmitted. Flow Control Size RFS, Enables pause frame transmission based occupied received FIFO size
FCRXS
Control
EP1C Control
Offset
Reset Value
Field EP1S0E
Bits
Type
Description Send DEP1, Disables send 1-byte function EEP1, Enables send 1-byte when more than frame_ interval's received Frame Interval Detail This value detailed scale frame interval, from 3ms. more than plus frame_interval NAK, sends 1-byte more than plus frame_interval NAK, sends 1-byte more than plus frame_interval NAK, sends 1-byte
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Field Bits Type Description Frame Interval This value multiply with frame interval, from 124ms 00001B, more than NAK, sends 1-byte 00010B, more than NAK, sends 1-byte 11111B, more than NAK, sends 1-byte
EEPROM Offset
EEPROMO EEPROM Offset
Offset
Reset Value
Field ROMO
Bits
Type
Description Offset sets this register when access EEPROM.
EEPROM Data
EEPROMDL EEPROM Data
Offset
Reset Value
Field ROMDL
Bits
Type
Description Data EEPROM Write: data this register will written EEPROM EEPROM Read: data from EEPROM will stored this register
EEPROM Data High
EEPROMDH EEPROM Data High
Offset
Reset Value
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Field ROMDH
Bits
Type
Description Data High EEPROM Write: data this register will written EEPROM EEPROM Read: data read from EEPROM will stored this register
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description EEPROM Access Control
EEPROMAC EEPROM Access Control
Offset
Reset Value
Field
Bits
Type
Description Done indicate successful completion EEPROM access. Clear when initiate access EEPROM Read Access EEPROM initiate read access EEPROM. sets this after well setting rom_offset. Write Access EEPROM initiate write access EEPROM. this after well setting rom_offset, romdata_lo romdata_hi.
Address
PHYA Address
Offset
Reset Value
Field PHYA
Bits
Type
Description Address
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Data
PHYDL Data
Offset
Reset Value
Field PHYDL
Bits
Type
Description Data this register when write register. this register when read data from register.
Data High
PHYDH Data High
Offset
Reset Value
Field PHYDH
Bits
Type
Description Data High this register when write register. this register when read data from register.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Access Control
PHYAC Access Control
Offset
Reset Value
Field
Bits
Type
Description Done indicate successful completion access. Clear when initiate access PHY. Read Access Register initiate read access register. this after well setting phy_addr phyreg_addr. Write Access Register initiate write access register. this after well setting phy_addr, phyreg_addr phyreg_data. Register Address
RDPHY
WRPHY
PHYRA
Status
USBBS Status
Offset
Reset Value
Field USBR
Bits
Type
Description Resume State indicate resumed state. Clear read this register. Suspend State indicate suspended state. Clear read this register.
USBS
Transmit Status
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Transmit Status
Offset
Reset Value
Field TXUE
Bits
Type
Description Underrun Error indicate underrun error. Clear read this register after accessed. Excessive Collision indicate excessive collision. Clear read this register after accessed. Late Collision Error indicate late collision error. Clear this register Read after accessed. Carrier indicate carrier. Clear this register Read after accessed. Carrier Loss indicate carrier loss. Clear this register Read after accessed. Jabber Time indicate jabber time out. Clear this register Read after accessed.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Transmit Status
Transmit Status
Offset
Reset Value
Field TXFF
Bits
Type
Description Fifo Full indicate fifo full. Clear this register Read after accessed. Fifo Empty indicate fifo empty. Clear this register Read after accessed. Packet Count indicate Ethernet transmit packet counts every interrupt polling. more than packets have been transmitted, this value will stay Clear read after accessed.
TXFE
TXPC
Receive Status
Receive Status
Offset
Reset Value
Field
Bits
Type
Description Pause indicate PAUSE frame received. Clear this register Read after accessed. Overflow indicate external SRAM overflow. Clear this register Read after accessed.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Receive Lost Packet Count High
RLPCH Receive Lost Packet Count High
Offset
Reset Value
Field RXLPC
Bits
Type
Description Received Packet Lost Lost Packet Counts [14:8] lost packet counts receive FIFO overflow. Clear this register Read after accessed.
Receive Lost Packet Count
RLPCL Receive Lost Packet Count
Offset
Reset Value
Field RXLPC
Bits
Type
Description Lost Packet Counts [7:0] lost packet counts receive FIFO overflow. Clear this register Read after accessed.
Wakeup Frame Mask
WUF0M_0 Wakeup Frame Mask
Offset
Reset Value
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Field
Bits
Type
Description Mask Bits Frame
Similar Registers Table WUF0M_1 WUF0M_2 WUF0M_3 WUF0M_4 WUF0M_5 WUF0M_6 WUF0M_7 WUF0M_8 WUF0M_9 WUF0M_10 WUF0M_11 WUF0M_12 WUF0M_13 WUF0M_14 WUF0M_15 Wakeup Frame Offset Wakeup Frame Mask Registers Register Long Name Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Offset Address Page Number
Register Short Name
WUF0O_0 Wakeup Frame Offset
Offset
Reset Value
Field
Bits
Type
Description Offset Wakeup Frame
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Frame
WUF0CRCL Wakeup Frame
Offset
Reset Value
Field F0CRCL
Bits
Type
Description Byte CRC16 Match Frame
Wakeup Frame High
WUF0CRCH Wakeup Frame High
Offset
Reset Value
Field F0CRCH
Bits
Type
Description High Byte CRC16 Match Frame
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Frame Mask
WUF1M_0 Wakeup Frame Mask
Offset
Reset Value
Field
Bits
Type
Description Mask Bits Frame
Similar Registers Table WUF1M_1 WUF1M_2 WUF1M_3 WUF1M_4 WUF1M_5 WUF1M_6 WUF1M_7 WUF1M_8 WUF1M_9 WUF1M_10 WUF1M_11 WUF1M_12 WUF1M_13 WUF1M_14 WUF1M_15 Wakeup Frame Offset Wakeup Frame Mask Registers Register Long Name Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Offset Address Page Number
Register Short Name
WUF1O Wakeup Frame Offset
Offset
Reset Value
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Field
Bits
Type
Description Offset Wakeup Frame
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Frame
WUF1CRCL Wakeup Frame
Offset
Reset Value
Field
Bits
Type
Description Byte CRC16 Match Frame
Wakeup Frame High
WUF1CRCH Wakeup Frame High
Offset
Reset Value
Field F1CRCH
Bits
Type
Description High Byte CRC16 Match Frame
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Frame Mask
WUF2M Wakeup Frame Mask
Offset
Reset Value
Field
Bits
Type
Description Mask Bits Frame
Similar Registers Table WUF2M_1 WUF2M_2 WUF2M_3 WUF2M_4 WUF2M_5 WUF2M_6 WUF2M_7 WUF2M_8 WUF2M_9 WUF2M_10 WUF2M_11 WUF2M_12 WUF2M_13 WUF2M_14 WUF2M_15 Wakeup Frame Offset Wakeup Frame Mask Registers Register Long Name Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Wakeup Frame Mask Offset Address Page Number
Register Short Name
WUF2O Wakeup Frame Offset
Offset
Reset Value
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Field
Bits
Type
Description Offset Wakeup Frame
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Frame
WUF2CRCL Wakeup Frame
Offset
Reset Value
Field F2CRCL
Bits
Type
Description Byte CRC16 Match Frame
Wakeup Frame High
WUF2CRCH Wakeup Frame High
Offset
Reset Value
Field F2CRCH
Bits
Type
Description High Byte CRC16 Match Frame
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Control
Wakeup Control
Offset
Reset Value
Field
Bits
Type
Description Enable Magic Packet enable magic packet wakeup function. EMP, Enables magic packet wakeup function Enable Link Status enable link status wakeup function. ELS, Enables link status wakeup function Enable Wakeup Frame enable wakeup frame0 wakeup function EWF0, Enables wakeup frame0 wakeup function Enable Wakeup Frame enable wakeup frame1 wakeup function EWF1, Enables wakeup frame1 wakeup function Enable Wakeup Frame enable wakeup frame2 wakeup function EWF2, Enables wakeup frame2 wakeup function CRC-16 Initial Type CRC16, CRC-16 initial contents 0000H CRC16, CRC-16 initial contents ffffH
EWF0
WUF1
WUF2
CRC16
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Wakeup Status
Wakeup Status
Offset
Reset Value
Field RXMP
Bits
Type
Description Receives Magic Packet when receive magic packet. Clear read this register. RMP, Means ADM8513 receives magic packet Receives Link Status Change when link status change.Clear read this register. RLS, Means ADM8513 receives link status change Receives Wakeup Frame when receive wakeup frame.Clear read this register. RWF, Means ADM8513 receives wakeup frame Indicate Current Link Status link_sts LOFF, Link LON, Link
RXWF
Internal Control
IPHYC Internal Control
Offset
Reset Value
Field EPHY
Bits
Type
Description Enable DIN, Disables internal 10/100 EIN, Enables internal 10/100
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Field PHYR Bits Type Description Internal Reset internal reset when this written with stops reset when this written with RIPHY, Reset internal
GPIO[5:4] Control
GPIO54C GPIO[5:4] Control
Offset
Reset Value
Field G5OE
Bits
Type
Description GPIO5 Output Enable GPIO5 used input OUT, GPIO5 used output GPIO5 Output Value When GPIO5 used output, this value driven GPIO5 pin. GPIO5 Input Value When GPIO5 used input, this field reflects status GPIO5. Default pulled-down. GPIO4 Output Enable GPIO4 used input OUT, GPIO4 used output GPIO4 Output Value When GPIO4 used output, this value driven GPIO4 pin. GPIO4 Input Value When GPIO4 used input, this field reflects status GPIO4. Default pulled-down.
G5OV G5IV
G4OE
G4OV G4IV
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description GPIO[1:0] Control
GPIO10C GPIO[1:0] Control
Offset
Reset Value
Field G1OE
Bits
Type
Description GPIO1 Output Enable GPIO1 used input OUT, GPIO1 used output GPIO1 Output Value When GPIO1 used output, this value driven GPIO1 pin. GPIO1 Input Value When GPIO1 used input, this field reflects status GPIO1. GPIO0 Output Enable GPIO0 used input OUT, GPIO0 used output GPIO0 Output Value When GPIO0 used output, this value driven GPIO0 pin. GPIO0 Input Value When GPIO0 used input, this field reflects status GPIO0.
G1OV
G1IV
G1OE
G0OV
G0IV
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description GPIO[3:2] Control
GPIO32C GPIO[3:2] Control
Offset
Reset Value
Field G3OE
Bits
Type
Description GPIO3 Output Enable GPIO3 used input OUT, GPIO3 used output GPIO3 Output Value When GPIO3 used output, this value driven GPIO3 pin. GPIO3 Input Value When GPIO3 used input, this field reflects status GPIO3. GPIO2 Output Enable GPIO2 used input OUT, GPIO2 used output GPIO2 Output Value When GPIO2 used output, this value driven GPIO2 pin. GPIO2 Input Value When GPIO2 used input, this field reflects status GPIO2.
G3OV
G3IV
G2OE
G2OV
G2IV
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description TEST
Test TEST
Offset
Reset Value
Field Test Mode
Bits
Type
Description Reserved
Test Mode
Offset
Reset Value
Field
Bits
Type
Description Reserved
Registers Description
Table Module
Registers Address SpaceRegisters Address Space Base Address 0000 0000H Address 0000 0006H Note
System Registers Table PHYI1 PHYI2
Registers Overview Register Long Name Control Status Identifier Identifier Auto-Negotiation Advertisement Offset Address Page Number
Register Short Name
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Table ANLPA Registers Overview (cont'd) Register Long Name Auto-Negotiation Link Partner Ability Auto-Negotiation Expansion Offset Address Page Number
Register Short Name
register addressed wordwise. Table Mode read/write read Register Access Types Symbol Description Register used input Description Register readable writable
Register written (register Value written software ignored between input output cycle hardware; that software write delay) value this field without affecting hardware behavior Target development.) Register (register between only read this register input output cycle delay) Physically, there register, only read this register input signal connected directly address multiplexer. Latch high signal high level, clear read register read Latch high signal low-level, clear read register read Latch high signal high level, register read register, with write mask cleared with written mask register cleared clears) Latch high signal low-level, register cleared read Differentiate input signal (low>high) register cleared read Differentiate input signal (high>low) register cleared read read register, with write mask register cleared clears) read register read register
Read only Read virtual
Latch high, self clearing Latch low, self clearing Latch high, mask clearing Latch low, mask clearing Interrupt high, self clearing Interrupt low, self clearing Interrupt high, mask clearing Interrupt low, mask clearing
lhsc llsc lhmk llmk ihsc ilsc ihmk ilmk
Differentiate input signal (highSW read register, with write mask >low) register cleared with written mask register cleared Differentiate input signal (low>high) register cleared with written mask Enables interrupt source interrupt generation register, value latched after first clock cycle after reset read register, with write mask register cleared read write this register Register readable writable
Interrupt enable register latch_on_reset Read/write self clearing rwsc
Register used input Writing register generates strobe register will cleared signal clock cycle) mechanism. Register readable writable
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description
Table
Registers Clock DomainsRegisters Clock Domains Description
Clock Short Name
6.2.1
Registers
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Control
Control
Offset
Reset Value 1000H
Field
Bits
Type rwsc
Description Reset Normal operation Reset Loopback Disable loopback Enable loopback Speed Selection 10M, Mbit/s 100M, Mbit/s Autonegotiation Enable DAN, Disable auto-neg EAN, Enable auto-neg Power Down Normal operation Power Down Isolate normal operation IPHY, isolate from Restart Autonegotiation RAN, Restart Auto-neg Duplex Mode Half Full Collision Test implemented
rwsc
Self Clearing Reset Reset this port only. This will cause following: Restart auto-negotiation process.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Reset registers their default values. Note that this does affect registers These registers reset this allow test configurations written then affected resetting port. Note: reset performed analogue sections port. There also physical reset internal clock synthesisers local clock recovery oscillator which will continue throughout reset period. However since port restarted autoneg re-run process locking frequency local oscillator (slave) reference oscillator (master) will repeated start link initialization process. LoopbackLoop back transmit data receive path closed wire possible. When inhibits actual transmission wire. Speed SelectionForces speed only when auto-negotiation disabled. default state this will determined power-up configuration this case. Otherwise defaults Auto-neg EnableDefaults programmed value. When cleared allows forcing speed duplex settings. When (after being cleared) causes re-start auto-neg process. programming power-up allows come disabled software write desired capability before allowing first negotiation commence. Restart NegotiationOnly effect when auto-negotiating. Restarts state machine. Power DownHas effect this device. Test mode power down modes implemented other specific modules. IsolatePuts RMII receive signals into high impedance state ignores transmit signals. Duplex ModeWhen bit12 cleared (i.e. autoneg disabled), this forces full duplex (bit half duplex (bit Collision TestAlways because collision signal implemented. Status
Status
Offset
Reset Value 7849H
Field 100T4 100FD
Bits
Type
Description BASE supported 100BASE-X Full Duplex 100FDN, 100BASE-X full duplex capable 100FD, 100BASE-X full duplex capable 100BASE-X Half Duplex 100HDN, 100BASE-X half duplex capable 100HD, 100BASE-X half duplex capable Mbit/s Full Duplex 10FDN, Mbit/s Full duplex capable 10FD, Mbit/s Full duplex capable Rev. 1.21, 2005-09-13
100HD
10FD
Data Sheet
ADM8513 Data Sheet
Registers Description Field 10HD Bits Type Description Mbit/s Half Duplex 10HDN, Mbit/s Half duplex capable 10HD, Mbit/s Half duplex capable 100BASE-T2 Full Duplex Supported 100BASE-T2 Half Duplex Supported Preamble Suppression MFPSN, cannot accept management frames with preamble suppression MFPS, accept management frames with preamble suppression Auto-neg Complete ANI, Auto-neg incomplete ANC, Auto-neg completed Remote Fault RFN, remote fault detected Remote fault detected Auto-neg Ability ANN, cannot auto-negotiate auto-negotiate Link Status Link down Link Jabber Detect JCD, Jabber condition detected Extended Capability BSC, Basic register capabilities only Extended register capabilities
100TFD 100THD MFPS
Note: Jabber Detect Only used 10Base-T mode. Read 100Base-TX mode. Identifier Each identifier, which assigned device. identifier contains total bits, which consists following: bits organizationally unique identifier (OUI) manufacturer; 6-bit manufacturer's model number; 4-bit manufacturer's revision number. explanation maps register, please refer IEEE 802-1990 clause
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Identifier
PHYI1 Identifier
Offset
Reset Value 001DH
Field PHYI
Bits 15:0
Type
Description Identifier[31-16] (bits 3-18)
Identifier
PHYI2 Identifier
Offset
Reset Value 2411H
Field PHYI1 PHYI2 PHYI3
Bits 15:10
Type
Description Identifier[15-10] (bits 19-24) Identifier[9-4] Manufacturer's Model Number (bits 5-0) Identifier[3-0] Revision Number (bits 3-0);Register Identifier
Note: This uses Infineon-ADMtek, device type
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Auto-Negotiation Advertisement
Auto-Negotiation Advertisement
Offset
Reset Value 0001H
Field
Bits
Type
Description Next Page NNP, Device Next Page Device Next Page Remote Fault NFD, fault detected Local remote fault sent link partner Implemented Technology ability bits A7-A6 Pause Technology ability Implemented Technology ability 100BASE-TX Full Duplex Technology ability 100NFD, Unit capable Full Duplex 100FD, Unit capable Full Duplex 100BASE-TX Half Duplex Technology ability 100NHD, Unit capable Half Duplex 100BASE-TX 100HD, Unit capable Half Duplex 10BASE-T Full Duplex Technology ability 10NFD, Unit capable Full Duplex 10BASE-T 10FD, Unit capable Full Duplex 10BASE-T 10BASE-T Half Duplex Technology ability 10NHD, Unit capable Half Duplex 10BASE-T 10HD, Unit capable Half Duplex 10BASE-T Selector Field Identifies type message being sent. Currently only value defined.
100FD
12:11
100HD
10FD
10HD
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Auto-Negotiation Link Partner Ability register used view advertised capabilities link partner once auto negotiation complete. contents this register should relied upon unless register (auto negotiation complete). After negotiation this register should contain copy link partner's register bits therefore defined same register 4.All bits readable only.This register used Base Page code word only.Base Page Register Format ANLPA Auto-Negotiation Link Partner Ability Offset Reset Value 0000H
Field
Bits
Type
Description Next Page Base Page requested Link Partner requesting Next Page function Acknowledge Link Partner acknowledgement Remote Fault Link Partner indicating fault Technology Ability Link Partner technology ability field. Selector Field Link Partner selector field
12:5
Auto-Negotiation Expansion
Auto-Negotiation Expansion
Offset
Reset Value 0004H
Field
Bits
Type
Description Parallel Detection Fault NFD, fault detected Local Device Parallel Detection Fault
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Registers Description Field LPNP Bits Type Description Link Partner Next Page Able NNP, Link Partner Next Page Able Link Partner Next Page Able Next Page Able Local device Next Page Able Local device Next Page Able Page Received NPR, Page been received Page been received Link Partner Auto Negotiation Able NAN, Link Partner Auto negotiation able Link Partner Auto negotiation able
LPAN
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Electrical Characteristics
Electrical Characteristics
Absolute Maximum Ratings
Table Parameter
Absolute Maximum Rating Symbol Min. Values Typ. Max. 2000 Idle State Suspend Mode Full Duplex Mode 100M Full Duplex Mode Unit Note Test Condition
Supply Voltage Input Voltage Output Voltage Power Consumption
VOUT
Storage Temperature Operation Temperature Rating
TSTG TAMB VESD
Operating Condition
Table Parameter
Operating Condition Symbol Min. Values Typ. Max. Unit Note Test Condition
Supply Voltage Supply Current
Specifications
7.3.1
Interface Specification
Table Parameter
Interface Specification Symbol Min. Values Typ. Max. Unit Note Test Condition
Input High Voltage Input Voltage Differential Input Sensitivity
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
EEPROM Interface Specification Table Parameter Differential Common Mode Range Output High Voltage Output Voltage Output Signal Crossover Voltage Interface Specification (cont'd) Symbol Min. Values Typ. Max. Unit Note Test Condition
VCRS
EEPROM Interface Specification
Recommended Operating Conditions
Table Parameter
EEPROM Interface Specification Symbol Min. Values Typ. Max. 1000 5.66 -0.5 Unit Note Test Condition
Input High Voltage Input Voltage Input Leakage Current Output High Voltage Output Voltage Input Capacitance
3.3V
GPIO Interface Specification
Table Parameter
GPIO Interface Specification Symbol Min. Values Typ. Max. 1000 5.64 -0.5 Unit Note Test Condition
Input High Voltage Input Voltage Input Leakage Current Output High Voltage Output Voltage Input Capacitance
Timing
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Timing
Reset Timing
ADM8513 reset either hardware, software reset. hardware reset accomplished asserting RST# after powering device. should have duration least ensure external crystal stable correct frequency. registers will reset default values. software reset accomplished setting reset (bit Ethernet Control Register (address 01H). This software reset will reset registers default values. When ADM8513 sees more than This reset will reset registers default values
Interface Timing
Table Parameter Rise Time Fall Time
GPIO Interface Specification Symbol Min. Values Typ. Max. 111.11 CL=50 CL=50 Unit Note Test Condition
Rise fall time matching
TFRFF
TFRFF =TFR /TFF
EEPROM Interface Timing
Table Parameter
EEPROM Interface Timing Symbol Min. Values Typ. Max. Unit Note Test Condition
tEESK EECS Setup Time EESK tEECSS EECS Hold Time from EESK tEECSH EEDO Hold Time from EESK tEEDOH EEDO Output Delay tEEDOP EEDI Setup Time EESK tEEDIS EEDI Hold Time from EESK tEEDIH
EESK Clock Frequency
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
EEPROM Interface Example
EECS
tEECSS tEECSH
EESK EEDI
tEESKS tEEDIS tEEDIH
tEEDOH
tEEDOP
EEDO
tEEDOP tEEDOH
Figure
EEPROM Interface Timing
EEPROM Interface Example
EEPROM contents from offset offset "FF_FF_FF_FF_FF_FF", EEPROM isn't programmed correctly. default values every field used instead loading from EEPROM. Table 06-07 0A[0] 0A[1] 0A[4:2] 0B[0] 0B[5:1] 0B[7:6] 0E-0F Data Sheet EEPROM Interface Description byte Ethernet node byte Ethernet node byte Ethernet node byte Ethernet node byte Ethernet node byte Ethernet node maximum power consumption. polling interval endpoint this value disabled. 0A[1] select internal transceiver. 0A[4:2]= node_id0 node_id1 node_id2 node_id3 node_id4 node_id5 Reserved Max_Pwr Ep3_Interval Reserved USB_Sel Mode Reserved Reserved Mode Languageid_lo Languageid_hi Reserved Manuid_lo Manuid_hi byte manufacture high byte manufacture Rev. 1.21, 2005-09-13 Refer assignment byte language high byte language
Offset(Byte) Field
ADM8513 Data Sheet
EEPROM Interface Example Table EEPROM Interface (cont'd) Description byte product high byte product length manufacture string. length product string. word offset address product string. length serial number string. word offset address serial number string. ProID_lo ProID_hi Manu_str_len Pro_str_len Pro_str_offset Seri_str_len Seri_str_offset
Offset(Byte) Field
Manu_str_offset word offset address manufacture string.
10.1
offset(byte) 0000H: 0008H: 0010H: 0018H: 0020H: 0028H: 0030H: 0038H: 0040H: 0048H: 0050H: 0058H: 0060H: 0068H: 0070H: 0078H: Table 00-05 0C-0D 10-11 12-13 Data Sheet
Example
Value EEPROM Example Description 00_00_E8_10 node _46_02 0904 A607 8513 maximum power 160mA interrupt endpoint polling interval isochronous endpoint disables, selects internal transceiver Uses internal Ethernet PHY, Wakes Language 0409 manufacture 07A6 product 8513 manufacture string length bytes manufacture string starts from word offset 10h, thus byte offset 20H. Rev. 1.21, 2005-09-13
Offset(Byte) Value
ADM8513 Data Sheet
EEPROM Interface Example Table 20-2E EEPROM Example (cont'd) Description product string length bytes product string starts from word offset 18h, thus byte offset 30H. serial number string length bytes serial number string starts from word offset 38h, thus byte offset 70H.
Offset(Byte) Value
0E:descriptor size bytes string descriptor 41.: UNICODE encoded string 1E:descriptor size bytes string descriptor 55.: UNICODE encoded string descriptor size bytes string descriptor 30.: UNICODE encoded string
30-4E
50-5A
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Package
Package
Figure
Package
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Package Note: This diagram 32pin. But, relative parameters presents 48pin package data. please ignore number regard diagram 48pin. Make example: Parameter (9mm) means distance between opposite sides. Parameter (0.8mm) means distance between adjacent pins. D&E1 means body size.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Package
Table Symbol
Dimensions LQFP Package Millimeter (mm) Min. Typ. 1.40 9.00 BSC. 7.00 9.00 7.00 0.08 0.08 0.09 0.45 0.20 0.30 3.5° 0.60 1.00 Ref. 0.35 0.80 BSC. 5.60 5.60 Tolerance Form Position 0.20 0.20 0.10 0.20 0.17 0.20 0.50 BSC. 5.00 5.00 Tolerance Form Position 0.20 0.20 0.08 0.08 0.17 0.20 0.27 0.007 0.27 0.007 0.45 0.008 0.0012 0.20 0.20 0.75 0.003 0.003 0.004 0.018 Max. 1.60 0.15 1.45 Min. 0.002 0.053 0.05 1.35 Inch Typ. 0.005 0.354 BSC. 0.276 BSC. 0.354 BSC. 0.276 BSC. 3.5° 0.024 0.039 Ref. 0.0014 0.031 BSC. 0.220 0.220 0.008 0.008 0.003 0.008 0.008 0.020 BSC. 0.197 0.197 0.008 0.008 0.003 0.003 0.008 0.011 0.011 0.018 0.008 0.008 0.030 Max. 0.063 0.006 0.057
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Package Table Symbol Dimensions LQFP Package (cont'd) Millimeter (mm) 0.50 BSC. 5.50 5.50 Tolerance Form Position 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 Inch 0.020 BSC. 0.217 0.217
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Appendix Layout Guide
Placement:
Appendix Layout Guide
side, place ADM8513 connector close possible. Ethernet side, place ADM8513, transformer RJ45 close possible. crystal device should closed ADM8513 away from following items analog signal edge other high frequency components their associated traces.
can't avoid those designs, please Resistor between Crystal OSC) ADM8513 chip clk48_I figure show:
clk48_I
CLKIN
22.1K 0.01UF
CLKOUT
clk48_O
20PF
10PF
2.2UH
Figure
Placement
Place filtering capacitor closed possible ADM8513 trace must short wide.
Figure
Placement
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Appendix Layout Guide Trace routing Keep differential pair data signal Trace width should wide possible. Make traces route same signal plane pass through other plane. Inhibit crossover termination resistance (R2,R3) decoupling capacitors (C1,C2) should closed ADM8513. Signal trace length should equal short possible. Arrangement trace Tx+/- Rx+/- trace avoid right angle round angle degree, suggested. Trace width must wide should wider than mils. Signal trace length between Tx+/- differential pairs should crossed have equal length.The total length should longer than same requirement applies Rx+/- also. Make trace route same signal plane pass through other plane. Every differential pairs cross possible, less than mils space should almost equal. Keep space large between differential pairs, even separated ground planes underneath signal pairs. Away from clock power traces. routed trace must cross, trace swapped between chip transformer, transformer RJ45,too.
Figure Trace Routing
Good
Figure
Trace Routing
Digital signal should away from analog signal traces. can't avoid this situation, analog signal trace should cross over degree other plane.
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Appendix Layout Guide
Figure
Trace Routing
trace should short prefer route format plane special GND. should have 0.1uF capacitors which placed with effective, capacitors should placed close possible pin. chassis ground plane connected type network connector chassis should isolated from signal plane with 0.1uF capacitors bead prevent radiation from leaking resulting failure. Right angle recommend when partition well planes. Avoid ground planes placing directly under transformer.See Figure below.
Power Ground
Figure
Power Ground
captive cable (plus shield wire) require additional filtering test pass length unshielded cable should limited less.
Figure Data Sheet
Power Ground Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Appendix Layout Guide Please connect Ribb resistance gnd, pin40(GndRef) pin37(GndR) first then signal (Specially layers board design).
Figure Power Ground
Good
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
References
References
Data Sheet
Rev. 1.21, 2005-09-13
ADM8513 Data Sheet
Terminology
Terminology
Data Sheet
Rev. 1.21, 2005-09-13
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Communication Edition 2005-09-13 Published Infineon Technologies

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