Product Overview Ability modify cell priority based FIFO threshol
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CelXpres® T8208 AInterconnect
Product Overview
Ability modify cell priority based FIFO thresholds Programmable priority control/data cells transmission onto cell Microprocessor access headers control cell Ability clear counters read Simplified looping system device with single register programming UTOPIA clock sourcing with additional settings Programmable operations maintenance resource management (OAM/RM) cell routing Support multicast broadcast cells Optional monitoring misrouted cells Counters dropped cells queue Digital loopback before cell Microprocessor interface, supporting both Motorola® Intel modes (multiplexed nonmultiplexed) Control cell transmission reception through microprocessor port Single power supply tolerant) 272-pin plastic ball grid array (PBGA) package Industrial temperature range (-40 insertion capability Eight GPIO pins JTAG support Compatible with Transwitch CellBus®
last issue this data sheet September, 2001. change bars have been installed text that changed. only change this data sheet ordering information page 214.
Features
OC-12 data throughput UTOPIA (16-bit) (independently UTOPIA) Shared UTOPIA mode UTOPIA Level (8-bit/16-bit) cell-level handshake interface (Aor layers) Multi-PHY (MPHY) operation Programmable Alayer supports ports Egress SDRAM buffer support extend UTOPIA output priority queues 512K cells: queues configurable four queues with programmable sizes Programmable number UTOPIA output queues with four levels priority Support Atraffic management partial packet discard (PPD), forward explicit congestion notification (FECN), cell loss priority (CLP) Programmable slew rate GTL+ I/O: Programmable arbiter Gbits/s cell operation Flexible port cell counters Cell header insertion with virtual path identifier (VPI) virtual channel identifier (VCI) translation external SRAM entries) Support network node interface (NNI) user network interface (UNI) header types with optional generic flow-control (GFC) insertion Optional sourcing cell clocks from device bypass option UTOPIA cell buffer increased cells better queue management with SDRAM queue bypass option Ability cell arbiter mask devices cell
Applications
Asymmetric digital subscriber line (ADSL) digital subscriber line access multiplexers (DSLAMs) Access gateways Access multiplexers/concentrators Multiservice platforms
CelXpres T8208 AInterconnect
Table Contents
Contents
Page
Product Overview.1 Features Applications Description Conventions Glossary Pinout Powerup/Reset Sequence Insertion.23 Configuration Microprocessor Interface Microprocessor Interface Configuration Microprocessor Interrupts.25 Accessing CelXpres T8208 Microprocessor Interface.25 6.3.1 Accessing Extended Memory Registers.26 6.3.1.1 Extended Memory Writes.26 6.3.1.2 Extended Memory Reads.26 6.3.2 CelXpres T8208 Access Performance General-Purpose (GPIO) Look-Up Table Look-Up Table RAM.29 Organization Look-Up Procedure Extended Records.38 Diagnostics.42 Setup Bypass.42 UTOPIA Interface.43 Incoming UTOPIA Cell Interface 9.1.1 Incoming Mode (Cells Received T8208) 9.1.2 Incoming AMode (Cells Received T8208).44 Outgoing UTOPIA Cell Interface 9.2.1 Outgoing Mode (Cells Sent T8208).45 9.2.2 Outgoing AMode (Cells Sent T8208) Counters.48 9.3.1 Dropped Cell Counters.49 55-Byte UTOPIA Mode.49 Shared UTOPIA Mode UTOPIA Modes 9.6.1 UTOPIA Modes 8-Bit UTOPIA Operation 9.6.2 UTOPIA Modes 16-Bit UTOPIA Operation UTOPIA Clocking Option Counters Clear Read.58 Cell Interface.59 10.1 General Architecture 10.2 Cell Frames.61 10.3 Cell Routing Headers 10.3.1 Control Cells.65 10.3.2 Data Cells.65 10.3.3 Loopback Cells.66 10.3.4 Multicast Routing.66 10.3.5 Broadcast Routing.67 Agere Systems Inc.
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Table Contents (continued)
Contents Page
10.4 Cell Arbitration 10.5 Cell Monitoring. 10.6 GTL+ Logic 10.7 Cell Write Read Clocks. 10.8 Modify Cell Request Priority Based FIFO Threshold. 10.9 Digital Loopback Before Cell SDRAM Interface. 11.1 Memory Configuration. 11.2 Powerup Sequence. 11.3 SDRAM Interface Timing 11.4 Queuing 11.5 SDRAM Refresh 11.6 SDRAM Throughput. Traffic Management. 12.1 Cell Loss Priority (CLP). 12.2 Forward Explicit Congestion Notification (FECN) 12.3 Partial Packet Discard (PPD). JTAG Test Access Port 13.1 Instruction Register 13.2 Boundary-Scan Register. Registers. 14.1 Register Types. 14.2 Direct Memory Access Registers. 14.2.1 Little-Endian Format (big_end Extended Memory Access Registers 30h-37h. 14.2.2 Big-Endian Format (big_end Extended Memory Access Registers 30h-37h 14.2.3 General-Purpose Control Registers 14.2.4 Control Cells 14.2.5 Multicast Memories 14.3 Extended Memory Registers. 14.3.1 Main Registers 14.3.2 UTOPIA Registers 14.3.2.1 UTOPIA Configuration 14.3.2.2 UTOPIA Monitoring 14.3.2.3 UTOPIA Count Monitoring 14.3.2.4 UTOPIA Configuration Monitoring 14.3.3 SDRAM Registers 14.3.3.1 SDRAM Control Memory 14.3.4 Various Internal Memories 14.3.4.1 Control Cell Memories 14.3.4.2 Multicast Number Memories 14.3.4.3 State Memory 14.3.5 Dropped Cell Count 14.3.6 External Memories 14.3.6.1 Look-Up Translation Memory 14.3.6.2 SDRAM Buffer Memory Absolute Maximum Ratings Recommended Operating Conditions. Handling Precautions. Electrical Requirements Characteristics 18.1 Crystal Information. 18.2 Electrical Characteristics.
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Table Contents (continued)
Contents Page
Timing Requirements 19.1 Microprocessor Interface Timing 19.2 UTOPIA Timing 19.3 External Memory Timing. 19.4 Cell Timing 19.5 SDRAM Interface Timing. Outline Diagram Ordering Information
List Figures
Figure Page
Figure Functional Block Diagram Figure Dual Implementation Figure 272-Pin PBGA-Top View Figure Translation Memory Map-8-Byte Records Figure Translation Record Types-8-Byte Records. Figure Translation Flow Diagram Figure Translation Record Types-Extended Mode Figure Translation Memory Map-Extended Mode. Figure Queue Priority Multiplexing Figure UTOPIA Cell Handling Figure UTOPIA Sharing 8-Bit UTOPIA Mode Figure UTOPIA Sharing 16-Bit UTOPIA Mode Figure Cell Frame Format (Bit Positions 16-User Mode) Figure Cell Frame Format (Bit Positions 32-User Mode) Figure Cell Routing Headers Figure GTL+ External Circuitry Figure SDRAM Timing Parameters Figure Crystal Figure Negative Resistance Plot Figure Nonmultiplexed Intel Mode Write Access Timing Figure Nonmultiplexed Intel Mode Read Access Timing. Figure Motorola Mode Write Access Timing. Figure Motorola Mode Read Access Timing Figure Multiplexed Intel Mode Write Access Timing. Figure Multiplexed Intel Mode Read Access Timing Figure External Memory Read Timing (cyc_per_acc cyc_per_acc Figure External Memory Write Timing (cyc_per_acc cyc_per_acc Figure Cell Timing Figure SDRAM Interface Timing.
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List Tables
Table Page
Table UTOPIA Pins Table Shared UTOPIA Pins Table Cell Pins Table SDRAM Interface Pins Table Microprocessor Interface Pins Table Translation SRAM Interface Table JTAG Pins Table General-Purpose Pins Table Power Pins Table Loop Filter Register Settings Table Access Times Table Active Ignore Truth Table Table Value Truth Table Table Routing Control Truth Table Table Translation Record Addresses Table-8-Byte Records Table Translation Record Addresses Table-Extended Mode Table Configuration 8-Bit UTOPIA Table Configuration 16-Bit UTOPIA Table Supported Memory Configurations Table Queue Organization Port Group Address/Priority Bits Ports 8-Bit UTOPIA Mode Table Queue Organization Port Group Address/Priority Bits Ports 8-Bit UTOPIA Mode Ports 16-Bit UTOPIA Mode Table Instruction Register Table Boundary-Scan Register Descriptions Table Register Table Identification (IDNT0) (00h) Table Identification (IDNT1) (01h) Table Identification (IDNT2) (02h) Table Direct Configuration/Control Register (DCCR) (28h). Table Interrupt Service Request (ISREQ) (29h) Table mclk Configuration (MPLLCF0) (2Ah) Table mclk Configuration (MPLLCF1) (2Bh) Table GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) Table GTL+ Control (GTLCNTRL) (2Fh) Table Extended Memory Address (Little Endian) (EMA1_LE) (30h) Table Extended Memory Address (Little Endian) (EMA2_LE) (31h) Table Extended Memory Address (Little Endian) (EMA3_LE) (32h) Table Extended Memory Address (Little Endian) (EMA4_LE) (33h) Table Extended Memory Access (Little Endian) (EMA_LE) (34h) Table Extended Memory Data (Little Endian) (EMDL_LE) (36h) Table Extended Memory Data High (Little Endian) (EMDH_LE) (37h) Table Extended Memory Address (Big Endian) (EMA4_BE) (30h) Table Extended Memory Address (Big Endian) (EMA3_BE) (31h) Table Extended Memory Address (Big Endian) (EMA2_BE) (32h) Table Extended Memory Address (Big Endian) (EMA1_BE) (33h) Table Extended Memory Access (Big Endian) (EMA_BE) (34h) Table Extended Memory Data High (Big Endian) (EMDH_BE) (36h) Table Extended Memory Data (Big Endian) (EMDL_BE) (37h) Table GPIO Output Enable (GPIO_OE) (39h) Table GPIO Output Value (GPIO_OV) (3Bh) Table GPIO Input Value (GPIO_IV) (3Dh)
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List Tables (continued)
Table Page
Table Control Cell Receive Direct Memory (CCRXDM) (5Ch 93h) .102 Table Control Cell Transmit Direct Memory (CCTXDM) (A0h D7h) .102 Table Port Control Cells Multicast Direct Memory (PP0MDM) (E0h FFh) .103 Table Main Configuration (MCF1) (0100h) .104 Table Main Interrupt Status (MIS1) (0102h) .105 Table Main Interrupt Enable (MIE1) (0104h) .106 Table UTOPIA Clock Configuration (TXUCCF) (010Ch) .107 Table UTOPIA Clock Configuration (RXUCCF) (010Eh) .108 Table Main Configuration/Control (MCFCT) (0110h) .109 Table Main Configuration (MCF2) (0112h) .110 Table UTOPIA Configuration (UCF) (0114h) .113 Table Main Configuration (MCF3) (0116h) .113 Table UTOPIA Configuration (UCF5) (0118h) .114 Table UTOPIA Configuration (UCF4) (011Ah) .114 Table UTOPIA Configuration (UCF3) (011Ch) .114 Table UTOPIA Configuration (UCF2) (011Eh) .114 Table Extended Control (ELUTCN) (0120h) .115 Table Generated Cell Clocks Control Register (GCBCCR) (0122h) .116 Table FIFO Thresholds Change Cell Request Priority (RXPFTCRP) (0126h) .118 Table Enable Request Upper Backplane Address (ERUB) (012Ch) .119 Table Enable Request Lower Backplane Address (ERLB) (012Ch) Table Cell Configuration/Status (CBCFS) (0130h) .120 Table Main Interrupt Status (MIS2) (0132h) .121 Table Main Interrupt Enable (MIE2) (0134h) .122 Table Loopback (LB) (0136h) .122 Table Extended Configuration (ELUTCF) (0138h) .122 Table Misrouted Cell (MLUT3) (013Ch) Table Misrouted Cell (MLUT2) (013Eh) Table Misrouted Cell (MLUT1) (0140h) .123 Table Misrouted Cell (MLUT0) (0142h) .123 Table Misrouted Cell (MLUT4) (0144h) .124 Table Misrouted Cell Header High (MCHH) (0146h) Table Misrouted Cell Header (MCHL) (0148h) Table Interrupt Status (HIS3) (0300h) Table Interrupt Status (HIS2) (0302h) Table Interrupt Status (HIS1) (0304h) .125 Table Interrupt Status (HIS0) (0306h) .125 Table Interrupt Enable (HIE3) (0308h) .126 Table Interrupt Enable (HIE2) (030Ah) .126 Table Interrupt Enable (HIE1) (030Ch) .126 Table Interrupt Enable (HIE0) (030Eh) .126 Table Interrupt Service Request (LUTISR3) (0310h) .127 Table Interrupt Service Request (LUTISR2) (0312h) .127 Table Interrupt Service Request (LUTISR1) (0314Ch) .127 Table Interrupt Service Request (LUTISR0) (0316h) .127 Table Configuration/Status (LUTXCFS) (0320h 039Eh) .128 Table Master Queue (MQ7) (0150h) Table Master Queue (MQ6) (0152h) Table Master Queue (MQ5) (0154h) Table 100. Master Queue (MQ4) (0156h) .131 Table 101. Master Queue (MQ3) (0158h) .131 Table 102. Master Queue (MQ2) (015Ah) .131
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List Tables (continued)
Table Page
Table 103. Master Queue (MQ1) (015Ch) Table 104. Master Queue (MQ0) (015Eh) Table 105. Slave Queue (SQ7) (0160h) Table 106. Slave Queue (SQ6) (0162h) Table 107. Slave Queue (SQ5) (0164h) Table 108. Slave Queue (SQ4) (0166h) Table 109. Slave Queue (SQ3) (0168h) Table 110. Slave Queue (SQ2) (016Ah) Table 111. Slave Queue (SQ1) (016Ch) Table 112. Slave Queue (SQ0) (016Eh) Table 113. FIFO Routing (TXPFR7) (0170h) Table 114. FIFO Routing (TXPFR6) (0172h) Table 115. FIFO Routing (TXPFR5) (0174h) Table 116. FIFO Routing (TXPFR4) (0176h) Table 117. FIFO Routing (TXPFR3) (0178h) Table 118. FIFO Routing (TXPFR2) (017Ah) Table 119. FIFO Routing (TXPFR1) (017Ch) Table 120. FIFO Routing (TXPFR0) (017Eh) Table 121. Global Bypass SDRAM Control Register (GBSCR) (01B0h) Table 122. Bypass SDRAM Service Request Register (BSSR) (01BEh) Table 123. Bypass SDRAM Queue Interrupt Status Register (BSQISR0) (01C0h) Table 124. Bypass SDRAM Queue Interrupt Status Register (BSQISR1) (01C2h) Table 125. Bypass SDRAM Queue Interrupt Status Register (BSQISR2) (01C4h) Table 126. Bypass SDRAM Queue Interrupt Status Register (BSQIS30) (01C6h) Table 127. Bypass SDRAM Queue Interrupt Status Register (BSQISR4) (01C8h) Table 128. Bypass SDRAM Queue Interrupt Status Register (BSQISR5) (01CAh) Table 129. Bypass SDRAM Queue Interrupt Status Register (BSQISR6) (01CCh) Table 130. Bypass SDRAM Queue Interrupt Status Register (BSQISR7) (01CEh) Table 131. Bypass SDRAM Queue Interrupt Status Register (BSQISR8) (01D0h) Table 132. Bypass SDRAM Queue Interrupt Status Register (BSQISR9) (01D2h) Table 133. Bypass SDRAM Queue Interrupt Status Register (BSQISR10) (01D4h) Table 134. Bypass SDRAM Queue Interrupt Status Register (BSQISR11) (01D6h) Table 135. Bypass SDRAM Queue Interrupt Status Register (BSQISR12) (01D8h) Table 136. Bypass SDRAM Queue Interrupt Status Register (BSQISR13) (01DAh) Table 137. Bypass SDRAM Queue Interrupt Status Register (BSQISR14) (01DCh) Table 138. Bypass SDRAM Queue Interrupt Status Register (BSQISR15) (01DEh) Table 139. Routing Information (RI1) (0200h) Table 140. Routing Information (RI2) (0202h) Table 141. Routing Information (RI3) (0204h) Table 142. Information (PPDI1) (0206h) Table 143. Information (PPDI2) (0208h) Table 144. Information (PPDI3) (020Ah) Table 145. Information (PPDI4) (020Ch) Table 146. Information (PPDI5) (020Eh) Table 147. Information (PPDI6) (0210h) Table 148. Information (PPDI7) (0212h) Table 149. Routing Information (RI4) (0214h) Table 150. Memory Write (PPDMW) (0418h) Table 151. Port Transmit Count Structure (PPXTXCNT) (0600h 06FEh) Table 152. Port Receive Count Structure (PPXRXCNT) (4000h 40FEh) Table 153. Port Configuration Structure (PPXCF) (4200h 42FEh) Table 154. SDRAM Control (SCT) (0400h) Table 155. SDRAM Interrupt Status (SIS) (0402h)
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List Tables (continued)
Tables Pages
Table 156. SDRAM Interrupt Enable (SIE) (0404h) .179 Table 157. SDRAM Configuration (SCF) (0408h) .180 Table 158. Refresh (RFRSH) (0410h) .181 Table 159. Refresh Lateness (RFRSHL) (0412h) .181 Table 160. Idle State (IS1) (0420h) .181 Table 161. Idle State (IS2) (0422h) .181 Table 162. Manual Access State (MAS1) (0424h) .182 Table 163. Manual Access State (MAS2) (0426h) .182 Table 164. SDRAM Interrupt Service Request (SISR7) (0430h) .183 Table 165. SDRAM Interrupt Service Request (SISR6) (0432h) .183 Table 166. SDRAM Interrupt Service Request (SISR5) (0434h) .183 Table 167. SDRAM Interrupt Service Request (SISR4) (0436h) Table 168. SDRAM Interrupt Service Request (SISR3) (0438h) .184 Table 169. SDRAM Interrupt Service Request (SISR2) (043Ah) .184 Table 170. SDRAM Interrupt Service Request (SISR1) (043Ch) .184 Table 171. SDRAM Interrupt Service Request (SISR0) (043Eh) .184 Table 172. Queue (QX) (0440h 053Eh) .185 Table 173. Queue Definition Structure (QXDEF) (2000h 2FFEh) .187 Table 174. Control Cell Receive Extended Memory (CCRXEM) (07FCh 0832h) .190 Table 175. Control Cell Transmit Extended Memory (CCTXEM) (0900h 0936h) .190 Table 176. Port Control Cells Multicast Extended Memory (PP0MEM) (0C00h 0C1Eh) .191 Table 177. Port Multicast Memory (PPXMM) (0C20h 0FFEh) .192 Table 178. Memory (PPDM) (1000h 13FEh) .193 Table 179. Queue Dropped Cell Count (QXDCC) (3000h 31FEh) .194 Table 180. Translation Memory (TRAM) (100000h 17FFFEh) .197 Table 181. SDRAM (SDRAM) (2000000h 3FFFFFEh) .197 Table 182. Maximum Rating Parameters Values .198 Table 183. Recommended Operating Conditions .198 Table 184. Threshold .198 Table 185. Crystal Specifications .199 Table 186. External Clock Requirements .199 Table 187. Electrical Characteristics .200 Table 188. Input Clocks .201 Table 189. Output Clocks .201 Table 190. Nonmultiplexed Intel Mode Write Access Timing .203 Table 191. Nonmultiplexed Intel Mode Read Access Timing .203 Table 192. Motorola Mode Write Access Timing .205 Table 193. Motorola Mode Read Access Timing .205 Table 194. Multiplexed Intel Mode Write Access Timing .207 Table 195. Multiplexed Intel Mode Read Access Timing .207 Table 196. UTOPIA Timing Load Outputs) .208 Table 197. UTOPIA Timing Load Outputs) .208 Table 198. External Memory Read Timing (cyc_per_acc .210 Table 199. External Memory Read Timing (cyc_per_acc .210 Table 200. External Memory Write Timing (cyc_per_acc .210 Table 201. External Memory Write Timing (cyc_per_acc .210 Table 202. Cell Timing .211 Table 203. SDRAM Interface Timing .212
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Product Overview (continued)
Description
CelXpres T8208 device integrates required functionality transport Acells across backplane architecture with high-speed cell traffic exceeding Gbits/s maximum destinations. management multiple service categories monitoring performance Aand interfaces incorporated device's functionality. Traffic delivery multi-PHYs (MPHYs) managed through UTOPIA interface. T8208 device meets AForum's universal test operations interface A(UTOPIA) Level Version 2.01 Level Version specifications cell-level handshake MPHY data path operation with rates Mbits/s. T8208 supports required MPHY operation described Sections AForum's level specification. T8208 supports MPHY operation with transmit cell available (TxCLAV) signal receive cell available (RxCLAV) signal ports 8-bit UTOPIA interface configuration. With four transmit cells available/enable (TxCLAV/Enb*) pairs signals receive cell available/enable (RxCLAV/Enb*) pairs signals, MPHYs supported. 16-bit UTOPIA interface configuration, T8208 supports MPHY operation with transmit cell available (TxCLAV) signal receive cell available (RxCLAV) signal ports. With four transmit cell available (TxCLAV/Enb*) signals four receive cell available (RxCLAV/Enb*) signals, MPHYs supported 16-bit UTOPIA interface configuration. addition required UTOPIA signals, optional transmit parity (TxPRTY) receive parity (RxPRTY) signals provided. T8208 configured level device providing cell routing between UTOPIA 32-bit wide cell bus. addition data signals, following signals: Read clock Write clock Frame sync Acknowledge Acells arriving from UTOPIA interface translation routing information from lookup table external SRAM. external synchronous dynamic random access memory (SDRAM) used extend buffering Acells destined UTOPIA interface. This external SDRAM partitioned into four less independently sized queues configuration MPHYs queues programmable number queues configuration MPHYs. four queues used support quality service (QoS) directing different traffic categories each queue. number cells queue programmable. CelXpres T8208 provides shared UTOPIA mode, which allows devices different cell buses share same UTOPIA Amode. Using glueless interface, T8208 devices resolve queue priorities arbitrate UTOPIA bus. This shared mode used provide redundancy increase UTOPIA traffic capacity supporting traffic from multiple cell busses. CelXpres T8208 supports transport control loopback cells with external microprocessor. Control loopback cells sent received through microprocessor interface. 8-bit microprocessor interface configured Motorola Intel compatible used configure monitor device.
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Product Overview (continued)
256K (LUT) SRAMs
LOOK-UP ENGINE UTOPIA UTOPIA INTERFACE UTOPIA FIFO CELLS) FIFO CELLS)
CELL ARBITER
MICROPROCESSOR
MICROPROCESSOR INTERFACE
CONTROL CELL FIFO CELL)
CELL OUTPUT FIFO CELLS) CELL INTERFACE CELL
LOOPBACK FIFO CELL) DIGITAL LOOPBACK
CONTROL CELL FIFO CELLS)
UTOPIA
UTOPIA INTERFACE
UTOPIA CELL BUFFER (256 CELLS)
FIFO (256 CELLS)
CELL INPUT FIFO CELLS) SDRAM INTERFACE CELL MONITORING
SDRAM 5-7542d
Figure Functional Block Diagram
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Product Overview (continued)
Figure illustrates CelXpres T8208 system with dual backplane cell buses using shared UTOPIA mode. this configuration, both T8208 devices each card receive cells from UTOPIA bus, each device uses translation table determine cell should transmitted backplane cell bus. egress direction, each T8208 device receives cells from cell transmit UTOPIA bus. MPHY arbitration queue priorities resolved using six-wire interface between devices. Although single Avirtual connection typically established both backplane cell buses simultaneously, restrictions exist single utilizing both backplane cell buses different virtual connections supporting higher throughput from interfaces. Redundant configurations supported event failure with T8208 devices configuring device assume responsibility from other.
DOWNSTREAM BUFFERING
UPSTREAM TRANSLATION UTOPIA
T8208
UTOPIA PHYs T8208
DOWNSTREAM BUFFERING
UPSTREAM TRANSLATION
DOWNSTREAM BUFFERING
UPSTREAM TRANSLATION UTOPIA
T8208 BACKPLANE T8208
UTOPIA PHYs
DOWNSTREAM BUFFERING
UPSTREAM TRANSLATION
0041b
Figure Dual Implementation
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Product Overview (continued)
Conventions
numbers this document decimals unless otherwise specified. Hexadecimal numbers identified suffix, e.g., A5h. Binary numbers either double quotes multiple bits single quotes individual bits, e.g., "1001" `0.' byte bits, word bits, double word (dword) bits. binary value high, binary value low. clear change multiple values `0.' change multiple values `1.' memory addresses specified hexadecimal. Addresses converted from bytes words double words using little-endian format, unless otherwise specified. signal name with trailing asterisk active-low, e.g., sd_we*. Bits will designated bits (y:x).
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PTI: Payload type identifier. 3-bit field cell header containing information about type data (user, OAM, traffic management) about encountered congestion. QoS: Quality service. Quality service parameters define performance requirements characteristics traffic assigned channel. Some parameters include cell loss ratio, cell transfer delay, cell delay variation, peak cell rate, sustained cell rate. Request Section: First bytes cell frame. request section occurs during first clock cycle cell frame. During this cycle, T8208 devices assert their transmission requests onto cell bus. Resource management. local management network resources. RxCLAV: Receive cell available signal described AForum's universal test operations interface A(UTOPIA) Level Version 2.01 Level Version specifications. RxENB: Receive enable signal described AForum's universal test operations interface A(UTOPIA) Level Version 2.01 Level Version specifications. TxCLAV: Transmit cell available signal described AForum's universal test operations interface A(UTOPIA) Level Version 2.01 Level Version specifications. TxENB: Transmit enable signal described AForum's universal test operations interface A(UTOPIA) Level Version 2.01 Level Version specifications. UNI: User network interface. interface between private network node public network node. VCI: Virtual channel identifier. 2-byte field cell header that identifies virtual channel used cell. VPI: Virtual path identifier. 8-bit field cell header 12-bit field cell header that identifies virtual path cell.
Product Overview (continued)
Glossary
Cell: Major content cell frame consisting bytes, bytes routing options bytes Acell content, which excludes HEC. cell preceded bytes request followed bytes grant parity information. CLP: Cell loss priority. 1-bit field cell header that becomes when cell violates negotiated quality service parameters. EFCI: Explicit forward congestion indication. EFCI 1-bit field field cell header that becomes when cell encounters congestion. FECN: Forward explicit congestion notification. FECN method used network signal destination when congestion encountered. EFCI used indicate congestion. GFC: Generic flow control. 4-bit field cell header that used support traffic congestion control. Typically, this field programmed "0000" indicating that generic flow control supported. used priority protocols. Grant Section: Last bytes cell frame. grant section occurs during last clock cycle cell frame. During this cycle, cell arbiter indicates which T8208 transmit during next cell unit cell frame. parity vector also transmitted during grant section. HEC: Header error control. 1-byte field cell header used error detection correction header. NNI: Network node interface. interface between nodes public network. Cell: Operations maintenance cell. cell carries local management information. PPD: Partial packet discard. technique relieve congestion. When cell packet lost, remaining cells packet, except last, discarded.
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Pinout
This section defines CelXpres T8208 pins. compatible inputs tolerant. GTL+ inputs tolerant. Table UTOPIA Pins Symbol
u_rxaddr[4:0]
Ball
Reset Type Value
Name/Description
UTOPIA Address Lines. drive, compatible I/O, tolerant. UTOPIA Data Lines. compatible input, tolerant.
u_rxdata[15:0] u_rxclk u_rxsoc u_rxclav[0]
u_rxclav[3:1]
u_rxenb*[0] u_rxenb*[3:1] u_rxprty u_txaddr[4:0]
P17, R19, R20, P18, u_txdata[15:0] Y18, U16, V17, W18, Y19, V18, W19, Y20, W20, V19, U19, U18, T17, V20, U20, u_txclk u_txsoc u_txclav[0]
UTOPIA Clock. drive, compatible I/O, tolerant. UTOPIA Start Cell (Active-High). compatible input, tolerant. UTOPIA Cell Available (Active-High). Main cell available single mode. drive, compatible I/O, tolerant. This internal pull-up resistor. UTOPIA Cell Available Lines (Active-High). compatible input, tolerant. These pins have internal pull-up resistor. UTOPIA Enable (Active-Low). Main enable single mode. drive, compatible I/O, tolerant. UTOPIA Enable Lines (Active-Low). drive, compatible I/O, tolerant. UTOPIA Parity. compatible input, tolerant. This internal pull-up resistor. UTOPIA Address Lines. drive, compatible I/O. tolerant. UTOPIA Data Lines. drive, compatible output.
u_txclav[3:1]
M17, M18,
u_txenb*[0] u_txenb*[3:1] u_txprty
P20, N18,
UTOPIA Clock. drive, compatible I/O, tolerant. UTOPIA Start Cell (Active-High). drive, compatible output. UTOPIA Cell Available (Active-High). Main cell available single mode. drive, compatible I/O. tolerant. This internal pull-up resistor. UTOPIA Cell Available Lines (Active-High). compatible input, tolerant. These pins have internal pull-up resistor. UTOPIA Enable (Active-Low). Main enable single mode. drive, compatible I/O, tolerant. UTOPIA Enable Lines (Active-Low). drive, compatible output. UTOPIA Parity. drive, compatible output.
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Pinout (continued)
Table Shared UTOPIA Pins Symbol u_shr_grant[1:0] Ball W17, Reset Value Type Name/Description Shared UTOPIA Grant. Used grant device shared. UTOPIA master indicate approval requested cell transfer. drive, compatible I/O. These pins have internal pull-up resistor. Shared UTOPIA Request. Used indicate cell transferred from requested queue device shared UTOPIA slave. drive, compatible I/O. These pins have internal pull-up resistor.
u_shr_req[3:0]
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Pinout (continued)
Table Cell Pins Symbol ua*[4:0] Ball B18, B17, C17, D16, A11, C11, B11, A12, B12, C12, D12, A13, B13, C13, A14, B14, C14, A15, B15, Reset Value Type Name/Description Unit Address Lines (Active-Low). Address assigned device cell identification. compatible input, tolerant. Cell Data Lines (Active-Low). GTL+ I/O.
cb_d*[31:0]
cb_wc*
cb_rc*
cb_fs* cb_ack*
arb_en*
cb_disable*
cb_iref
cb_vref
cb_vref_vss cb_gen_wc
cb_gen_rc
Cell Write Clock (Active-Low). Uses falling edge output data cell bus. Write read clocks have same frequency different phase. GTL+ input. Cell Read Clock (Active-Low). Uses falling edge latch data from cell bus. Write read clocks have same frequency different phase. GTL+ input. Cell Frame Sync (Active-Low). GTL+ I/O. Cell Acknowledge Signal (Active-Low). Driven cycle following frame when valid cell received from cell bus. This signal driven broadcast multicast cells. GTL+ I/O. Cell Arbiter Enable (Active-Low). Cell arbiter enable. Only device cell configured arbiter. TTL-compatible input, tolerant. This internal pull-up resistor. Cell Disable (Active-Low). CMOS input that 3states GTL+ outputs when low, GTL+ buffer inputs active. This internal pull-up resistor. Cell Current Reference. Precision current reference GTL+ buffers. resistor must connected between this GND. Cell Voltage Reference. GTL+ buffer threshold voltage reference (1.0 typical). This voltage reference VTT, created using voltage divider three resistors between cb_vref_vss. Cell Voltage Reference Ground. Cell Generated Write Clock. Compatible driver. drive. This write clock generated T8208 device. Read/write clock delay register 0122h bits[15:13]. Cell Generated Read Clock. Compatible driver. drive. This read clock generated T8208 device. Read/write clock delay register 0122h bits[15:13].
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Pinout (continued)
Table SDRAM Interface Pins Symbol sd_a[11:0] Ball L19, L18, L20, K20, K19, K18, K17, J20, J19, J18, J17, F19, E20, G17, F18, E19, D20, E18, D19, E17, D18, C19, B20, C18, B19, H18, Reset Value Type Name/Description SDRAM Address Lines. drive, compatible output. These buffers impedance matching buffers. Long printed-wiring board traces should have nominal impedance. SDRAM Data Lines. drive, compatible I/O. These buffers impedance matching buffers. Long printedwiring board traces should have nominal impedance.
sd_d[15:0]
sd_bs[1:0]
sd_ras*
sd_cas*
sd_we*
sd_clk
sd_iref
SDRAM Bank Selects. drive, compatible output. These buffers impedance matching buffers. Long printed-wiring board traces should have nominal impedance. SDRAM Address Select (Active-Low). drive, compatible output. This buffer impedance matching buffer. Long printed-wiring board traces should have nominal impedance. SDRAM Column Address Select (Active-Low). drive, compatible output. This buffer impedance matching buffer. Long printed-wiring board traces should have nominal impedance. SDRAM Write Enable (Active-Low). drive, compatible output. This buffer impedance matching buffer. Long printed-wiring board traces should have nominal impedance. SDRAM Clock. drive, compatible output. This buffer impedance matching buffer. Long printedwiring board traces should have nominal impedance. SDRAM Current Reference. Precision current reference SDRAM buffers. resistor must connected between this GND.
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Pinout (continued)
Table Microprocessor Interface Pins Symbol a[7:1] a[0]/ale Ball Reset Value Type Name/Description Microprocessor Port Address Lines. Most significant bits address bus. compatible input, tolerant. Microprocessor Port Address 0/Address Latch Enable. Least significant address nonmultiplexed mode address latch enable multiplexed mode. Microprocessor Port Data Lines. drive, compatible I/O, tolerant. Microprocessor Chip Select (Active-Low). compatible input, tolerant. Microprocessor Write/Data Strobe. Active-low write enable Intel mode. Active-low data strobe Motorola mode. compatible input, tolerant. Microprocessor Read/Write. Active-low read enable Intel mode, read/write* enable Motorola mode, where read active-high write active-low. compatible input, tolerant. Interrupt. Active-high Intel mode active-low Motorola mode. drive, compatible output. Ready/Data Transfer Acknowledge. Active-high ready signal Intel mode active-low data transfer acknowledge Motorola mode. Indicates access complete. drive, compatible output. Intel/Motorola Selection. Intel, Motorola. compatible input, tolerant. Microprocessor Multiplex Select. Active-high multiplex mode. compatible input, tolerant.
d[7:0]
sel* wr*_ds*
W10, V10, Y10,
rd*_rw*
int_irq* rdy_dtack*
mot_sel
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Pinout (continued)
Table Translation SRAM Interface Symbol tr_a[17:0] Ball Reset Value Type Name/Description Translation Address Lines. drive, compatible output.
tr_d[7:0] tr_cs*[1:0]
tr_oe* tr_we*
Translation Data Lines. drive, compatible I/O, tolerant. Translation Chip Selects (Active-Low). Chip selects select external SRAMs. connection external device, tr_cs*[0] used. drive, compatible output. External Output Enable (Active-Low). drive, compatible output. External Write Enable (Active-Low). drive, compatible output.
Table JTAG Pins Symbol jtag_tdi jtag_tdo jtag_trst* Ball Reset Value Type Name/Description Test Data Input (JTAG). compatible input, tolerant. This internal pull-up resistor. Test Data Output (JTAG). drive, compatible output. Test Reset (JTAG) (Active-Low). Should pulled when part normal operation. compatible input, tolerant. This internal pull-up resistor. Test Clock (JTAG). compatible input, tolerant. This internal pull-up resistor. Test Mode Select (JTAG). compatible input, tolerant. This internal pull-up resistor.
jtag_tclk jtag_tms
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Pinout (continued)
Table General-Purpose Pins Symbol gpio[7:0] reset* xtalin Ball Reset Value Type Name/Description General-Purpose I/O. drive, compatible I/O, tolerant. These pins have internal pull-up resistor. Reset (Active-Low). Schmitt trigger, compatible input, tolerant. Crystal Input (pclk). This input driven either crystal external clock. crystal used, connect between this xtalout connect appropriately valued capacitor from this VSS. external clock used, this tolerant CMOS input with input frequency. Crystal Output Feedback. crystal used, connect between this xtalin connect appropriately valued capacitor from this VSS. external clock used drive xtalin, this must left unconnected. Buffered Clock Output. enabled, pclk output this pin. drive, compatible output. This high impedance enabled. Enable. Enable buffered clock output. used, this enable low. Active-high, compatible input, tolerant. Connection. Reserved.
xtalout
cko_e
A16, Y15,
Table Power Pins Symbol Ball D11, D15, F17, L17, R17, U10, D13, D17, H17, J10, J11, J12, K10, K11, K12, L10, L11, L12, M10, M11, M12, N17, U13, Name/Description Power. These pins should properly decoupled using 0.01 capacitors. Ground.
VDDA
Clock Oscillator Power. This should properly decoupled using 0.01 capacitors.
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Pinout (continued)
5-8013(f)
Figure 272-Pin PBGA-Top View
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Powerup/Reset Sequence
following methods used reset T8208: Assert reset* least pclk periods whichever longer, then return high hardware reset. powerup reset, reset* should held least pclk periods whichever longer, after power supply ramps operating voltage crystal oscillator stable. Write both srst* srst_reg* bits direct configuration/control register (address 28h) `0,' leave them that value least perform software reset.
device reset state, following start-up procedure must executed ensure proper operation: After pclk (xtalin) provided T8208, device reset state: Write mclk configuration registers addresses 2Bh. Continue after stabilized srst_reg* take main registers reset), program cyc_per_acc big_end bits direct configuration/control register (address 28h). Wait circuit stabilize.
Extended memory accesses performed only main register group. Write desired values main configuration register (address 0100h), UTOPIA clock configuration register (address 010Ch), UTOPIA clock configuration register (address 010Eh) extended memory registers. These bits should modified later time without returning reset state. Program main configuration register (address 0112h) UTOPIA configuration register (address 0114h). These registers should modified later time without returning reset state. Program cb_arb_sel cb_usr_mode bits cell configuration/status register (address 0130h). Wait clock period slowest clock (cell bus, UTOPIA, pclk) circuit stabilize. srst* direct configuration/control register (address 28h). Wait three clock periods slowest clock (cell bus, UTOPIA, pclk) circuit stabilize.
T8208 device reset state. Initialize SDRAM SDRAM specifications. Enable SDRAM setting sdram_en SDRAM control register (address 0400h). Initialize benign values (recommended). Initialize multicast memory (recommended). Program four routing information registers (addresses 0200h through 0204h 0214h) seven information registers (addresses 0206h through 0212h).
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Insertion
When connector with proper sequencing used, Agere Systems Inc. GTL+ buffers withstand insertion into backplane without corrupting cell damaging device. ground pins connector should extend beyond other pins that ground connections made first. addition, power pins connector should extend beyond signal pins that power connections made before signal after ground connections. During insertion, cell corrupted because GTL+ outputs high-impedance state during powerup reset. Therefore, proper timing should external powerup reset circuit.
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Configuration
frequency device's main clock (mclk) derived from clock xtalin input (pclk) given following equation when engaged: fmclk fpclk MOD8 Note: When engaged, mclk output PLL. pll_m[4:0] pll_n[2:0] counter values mclk configuration register (address 2Bh) must that voltage-controlled oscillator (VCO) operates appropriate range. maximum value fmclk MHz. valid range between inclusive, valid range between inclusive. When multiple sets values achieve desired result, choose lowest value corresponding value Note: output must always least MHz. loop filter must properly correct operation PLL. proper setting loop filter bits, lf[3:0], mclk configuration register (address 2Ah) determined chosen value following table lists lf[3:0] settings given values Typical lock-in time Table Loop Filter Register Settings 16-21 10-15 Mclk Configuration (2Ah) lf[3:0] "0111" "0110" "0101" "0100" "0011" "0010"
Configuration Example: Given pclk frequency desired mclk frequency MHz, proper values lf[3:0] following: lf[3:0] "0010" bypass (bypb) enable (pllen) bits used select source mclk T8208. select output clock, both bits must programmed `1,' select pclk clock, both bits must programmed `0.'
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Microprocessor Interface
Microprocessor Interface Configuration
microprocessor interface configured either Intel Motorola mode mot_sel input. mot_sel high select Motorola mode select Intel mode. addition, address data buses configured multiplexed nonmultiplexed mode using input. select multiplexed mode, high, select nonmultiplexed mode, low. multiplexed mode, d[7:0] used both address data bus, a[0] input becomes address latch enable (ale) signal. nonmultiplexed mode, separate address, a[7:0], data, d[7:0], buses used. both modes, active-low sel* input selects device microprocessor read write accesses. data leads 3-stated when sel*, wr*_ds*, rd*_wr* signal high. Motorola mode, rd*_rw* read/write enable signal, which indicates current access read when high write when low. wr*_ds* signal data strobe Motorola mode. rdy_dtack* output active-low data transfer acknowledge signal. T8208 takes this signal when microprocessor access complete. rdy_dtack* output returns high when microprocessor acknowledges access taking sel* wr*_ds* signal high. rdy_dtack* output then goes high-impedance. Intel mode, rd*_rw* input active-low read enable signal, wr*_ds* active-low write enable signal. logic level rd*_rw* indicates T8208 that current access read, logic level wr*_ds* indicates access write. Finally, rdy_dtack* output active-high ready signal. T8208 asserts this signal high when microprocessor access complete. rdy_dtack* output then goes high-impedance when sel*, wr*_ds*, rd*_wr* signal goes high.
Microprocessor Interrupts
int_irq* output active-high interrupt Intel mode active-low interrupt request Motorola mode. Intel mode, int_irq* normally goes high when interrupt generated. Motorola mode, interrupt request signal normally high goes during interrupt. Interrupts generated when enabled interrupt status becomes set. interrupt status bits T8208 have corresponding interrupt enable bit. When enable cleared, corresponding interrupt status enabled will generate interrupt. Several registers containing interrupt status bits exist four separate extended memory register groups (main, UTOPIA, SDRAM, bypass SDRAM) T8208. interrupt service request register direct address indicates which register group generating interrupt. Only enabled interrupts will cause int_serv_mainreg, int_serv_sdramreg, int_serv_utopiareg bits become set. main register group, special case exists. ctrl_cell_sent ctrl_cell_av interrupts main interrupt status register) cause main group indication interrupt service request register. These interrupts have their dedicated service request bits optimize sending receiving control cells. ctrl_cell_sent ctrl_cell_av bits become whether corresponding interrupt enabled not.
Accessing CelXpres T8208 Microprocessor Interface
CelXpres T8208 distinct memory spaces: direct memory access registers extended memory registers. direct memory access registers directly addressed 8-bit (byte) registers mapped between addresses FFh. extended memory registers indirectly addressed mapped between addresses 0100h 3FFFFFEh. extended memory contains SDRAM memory, translation RAM, internal memories, device's configuration, status, control registers. Extended memory registers bits wide, accesses extended memory registers executed internally bits. Direct memory access registers located Section 14.2, Direct Memory Access Registers, extended memory registers located Section 14.3, Extended Memory Registers.
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6.3.1
Microprocessor Interface (continued)
Accessing Extended Memory Registers
Before accessing extended memory registers, powerup sequence, described Section Powerup/ Reset Sequence, must completed. Accesses extended memory word accesses internally; therefore, least significant address always `0'. Only most significant bits supplied extended memory address registers (addresses 30h-34h). following procedure outlines steps needed extended memory accesses T8208 device. 6.3.1.1 Extended Memory Writes
Write ext_a [25] extended memory address register (little endian endian) (optional). Write ext_a [24:17] byte extended memory address register (little endian endian) (optional). Write ext_a [16:9] byte extended memory address register (little endian endian) (optional). Write ext_a [8:6] bits extended memory address register (little endian endian) (optional). Write ext_d [15:8] byte extended memory data high register (little endian endian) (optional). Write ext_d [7:0] byte extended memory data register (little endian endian) (optional). Write ext_a [5:1] bits; write "01," "10," "11" ext_we[1:0]; write ext_strt_acc extended memory access register (little endian endian) (mandatory). Read extended memory access register (little endian endian) determine that ext_strt_acc been cleared hardware (mandatory). Extended Memory Reads
6.3.1.2
Write ext_a [25] extended memory address register (little endian endian) (optional). Write ext_a [24:17] byte extended memory address register (little endian endian) (optional). Write ext_a [16:9] byte extended memory address register (little endian endian) (optional). Write ext_a [8:6] bits extended memory address register (little endian endian) (optional). Write ext_a [5:1] bits; write "00" ext_we[1:0]; write ext_strt_acc extended memory access register (little endian endian) (mandatory). Read extended memory access register (little endian endian) determine that ext_strt_acc been cleared hardware (mandatory). Read ext_d [15:8] byte from extended memory data high register (little endian endian) (optional). Read ext_d [7:0] byte from extended memory data register (little endian endian) (optional). Once ext_strt_acc software, only extended memory access register should accessed until ext_strt_acc cleared hardware.
Note:
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6.3.2
Microprocessor Interface (continued)
CelXpres T8208 Access Performance
times represented following table reflect access times various microprocessor interface reads writes. direct access registers, values represent time until rdy_dtack signal transitions indicating data transfer portion access complete. accesses extended memory, values represent time from completion write register until ext_strt_acc cleared. actual times dependent frequency pclk mclk clocks (see Section Configuration). terms pclkp mclkp table represent period pclk mclk, respectively, Table Access Times Description Read/Write 28h-3Dh Reads 60h-93h, A0h-D7h, E0h-FFh (direct internal memory) Writes 60h-93h, A0h-D7h, E0h-FFh (direct internal memory) Reads Extended Memory Internal Structures Writes Extended Memory Internal Structures Read from SRAM Write SRAM pclkp pclkp mclkp pclkp pclkp mclkp pclkp pclkp mclkp Unit
pclkp
pclkp mclkp
pclkp mclkp
pclkp mclkp pclkp pclkp mclkp pclkp
pclkp mclkp pclkp mclkp
pclkp mclkp pclkp mclkp pclkp mclkp pclkp mclkp
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General-Purpose (GPIO)
T8208 eight programmable general-purpose pins called GPIO. These GPIO pins independently programmed, GPIO_oe[7:0] bits GPIO output enable register (address 39h), inputs outputs. GPIO_oe `1,' corresponding GPIO output, cleared `0,' corresponding GPIO input. Input values read from GPIO_in[7:0] bits GPIO input value register (address 3Dh), output values written GPIO_out[7:0] bits GPIO output value register (address 3Bh). GPIO[7:0] pins have internal pull-up resistors.
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Look-Up Table
Cells arriving from UTOPIA obtain information from external static look-up table (LUT), which divided among VPI, VCI, OAM/RM records. Each these records contains specific VPI/VCI translation cell routing information. size records programmable bytes extended bytes. 16-byte mode adds 32-bit counters each record. 16-byte mode discussed Section 8.4, Extended Records. value header, addition port number, incoming cell points record look-up table. This record examined first. record indicates routing, record, which record points, provides routing VPI/VCI translation information. routing indicated, information about type translation, only VPI/VCI, obtained from original record. only translation, routing information obtained from record, full partial translation performed. VPI/VCI translation, record points appropriate record, where VPI/VCI translation routing information stored. record indicates routing, record, which record points, provides routing VPI/VCI translation information. routing indicated, VPI/VCI translation cell routing performed using information record.
Look-Up Table
number memory devices two) used look-up table size external SRAM programmable. tram_qnty_sel main configuration register (address 0100h) specifies whether chips used. memory devices used, separate chip select signals generated. These chip selects created from decoded addresses. tram_size configuration bits, also main configuration register, used select memory sizes Kbytes, Kbytes, Kbytes, Kbytes. Therefore, maximum look-up table size Kbytes realized when chips Kbytes each used. single SRAM Kbytes used (instead SRAMs Kbytes each), then main configuration register must `1.' single SRAM Kbytes used, this must cleared `0.'
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Look-Up Table (continued)
Organization
Organization discussed terms 8-byte records. Differences organization 8-byte records 16-byte records will discussed Section 8.4, Extended Records. look-up table configured support ports when multi-PHY mode used, effectively creating separate look-up table each port. VPI, VCI, OAM/RM records either bytes bytes length. (See Section 8.4, Extended Records information 16-byte records.) Figure shows translation memory 8-byte records. OAM/RM translation records located bottom memory space with OAM/RM records used each port. device configured support ports, first 4096 records will used translation records. This translates Kbytes memory 8-byte records. remaining memory then used records. 8-byte records, base addresses records calculated from following equation: this equation, base address, port number, number bytes record, number records port. example, OAM/RM translation records port will have base address 1024 400h. Note: device configured less than ports, OAM/RM translation record memory space will allocated enough memory handle ports through maximum port number used. example, device configured ports (see Section UTOPIA Interface), OAM/RM translation record memory space will records (for ports through OAM/RM translation record memory space ports will skipped even though ports used. Note: device configured mode (see Section UTOPIA Interface), device supports only single translation memory will addressed port Separate record base addresses each port multi-PHY mode, number incoming bits used pointer into look-up table programmed. (See Section 14.3, Extended Memory Registers, Table 153, Port Configuration Structure (PPXCF) (4200h 42FEh).) 8-byte records, total memory used records calculated using following equation: this equation, memory size used records, number ports used, number bytes record, number incoming bits used address look-up table. This calculated memory space must reserved records.
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Look-Up Table (continued)
Routing Look-Up Memory 0000h 0200h 0400h 0600h 0800h 0A00h 0C00h 0E00h 1000h 1200h 1400h Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port +0000h
Cell Routing Port Record (F4)
+00F8h +0100h +0108h +0110h +0118h +0120h +0128h +0130h (F4) "110" (F4) (RM-VPC) "100" (F5) "101" (F5) "110" (F5) "111" (F5) Reserved Reserved
7A00h 7C00h 7E00h 8000h Cell Routing Port Cell Routing Port Cell Routing Port Purpose Look-Up Memory Shared Between Each Ports 7FFFFh
+01F8h Reserved
Figure Translation Memory Map-8-Byte Records four translation record types (VCI, OAM/RM, only, VPI/VCI) 8-byte records illustrated Figure There types translation records: translation only VPI/VCI translation. only translation record differs from other records that bits which used indicate full partial translation. (See Table Value Truth Table.) other record used when VPI/VCI translation occurs. offset bits value bits which used point record where translation routing information reside. maximum offset bits length; therefore, only bits through stored record. address appropriate translation record, from cell's header multiplied added bits through offset which obtained from record. This final offset into lookup table. This final offset should then added Translation Memory beginning address 100000h (Table 180) obtain final address. value indicates maximum number translation records table. Therefore, from cell's header greater than value, cell's range counted misrouted cell. Note that records from different ports reference same translation record. Other control bits these records described following Figure
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Look-Up Table (continued)
Only Translation Record VPI[11:0] Reserved Cell Routing Header[15:0] Tandem Routing Header[15:0] VPI/VCI Translation Record Reserved Bits Through Offset[15:0] Value[15:0] Reserved Translation Record VPI[11:0] VCI[15:0] Cell Routing Header[15:0] Tandem Routing Header[15:0] OAM/RM Translation Record VPI[11:0] VCI[15:0] Cell Routing Header[15:0] Tandem Routing Header[15:0]
Figure Translation Record Types-8-Byte Records
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Look-Up Table (continued)
routing control bits VPI, VCI, OAM/RM records described below: Active (A). This when considered active. truth table (Table below. This used types records. Ignore (I). When this one, ignored. truth table (Table below. This used types records. masking required (when `1'), then mask_ignore (bit register 0112h) used achieve this masking. When this T8208 ignores ignore that programmed look-up records that control translation incoming UTOPIA cells. This used redundancy desired. redundancy, software populate look-up tables T8208 devices (one active inactive redundancy). ignore needs both active inactive devices. active device mask_ignore inactive device mask_ignore This inactive device will count, route translate incoming cells (ignores them). When active device fails, mask_ignore becomes inactive device becomes active setting mask_ignore failed device will longer count, route, translate incoming cells, active device takes over cell routing VPI/VCI translation. Table Active Ignore Truth Table Action cell discarded, considered misrouted, counted received cell. cell discarded, flagged misrouted, counted received cell. cell valid counted received cell. cell discarded, flagged misrouted, counted received cell.
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Look-Up Table (continued)
Enable OAM/RM Routing (E). When this record less than routing translation information obtained from appropriate OAM/RM record. this record most significant cell header `1,' routing translation information obtained from appropriate OAM/RM record. This used only records. Translation (P). When this `1,' translation only. When this `0,' VPI/VCI translation performed. This used only records. Value High (SH). When this `1,' bits through incoming replaced with corresponding bits record. truth table (Table below. This used only translation records. Value (SL). When this `1,' bits through incoming replaced with corresponding bits record. truth table (Table below. This used only translation records.
Table Value Truth Table Action translation performed. translation performed only bits incoming VPI. translation performed only bits 8-11 incoming VPI. Complete translation performed.
Routing Control (C1, C0). These bits determine cell routed OAM/RM VPI/VCI translation performed. truth table (Table below. These bits used only OAM/RM records. Table Routing Control Truth Table Action Both incoming substituted with VPI1 VCI, respectively, OAM/RM record, cell routed according cell tandem routing headers OAM/RM record. cell routed OAM/RM. record OAM/RM cell translated routed according cell tandem routing headers original record. record OAM/ cell translated routed according cell tandem routing headers original record. incoming will preserved, cell routed according cell tandem routing headers OAM/RM record. Reserved.
most significant bits will only substituted global rplc_gfc direct configuration/control register (address 28h) mode port configured mode.
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Look-Up Table (continued)
Look-Up Procedure
Look-up procedure discussed terms 8-byte records. Differences look-up procedures 8-byte records 16-byte records will discussed Section 8.4, Extended Records. When cell received, lutX_vpi_mask bits port configuration structure (Table 153) indicate which incoming bits used address record look-up table. selected incoming bits multiplied eight (for 8-byte records) create offset into table. this offset base address, found port configuration structure, creates actual look-up table address record associated with cell. Note that only bits through base address stored port configuration structure. lutX_vpi_chk set, unused bits cell header must `0,' cell will considered range. port configured UNI, upper four bits (GFC field) will ignored verification. When cell range, discarded counted received cell. validity accessed record determined checking active ignore bits. cell valid, enable OAM/RM routing consulted determine type cell treatment should occur. (See definition these bits Section 8.2, Organization.) When incoming less than record associated with cell read. calculate translation record address OAM/RM cell, incoming multiplied eight (for 8-byte records), resulting product added port's base address. (See Section 8.2, Organization.) special case exists when incoming cell header "110." this case, translation record address port's base address 100h. Next, validity record determined checking bits. valid, cell routed described routing control (C1, bits. (See definition these bits Section 8.2, Organization.) record bits record zero one, respectively, cell does receive routing. cell routed OAM, virtual path routing bit) original checked determine cell receives only VPI/VCI routing. indicates only routing, cell's replaced indicated switch high (SH, bits only translation record. (See definition these bits Section 8.2, Organization.) cell routing header tandem routing header then added cell, cell transmitted cell bus. indicates VPI/VCI routing, translation record accessed using offset value bits VPI/VCI translation record. (The offset value bits described Section 8.2, Organization.) Again, validity translation record determined checking bits. Next, cell valid, record most significant value cell header examined determine type cell treatment should occur. value incoming cell's port number determines address OAM/RM record space. following table outlines look-up table offsets used 8-byte records. translation record address this offset port's base address. Table Translation Record Addresses Table-8-Byte Records "100" "101" "110" "111" Translation Offset Port's base address plus 108h Port's base address plus 110h Port's base address plus 118h Port's base address plus 120h
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Look-Up Table (continued)
Next, validity record determined checking bits. valid, cell routed described routing control (C1, bits. (See definition these bits Section 8.2, Organization.) record bits record zero one, respectively, cell does receive routing. cell routed cell, information translation record used route cell. cell's replaced with VCI, respectively, record. most significant bits will only substituted global rplc_gfc direct configuration/control register (address 28h) port configured mode. cell routing header tandem routing header then added cell, cell transmitted cell bus. Note: Unused cell routing records memory space used other purposes.
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Look-Up Table (continued)
This look-up procedure outlined flow diagram below.
CELL
READ FROM ACELL HEADER
READ FROM ACELL HEADER
UNUSED BITS LUTX_VPI_CHECK `0'? READ RECORD
CELL DISCARDED
RANGE? READ RECORD
CELL DISCARDED
CELL DISCARDED PTI[2] `1'? READ RECORD
CELL DISCARDED
READ RECORD
CELL DISCARDED "00" VPI/VCI TRANSLATION; ROUTING FROM RECORD VPI/VCI PRESERVED; ROUTING FROM RECORD "10" VPI/VCI TRANSLATION; ROUTING FROM RECORD
CELL DISCARDED
"00" "10"
VPI/VCI TRANSLATION; ROUTING FROM RECORD VPI/VCI PRESERVED; ROUTING FROM RECORD
TRANSLATION; ROUTING FROM RECORD
5-7781F 5-7782F
Figure Translation Flow Diagram
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Look-Up Table (continued)
Extended Records
length translation records extended bytes support cell counts each translation record. lut_rec_form bits extended configuration register (address 0138h) used select this extended mode. extended (16-byte) mode, 32-bit counters appended 8-byte records. first counter translation record, total cell count, keeps total count incoming cells received from UTOPIA whether ultimately routed discarded except those which range. definition bits Section 8.2, Organization. second counter, special cell count, subset total cell count counter. This counter counts only cells whose values cell header match values specified extended control register (address 0120h). example, this counter used track specific type OAM/RM cells cells indicating forward congestion (EFCI lower priority (CLP
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Look-Up Table (continued)
four translation record types extended mode illustrated Figure below.
Extended Only Translation Record VPI[11:0] Reserved Cell Routing Header[15:0] Tandem Routing Header[15:0] Total Cell Count[31:16] Total Cell Count[15:0] Special Cell Count[31:16] Special Cell Count[15:0]
Extended VPI/VCI Translation Record Reserved Bits Through Offset[15:0] Value[15:0] Reserved Reserved Reserved Reserved Reserved Extended Translation Record VPI[11:0] VCI[15:0] Cell Routing Header[15:0] Tandem Routing Header[15:0] Total Cell Count[31:16] Total Cell Count[15:0] Special Cell Count[31:16] Special Cell Count[15:0] Extended OAM/RM Translation Record VPI[11:0] VCI[15:0] Cell Routing Header[15:0] Tandem Routing Header[15:0] Total Cell Count[31:16] Total Cell Count[15:0] Special Cell Count[31:16] Special Cell Count[15:0]
Figure Translation Record Types-Extended Mode
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Look-Up Table (continued)
Because translation records larger extended mode, look-up table memory changes, translation record address calculations change, memory size calculations change. Figure shows translation memory 16-byte records when device configured ports.
0000h 0400h 0800h 0C00h 1000h 1400h 1800h 1C00h 2000h 2400h 2800h
Routing Look-Up Memory Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port Cell Routing Port
+0000h
Cell Routing Port Record (F4)
+01F0h +0200h +0210h +0220h +0230h +0240h +0250h +0260h (F4) "110" (F4) (RM-VPC) "100" (F5) "101" (F5) "110" (F5) "111" (F5) Reserved Reserved
F400h F800h FC00h 10000h Cell Routing Port Cell Routing Port Cell Routing Port Purpose Look-Up Memory Shared Between Each Ports 7FFFFh
+03F0h Reserved
Figure Translation Memory Map-Extended Mode
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Look-Up Table (continued)
OAM/RM translation records bottom memory Kbytes memory when device configured support MPHY ports, base addresses records calculated using following equation: this equation, base address, port number, number bytes record, number records port. calculate 16-byte translation record address type cell, incoming multiplied resulting product added port's base address. special case when incoming cell header "110", translation record address port's base address 200h. 16-byte type translation record offset determined from incoming cell's using following table. translation record address this offset port's base address. Table Translation Record Addresses Table-Extended Mode "100" "101" "110" "111" Translation Offset Port's base address plus 210h Port's base address plus 220h Port's base address plus 230h Port's base address plus 240h
extended mode, memory space used records also changes. total memory used records calculated using following equation: this equation, memory size used records, number ports used, number bytes record, number incoming bits used address look-up table. address 16-byte translation record, selected incoming bits (see Section 8.3, Look-Up Procedure) multiplied create offset into look-up table. this offset base address creates actual translation record address associated with incoming cell. Note that only bits through base address stored port configuration structure. address 16-byte translation record, from cell's header multiplied added bits through offset, which obtained from record. This final offset into look-up table. This final offset should then added translation memory beginning address 100000h (Table 180) obtain final address.
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Look-Up Table (continued)
Diagnostics
T8208 also includes diagnostics track misrouted cells. cell considered misrouted bits "00", range, lutX_vpi_chk unused bits incoming cell header zero (see Section 8.3, Look-Up Procedure). When misrouted cell detected, misrouted cell header high registers (addresses 0146h 0148h) updated. enabled, mis_cell interrupt, vci_or interrupt, vpi_or interrupt will generated appropriate (see Table Section 14.3, Extended Memory Registers). misrouted cell header high registers contain first four header bytes selected misrouted cells. Only misrouted cell from port whose mis_cell_lut_sel will update these registers, this misrouted cell will update registers only first received after mis_cell_clr set. lst_mis_cell_lut bits indicate port from which header bytes misrouted cell header high registers were received. mis_cell_lut_sel bits located misrouted registers (addresses 0142h, 0140h, 013Eh, 013Ch respectively). mis_cell_clr, mis_cell_latch, lst_mis_cell_lut bits located misrouted register (address 0144h). (See Tables Section 14.3, Extended Memory Registers, complete description above bits.)
Setup
When configuring lut_en bits configuration/status register (addresses 0320h through 039Eh), care must taken ensure that enabled ports' LUTs correspond ports chosen UTOPIA mode. (See Section 9.6, UTOPIA Modes.) enabled, corresponding bits port configuration structure (Section 14.3.2.4, UTOPIA Configuration Monitoring, Table 153) will ignored. Also, when device configured UTOPIA mode (see Section UTOPIA Interface), only port entries external look-up table used; therefore, look-up table should accordingly.
Bypass
This feature allows elimination SRAM (which information) implementations that provide cell routing header (CBRH) tandem routing header (TRH) T8208 device. This feature enabled when register 0100h `1'. When this bypass feature enabled, T8208 expecting 58-byte cells 16-bit UTOPIA mode 57-byte cells 8-bit UTOPIA mode UTOPIA. register 0100h cleared `0,' then T8208 device expects before CBRH incoming cells. But, register 0100h `1', T8208 device expects CBRH before incoming cells.
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UTOPIA Interface
CelXpres T8208 supports AForum's UTOPIA level level specifications cell-level handshake MPHY operation with rates Mbits/s. device configured Alayer layer programming phyen* main configuration register (address 0100h). device configured data operation setting utopia_16 (bit register 0112h. utopia-16 (bit register 0112h cleared `0,' then UTOPIA interfaces T8208 configured data operation. UTOPIA data mode, maximum MPHYs queues) supported. UTOPIA 8-bit data mode, maximum MPHYs (128 queues) supported. Alayer, device interface with single layer multiple layers 64). Also Alayer, configured shared UTOPIA mode (8-bit data mode) (16-bit data mode) MPHYs. (Note that shared UTOPIA mode used, slave_en main configuration/control register (address 0110h) must cleared device setup.) mode, T8208 functions single device UTOPIA devices UTOPIA level bus. addition required UTOPIA signals, T8208 supports additional three transmit three receive enable (u_txenb*[3:1] u_rxenb*[3:1]) signals, additional three transmit three receive cell available (u_txclav[3:1] u_rxclav[3:1]) signals, transmit parity (u_txprty) signal, receive parity (u_rxprty) signal. T8208 UTOPIA signal names begin with u_tx, UTOPIA transmit, u_rx, UTOPIA receive. References transmit receive made relative UTOPIA data flow Alayer UTOPIA interface. Therefore, signals starting with u_rx, such u_rxenb*[3:0] u_rxdata[15:0], receive UTOPIA signals devices Amode transmit UTOPIA signals devices mode. Furthermore, signals such u_txclav[3:0] u_txaddr[4:0] transmit UTOPIA signals devices Amode receive UTOPIA signals devices mode. above terminology will used throughout this UTOPIA Interface section.
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9.1.1
UTOPIA Interface (continued)
Incoming UTOPIA Cell Interface
Incoming Mode (Cells Received T8208)
mode, only enable (u_rxenb*[0]) signal cell available (u_rxclav[0]) signal used. u_rxenb*[0] signal input connected Alayer's TxEnb* signal, u_rxclav[0] signal output connected Alayer's TxClav signal. device, T8208 uses only configuration/status register (address 0320h) port configuration structure register (addresses 4200h-4202h). UTOPIA level functionality, address programmed addr_match bits UTOPIA configuration register (address 0114h), addr_clav_en bits main configuration register (address 0112h) programmed value mentioned register except "0000." specified UTOPIA level specification, during polling process, T8208 drives u_rxclav[0] signal during clock cycle following cycle which address appears u_rxaddr pins. u_rxclav[0] goes high impedance when selected support MPHY operation. UTOPIA level above level bits meaningful; therefore, addr_clav_en bits must programmed "0000," u_rxaddr pins must grounded, addr_match bits cleared. When T8208 device mode, (dont_inhibit_rxphy_clav) register 0112h cleared `0,' rx_clav signal deasserted UTOPIA FIFO considered full. this `1,' T8208 keeps rx_clav signal always asserted high indicating capability accept cells even UTOPIA FIFO could overrun, actually overrun. 9.1.2 Incoming AMode (Cells Received T8208)
Amode, T8208 connect devices that either meet level level UTOPIA specifications. connection devices that meet only UTOPIA level specifications, T8208 access four these devices using four enable (u_rxenb*[3:0]) cell available (u_rxclav[3:0]) signals. Connection more than device possible only PHY's data, start cell, parity outputs high impedance when device enabled. Polling cell available signals usually occurs while current cell received. T8208 connects devices meeting level UTOPIA specifications, 8-bit data mode, MPHY ports accessed. 8-bit UTOPIA mode, MPHYs supported with four RxCLAV/RxENB pairs with 16-port addressing RxCLAV/RxENB pair. ports, RxCLAV/RxENB pairs support groups ports total ports. 16-bit UTOPIA mode, T8208 supports PHYs with four RxCLAV/RxENB pairs with 8-port addressing RxCLAV/RxENB pair. AMPHY mode, u_rxdata[15:0], u_rxaddr[4:0], u_rxsoc, u_rxprty signals connected each port. addition, T8208 generates address (u_rxaddr[4:0]) signals, permitting selection arbitration among MPHY ports. number address lines used connection vary from four, giving maximum address value (All five address lines must connected provide NULL address.) Refer Section 9.6, UTOPIA Modes, more information about possible combinations address, cell available, enable signals. UTOPIA specification operation with TxClav RxClav used when T8208 connects multiple level devices. Whether T8208 connected several level level devices, round robin algorithm implemented that ensures that devices serviced (accessed) timely manner. addition, number clock cycles wasted arbitration minimized because polling performed during cell transfer. Amode, unused u_rxclav inputs require connection ground. Note: u_rxenb outputs high impedance during powerup reset. attached interpret this high-impedance state enable; however, T8208 ready properly handle input data during this time. Attach pull-up resistors these outputs problem anticipated. When T8208 Amode, (inhibit_rxuto_fifo_overrun) register 0112h `1,' T8208 prevents UTOPIA FIFO from overflowing deasserting rx_enb* signal even though rx_clav signal high when polled, UTOPIA FIFO considered full. this cleared `0,' rx_enb* signal deasserted even UTOPIA FIFO considered full. Agere Systems Inc.
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9.2.1
UTOPIA Interface (continued)
Outgoing UTOPIA Cell Interface
Outgoing Mode (Cells Sent T8208)
mode, only enable (u_txenb*[0]) signal cell available (u_txclav[0]) signal used. u_txenb*[0] signal input connected Alayer's RxEnb* signal, u_txclav[0] signal output connected Alayer's RxClav signal. device, T8208 queue group (queues SDRAM UTOPIA cell buffer. div_queue bits main configuration register (address 0112h) programmed "000" queues "111" queue, port_rte[127:0] bits FIFO routing registers (addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017Ah, 017Ch, 017Eh) must programmed zero. only queue used, configure only queue registers addresses 0440h 2000h through 2016h. Also, only queue used, program mphy_select bits priority_select bits routing information registers addresses 0200h, 0202h, 0204h, 0214h zero value "110000." queues used, configure only queue registers addresses 0440h through 0446h 2000h through 2076h. Also, queues used, only mphy_select bits routing information registers (addresses 0200h, 0202h, 0214h) must programmed zero value "110000." UTOPIA level functionality, address programmed addr_match bits UTOPIA configuration register (address 0114h), addr_clav_en bits main configuration register (address 0112h) programmed value mentioned register except "0000." specified UTOPIA level specification, T8208 drives u_txclav[0] signal during clock cycle following with address u_txaddr pins. u_txclav[0] goes high impedance when selected support MPHY operation. When tx_utopia_hi_z main configuration register (address 0100h) cleared, u_txsoc, u_txdata[7:0], u_txprty outputs high impedance when selected, allowing multiple PHYs connected same UTOPIA bus. UTOPIA level above level bits meaningful; therefore, addr_clav_en bits must programmed "0000," u_txaddr pins must grounded, addr_match bits cleared. Note: SDRAM bypassed, UTOPIA cell buffer T8208 device divided into minimum queue maximum queues. Note: Even though outgoing (egress) queues 0-3, egress port determined address match bits register 0114h.
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9.2.2
UTOPIA Interface (continued)
Outgoing AMode (Cells Sent T8208)
Amode, T8208 connect devices that either meet level level UTOPIA specifications. connection devices that meet only UTOPIA level specifications, T8208 access four these devices using four enable (u_txenb*[3:0]) cell available (u_txclav[3:0]) signals. Polling cell available signals occurs while current cell transmitted. T8208 connects devices meeting level UTOPIA specifications, 8-bit data mode, MPHY ports accessed. 8-bit UTOPIA mode, MPHYs supported with four TxCLAV/TxENB pairs with 16-port addressing TxCLAV/TxENB pair. ports, TxCLAV/TxENB pairs support groups ports total ports. 16-bit UTOPIA mode, T8208 supports PHYs with four TxCLAV/TxENB pairs with 8-port addressing TxCLAV/TxENB pair. AMPHY mode, u_txdata[15:0], u_txaddr[4:0], u_txsoc, u_txprty signals connected each port. addition, T8208 generates address (u_txaddr[4:0]) signals, permitting selection arbitration among MPHY ports. number address lines used connection vary from four, giving maximum address value (All five address lines must connected provide NULL address.) Refer Section 9.6, UTOPIA Modes, more information about possible combinations address, cell available, enable signals. UTOPIA specification operation with TxClav RxClav used when T8208 connects multiple UTOPIA devices. Amode, unused u_txclav inputs require connection ground. Note: u_txenb outputs high impedance during powerup reset. attached interpret this high-impedance state enable; however, T8208 ready send data during this time. Attach pull-up resistors these outputs problem anticipated. UTOPIA cell buffer holds next cells transmitted onto UTOPIA bus. This UTOPIA cell buffer, which holds cells, divided into queues using div_queue bits main configuration register (address 0112h). number ports that T8208 supports determines number queues that should chosen. (See Section 9.6, UTOPIA Modes.) number cells queue, held buffer, determined dividing (maximum number cells that UTOPIA cell buffer holds) number queues selected (e.g., cells queue queues cells queue four queues).
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UTOPIA Interface (continued)
Each port assigned four queues UTOPIA cell buffer except case ports (for 8-bit UTOPIA) ports (for 16-bit UTOPIA). case ports (for 8-bit UTOPIA) ports (for 16-bit UTOPIA), each port assigned queues programmable number queues PHY. Each group four queues priority encoded where lowest-numbered queue highest priority. Groups four queues shared among ports follows: Queues shared between ports Queues shared between ports Queues 8-11 shared between ports Queues 12-15 shared between ports Queues 16-19 shared between ports Queues 20-23 shared between ports Queues 24-27 shared between ports Queues 28-31 shared between ports Queues 32-35 shared between ports Queues 36-39 shared between ports Queues 40-43 shared between ports Queues 44-47 shared between ports Queues 48-51 shared between ports Queues 52-55 shared between ports Queues 56-59 shared between ports Queues 60-63 shared between ports Queues 64-67 shared between ports Queues 68-71 shared between ports Queues 72-75 shared between ports Queues 76-79 shared between ports Queues 80-83 shared between ports Queues 84-87 shared between ports Queues 88-91 shared between ports Queues 92-95 shared between ports Queues 96-99 shared between ports Queues 100-103 shared between ports Queues 104-107 shared between ports Queues 108-111 shared between ports Queues 112-115 shared between ports Queues 116-119 shared between ports Queues 120-123 shared between ports Queues 124-127 shared between ports
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UTOPIA Interface (continued)
less ports 8-bit UTOPIA less ports 16-bit UTOPIA used, then each port uses four queues with priorities from where highest priority. lowest-numbered queue group four assigned priority highest-numbered queue group assigned priority ports 8-bit UTOPIA ports 16-bit UTOPIA, four queues each group assigned either even odd-numbered port. example, which will called normal 64-port mode, assigns queues with priorities even-numbered ports queues with priorities odd-numbered ports. configuration queues ports supported port-rte[127:112] [15:0] bits FIFO routing register structures. Please addresses 0170h through 017Eh (Tables through 120). Figure illustrates selection ports when used.
PRIORITY
QUEUE QUEUE QUEUE QUEUE CELL CELL FIFO QUEUE QUEUE QUEUE QUEUE
UTOPIA PORT
DEMULTIPLEXER CONTROLLED PORT_RTE[127:112], PORT_RTE[15:0] FIFO ROUTING REGISTERS STARTING ADDRESS 0170h
5-7784.c
Figure Queue Priority Multiplexing UTOPIA cell buffer kept full cells transferred from SDRAM. Each port equal priority transmitting onto UTOPIA bus. cell transmitted port determined priority queues with cells waiting transmitted. addition, number clock cycles wasted arbitration minimized because polling performed during cell transfer. Cells arriving from cell have their header error check (HEC) bytes removed. Therefore, T8208 calculates inserts into each cell before transmitting onto UTOPIA bus. Figure
Counters
each port selected MPHY mode, 16-bit registers (in_cnt_phyX[31:16] in_cnt_phyX[15:0] Table 152) used 32-bit free-running incoming cell counter. Each port's counter counts valid misrouted incoming cells. Incoming cells counted they encounter ignore their translation records that their and/or range. counter port found addresses 4000h 4002h. Table Section 14.3.2.3, UTOPIA Count Monitoring, addresses other ports' incoming cell counters. Also, each port selected MPHY mode, 16-bit registers (out_cnt_phyX[31:16] out_cnt_phyX[15:0] Table 151) used 32-bit free-running outgoing cell counter. Each port's counter counts outgoing cells UTOPIA bus. counter port found addresses 0600h 0602h. Table Section 14.3.2.2, UTOPIA Monitoring, addresses other ports' outgoing cell counters.
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9.3.1
UTOPIA Interface (continued)
Dropped Cell Counters
There 24-bit counter each queue T8208 device that counts dropped cells. counter queue found addresses 3000h 3002h. drop_cell_cnt [15:0] address 3002h) drop_cell_cnt [23:16] address 3000h) count number dropped cells queue drop_cell_cnt_ovfl (bit register 3000h), when `1,' indicates that drop cell counter overflowed since last read microprocessor clear_on_read enabled. drop_cell_cnt_clp0 (bit register 3000h), when `1,' indicates that cells have been discarded since last read microprocessor clear_on_read enabled. drop cell counters remaining queues 127) addresses 3004h 31FEh.
55-Byte UTOPIA Mode
this special UTOPIA mode, T8208 transmits 55-byte cell, opposed bytes, UTOPIA bus. extra bytes tandem routing header received with cell from cell bus. These bytes appended beginning cell with tandem routing header [15:8] byte first, followed tandem routing header [7:0] byte. Clearing sp_utopia_sel* main configuration register (address 0100h) enables this mode. start cell signal (u_txsoc) asserted only once with first tandem routing header byte. T8208 configured 55-byte UTOPIA mode whether device 8-bit 16-bit UTOPIA mode (bit register 112h).
QUEUE UTOPIA CELL BUFFER CELLS) EXTERNAL SDRAM QUEUE UTOPIA CELL BUFFER CELLS) EFCI INSERTION QUEUE UTOPIA CELL BUFFER CELLS) FECN QUEUE UTOPIA CELL BUFFER CELLS)
MODIFIED FROM 5-7783aF
SDRAM CONTROLLER
INSERTION
53-byte CELL UTOPIA
QUEUE FILL MANAGER
Figure UTOPIA Cell Handling
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UTOPIA Interface (continued)
Shared UTOPIA Mode
shared UTOPIA mode allows T8208 devices different cell buses share same UTOPIA bus. Shared UTOPIA mode functionality requires T8208 devices configured Amode. This configuration supported both UTOPIA level configurations. shared mode used provide system backplane redundancy increase cell system capacity. T8208 device configured master other slave, using slave_en main configuration/control register (address 110h). master slave communicate each other through shared UTOPIA pins; u_shr_grant[1:0] u_shr_req[3:0]. master, u_shr_grant[1:0] functions grant outputs cell specific queue sent, u_shr_req[3:0] pins function request inputs identify which cell queues sent. slave, u_shr_grant[1:0] functions grant input, u_shr_req[3:0] request output. configuration addr_clav_en bits must same both devices MCF2 (0112h) port_rte (0170h 017Eh) registers. Note: T8208 will support shared UTOPIA mode queues MPHYs) 8-bit UTOPIA mode will support only queues MPHYs) 16-bit UTOPIA mode. UTOPIA cell buffers master slave divided into same number queues different number queues. register settings mast_queue_in[127:112], mast_queue_in[111:96], mast_queue_in[95:80], mast_queue_in[79:64] mast_queue_in[63:48], mast_queue_in[47:32], mast_queue_in[31:16], mast_queue_in[15:0] slav_queue_in[127:112], slav_queue_in[111:96], slav_queue_in[95:80], slav_queue_in[79:64] slav_queue_in[63:48], slav_queue_in[47:32], slav_queue_in[31:16], slav_queue_in[15:0] must configured master device. These bits indicate which queues master which queues slave enabled. master's priority algorithm uses mast_queue_in information determine which waiting cell should transmitted. slav_queue_in (0160h 016Eh) registers ignored slave. transmit operation shared UTOPIA mode illustrated Figure 8-bit UTOPIA mode Figure 16-bit UTOPIA mode. transmit interface, enable, start cell, data signals occur relative lowgoing start grant signal from master. start grant signal occurs every clock cycles 8-bit UTOPIA mode clock cycles 16-bit UTOPIA mode always preceded least clock cycles ones. Both devices transmit UTOPIA bus; master arbitrates grants slave access u_shr_grant pins. When slave cells waiting transmission, makes request each queue 8-bit UTOPIA mode 16-bit UTOPIA mode) that contains cells. make this request, slave pulls u_shr_req pins clock cycle during queue's request period. request clock period each queue assigned relative master's start grant signal. request period first group queues occurs clock cycles after falling edge start grant. 8-bit UTOPIA mode, next clock cycles evaluate queues corresponding queue queues represents queue containing cell sent. 16-bit UTOPIA mode, next clock cycles evaluate queues corresponding queue queues represents queue containing cell sent. master uses received queue requests priority algorithm determine slave's cell should transmitted before own. Both master slave have equal chance transmit cells cells have equal priority. first grant[0] low-going grant signal. next clock cycles designate queue number cell transmitted which only requires bits represent queues 8-bit UTOPIA mode bits represent queues 16-bit UTOPIA mode. additional bits clock cycles reserved. slave then cycles (8-bit UTOPIA mode) cycles (16-bit UTOPIA mode) 55/28 cycles transmit cell depending mode.
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UTOPIA Interface (continued)
UTOPIA receive mode, master controls UTOPIA bus, slave only monitors bus. Both master slave receive cells their individual look-up tables determine which cells destined their cell bus. master controls enable (u_rxenb[3:0]) address (u_rxaddr[4:0]) signals UTOPIA bus. slave monitors these signals determine when cell starts which port sending cell. shared UTOPIA mode, master always drives u_rxaddr[4:0], u_txaddr[4:0], u_txsoc, u_rxenb*[3:0], u_txenb*[3:0] signals. These signals become high impedance slave when slave_en main configuration/control register (address 0110h) set. Both master slave drive u_txprty u_txdata[7:0] signals when they transmit cell; therefore, these signals must high impedance when active. Clear tx_utopia_hi_z main configuration register (address 0100h) force u_txprty u_txdata[7:0] signals high-impedance state when inactive.
U_TXCLK
U_TXENB*
U_TXSOC
U_TXDATA[7:0]
U_TXPRTY
GRANT[0]
QS[6] QS[4] QS[2] QS[0]
R[0]
GRANT[1]
QS[5] QS[3] QS[1] VALID
REQUEST[0]
INVALID
INVALID
REQUEST[1]
INVALID
INVALID
REQUEST[2]
INVALID
QR10
INVALID
REQUEST[3]
INVALID
QR11
INVALID
5-7786bF
Figure UTOPIA Sharing 8-Bit UTOPIA Mode
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UTOPIA Interface (continued)
U_TXCLK
U_TXENB*
U_TXSOC
U_TXDATA[15:0]
P40/41 P42/43 P44/45 P46/47
H0/1
H2/3
HEC/00
P46/47 P44/45
U_TXPRTY
GRANT[0]
QS[4] QS[2] QS[0]
R[0]
GRANT[1]
QS[5] QS[3] QS[1] VALID
REQUEST[0]
INVALID
INVALID
REQUEST[1]
INVALID
INVALID
REQUEST[2]
INVALID
QR10
INVALID
REQUEST[3]
INVALID
QR11
INVALID
5-7786cF
Figure UTOPIA Sharing 16-Bit UTOPIA Mode
9.6.1
UTOPIA Modes
UTOPIA Modes 8-Bit UTOPIA Operation
multi-PHY mode, T8208 interfaces with ports 8-bit UTOPIA operation. Each port numbered accessed using certain combination cell available/enable (Clav/Enb*) address (Addr) signals. addr_clav_en bits main configuration register (address 0112h) used select this combination cell available/enable address signals. Table indicates port numbering each possible configurations 8-bit UTOPIA operation. first selection zero address four cell available/enable signals value "0000" bits register 0112h) used connection UTOPIA level devices. this selection connect from four devices T8208 Amode. only connected, four cell available signals connected PHY. devices, connect two, (internal port number must matched Clav being used). unused u_rxclav inputs require connection ground. Four queues allocated this configuration. second selection address four cell available/enable signals value "0010" bits register 0112h) used connection UTOPIA level devices. selection used four groups ports each. (See Appendix AForum Technical Committee UTOPIA Level Version specification.) unused u_rxclav inputs require connection ground. Four queues allocated this configuration. Agere Systems Inc.
CelXpres T8208 AInterconnect
UTOPIA Interface (continued)
third selection address four cell available/enable signals value "0101" bits register 0112h) used connection four UTOPIA level groups four ports each. Four queues allocated this configuration. fourth selection four address cell available/enable signals value "0011" bits register 0112h) used connection UTOPIA level groups sixteen ports each. unused u_rxclav inputs require connection ground. Four queues allocated this configuration. fifth selection three address four cell available/enable signals value "1011" bits register 0112h) used connection four UTOPIA level groups eight ports each. Four queues allocated this configuration. sixth selection four address four cell available/enable signals value "1000" bits register 0112h) used connection four UTOPIA level groups sixteen ports each. queues allocated normal 64-port mode described Section 11.4 Queuing used programmable number queues allocated based settings registers 0170h-017Eh. Table Configuration 8-Bit UTOPIA addr clav/enb* Ports Port enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr Port Port enb*[1], clav[1], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr Port Port Port Port Port enb*[2], enb*[3], clav[2], clav[3], addr addr enb*[1], enb*[1], clav[1], clav[1], addr addr enb*[0], enb*[0], clav[0], clav[0], addr addr enb*[0], enb*[0], enb*[0], enb*[0], enb*[0], clav[0], clav[0], clav[0], clav[0], clav[0], addr addr addr addr addr enb*[0], enb*[0], clav[0], clav[0], addr addr enb*[0], enb*[0], enb*[0], enb*[0], enb*[0], clav[0], clav[0], clav[0], clav[0], clav[0], addr addr addr addr addr Ports 8-15 Port Port Port Port Port Port enb*[2], enb*[3], enb*[3], clav[2], clav[3], clav[3], addr addr addr enb*[1], enb*[1], enb*[1], clav[1], clav[1], clav[1], addr addr addr enb*[0], enb*[0], enb*[0], enb*[0], enb*[0], enb*[0], clav[0], clav[0], clav[0], clav[0], clav[0], clav[0], addr addr addr addr addr addr enb*[0], enb*[0], enb*[0], clav[0], clav[0], clav[0], addr addr addr enb*[0], enb*[0], enb*[0], enb*[0], enb*[0], enb*[0], clav[0], clav[0], clav[0], clav[0], clav[0], clav[0], addr addr addr addr addr addr
enb*[0], clav[0], addr
enb*[0], clav[0], addr Port
addr
clav/enb*
enb*[0], clav[0], addr
enb*[0], clav[0], addr
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CelXpres T8208 AInterconnect
UTOPIA Interface (continued)
Table Configuration 8-Bit UTOPIA (continued) addr clav/enb* Ports 16-23 Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port enb*[3], clav[3], addr enb*[1], clav[1], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port Port Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port Port Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port Port
enb*[1], clav[1], addr
enb*[1], clav[1], addr
enb*[1], clav[1], addr
enb*[1], clav[1], addr
enb*[1], clav[1], addr Port
enb*[1], clav[1], addr Port
enb*[1], clav[1], addr Port
enb*[1], clav[1], addr Port
addr
clav/enb*
Ports 24-31 enb*[3], enb*[3], enb*[3], clav[3], clav[3], clav[3], addr addr addr enb*[1], enb*[1], enb*[1], enb*[1], enb*[1], enb*[1], clav[1], clav[1], clav[1], clav[1], clav[1], clav[1], addr addr addr addr addr addr enb*[1], enb*[1], enb*[1], clav[1], clav[1], clav[1], addr addr addr enb*[1], enb*[1], enb*[1], enb*[1], enb*[1], enb*[1], clav[1], clav[1], clav[1], clav[1], clav[1], clav[1], addr addr addr addr addr addr Ports 32-39 Port Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port
enb*[1], clav[1], addr
enb*[1], clav[1], addr
addr
clav/enb*
enb*[2], clav[2], addr
enb*[2], clav[2], addr
enb*[2], clav[2], addr
enb*[2], clav[2], addr
Agere Systems Inc.
CelXpres T8208 AInterconnect
UTOPIA Interface (continued)
Table Configuration 8-Bit UTOPIA (continued) addr clav/enb* Ports 40-47 Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port Port Port Port Port Port Port enb*[2], enb*[2], enb*[2], clav[2], clav[2], clav[2], addr addr addr enb*[2], enb*[2], enb*[2], enb*[2], enb*[2], enb*[2], clav[2], clav[2], clav[2], clav[2], clav[2], clav[2], addr addr addr addr addr addr Ports 48-55 Port Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port Port Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port Port Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port Port
enb*[2], clav[2], addr
addr
clav/enb*
enb*[3], clav[3], addr Port
enb*[3], clav[3], addr Port
enb*[3], clav[3], addr Port
enb*[3], clav[3], addr Port
addr
clav/enb*
Ports 56-63 enb*[3], enb*[3], enb*[3], clav[3], clav[3], clav[3], addr addr addr enb*[3], enb*[3], enb*[3], enb*[3], enb*[3], enb*[3], clav[3], clav[3], clav[3], clav[3], clav[3], clav[3], addr addr addr addr addr addr
enb*[3], clav[3], addr
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CelXpres T8208 AInterconnect
9.6.2
UTOPIA Interface (continued)
UTOPIA Modes 16-Bit UTOPIA Operation
multi-PHY mode, T8208 interfaces with ports 16-bit UTOPIA operation. Each port numbered accessed using certain combination cell available/enable (Clav/Enb*) address (Addr) signals. addr_clav_en bits main configuration register (address 0112h) used select this combination cell available/enable address signals. Table indicates port numbering each possible configurations 16-bit UTOPIA operation. first selection zero address four cell available/enable signals value "0000" bits register 0112h) used connection UTOPIA level devices. this selection connect from four devices T8208 Amode. only connected, four cell available signals connected PHY. devices, connect two. unused u_rxclav inputs require connection ground. Four queues allocated this configuration. second selection address four cell available/enable signals value "0010" bits register 0112h) used connection UTOPIA level devices. selection used four groups ports each. (See Appendix AForum Technical Committee UTOPIA Level Version specification.) unused u_rxclav inputs require connection ground. Four queues allocated this configuration. third selection address four cell available/enable signals value "0101" bits register 0112h) used connection four UTOPIA level groups four ports each. Four queues allocated this configuration. fourth selection three address four cell available/enable signals value "1001" bits register 0112h) used connection four UTOPIA level groups eight ports each. queues allocated normal 64-port mode described Section 11.4 Queuing used programmable number queues allocated based settings registers 0170h-017Eh.
Agere Systems Inc.
CelXpres T8208 AInterconnect
UTOPIA Interface (continued)
Table Configuration 16-Bit UTOPIA addr addr clav/enb* clav/enb* Ports Port enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port enb*[0], clav[0], addr Port enb*[1], clav[1], addr Port enb*[2], clav[2], addr Port enb*[3], clav[3], addr Port enb*[1], clav[1], addr enb*[0], clav[0], addr enb*[0], clav[0], addr enb*[0], clav[0], addr Port enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port Port Port enb*[0], clav[0], addr Port enb*[1], clav[1], addr Port enb*[2], clav[2], addr Port enb*[3], clav[3], addr Port enb*[3], clav[3], addr enb*[1], clav[1], addr enb*[0], clav[0], addr enb*[0], clav[0], addr Port enb*[3], clav[3], addr enb*[1], clav[1], addr enb*[1], clav[1], addr Port enb*[2], clav[2], addr enb*[2], clav[2], addr Port enb*[3], clav[3], addr enb*[3], clav[3], addr Port enb*[0], clav[0], addr Port enb*[1], clav[1], addr Port enb*[2], clav[2], addr Port enb*[3], clav[3], addr enb*[2], clav[2], addr enb*[1], clav[1], addr enb*[0], clav[0], addr enb*[0], enb*[0], clav[0], clav[0], addr addr Ports 8-15 Port Port enb*[3], clav[3], addr enb*[1], clav[1], addr enb*[1], enb*[1], clav[1], clav[1], addr addr Ports 16-23 Port Port enb*[2], clav[2], addr enb*[2], enb*[2], clav[2], clav[2], addr addr Ports 24-31 Port Port enb*[3], clav[3], addr enb*[3], enb*[3], clav[3], clav[3], addr addr
addr addr
clav/enb* clav/enb*
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CelXpres T8208 AInterconnect
UTOPIA Interface (continued)
UTOPIA Clocking
UTOPIA signals T8208 clocked rising edge UTOPIA clock, UTOPIA signals clocked rising edge UTOPIA clock. UTOPIA specifications state that Alayer supplies transmit receive UTOPIA interface clocks layers. T8208 configured drive these clocks driven them. T8208, clocks transmit receive UTOPIA interfaces independently derived from several sources. addition, each these clocks independently configured. UTOPIA clock configuration (address 010Ch) UTOPIA clock configuration (address 010Eh) registers used select configure transmit UTOPIA interface receive UTOPIA interface clocks, respectively. these register descriptions more information.
Option Counters Clear Read
counters (addresses 0600h-06FEh, 3000h-31FEh, 4000h-40FEh, total special cell counters look-up record extended records mode selected) cleared automatically when read microprocessor, clear_on_read (bit register 0112h) `1.' Both registers every (and every queue dropped cell count) must read consecutively, (bits 31:16 first, bits 15:0 next) that both registers cleared automatically. this (bit register 0112h) cleared then microprocessor will have clear counters individually writing them after reading, needed.
Agere Systems Inc.
CelXpres T8208 AInterconnect
Cell Interface
10.1 General Architecture
high bandwidth, 32-bit cell used interconnect T8208 devices. devices connected bus, cell exchange occur between these devices. Each cell frame clock cycles, during these cycles, cell transmitted. T8208 designed operate with maximum cell frequency MHz, which translates cell bandwidth Gbits/s. maximum achievable frequency given implementation dependent loading other design considerations. addition bits data, cell uses four additional control signals. four signals include read clock, write clock, frame synchronization signal, acknowledge signal. read write clocks (cb_rc* cb_wc* pins, respectively) establish timing reading writing cells generated internally from T8208 device from external clock source. internal clock source offers capability program required timing skew between write read clocks. Separate pins provided read write clock signals. read clock used read cell from cell bus, write clock used write cell cell bus. Because devices cell read write same clock edge, write clock delayed slightly, relative read clock, ensure sufficient data hold time. active-low frame sync (cb_fs*) generated arbiter indicates first cycle cell frame 16-user mode first cycle cell frames 32-user mode. This signal generated every clock cycles 16-user mode every clock cycles 32-user mode. acknowledge (cb_ack*) signal used acknowledge successful receipt cell. This signal asserted during next request cycle T8208 that receives cell. This signal asserted multicast broadcast cells. event overflow control cell FIFO, loopback FIFO, FIFO, cell input FIFO, acknowledge signal will assert low. case overflow, this signal will assert multicast broadcast cells. When cb_disable* asserted, device receive data cb_d*[31:0] cannot transmit data. device cannot assert cb_ack* even when valid cell received from cell bus, cb_disable* asserted. Several T8208 devices reside cell bus, device must configured arbiter clearing cb_arb_sel cell configuration/status register (address 0130h) pulling arb_en* lead low. cell arbiter receives requests access from resident devices during first cycle cell frame grants these requests during last cycle cell frame. Before issuing grant while cell transmitted cell bus, arbiter executes arbitration algorithm determine next device transmit bus. arbiter also generates frame synchronization signal. Software will designate only device cell arbiter, given time, ensure proper operation bus. 5-bit unit address assigned each device bus. Each device uses this address request cell transmission identify incoming cells destined them. Each device given unique unit address individually tying each address (ua*[4:0]) input high low. unit address inputs active-low; therefore, device with ua*[4:0] inputs tied "10000" address Each device also given unique unit address writing address into bits register 0130h, provided register 0130h also device makes cell transmission request driving assigned bits during request cycle, which first cycle frame. example, device uses bits request cycle request bits. (See Section 10.2, Cell Frames.) Also, each device uses unit address determine received cell destined (See Section 10.3, Cell Routing Headers.)
Agere Systems Inc.
CelXpres T8208 AInterconnect
Cell Interface (continued)
cell configured 16-user 32-user mode, using cb_usr_mode cell configuration/status register (address 0130h). 16-user mode, devices assert their transmission requests during first cycle each frame, transmission grant next frame given during last cycle frame. 32-user mode, frame synchronization signal asserted every cell frames. frames termed even frames. frame synchronization signal marks beginning even frame, frame starts clock cycles later. During request cycle even frame, devices zero through assert their transmission requests, during request cycle frame, devices through assert theirs. Requests received from even frames serviced group, grants given order that requests received with highest priority serviced first with same priority requests serviced using round robin algorithm. Transmission grants next frame always given current frame. Cells transmitted onto cell come from three sources internal T8208. Data cells from UTOPIA placed FIFO await transmission onto cell bus. Control cells from microprocessor wait control cell FIFO, loopback cells from cell wait loopback FIFO. Cells from these three FIFOs priority multiplexed onto cell output FIFO transmitted onto cell bus. Optional high priority established data cells control cells sent cell bus. register 0130h cleared then cells from FIFO have highest priority, cells from control cell FIFO have next highest, finally, cells from loopback FIFO have lowest. register 0130h `1,' then cells from control cell FIFO have highest priority, cells from FIFO have next highest priority, finally, cells from loopback FIFO have lowest priority. This default `0.' Incoming cells broadcast, multicast, single address types. T8208 receiving device accepts single address cells with address field cell routing header that matches device's unit address. addition, device accepts broadcast cells certain multicast cells that configured accept. (See Section 10.3.4, Multicast Routing.) Before cell accepted, check done previous grant verify whether valid grant not. receiving device verifies cell routing header cyclic redundancy check (CRC-4) value least significant bits cell routing header. also verifies interleave parity (BIP-8) value from bits last cell frame cycle. either corrupt, cell discarded. kept, cells routed loopback FIFO, control FIFO, FIFO, based information cell routing header. Section 10.3, Cell Routing Headers.
Agere Systems Inc.
CelXpres T8208 AInterconnect
Cell Interface (continued)
10.2 Cell Frames
cell frame always clock cycles. cell frame three sections (request, cell, grant). During request section, which first clock cycle frame, devices assert their transmission requests onto bus. During cell section, which next clock cycles, cell transmitted cell bus. This cell includes cell routing header, tandem routing header, 52-byte body cell. During grant section, which last clock cycle frame, grant asserted, indicating which device transmit cell during next frame. Also, during this last clock cycle, parity vector placed transmitting device that error detection performed cell. Figure illustrates format cell frame.
CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE
CELL ROUTING HEADER GFC/ VPI[11:8] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE INTERLEAVE PARITY VPI[7:0] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE
TANDEM ROUTING HEADER VCI[15:0] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE GRANT NUMBER
Figure Cell Frame Format (Bit Positions 16-User Mode)
Agere Systems Inc.
CelXpres T8208 AInterconnect
Cell Interface (continued)
CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE
CELL ROUTING HEADER GFC/ VPI[11:8] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE INTERLEAVE PARITY VPI[7:0] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE
TANDEM ROUTING HEADER VCI[15:0] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE GRANT NUMBER
CELL ROUTING HEADER GFC/ VPI[11:8] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE INTERLEAVE PARITY VPI[7:0] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE
TANDEM ROUTING HEADER VCI[15:0] PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE PAYLOAD BYTE GRANT NUMBER
Figure Cell Frame Format (Bit Positions 32-User Mode)
Agere Systems Inc.
CelXpres T8208 AInterconnect
Cell Interface (continued)
Devices cell make their requests during first cycle each frame. 16-user mode, each device asserts request every frame. 32-user mode, each device asserts request every frames. 32-user mode, devices with unit addresses through assert their requests during even frames, devices with unit addresses through assert their requests during frames. During cycle their assigned frame, each device drives data bits available. position request bits each device based device's unit address. assigned positions each device illustrated Figure Figure 16-user 32-user modes, respectively. example, figures, device with unit address makes requests using bits labeled bits, instead one, used each device priority request included. priori
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