UPB1009K µPB1009K silicon monolithic developed receivers. This in

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NEC's POWER RECEIVER BIPOLAR ANALOG INTEGRATED CIRCUIT
UPB1009K
µPB1009K silicon monolithic developed receivers. This integrates full VCO, second filter, 4-bit ADC, digital control interface reduce cost mounting space. addition, power consumption low. Moreover, TCXO with frequency 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, switchable with on-chip divider possible. NEC's stringent quality assurance test procedures ensure highest reliability performance.
FEATURES
Double conversion Multiple system clocks converter High-density block Supply voltage current consumption High-density surface mountable fREFin 16.368 MHz, f1stIFin 61.380 MHz, f2ndIFin 4.092 fREFin 14.4, 16.384, 19.2, MHz, f1stIFin 62.980 MHz, f2ndIFin 2.556 On-chip switchable frequency divider (1/N 100, 3/256, 9/1024, 65/4096) On-chip 4-bit converter On-chip tank circuit 2ndIF filter 26.0 TYP. 44-pin plastic
APPLICATIONS
Consumer receiver reference frequency 16.368 MHz, frequency 4.092 Consumer receiver reference frequency 14.4, 16.384, 19.2, MHz, 2ndIF frequency 2.556
UPB1009K
ORDERING
Part Number
INFORMATION
Package 44-pin plastic Supplying Form wide embossed taping indicates pull-out direction tape kpcs/reel, pack specification
µPB1009K-E1-A
Remark order evaluation samples, contact your nearby sales office. Part number sample order: µPB1009K
UPB1009K
PRODUCT
Type
LINE-UP +25°C,
Functions (Frequency unit: MHz) Pre-amplifier RF/IF downconverter synthesizer 16.368 1stIF 61.380/2ndIF 4.092 14.4, 16.384, 19.2, 1stIF 62.980/2ndIF 2.556 On-chip 4-bit Pre-amplifier RF/IF down-converter synthesizer 27.456 1stIF 175.164/2ndIF 0.132 On-chip 2-bit Pre-amplifier RF/IF downconverter synthesizer 16.368 1stIF 61.380/2ndIF 4.092 16.368 1stIF 61.380/2ndIF 4.092 (mA) 26.0 (dB) Package Status
Part Number
Clock Frequency Specific chip
µPB1009K
44-pin plastic
Device
µPB1008K
18.0
36-pin plastic
µPB1007K
25.0
36-pin plastic
Available
µPB1005K
36-pin plastic
Remark Typical performance. Please refer ELECTRICAL CHARACTERISTICS detail.
SYSTEM
APPLICATION
EXAMPLE
receiver block diagram figure Power Save Mode control pins. figure TXCO (GPS, W-CDMA, PDC, GSM) control pins.
Caution This diagram schematically shows only PB1009K's internal functions system. This diagram does present actual application circuits.
UPB1009K
CONNECTION INTERNAL BLOCK DIAGRAM
UPB1009K
EXPLANATION
Name Function Application Internal Equivalent Circuit
PreAMPout Rext
Output preamplifier. Connect resistor reference constantcurrent power supply this pin. Ground this Ground regulator. Power supply voltage preamplifier. Connect bypass capacitor this reduce high-frequency impedance. Ground preamplifier. Input preamplifier.
RegGND PreAmpVCC
PreAmpGND PreAmpin
1stMIXin 1stMIXGND 1stMIXVCC
1stMIX input pin. Ground first MIX. Power supply voltage mixer. Connect bypass capacitor this reduce high-frequency impedance. Output mixer. Insert IFSAW filter between this oscillation signal monitored this pin.
1stIFout
UPB1009K
Name
Function Application
Internal Equivalent Circuit
High
TCXO 16.368, 16.384
TCXO 19.2 TCXO 14.4 TCXO
CPout
Output charge pump. Connect external this dumping factor natural angular frequency (Isink Isource 0.45 mA).
Refin
Reference frequency input pin. Connect external reference transmitter (such TCXO) this pin.
PLLVCC
Power supply voltage PLL. Connect bypass capacitor this reduce high-frequency impedance.
PLLGND
Ground PLL.
CLKout
Clock (fTCXO) output test pin).
UPB1009K
Name
Function Application
Internal Equivalent Circuit
LoVCC
Power supply voltage VCO. Connect bypass capacitor this reduce high-frequency impedance.
VCO1 VCO2
test pin. Leave this open when µPB1009K mounted board.
LoGND
Ground VCO.
IFGND
Ground block.
2ndIFout
Output amplifier.
1stIFin
Input second mixer.
IFVCC
Power supply voltage block.
UPB1009K
Name
Function Application
Internal Equivalent Circuit
2ndIFin
Input buffer amplifier.
DCOFFout
Output trimming amplifier.
DCOFFin
trimming pulse input pin. Connect this capacitor convert input pulse signal into
GNDana GNDbuf
Ground amplifier power supply.
VDDana
Power supply amplifier comparator.
VDDbuf
Power supply output driver amplifier ADC. Connect this ground converter bypass capacitor reduce high-frequency impedance.
GNDsub
Ground CMOS substrate.
SCKin
Digital signal output pins.
Sampling clock signal input pin.
AGCin
control pulse signal input pin.
AGCout
control signal output pin.
UPB1009K
Name Function Application Internal Equivalent Circuit
VDDlogi
Power supply voltage power control logic. Ground power control logic. High Sleep mode (all circuits off). Warm-up mode (PLL on). Calibration mode Active mode (all circuits on).
GNDlogi
UPB1009K
ABSOLUTE MAXIMUM RATINGS
Symbol ICCTotal Tstg +25°C +25°C +25°C Note Test Conditions Ratings +125 Unit
Parameter Supply Voltage Total Circuit Current Power Dissipation Operating Ambient Temperature Storage Temperature
Mounted double-sided copper-clad epoxy glass
RECOMMENDED
Parameter Supply Voltage
OPERATING
Symbol fRFin f1stLOin f1stIFin f2ndLOin f2ndIFin fREFin fREFout VIL1
RANGE
MIN. TYP. 575.42 636.8/1 638.4 61.38/62.98 65.472/65.536 4.092/2.556 TCXO MAX. Unit
Operating Ambient Temperature Input Frequency Oscillating Frequency Input Frequency Input Frequency Input Frequency Reference Input/Output Frequency
Clock mode control voltage (Low Level) Clock mode control voltage (High Level) Power-down control voltage (Low Level) Power-down control voltage (High Level)
VIH1
VIL2
VIH2
UPB1009K
POWER-DOWN CONTROL MODE
µPB1009K consists block, block, block. controlling reduction power each block applying voltage pins), following four modes used.
Mode Mode Name Test Conditions Active mode Calibration mode Warm-up mode Sleep mode Block Block ADC) Block
Caution only active mode sleep mode, select desired mode with PD2.
REFERENCE
CLOCK
CONTROL
MODE
divided frequency selected follows that shared with TCXO each system.
TCXO Frequency Test Conditions 16.368 (GPS) 16.384 (GPS) 19.2 (W-CDMA) 14.4 (PDC) (GSM) 1/100 16.368 16.384 19.2 14.4 Phase Comparison Frequency
3/256 9/1024 65/4096
Caution When reference clock frequency 16.368 MHz, 1stIF frequency 2ndIF frequency 61.38 4.092 MHz, respectively. 2.556 other cases. They respectively 62.98
UPB1009K
ELECTRICAL
Parameter Rest current overall each mode Sleep mode Note Warm-up mode Calibration mode Active mode Rest current block each clock mode Current when 1/100 divider used Current when 256/3 divider used Current when 1024/9 divider used Current when 4096/65 divider used Maximum mode control current application application application application application application application application <Pre-amplifier> Circuit Current Power Gain Noise Figure Saturated Output Power Input Compression Level Input Order Intercept Point Input Inpedance fRFin 575.42 ICC1 GLNA NFLNA Signals, 1-pin current PRFin fRFin 12.5 -4.0 15.0 -2.7 -21.8 -9.5 11.2 j21.5 16.4 j136.6 17.5
CHARACTERISTICS +25°C,
Symbol Test Conditions MIN. TYP. MAX. Unit
Rest status without input signal, including sampling clock. 10.5 18.0 22.1 13.0 22.0 26.0 15.5 25.3 30.0
Current block. Overall current calibration mode active mode increases from that basic mode (MS1 10.2 10.4 11.3 12.1 12.3 12.6 13.5 13.9
PO(SAT)LNA PRFin PLNA-1 IIP3LNA ZinLNA fRFin 575.42 fRFin 575.42 MHz, 576.42 Calculated from S-parameter where input capacitance output load capacitance
Output Inpedance
ZoutLNA
Most current flows into ladder resistor (VDDana GNDana) sleep mode, sleep mode current between other (VDD) maximum.
UPB1009K
ELECTRICAL
Parameter mixer> Circuit Current Conversion Gain Noise Figure
CHARACTERISTICS +25°C,
Symbol Test Conditions MIN. TYP. MAX. Unit
575.42 MHz, f1stLOin 636.80 MHz, f1stIF 61.38 ICC2 CGRF Signals, current PRFMIXin SSBNF 10*log (2*DSBNF (Linear value) PRFMIXin PRFMIX-1 IIP3RFMIX fRFMIXin 575.42 fRFMIXin 575.42 MHz, 576.42 f1stLO 636.8 Leakage 636.8 frequency when oscillates correctly. Calculated from S-parameter where input capacitance output capacitance 14.0 16.1 12.8 19.0 16.0
Maximum Output Input Compression Level Input Order Intercept Point
-4.0 -29.0 -19.0
-0.8 -25.5 -17.2
Leakage Leakage Input Inpedance
LOIF LORF ZinMIX
-34.5 -54.7 50.1 j22.3 57.3 j2.6
Output Inpedance
ZoutMIX
mixer, LPF, IFamp> Circuit Current Conversion Gain
f1stFin 61.38 MHz, f2ndLOin 65.472 MHz, ICC3 Signals, current 66.0 45.0 19.5 20.0 70.3 51.2 26.4 25.0 75.0 58.0 33.5
(GV) VAGC VAGC VAGC
Band Gain Fluctuation Band Attenuation
Range NFIF PIF-1
3.092 5.092 Gain difference 4.092 9.092 MHz, VAGC VAGC VAGC maximum gain) dBm, VAGC f1stIFin 61.38 VAGC VAGC VAGC
Conversion Gain Range Noise Figure Maximum 2ndIF Output Input Compression Level
32.5 -70.5 -53.5 -37.0 -56.0 -38.0 -27.0
43.9 13.7 -64.4 -44.9 -30.6 -51.3 -30.7 -21.4 69.3 j4.8 j3.8
17.5
Input Order Intercept Point
IIP3IF
f1stIFin1 61.28 f1stIFin2 61.38
VAGC VAGC
f2ndLO 65.472 VAGC Input Inpedance ZinIF Calculated from S-parameter where input capacitance output capacitance
Output Inpedance
ZoutIF
UPB1009K
ELECTRICAL
Parameter <PLL Synthesizer> Circuit Current Charge Pump Output Current ICC4 Icpsink cpsource Loop Filer Output (High Level) Loop Filer Output (Low Level) Reference Input Level Modulation Sensitivity Control Voltage <A/D Converter> Circuit Current Resolution Sampling Clock Input Band Width Integral Non-linear Error Signal-to-noise Ratio Signal-to-noise Distortion Ratio Number Total Harmonic Distortion Ratio ICC5 ResAD ADBW SINAD ENOB characteristics 5.17 MHz, 20.48 5.17 MHz, 20.48 ENOB (SINAD-1.763)/6.02 5.17 MHz, 20.48 Second-degree fifth-degree distortion components 22.0 20.0 25.3 25.1 bits bits VREFin Center frequency When Locked PLL, current, VCC/2 -0.55 0.35 VCC-0.3 70.0 -0.45 0.45 81.0 10.6 -0.35 0.55 dBc/Hz
CHARACTERISTICS +25°C,
Symbol Test Conditions MIN. TYP. MAX. Unit
Remarks Timing characteristics during normal operation buffer amplifier internally inserted before core µPB1009K. bias this buffer amplifier controlled signal input from trim pin, used eliminate offset ADC. Because ladder resistor directly connected between VDDana GNDana, changes VDDana affect resolution ADC.
UPB1009K
illustrated operation timing chart below, data SampleN pipeline delayed clocks during normal operation, output rising edge sample clock with output delay time Tod. When operation changed from normal operation power-down operation, status output data immediately before power-down operation retained (drive status).
following table shows each timing parameter reference purposes.
Symbol Tpld Parameter Output Delay Pipeline Delay Sampling Delay (Aperture Delay) Output Hold Time Test Conditions fclk 19.2 MIN. TYP. MAX. Unit clock
UPB1009K
Remarks Power-down timing characteristics output code µPB1009K undefined clocks after power-down signal cleared when returns from power-down status normal operation.
output data undefined from start power-down operation 7.5th clock from falling edge clock which power-down operation cleared.
UPB1009K
TYPICAL CHARACTERISTICS +25°C, unless otherwise specified)
TOTAL CHARACTERISTICS
Remark graphs indicate nominal characteristics.
UPB1009K
PRE-AMPLIFIER BLOCK CHARACTERISTICS
Remark graphs indicate nominal characteristics.
UPB1009K
BLOCK CHARACTERISTICS
Remark graphs indicate nominal characteristics.
UPB1009K
BLOCK CHARACTERISTICS
Remark graphs indicate nominal characteristics.
UPB1009K
MODULATION SENSITIVITY CHARACTERISTICS
CHARACTERISTICS
Remark graphs indicate nominal characteristics.
UPB1009K
SINAD MHz) CHARACTERISTICS CONVERTOR (IFin 5.17 MHz, SCLKin 20.48
Remark graphs indicate nominal characteristics.
UPB1009K
MEASUREMENT CIRCUIT
UPB1009K
PINS
TEST
CIRCUIT
Sampling Signal Input Input Function Offset Input Digital Signal Output Name DCOFFin SCKin AGCin
Function Preamplifier Input Preamplifier Output Mixer Input Prescaler Input Power Control
Name PreAmpin PreAmpout 1stMIXin Presin VCOc
Measurement (Charge Pump CPout Output) Reference Clock Input Clock Output 2ndIF Output 2ndIF Input Offset Output REFin CLKout 2ndIFout 2ndIFin DCOFFout
Control Voltage Output Output (Default onboard GND) Output (Default board VCC) 1stIF Input 1stIF Output
AGCout 1stIFin 1stIFout
UPB1009K
APPLICATION CIRCUIT
Power-down mode Sleep mode (full off) Warm-up mode (PLL Calibration mode (PLL Active mode (full
TCXO 16.368/16.384 19.2 14.4 26.0
256/3 1024/9 4096/65
UPB1009K
PACKAGE 44-PIN DIMENSIONS (UNIT:
PLASTIC
Caution island pins located corners needed fabricate products plant, serve other function. Consequently island pins should soldered should remain non-connection pins.
UPB1009K
NOTES CORRECT
Observe precautions handling because electro-static sensitive devices. Form ground pattern widely possible minimize ground impedance prevent abnormal oscillation). Keep wiring length ground pins short possible. Connect bypass capacitor pin. High-frequency signal pins must coupled with external circuit using coupling capacitor.
RECOMMENDED
SOLDERING
CONDITIONS
This product should soldered mounted under following recommended conditions. soldering methods conditions other than those recommended below, contact your nearby sales office.
Soldering Method Infrared Reflow Soldering Conditions Peak temperature (package surface temperature) Time peak temperature Time temperature 220°C higher Preheating time 180°C Maximum number reflow processes Maximum chlorine content rosin flux mass) Peak temperature (package surface temperature) Time temperature 200°C higher Preheating time 150°C Maximum number reflow processes Maximum chlorine content rosin flux mass) Peak temperature (molten solder temperature) Time peak temperature Preheating temperature (package surface temperature) Maximum number flow processes Maximum chlorine content rosin flux mass) Peak temperature (pin temperature) Soldering time (per side device) Maximum chlorine content rosin flux mass) 260°C below seconds less seconds less 120±30 seconds times 0.2%(Wt.) below 215°C below seconds seconds times 0.2%(Wt.) below 260°C below seconds less 120°C below time 0.2%(Wt.) below 350°C below seconds less 0.2%(Wt.) below Condition Symbol IR260
VP215
Wave Soldering
WS260
Partial Heating
HS350
Caution different soldering methods together (except partial heating).
4590 Patrick Henry Drive Santa Clara, 95054-1817 Telephone: (408) 919-2500 Facsimile: (408) 988-0279
Subject: Compliance with Directives certifies, knowledge, that semiconductor laser products detailed below compliant with requirements European Union (EU) Directive 2002/95/EC Restriction Hazardous Substances electrical electronic equipment (RoHS) requirements Directive 2003/11/EC Restriction Penta Octa BDE. Pb-free products have same base part number with suffix added. suffix indicates that device Pb-free. suffix used designate devices containing which exempted from requirement RoHS directive (*). cases devices have Pb-free terminals. devices with these suffixes meet requirements RoHS directive. This status based CEL's understanding Directives knowledge materials that into products date disclosure this information.
Restricted Substance RoHS Lead (Pb) Mercury Cadmium Hexavalent Chromium PBDE Concentration Limit RoHS (values fixed) 1000 1000 1000 1000 1000 Concentration contained devices Detected Detected Detected Detected Detected Detected
should have additional questions regarding devices compliance environmental standards, please hesitate contact your local representative.
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UPB1009K µPB1009K silicon monolithic developed receivers. This in

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