0.3A, 60V, Ohm, Rated, Current Limited, Voltage Clamped, Logic Level N
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
0.3A, 60V, Ohm, Rated, Current Limited, Voltage Clamped, Logic Level N-Channel Power MOSFETs
These intelligent monolithic power circuits which incorporate lateral bipolar transistor, resistors, zener diodes power transistor. current limiting these devices allow used safely circuits where shorted load condition encountered. drain source voltage clamping offers precision control circuit voltage when switching inductive loads. "Logic Level" gate allows this device fully biased with only from gate source, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. These devices incorporate protection designed withstand (Human Body Model) ESD. Formerly developmental type TA49028.
Features
0.30A, rDS(ON) Built Current Limit ILIMIT 0.140 0.210A 150oC Built Voltage Clamp Temperature Compensating PSPICE® Model Protected Controlled Switching Limits Related Literature TB334 "Guidelines Soldering Surface Mount Components Boards"
Symbol
Ordering Information
PART NUMBER RLD03N06CLE RLD03N06CLESM RLP03N06CLE PACKAGE TO-251AA TO-252AA TO-220AB BRAND 03N06C 03N06C 03N06CLE
NOTE: When ordering, entire part number. suffix obtain TO-252AA variant tape reel, i.e. RLD03N06CLESM9A.
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Absolute Maximum Ratings
25oC, Unless Otherwise Specified RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE +5.5 Self Limited UNITS W/oC
Drain Source Voltage (Note VDSS Drain Gate Voltage. VDGR Gate Source Voltage (Reverse Voltage Gate Bias Allowed) Continuous Drain Current Power Dissipation Derate Above 25oC Electrostatic Discharge Rating MIL-STD-883, Category B(2) .ESD Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief .Tpkg
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: 25oC 150oC.
Electrical Specifications
PARAMETER
25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) IDS(LIMIT) td(ON) td(OFF) tOFF CISS COSS CRSS TO-220 Package TO-251 TO-252 Packages 25V, 1MHz TEST CONDITIONS 250µA, VDS, 250µA 45V, 0.100A, 15V, 25oC 150oC 25oC 150oC 25oC 150oC 25oC 150oC 12.0 12.5 UNITS
oC/W oC/W oC/W
Drain Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate Source Leakage Current
Drain Source Resistance (Note
Limiting Current
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction Case Thermal Resistance Junction Ambient
30V, 0.10A, 300,
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage Diode Reverse Recovery Time NOTES: Pulsed: pulse duration 300µs maximum, duty cycle Repititive rating: pulse width limited maximum junction temperature. SYMBOL TEST CONDITIONS 0.1A 0.1A, dISD/dt 100A/µs UNITS
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
POWER DISSIPATION MULTIPLIER CASE TEMPERATURE (oC) DRAIN CURRENT
Unless Otherwise Specified
25oC, RATED OPERATION THIS AREA LIMITED JUNCTION TEMPERATURE
25oC 175oC
OPERATION THIS AREA LIMITED rDS(ON)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE FORWARD BIAS SAFE OPERATING AREA
NORMALIZED THERMAL IMPEDANCE 0.05 0.02 0.01 SINGLE PULSE
0.01 10-5
NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 10-1 RECTANGULAR PULSE DURATION
10-4
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
I(CLAMP) CLAMPED DRAIN CURRENT
DRAIN CURRENT
25oC TEMPERATURES LISTED STARTING JUNCTION TEMPERATURES
0.40
7.5V
0.30 0.20
25oC 50oC 75oC 100oC 150oC 0.001 0.01 TIME CLAMP 125oC
0.10 PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC DRAIN SOURCE VOLTAGE
FIGURE SELF-CLAMPED INDUCTIVE SWITCHING
FIGURE SATURATION CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
ID(ON) STATE DRAIN CURRENT 0.60 0.50 NORMALIZED DRAIN SOURCE RESISTANCE PULSE TEST PULSE DURATION 80µs DUTY CYCLE 0.5% -55oC
Unless Otherwise Specified (Continued)
PULSE DURATION 80µs DUTY CYCLE 0.5% 0.10A
0.40 0.30 0.20
25oC
175oC 0.10 GATE SOURCE VOLTAGE
JUNCTION TEMPERATURE (oC)
FIGURE TRANSFER CHARACTERISTICS
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
VDS, 250µA NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE
10mA
NORMALIZED GATE THRESHOLD VOLTAGE
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE TEMPERATURE
NORMALIZED DRAIN LIMITING CURRENT
1MHz CISS CRSS COSS
PULSE DURATION 80µs DUTY CYCLE 0.5% MAX.
CAPACITANCE (pF)
CISS COSS
CRSS DRAIN SOURCE VOLTAGE
JUNCTION TEMPERATURE (oC)
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN LIMITING CURRENT JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
DRAIN SOURCE VOLTAGE
Unless Otherwise Specified (Continued)
5.00 GATE SOURCE VOLTAGE
BVDSS 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS IG(REF) 0.1mA
3.75
2.50
1.25
TIME (µs)
0.00
NOTE: Refer Fairchild Application Notes AN7254 AN7260. FIGURE NORMALIZED SWITCHING WAVEFORMS CONSTANT GATE CURRENT.
Test Circuits Waveforms
td(ON) tOFF td(OFF)
PULSE WIDTH
FIGURE RESISTIVE SWITCHING TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
Detailed Description
Temperature Dependence Current Limiting Switching Speed Performance
RLD03N06CLE, CLESM RLP03N06CLE monolithic power devices which incorporate Logic Level power MOSFET transistor with current sensing scheme control circuitry enable device self limit drain source current flow. current sensing scheme supplies current resistor that connected across base emitter bipolar transistor control section. collector this bipolar transistor connected gate power MOSFET transistor. When ratiometric current from current sensing reaches value required forward bias base emitter junction this bipolar transistor, bipolar "turns on". resistor incorporated series with gate power MOSFET transistor allowing bipolar transistor adjust drive gate power MOSFET transistor voltage which then maintains constant current power MOSFET transistor. Since both ratiometric current sensing scheme base emitter unction
©2002 Fairchild Semiconductor Corporation
voltage bipolar transistor vary with temperature, current which device limits function temperature. This dependence shown Figure resistor series with gate power MOSFET transistor also results much slower switching performance than standard power MOSFET transistors. This advantage where fast switching cause RFI. switching speed very predictable.
Operation
limit drain source voltage operation current limiting steady state (DC) basis shown equation below. dissipation device simply applied drain source voltage multiplied limiting current. This device, like most power MOSFET devices today, limited 175oC. maximum voltage allowable can, therefore, expressed shown Equation
150°C AMBIENT (EQ.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
results this equation plotted Figure various heatsinks. These values plotted Figures through various heatsink thermal resistances.
Duty Cycle Operation
many applications either drain source voltage gate drive available 100% time. copper header which RLD03N06CLE, CLESM RLP03N06CLE mounted very large thermal storage capability, pulse widths less then 1ms, temperature header considered constant, thereby junction temperature calculated simply shown Equation
AMBIENT (EQ.
Limited Time Operations
Protection limited period time sufficient many applications. stated above heat storage silicon chip usually ignored computations over thereby thermal equivalent circuit reduces simple enough circuit allow easy computation limiting conditions. variation limiting current with temperature complicates calculation junction temperature, simple straight line approximation variation accurate enough allow meaningful computations. curves shown Figures through (RLP03N06CLE) Figure through (RLD03N06CLE RLD03N06CLESM) give accurate indication long specified voltage applied device current limiting mode without exceeding maximum specified 175oC junction temperature. practice this tells long have alleviate condition causing current limiting occur.
Generally heat storage capability silicon chip power transistor ignored duty cycle calculations. Making this assumption, limiting junction temperature 175oC using calculated Equation expression maximum under duty cycle operation shown Equation
(EQ.
Typical Performance Curves
DRAIN SOURCE VOLTAGE APPLIED VOLTAGE HSTR 5oC/W HSTR 10oC/W HSTR 0oC/W HSTR 1oC/W HSTR 2oC/W 175oC ILIM 0.210A 5.0oC/W 175oC ILIM 0.210A 5.0oC/W DUTY CYCLE PULSE WIDTH 100ms AMBIENT TEMPERATURE (oC)
HSTR 25oC/W
HSTR 80oC/W
AMBIENT TEMPERATURE (oC)
NOTE: Heat Sink Thermal Resistance HSTR. FIGURE OPERATION CURRENT LIMITING
DRAIN SOURCE VOLTAGE
FIGURE MAXIMUM AMBIENT TEMPERATURE CURRENT LIMITING. (HEATSINK THERMAL RESISTANCE 1oC/W)
DRAIN SOURCE VOLTAGE 175oC ILIM 0.210A 5.0oC/W DUTY CYCLE PULSE WIDTH 100ms AMBIENT TEMPERATURE (oC)
175oC ILIM 0.210A 5.0oC/W DUTY CYCLE PULSE WIDTH 100ms
AMBIENT TEMPERATURE (oC)
FIGURE MAXIMUM AMBIENT TEMPERATURE CURRENT LIMITING. (HSTR 2oC/W)
FIGURE MAXIMUM AMBIENT TEMPERATURE CURRENT LIMITING. (HSTR 5oC/W)
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
DRAIN SOURCE VOLTAGE AMBIENT TEMPERATURE (oC) 175oC ILIM 0.210A 5.0oC/W DUTY CYCLE DRAIN SOURCE VOLTAGE
(Continued)
175oC ILIM 0.210A 5.0oC/W DUTY CYCLE
PULSE WIDTH 100ms
PULSE WIDTH 100ms
AMBIENT TEMPERATURE (oC)
FIGURE MAXIMUM AMBIENT TEMPERATURE CURRENT LIMITING. (HSTR 10oC/W)
175oC ILIM 0.210A 5.0oC/W
FIGURE MAXIMUM AMBIENT TEMPERATURE CURRENT LIMITING. (HSTR 25oC/W)
STARTING 75oC STARTING 100oC STARTING 125oC STARTING 150oC
DRAIN SOURCE VOLTAGE
TIME 175oC
AMBIENT TEMPERATURE (oC)
NOTE:
Duty Cycyle Pulse Width 100ms.
DRAIN SOURCE VOLTAGE
FIGURE MAXIMUM AMBIENT TEMPERATURE CURRENT LIMITING. (HSTR 80oC/W)
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 25oC/W) (HEATSINK THERMAL CAPACITANCE 0.5J/oC)
STARTING 75oC STARTING 100oC STARTING 125oC STARTING 150oC
TIME 175oC
TIME 175oC STARTING 75oC STARTING 100oC STARTING 125oC STARTING 150oC
DRAIN SOURCE VOLTAGE
DRAIN SOURCE VOLTAGE
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 10oC/W) (HEATSINK THERMAL CAPACITANCE 1.0J/oC)
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 5oC/W) (HEATSINK THERMAL CAPACITANCE 2.0J/oC)
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves
(Continued)
STARTING 75oC
TIME 175oC STARTING 100oC TIME 175oC
STARTING 75oC STARTING 100oC STARTING 125oC STARTING 150oC
STARTING 125oC
STARTING 150oC DRAIN SOURCE VOLTAGE
DRAIN SOURCE VOLTAGE
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 2oC/W) (HEATSINK THERMAL CAPACITANCE 4J/oC)
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 25oC/W) (HEATSINK THERMAL CAPACITANCE 0.5J/oC)
TIME 175oC
TIME 175oC
STARTING 75oC STARTING 100oC STARTING 125oC STARTING 150oC
STARTING 75oC STARTING 100oC STARTING 125oC STARTING 150oC
DRAIN SOURCE VOLTAGE
DRAIN SOURCE VOLTAGE
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 10oC/W) (HEATSINK THERMAL CAPACITANCE 1.0J/oC)
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 5oC/W) (HEATSINK THERMAL CAPACITANCE 2.0J/oC)
STARTING 75oC
TIME 175oC
STARTING 100oC STARTING 125oC STARTING 150oC
DRAIN SOURCE VOLTAGE
FIGURE TIME 175oC CURRENT LIMITING (HEATSINK THERMAL RESISTANCE 2oC/W) (HEATSINK THERMAL CAPACITANCE 4J/oC)
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE PSPICE Electrical Model
SUBCKT RLD03N06CLE 0.547e-9 0.547e-9 0.301e-9 DBODY DBDMOD DBREAK DBKMOD DESD1 DESD1MOD DESD2 DESD2MOD DPLCAP DPLCAPMOD EBREAK 66.5 EVTO LDRAIN 1e-9 LGATE 2.96e-9 LSOURCE 2.96e-9 MOS1 MOSMOD 0.99 MOS2 MOSMOD 0.01 QCONTROL QMOD RBREAK RBKMOD RDRAIN RDSMOD 1.123 RGATE 3200 RSOURCE1 RDSMOD 1.12 RSOURCE2 RSMOD 2.16 RVTO RVTOMOD S1AMOD S1BMOD S2AMOD S2BMOD VBAT 0.22 .MODEL DBDMOD 7.97e-17 1.82 TRS1 3.91e-3 TRS2 1.24e-5 3.00e-10 1.83e-7) .MODEL DBKMOD 3150 TRS1 TRS2 .MODEL DESD1MOD 13.54 TBV1 TBV2 45.5 TRS1 TRS2 .MODEL DESD2MOD 11.46 TBV1 -7.576e-4 TBV2 -3.0e-6 TRS1 TRS2 .MODEL DPLCAPMOD (CJO 74.2e-12 1e-30 .MODEL MOSMOD NMOS (VTO 1.67 3.40 1e-30 .MODEL QMOD .MODEL RBKMOD (TC1 4e-4 1.13e-8) .MODEL RDSMOD (TC1 6.80e-3 6.5e-6) .MODEL RSMOD (TC1 2.95e-3 -1e-6) .MODEL RVTOMOD (TC1 -2.22e-3 -1.95e-6) .MODEL S1AMOD VSWITCH (RON 1e-5 ROFF VOFF .MODEL S1BMOD VSWITCH (RON 1e-5 ROFF VOFF .MODEL S2AMOD VSWITCH (RON 1e-5 ROFF -2.85 VOFF 2.15) .MODEL S2BMOD VSWITCH (RON 1e-5 ROFF 2.15 VOFF -2.85) .ENDS NOTE: further discussion PSPICE model consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991.
4/18/94
DRAIN LDRAIN
DBREAK
DPLCAP
EBREAK
EVTO
RDRAIN
DBODY
GATE LGATE DESD1 DESD2
RGATE
MOS1
MOS2
RSOURCE1 RSOURCE2
LSOURCE SOURCE
RBREAK RVTO VBAT
©2002 Fairchild Semiconductor Corporation
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Rev.
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FAST
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First Production
Identification Needed
Full Production
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Production
This datasheet contains specifications product that been discontinued Fairchild semiconductor. datasheet printed reference information only.
Rev.
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