LM555JAN Timer LM555 highly stable device generating accurate tim

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LM555JAN Timer LM555 highly stable device generating accurate tim

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LM555JAN Timer
LM555JAN Timer
LM555 highly stable device generating accurate time delays oscillation. Additional terminals provided triggering resetting desired. time delay mode operation, time precisely controlled external resistor capacitor. astable operation oscillator, free running frequency duty cycle accurately controlled with external resistors capacitor. circuit triggered reset falling waveforms, output circuit source sink 200mA drive circuits. Adjustable duty cycle Output source sink Output supply compatible Temperature stability better than 0.005% Normally normally output
Applications
Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Linear ramp generator
Features
Direct replacement SE555/NE555 Timing from microseconds through hours Operates both astable monostable modes
Ordering Information
Part Number JL555SPA JL555SGA Part Number JM38510/10901SPA JM38510/10901SGA Package Number J08A H08A Package Description Ceramic Metal
Connection Diagrams
Dual-In-Line Package Metal Package
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2005 National Semiconductor Corporation
DS201537
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LM555JAN
Schematic Diagram
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LM555JAN
Absolute Maximum Ratings (Note
Supply Voltage Discharge Current Output Sink Current Output Source Current Power Dissipation (Note Metal CERDIP Operating Temperature Range Maximum Junction Temperature (TJmax) Storage Temperature Range Soldering Information (Soldering Seconds) Thermal Resistance CERDIP Still CERDIP 500LF Flow Metal Still Metal 500LF Flow CERDIP Metal Tolerance (Note 18°C/W 41°C/W 123°C/W 69°C/W 171°C/W 92°C/W 300mW +125°C 370mW +125°C -55°C +125°C +175°C -65°C +150°C 300°C +18V +200mA +200mA -200mA
Recommended Operating Conditions
Supply Voltage Range +4.5V +16VDC
Quality Conformance Inspection
Mil-Std-883, Method 5005 Group Subgroup Description Static tests Static tests Static tests Dynamic tests Dynamic tests Dynamic tests Functional tests Functional tests Functional tests Switching tests Switching tests Switching tests Settling time Settling time Settling time Temp
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LM555JAN
Electrical Characteristics Parameters
Symbol VTrig Parameter Power Supply Current Trigger Voltage Conditions 4.5V 16.5V 4.5V 1.15 16.5V ITrig Trigger Current Threshold Voltage 16.5V 4.5V 16.5V Threshold Current Logical Output Voltage 16.5V 4.5V, ISink 4.5V, ISink 50mA 16.5V, ISink 10mA 16.5V, ISink 50mA 16.5V, ISink 100mA Logical Output Voltage 4.5V, ISource -100mA 16.5V, ISource -100mA ICEX VSat Discharge Transistor Leakage Current 16.5V 14.6 3,000 (Note (Note -1.6 -5.0 10.7 10.6 11.3 11.4 2,500 0.25 0.35 0.15 0.25 Notes Unit Subgroups
Discharge Transistor Saturation 16.5V Voltage Reset Voltage Reset Current 16.5V 16.5V
Parameters
Symbol tPLH Parameter Propagation Delay Time Conditions 4.5V 16.5V tPHL Propagation Delay Time 4.5V 16.5V Notes Unit Subgroups
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LM555JAN
Electrical Characteristics Parameters
Symbol tTLH tTHL tDOH Transition Time Transition Time Time Delay Output High Time Delay Output High 100K Drift Time Delay Temperature Coefficient Time Delay Capacitor Charge Time Capacitor Charge Time 100K tDis Capacitor Discharge Time Capacitor Discharge Time 100K tRes Drift Capacitor Charge Time Temperature Coefficient Capacitor Charge Time Reset Time (Continued)
(Continued)
Parameter
Conditions 4.5V 16.5V 4.5V 16.5V 4.5V 16.5V 4.5V 16.5V 4.5V 16.5V 16.5V 4.5V 16.5V 4.5V 16.5V 4.5V 16.5V 4.5V 16.5V 4.5V 16.5V 16.5V 16.5V
Notes
Unit nS/V nS/°C nS/V nS/°C
Subgroups
106.7 113.3 106.7 113.3 10.67 11.33 10.67 11.33 (Note -220 11.3 11.3 57.5 57.5 -820 (Note
Drift Parameters
Delta calculations performed devices Group Subgroup only. Symbol VTrig ICEX Parameter Trigger Voltage Threshold Voltage Logical Output Voltage Discharge Transistor Leakage Current Conditions 16.5V 16.5V 16.5V, ISink 10mA 16.5V Notes -0.05 -0.05 -0.05 0.05 0.05 0.05 Unit Subgroups
Note Absolute Maximum Ratings indicate limits beyond which damage device occur. Operating Ratings indicate conditions which device functional, guarantee specific performance limits. guaranteed specifications test conditions, Electrical Characteristics. guaranteed specifications apply only test conditions listed. Some performance characteristics degrade when device operated under listed test conditions. Note maximum power dissipation must derated elevated temperatures dictated TJmax (maximum junction temperature), (package junction ambient thermal resistance), (ambient temperature). maximum allowable power dissipation temperature PDmax (TJmax TA)/JA number given Absolute Maximum Ratings, whichever lower. Note Human body model, 1.5K series with 100pF. Note Parameter tested go-no-go, only. Note Datalog reading 0.7V will reflect Reset Voltage levels passing reading 0.5V 1.5V reflects Reset voltage levels failing level high level respectfully. Note Calculated parameter.
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LM555JAN
Typical Performance Characteristics
Minimum Pulse Width Required Triggering Supply Current Supply Voltage
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High Output Voltage Output Source Current
Output Voltage Output Sink Current
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Output Voltage Output Sink Current
Output Voltage Output Sink Current
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LM555JAN
Typical Performance Characteristics
Output Propagation Delay Voltage Level Trigger Pulse
(Continued) Output Propagation Delay Voltage Level Trigger Pulse
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Discharge Transistor (Pin Voltage Sink Current
Discharge Transistor (Pin Voltage Sink Current
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LM555JAN
Applications Information
MONOSTABLE OPERATION this mode operation, timer functions one-shot (Figure external capacitor initially held discharged transistor inside timer. Upon application negative trigger pulse less than flip-flop which both releases short circuit across capacitor drives output high.
during this time application negative pulse reset terminal (pin output will then remain state until trigger pulse again applied. When reset function use, recommended that connected avoid possibility false triggering. Figure nomograph easy determination values various time delays. NOTE: monostable operation, trigger should driven high before timing cycle.
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FIGURE Monostable voltage across capacitor then increases exponentially period which time voltage equals VCC. comparator then resets flip-flop which turn discharges capacitor drives output state. Figure shows waveforms generated this mode operation. Since charge threshold level comparator both directly proportional supply voltage, timing internal independent supply.
FIGURE Time Delay ASTABLE OPERATION circuit connected shown Figure (pins connected) will trigger itself free multivibrator. external capacitor charges through discharges through Thus duty cycle precisely ratio these resistors.
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TIME ms/DIV. 9.1k 0.01µF
Trace: Input 5V/Div. Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 2V/Div.
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FIGURE Monostable Waveforms During timing cycle when output high, further application trigger pulse will effect circuit long trigger input returned high least 10µs before timing interval. However circuit reset
FIGURE Astable this mode operation, capacitor charges discharges between VCC. triggered mode, charge discharge times, therefore frequency independent supply voltage.
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LM555JAN
Applications Information
(Continued)
FREQUENCY DIVIDER monostable circuit Figure used frequency divider adjusting length timing cycle. Figure shows waveforms generated divide three circuit.
Figure shows waveforms generated this mode operation.
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TIME 20µs/DIV. 3.9k 0.01µF
Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 1V/Div. TIME 20µs/DIV. 9.1k 0.01µF Trace: Input 4V/Div. Middle Trace: Output 2V/Div.
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Bottom Trace: Capacitor 2V/Div.
FIGURE Astable Waveforms charge time (output high) given 0.693 discharge time (output low) 0.693 (RB) Thus total period 0.693 +2RB) frequency oscillation
FIGURE Frequency Divider PULSE WIDTH MODULATOR When timer connected monostable mode triggered with continuous pulse train, output pulse width modulated signal applied Figure shows circuit, Figure some waveform examples.
Figure used quick determination these values. duty cycle
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FIGURE Pulse Width Modulator
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FIGURE Free Running Frequency
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LM555JAN
Applications Information
(Continued)
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TIME ms/DIV. 9.1k 0.01µF
Trace: Modulation 1V/Div. Bottom Trace: Output Voltage 2V/Div.
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TIME ms/DIV. 3.9k 0.01µF
Trace: Modulation Input 1V/Div. Bottom Trace: Output 2V/Div.
FIGURE Pulse Width Modulator FIGURE Pulse Position Modulator PULSE POSITION MODULATOR This application uses timer connected astable operation, Figure with modulating signal again applied control voltage terminal. pulse position varies with modulating signal, since threshold voltage hence time delay varied. Figure shows waveforms generated triangle wave modulation signal. LINEAR RAMP When pull-up resistor, monostable circuit replaced constant current source, linear ramp generated. Figure shows circuit configuration that will perform this function.
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FIGURE FIGURE Pulse Position Modulator Figure shows waveforms generated linear ramp. time interval given
0.6V
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LM555JAN
Applications Information
(Continued)
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TIME 20µs/DIV. 100k 0.01
Trace: Input 3V/Div. Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 1V/Div.
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FIGURE Duty Cycle Oscillator Note that this circuit will oscillate greater than because junction cannot bring down trigger lower comparator. ADDITIONAL INFORMATION Adequate power supply bypassing necessary protect associated circuitry. Minimum recommended 0.1µF parallel with electrolytic. Lower comparator storage time long 10µs when driven fully ground triggering. This limits monostable pulse width 10µs minimum. Delay time reset output 0.47µs typical. Minimum reset pulse width must 0.3µs, typical. current switches within 30ns output (pin voltage.
FIGURE Linear Ramp DUTY CYCLE OSCILLATOR duty cycle, resistors connected Figure time period output high same previous, 0.693 output
Thus frequency oscillation
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LM555JAN
Revision History
Date Released 08/04/05 Revision Section Release corporate format Originator Lytle Changes datasheet converted into corporate format. MJLM555-X archived
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LM555JAN
Physical Dimensions
inches (millimeters) unless otherwise noted
Ceramic Package Package Number J08A
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LM555JAN Timer
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Metal Package Package Number H08A
National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications. most current product information visit www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT GENERAL COUNSEL NATIONAL SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products uses packing materials that meet provisions Customer Products Stewardship Specification (CSP-9-111C2) Banned Substances Materials Interest Specification (CSP-9-111S2) contain ``Banned Substances'' defined CSP-9-111S2. Leadfree products RoHS compliant.
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critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.

LM555JAN Timer LM555 highly stable device generating accurate tim

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