28F640W30, 28F320W30, 28F128W30 High Performance Read-While-Write
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Intel® Wireless Flash Memory (W30)
28F640W30, 28F320W30, 28F128W30
High Performance Read-While-Write/Erase Burst Frequency Initial Access Speed Page-Mode Read Speed Burst-Mode Read Speed Burst-Mode Page-Mode Blocks across Partition Boundaries Burst Suspend Feature Enhanced Factory Programming: Word Program Time Programmable WAIT Signal Polarity Flash Power 1.70 1.90 VCCQ 2.20 3.30 Standby Current (130 (typ.) Read Current word burst, typical) Flash Software µs/9 (typ.) Program/Erase Suspend Latency Time Intel® Flash Data Integrator (FDI) Common Flash Interface (CFI) Compatible Quality Reliability Operating Temperature: 100K Minimum Erase Cycles ETOXVIII Process ETOXVII Process
Flash Architecture Multiple 4-Mbit Partitions Dual Operation: Parameter Block Size 4-Kword Main block size 32-Kword Bottom Parameter Blocks Flash Security 128-bit Protection Register: Unique Device Identifier Bits; User Protection Register Bits Absolute Write Protection with Ground Program Erase Lockout during Power Transitions Individual Instantaneous Block Locking/Unlocking with Lock-Down Density Packaging 32Mb, 64Mb, 128Mb Package; 64Mb, 128Mb QUAD+ Package 32Mb 128Mb Densities Package; 64Mb Density µBGA* Package Active Ball Matrix, 0.75 Ball-Pitch 16-bit Data
Intel® Wireless Flash Memory (W30) device combines state-of-the-art Intel® Flash technology provide versatile memory solution high performance, power, board constraint memory applications. flash memory device offers multi-partition, dual-operation flash architecture that enables flash device read from partition while programming erasing another partition. This Read-While-Write Read-While-Erase capability makes possible achieve higher data throughput rates compared single partition devices. processors interleave code execution, because program erase operations occur background processes. flash memory device incorporates Enhanced Factory Programming (EFP) mode improve factory programming performance. This feature helps eliminate manufacturing bottlenecks associated with programming high-density flash memory devices. program time word, compared standard factory program time word, mode saves significant factory programming time improved factory efficiency. flash memory device also includes block lock-down programmable WAIT signal polarity, supported array software tools. Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design. Order Number: 290702, Revision: June 2005
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June 2005
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Contents
Introduction
Document Purpose Nomenclature Conventions
Functional Overview
Overview Memory Partitioning
Package Information
Flash Memory Device Lithography Flash Memory Device Lithography
Ballout Signal Descriptions.
Signal Ballout Signal Descriptions
Maximum Ratings Operating Conditions
Absolute Maximum Ratings Operating Conditions
Electrical Specifications
Current Characteristics Voltage Characteristics.28
Characteristics
Read Operations Lithography.29 Read Operations Lithography.30 Write Characteristics. Erase Program Times
Power Reset Specifications
Active Power Automatic Power Savings (APS) Standby Power Power-Up/Down Characteristics 8.4.1 System Reset RST# 8.4.2 VCC, VPP, RST# Transitions Power Supply Decoupling. Reset Specifications Test Conditions Flash Device Capacitance
Flash Device Operations
Operations 9.1.1 Read 9.1.2 Burst Suspend
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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28F640W30, 28F320W30, 28F128W30
9.1.3 Standby. 9.1.4 Reset 9.1.5 Write Flash Device Commands. Command Sequencing
10.0 Read Operations
10.1 10.2 10.3 10.4 10.5 Read Array. Read Device Read Query (CFI) Read Status Register. Clear Status Register.
11.0 Program Operations
11.1 11.2 11.3 Word Program Factory Programming Enhanced Factory Program (EFP) 11.3.1 Requirements Considerations 11.3.2 Setup 11.3.3 Program 11.3.4 Verify. 11.3.5 Exit.
12.0 Program Erase Operations
12.1 12.2 12.3 Program/Erase Suspend Resume Block Erase. Read-While-Write Read-While-Erase
13.0 Security Modes.
13.1 Block Lock Operations. 13.1.1 Lock 13.1.2 Unlock. 13.1.3 Lock-Down. 13.1.4 Block Lock Status 13.1.5 Lock During Erase Suspend 13.1.6 Status Register Error Checking 13.1.7 Lock-Down Control Protection Register 13.2.1 Reading Protection Register. 13.2.2 Programing Protection Register. 13.2.3 Locking Protection Register. Protection
13.2
13.3
14.0 Read Configuration Register
14.1 14.2 14.3 14.4 14.5 14.6 Read Mode (RCR[15]) First Access Latency Count (RCR[13:11]). 14.2.1 Latency Count Settings. WAIT Signal Polarity (RCR[10]). WAIT Signal Function Data Hold (RCR[9]). WAIT Delay (RCR[8])
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14.7 14.8 14.9 14.10
Burst Sequence (RCR[7]) Clock Edge (RCR[6]) Burst Wrap (RCR[3]). Burst Length (RCR[2:0])
Appendix Appendix Appendix
Write State Machine Common Flash Interface. Ordering Information.
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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28F640W30, 28F320W30, 28F128W30
Revision History
Date Revision 09/19/00 Version -001 Initial release 28F3208W30 product references removed (product discontinued) 28F640W30 product added Revised Table Signal Descriptions (DQ15-0, ADV#, WAIT, S-UB#, S-LB#, VCCQ) Revised Section 3.1, Operations Revised Table Command Definitions, Notes Revised Section 4.2.2, First Latency Count (LC2-0); revised Figure Data Output with Setting Code added Figure First Access Latency Configuration Revised Section 4.2.3, WAIT Signal Polarity (WT) Added Section 4.2.4, WAIT Signal Function Revised Section 4.2.5, Data Output Configuration (DOC) Added Figure Data Output Configuration with WAIT Signal Delay Revised Table Status Register Description Revised entire Section 5.0, Program Erase Voltages Revised entire Section 5.3, Enhanced Factory Programming (EFP) 03/14/01 -002 Revised entire Section 8.0, Flash Security Modes Revised entire Section 9.0, Flash Protection Register; added Table Simultaneous Operations Allowed with Protection Register Revised Section 10.1, Power-Up/Down Characteristics Revised Section 11.3, Characteristics. Changed ICCS,ICCWS, ICCES Specs from 21µA; changed ICCR Spec from (burst length Added Figure WAIT Signal Synchronous Non-Read Array Operation Waveform Added Figure WAIT Signal Asynchronous Page-Mode Read Operation Waveform Added Figure WAIT Signal Asynchronous Single-Word Read Operation Waveform Revised Figure Write Waveform Revised Section 12.4, Reset Operations Clarified Section 13.2, SRAM Write Operation, Note Revised Section 14.0, Ordering Information Minor text edits Deleted SRAM Section Added 128M Specifications 04/05/02 -003 Added Burst Suspend Added Read While Write Transition Waveforms Various text edits Revised Device 04/24/02 -004 Revised Write Speed Various text edits Added Latency Count Tables 10/20/02 -005 Updated Packing Ball-Out Dimension Various text edits Minor text clarifications Description
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Date Revision
Version
Description Revised Table Current Characteristics, ICCS Revised Table Current Characteristics, ICCAPS
01/14/03
-006
Removed Intel Burst order Minor text edits Updated Package Drawing Dimensions Revised Table Read Operations, tAPA
03/22/03
-007
Added note table Configuration Register Descriptions Added note section 3.1.1, Read Updated Block Lock Operations (Sect. Fig. Updated improved timings Added QUAD+ package option, Appendix Minor text edits including product-naming conventions Corrected Absolute Maximum Rating VCCQ (Sect. 10.1, Table Minor text edits Restructured datasheet according layout. Timing Diagram Nomenclature Synergy with other product families Added Ordering information Minor Text Edits
11/17/03
-008
05/06/04 05/17/04 06/2005
-009 -010 -011
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
June 2005
28F640W30, 28F320W30, 28F128W30
Introduction
Document Purpose
This datasheet contains information about Intel® Wireless Flash Memory (W30) device family. Throughout this document, this device family referred flash memory device.
This chapter provides flash memory overview. Chapter through Chapter describe memory functionality. Chapter describes electrical specifications extended temperature product offerings. Appendix describes Write State Machine (WSM), Appendix describes Intel® Common Flash Interface (CFI) applies flash memory device. device family.
Appendix provides ordering information Intel® Wireless Flash Memory (W30)
Nomenclature
Acronyms that describe product features usage defined here:
Automatic Power Savings Block Base Address Common Flash Interface Command User Interface Enhanced Factory Programming Flash Data Integrator Connect One-Time Programmable Partition Base Address Read Configuration Register Read-While-Erase Read-While-Write SCSP Stacked Chip Scale Package Status Register Data Very-thin, Fine-pitch, Ball Grid Array Write State Machine
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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Conventions
following abbreviated terms phrases used throughout this document:
refers operating voltage range (except where noted). refers VCCQ operating voltage range refers When referring registers, term means logical cleared means logical connections package. (Ball term used BGA).
terms signal often used interchangeably refer external signal word bytes, bits. Signal names CAPS (for example, WAIT). Voltage applied signal subscripted (for example, VPP).
Throughout this document, references made top, bottom, parameter, partition. clarify these references, following conventions have been adopted:
block group bits words) that erase simultaneously with block erase
instruction.
main block contains Kwords. parameter block contains Kwords. Block Base Address (BBA) first address block. partition group blocks that share erase program circuitry common status register. 32-Mbit top-parameter flash device, partition number 0x140000.
Partition Base Address (PBA) first address partition. example, partition located highest physical flash device address. This partition
main partition parameter partition.
bottom partition located lowest physical flash device address. This partition
main partition parameter partition.
main partition contains only main blocks. parameter partition contains mixture main blocks parameter blocks. parameter device (TPD) parameter partition memory with
parameter blocks that partition. This flash device type formerly referred top-boot flash device.
bottom parameter device (BPD) parameter partition bottom memory
with parameter blocks bottom that partition. This flash device type formerly referred bottom-boot block flash device.
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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28F640W30, 28F320W30, 28F128W30
Functional Overview
This section provides overview flash memory device features architecture.
Overview
flash memory device provides Read-While-Write (RWW) Read-White-Erase (RWE) capability. This capability provides high-performance synchronous asynchronous reads package-compatible densities using 16-bit data bus. Individually-erasable memory blocks optimally sized code data storage. Eight 4-Kword parameter blocks located parameter partition either bottom memory map. rest memory array grouped into 32-Kword main blocks. memory architecture flash memory device consists multiple 4-Mbit partitions, exact number depending flash device density. dividing memory array into partitions, program erase operations take place simultaneously during read operations. Burst reads traverse partition boundaries, user application code responsible ensuring that burst reads extend into partition that actively programming erasing. Although each partition burst-read, write, erase capabilities, simultaneous operation limited write erase partition while other partitions read mode. Augmented erase-suspend functionality further enhances capabilities flash memory device. erase suspended perform program read operation within block, except block that erase-suspended. program operation nested within suspended erase subsequently suspended read another memory location. After power-up reset, flash memory device defaults asynchronous read configuration. Writing flash memory device Read Configuration Register (RCR) enables synchronous burst-mode read operation. synchronous mode, input increments internal burst address generator. also synchronizes flash memory device with host outputs data every, every other, valid cycle after initial latency. programmable WAIT output signals when data from flash memory device ready. addition improved architecture interface, flash memory device incorporates Enhanced Factory Programming (EFP), feature that enables fast programming low-power designs. feature provides fast program performance, which increase manufacturing throughput factory. flash memory device supports read operations erase program operations With 1.8-V option, tied together ultra-low-power design. addition voltage flexibility, dedicated input provides extensive data protection when VPPLK. 128-bit protection register implement security techniques data protection schemes:
combination factory-programmed user-OTP data cells provide unique flash device
identification, help implement fraud cloning prevention schemes, help protect content.
Zero-latency locking/unlocking memory block provides instant complete
protection critical system code data.
additional block lock-down capability provides hardware protection where software
commands alone cannot change block protection status.
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flash device Command User Interface (CUI) links system processor internal flash memory operation. valid command sequence written initiates flash device Write State Machine (WSM) operation, which automatically executes algorithms, timings, verifications necessary manage flash memory program erase. internal status register provides ready/busy indication results operation (success, fail, on). Three power-saving features- Automatic Power Savings (APS), standby, RST#- significantly reduce power consumption.
flash device automatically enters mode following read cycle completion. Standby mode begins when system deselects flash memory de-asserting CE#. Driving RST# produces power savings similar standby mode. also resets part
read-array mode (important system-level reset), clears internal status registers, provides additional level flash device write protection.
Memory Partitioning
flash memory device divided into 4-Mbit physical partitions. This partitioning allows simultaneous operations, enables users segment code data areas 4-Mbit boundaries. flash memory array asymmetrically blocked, which enables system code data integration within single flash device. Each block erased independently block erase mode. Simultaneous program erase operations allowed; only partition time actively programming erasing. Table "Bottom Parameter Memory Map" page Table "Top Parameter Memory Map" page
32-Mbit flash device eight partitions. 64-Mbit flash device partitions. 128-Mbit flash device partitions.
Each flash device density contains parameter partition several main partitions. 4-Mbit parameter partition contains eight 4-Kword parameter blocks seven 32-Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks. bulk flash memory array divided into main blocks that store code data, parameter blocks that allow storage frequently updated small parameters that normally stored EEPROM. using software techniques, word-rewrite functionality EEPROMs emulated.
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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Table
Size (KW) Sixteen Partitions
Bottom Parameter Memory
Mbit Mbit Mbit 7F8000-7FFFFF 400000-407FFF 3F8000-3FFFFF 200000-207FFF 1F8000-1FFFFF 100000-107FFF 0F8000-0FFFFF 0C0000-0C7FFF 0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Eight Partitions
3F8000-3FFFFF
200000-207FFF
Four Partitions
1F8000-1FFFFF
1F8000-1FFFFF 100000-107FFF 0F8000-0FFFFF 0C0000-0C7FFF 0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Main Partitions
100000-107FFF
Partition
0F8000-0FFFFF
0C0000-0C7FFF
Partition
0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Partition
Parameter Partition
Partition
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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Table
Size (KW) Parameter Partition
Parameter Memory
Mbit 1FF000-1FFFFF Mbit 3FF000-3FFFFF Mbit 7FF000-7FFFFF 7F8000-7F8FFF 7F0000-7F7FFF 7C0000-7C7FFF 7B8000-7BFFFF 780000-787FFF 778000-77FFFF 740000-747FFF 738000-73FFFF 700000-707FFF 6F8000-6FFFFF 600000-607FFF 5F8000-5FFFFF 400000-407FFF 3F8000-3FFFFF 000000-007FFF
Partition
1F8000-1F8FFF 1F0000-1F7FFF
3F8000-3F8FFF 3F0000-3F7FFF
1C0000-1C7FFF
3C0000-3C7FFF
Partition
1B8000-1BFFFF
3B8000-3BFFFF 380000-387FFF 378000-37FFFF 340000-347FFF 338000-33FFFF 300000-307FFF 2F8000-2FFFFF 200000-207FFF 1F8000-1FFFFF 000000-007FFF
18000-187FFF
Partition
178000-17FFFF
140000-147FFF
Partition
138000-13FFFF 100000-107FFF 0F8000-0FFFFF 000000-007FFF
Main Partitions
Four Partitions
Eight Partitions Sixteen Partitions
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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28F640W30, 28F320W30, 28F128W30
Figure
Package Information
Flash Memory Device Lithography
Package Drawing
rner rner
Bottom
eatin
Table
Package Specifications
Millimeters Dimension Symbol 0.665 0.375 7.700 11.000 9.000 0.750 1.225 2.2875 2.250 1.000 0.425 7.800 11.100 9.100 0.100 1.325 2.975 2.350 0.0059 0.0128 0.2992 0.4291 0.3504 0.0443 0.1093 0.0846 0.0262 0.0148 0.3031 0.4331 0.3543 0.0295 0.0482 0.1132 0.0886 0.0394 0.0167 0.3071 0.4370 0.3583 0.0039 0.0522 0.1171 0.0925 0.150 0.325 7.600 10.900 8.900 1.125 2.775 2.150 Inches
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Width (128 Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along (128 Corner Ball Distance Along Mb,128
June 2005
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Figure
32Mb, 64Mb 128Mb QUAD+ Package Drawing
Index Mark
View Ball Down
Bottom View Ball
Drawing scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along
Symbol
0.200 0.325 9.900 7.900
Millimeters 1.200 0.860 0.375 10.000 8.000 0.800 1.200 0.600
Notes
0.0079
Inches
0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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28F640W30, 28F320W30, 28F128W30
Figure
Flash Memory Device Lithography
64Mb µBGA* Package Drawing Dimensions
ilic
Symbol Millimeters 0.850 0.150 0.612 0.300 7.600 8.900
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along
1.000 0.812 0.400 7.800 9.100
Notes
0.712 0.350 7.700 9.000 0.750 1.225 2.250
Inches 0.0335 0.0059 0.0241 0.0118 0.2992 0.3503
0.0394 0.0320 0.0157 0.3071 0.3583
0.0280 0.0138 0.3031 0.3543 0.0295 0.0482 0.0886
1.125 2.150
0.100 1.325 2.350
0.0443 0.0846
0.0039 0.0522 0.0925
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Figure
32Mb Package Drawing
Ball Corner Ball Corner
View Bump Side Down eating lane Side Note: Drawing scale Bottom View Ball Side
Figure
128Mb Package Drawing
Ball Corner Ball Corner
Bottom View Ball Side
View Bump Side Down
Seating Plane Side View Note: Drawing scal
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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28F640W30, 28F320W30, 28F128W30
Table
32Mb 128Mb Package Dimensions
Millimeters Dimension Symbol 0.665 0.375 7.700 9.000 12.500 12.000 0.750 1.225 2.250 2.875 3.000 1.000 0.715 0.425 7.800 9.100 12.600 12.100 0.100 1.325 2.350 2.975 3.1000 0.0335 0.0059 0.0242 0.0128 0.2992 0.3503 0.4882 0.4685 0.0443 0.0846 0.1093 0.1142 0.0262 0.0148 0.3031 0.3543 0.4921 0.4724 0.0295 0.0482 0.0886 0.1132 0.1181 0.0394 0.0281 0.0167 0.3071 0.3583 0.4961 0.4764 0.0039 0.0522 0.0925 0.1171 0.1220 0.850 0.150 0.615 0.325 7.600 8.900 12.400 11.900 1.125 2.150 2.775 2.900 Inches
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width 32Mb Package Body Length32Mb Package Body Width 128Mb Package Body Length 128Mb Pitch Ball (Lead) Count 32Mb Ball (Lead) Count 128Mb Seating Plane Coplanarity Corner Ball Distance Along 32Mb Corner Ball Distance Along 32Mb Corner Ball Distance Along 128Mb Corner Ball Distance Along 128Mb
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Ballout Signal Descriptions
Signal Ballout
flash memory device available 56-ball µBGA Chip Scale Package with 0.75 ball pitch, QUAD+ SCSP package. Figure shows µBGA package ballout. Figure shows QUAD+ package ballout.
Figure
56-Ball BGA/ µBGA Ballout
VCCQ VSSQ VCCQ VSSQ VSSQ VCCQ VSSQ DQ14 DQ13 DQ11 DQ10 DQ10 DQ11 DQ13 DQ14 DQ15 DQ15 VCCQ WAIT DQ12 DQ12 WAIT ADV# ADV# RST# RST#
View Ball Side Down Complete Mark Shown
Bottom View Ball Side
Notes: lower density flash memory devices, upper address balls treated (that 32-Mbit density, NC). Appendix "Ordering Information" page mechanical specifications package.
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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Figure
88-Ball Active Balls) QUAD+ Ballout
F1-VCC F2-VCC
R-LB# S-CS2
F-VPP, F-VPEN R-WE# P1-CS#
F-WP# ADV#
R-UB# F-RST# F-WE#
WAIT F2-CE#
R-OE# F2-OE#
S-CS1# F1-OE# VCCQ
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE
VCCQ F1-VCC
View Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific
Notes: lower density flash memory devices, upper address balls treated (that 64-Mb density, A[25:23]are Appendix "Ordering Information" page mechanical specifications package.
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Signal Descriptions
Table describes signals 56-ball µBGA Chip Scale Package. Table describes signals QUAD+ package ballout.
Table
Symbol A[22:0]
Signal Descriptions µBGA Package Package (Sheet
Type Input Name Function ADDRESS INPUTS: memory addresses. Mbit: A[20:0]; Mbit: A[21:0]; Mbit: A[22:0] DATA INPUTS/OUTPUTS: Inputs data commands during write cycles. Outputs data during reads. Data pins High-Z when flash device outputs deselected. Data internally latched during writes.
D[15:0]
Input/ Output
ADV#
Input
ADDRESS VALID: ADV# indicates valid address presence address inputs. During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. CHIP ENABLE: Asserting activates internal control logic, buffers, decoders, sense amps. De-asserting deselects flash device, places standby mode, tri-states outputs. CLOCK: synchronizes flash device system frequency during synchronous reads increments internal address generator. During synchronous read operations, addresses latched ADV#'s rising edge CLK's rising falling) edge, whichever occurs first. OUTPUT ENABLE: When asserted, enables flash device output data buffers during read cycle. When deasserted, data outputs placed high-impedance state. RESET: When low, RST# resets internal automation inhibits write operations. This reset provides data protection during power transitions. De-asserting RST# enables normal operation places flash device asynchronous read-array mode. WAIT: WAIT signal indicates valid data during synchronous read modes. configured asserted-high asserted-low, based Read Configuration Register. WAIT tri-stated deasserted. WAIT gated OE#. WRITE ENABLE: controls writes array. Addresses data latched rising edge WE#. WRITE PROTECT: Disables/enables lock-down function. When asserted, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software. Section 13.1, "Block Lock Operations" page details block locking. ERASE PROGRAM POWER: valid voltage this allows erasing programming. Flash memory contents cannot altered when VPPLK. attempt block erase program operations invalid voltages.
Input
Input
Input
RST#
Input
WAIT
Output
Input
Input
Power/ Input
in-system program erase operations. accommodate resistor diode drops from system supply, level VPPL min. must remain above VPPL perform in-system flash device modification. during read operations. VPPH applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. connected cumulative total exceed hours. Extended this might reduce block cycling capability.
VCCQ
Power Power Power
FLASH DEVICE POWER SUPPLY: Writes inhibited VLKO. attempt flash device operations invalid voltages. OUTPUT POWER SUPPLY: Enables outputs driven VCCQ. GROUND: Pins internal flash device circuitry must connected system ground.
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28F640W30, 28F320W30, 28F128W30
Table
Symbol VSSQ
Signal Descriptions µBGA Package Package (Sheet
Type Power Name Function OUTPUT GROUND: Provides ground outputs which driven VCCQ. This signal tied directly VSS. USE: this pin. connect this power supplies, signals, other pins; this must floated. CONNECT: internal connection; driven floated.
Table
Symbol
Signal Descriptions QUAD+ Package (Sheet
Type Description ADDRESS INPUTS: Inputs addresses during read write operations.
A[MAX:MIN]
Input
32-Mbit AMAX lowest-order 16-bit wide address. A[25:24] denote high-order addresses reserved future flash device densities. DATA INPUTS/OUTPUTS: Inputs data commands during write cycles. Outputs data during read cycles. Data signals float when flash device outputs deselected. Data internally latched during writes flash device. FLASH CHIP ENABLE: Low-true input. F[3:1]-CE# selects associated flash memory die. When asserted, flash memory internal control logic, input buffers, decoders, sense amplifiers active.
128-Mbit AMAX 64-Mbit AMAX
DQ[15:0]
Input/ Output
F[3:1]-CE#
Input
When deasserted, associated flash deselected, power reduced standby levels, data WAIT outputs placed high-Z state. F1-CE# selects deselects flash F2-CE# selects deselects flash combinations with only flash die. F3-CE# selects deselects flash stacked combinations with only flash dies. SRAM CHIP SELECT: Low-true High-true input (S-CS1# S-CS2 respectively). When either/both SRAM Chip Select signals asserted, SRAM internal control logic, input buffers, decoders, sense amplifiers active.
S-CS1# S-CS2
Input
When either/both SRAM Chip Select signals deasserted, SRAM deselected power reduced standby levels. S-CS1# S-CS2 available stacked combinations with SRAM stacked combinations without SRAM die. PSRAM CHIP SELECT: Low-true input. When asserted, PSRAM internal control logic, input buffers, decoders, sense amplifiers active.
P[2:1]-CS#
Input
When deasserted, PSRAM deselected power reduced standby levels. P1-CS# selects PSRAM available only stacked combinations with PSRAM die. This ball stacked combinations without PSRAM. P2-CS# selects PSRAM available only stacked combinations with PSRAM dies. This ball stacked combinations without PSRAM with single PSRAM.
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Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Table
Symbol
Signal Descriptions QUAD+ Package (Sheet
Type FLASH OUTPUT ENABLE: Low-true input. Fx-OE# enables output buffers selected flash memory device. F[2:1]-OE# high disables output buffers selected flash memory device, placing them High-Z. F1-OE# controls outputs flash F2-OE# controls outputs flash flash F2-OE# available stacked combinations with three flash die, stacked combinations with only flash die. OUTPUT ENABLE: Low-true input. R-OE# enables output buffers selected RAM. Description
F[2:1]-OE#
Input
R-OE#
Input
R-OE# high disables output buffers, places selected outputs High-Z. R-OE# available stacked combinations with PSRAM SRAM die, flash-only stacked combinations. FLASH WRITE ENABLE: Low-true input.
F-WE#
Input
F-WE# controls writes selected flash die. Address data latched rising edge F-WE#. WRITE ENABLE: Low-true input. R-WE# controls writes selected die. R-WE# available stacked combinations with PSRAM SRAM die, flash-only stacked combinations. CLOCK: Synchronizes flash with system clock synchronous read mode increments internal address generator.
R-WE#
Input
Input
During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. During asynchronous mode read operations, addresses latched rising edge ADV#, continuously flow-through when ADV# kept asserted. WAIT: Output signal. Indicates invalid data during synchronous array non-array flash memory reads. Read Configuration Register (RCR[10]) determines WAIT-asserted polarity (high low). WAIT High-Z F-CE# deasserted; WAIT gated F-OE#. synchronous array non-array flash memory read modes, WAIT indicates invalid data when asserted valid data when deasserted. asynchronous flash memory page read, flash memory write modes, WAIT asserted. FLASH WRITE PROTECT: Low-true input. F-WP# enables/disables lock-down protection mechanism selected flash die.
WAIT
Output
F-WP#
Input
F-WP# enables lock-down mechanism where locked down blocks cannot unlocked using software commands. F-WP# high disables lock-down mechanism, allowing locked down blocks unlocked using software commands. ADDRESS VALID: Low-true input. During synchronous flash memory read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. During asynchronous flash memory read operations, addresses latched rising edge ADV#, continuously flow-through when ADV# kept asserted.
ADV#
Input
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Table
Symbol
Signal Descriptions QUAD+ Package (Sheet
Type Description UPPER LOWER BYTE ENABLES: Low-true input. During read write cycles:
R-UB# R-LB#
Input
R-UB# enables high order bytes D[15:8]. R-LB# enables low-order bytes D[7:0]. R-UB# R-LB# available stacked combinations with PSRAM SRAM die, flash-only stacked combinations. FLASH RESET: Low-true input. F-RST# initializes flash device internal circuitry disables flash device operations. F-RST# high enables flash device operation. Exit from reset places flash device asynchronous read array mode. P-Mode (PSRAM Mode): Low-true input. P-Mode programs Configuration Register, enters/exits Power Mode PSRAM die.
F-RST#
Input
P-Mode, P-CRE
P-Mode available stacked combinations with asynchronous-only PSRAM die. Input P-CRE (PSRAM Configuration Register Enable): High-true input. P-CRE high, write operations load Refresh Control Register Control Register. P-CRE applies only combinations with synchronous PSRAM die. P-Mode, P-CRE stacked combinations without PSRAM die. FLASH PROGRAM ERASE POWER: Valid voltage this ball enables flash memory device program/erase operations. Power Flash memory array contents cannot altered when F-VPP(F-VPEN) VPPLK (VPENLK). attempt erase program operations invalid F-VPP (F-VPEN) voltages. F-VPEN (Erase/Program/Block Lock Enables) available L18/L30 SCSP products. FLASH LOGIC POWER: F1-VCC supplies power core logic flash F2-VCC supplies power core logic flash flash
F-VPP, F-VPEN
F[2:1]-VCC
Power
Write operations inhibited when F-VCC VLKO. attempt flash device operations invalid F-VCC voltages. F2-VCC available stacked combinations with three flash dies, stacked combinations with only flash die. SRAM POWER SUPPLY: Supplies power SRAM operations.
S-VCC
Power
S-VCC available stacked combinations with SRAM die, stacked combinations without SRAM die. PSRAM POWER SUPPLY: Supplies power PSRAM operations. P-VCC available stacked combinations with PSRAM die, stacked combinations without PSRAM die. FLASH DEVICE POWER: Supply power flash device input output buffers. FLASH DEVICE GROUND: Connect system ground. float connection. RESERVED FUTURE USE: Reserved future flash device functionality/ enhancements. Contact Intel regarding balls designated RFU. USE: connect other signal, power supply; must left floating.
P-VCC VCCQ
Power Power Power
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Warning:
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
Stressing flash device beyond Absolute Maximum Ratings Table might cause permanent damage. These stress ratings only.
Notice: This datasheet contains information products design phase development. information here subject change without notice. finalize design with this information.
Table
Absolute Maximum Ratings
Parameter Temperature under Bias Storage Temperature Voltage (except VCCQ, VPP) Voltage Voltage VCCQ Voltage Output Short Circuit Current Maximum Rating +125 -0.5 +3.8 -0.2 -0.2 +2.45 -0.2 +3.8 1,2,3 Note
Notes: specified voltages relative VSS. Minimum voltage -0.5 input/output pins -0.2 pins. During transitions, this level might undershoot -2.0 periods Maximum voltage input/output pins +0.5 which, during transitions, might overshoot +2.0 periods Maximum voltage might overshoot +14.0 periods program voltage normally VPPL. 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. Output shorted more than second. more than output shorted time.
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Operating Conditions
operate flash memory device beyond Operating Conditions Table Extended exposure beyond these Operating Conditions might affect flash device reliability.
Table
Extended Temperature Operation
Symbol VCCQ VPPL VPPH tPPH Block Erase Cycles Parameter1 Operating Temperature Supply Voltage Supply Voltage Voltage Supply (Logic Level) Factory Programming Maximum Hours Main Parameter Blocks Main Blocks Parameter Blocks 0.90 11.4 100,000 1.80 12.0 1.90 1.95 12.6 1000 2500 Cycles Hours Unit Notes
Notes: Section 6.1, Current Characteristics" page Section 6.2, Voltage Characteristics" page specific voltage-range specifications. normally VPPL. connected 11.4 V-12.6 1000 cycles main blocks extended temperatures 2500 cycles parameter blocks extended temperature. Contact your Intel field representative VCC/VCCQ operations down 1.65 tables Section 6.0, "Electrical Specifications" page Section 7.0, Characteristics" page operating characteristics
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Table
Electrical Specifications
Current Characteristics
Current Characteristics (Sheet
VCCQ=
Parameter
Note
32/64 Mbit
Mbit
Unit
Test Conditions
Input Load
VCCQ VCCQMax VCCQ VCCQ VCCQMax VCCQ VCCQ VCCQMax VCCQ RST# =VCCQ VCCQ VCCQMax VSSQ RST# =VCCQ other inputs =VCCQ Word Read Burst length Burst length Burst length Burst length Continuous VPPL, Program Progress VPPH, Program Progress VPPL, Block Erase Progress VPPH, Block Erase Progress VCC, Program Suspended VCC, Erase Suspended VCCMax Inputs
ICCS ICCS ICCAPS ICCAPS
Output Leakage
DQ[15:0]
Standby Asynchronous Page Mode f=13
ICCR
Average Read
Synchronous
ICCW
Program
3,4,5 3,4,5
ICCE ICCWS ICCES IPPS (IPPWS, IPPES) IPPR
Block Erase Program Suspend Erase Suspend Standby Program Suspend Erase Suspend Read
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Table
Current Characteristics (Sheet
VCCQ=
Parameter
Note
32/64 Mbit 0.05 0.10 0.10
Mbit 0.05 0.05 0.10
Unit
Test Conditions
IPPW
Program
0.05 0.10
VPPL, Program Progress VPPH, Program Progress
IPPE
Erase
VPPL, Erase Progress VPPH, Erase Progress
Notes: currents unless noted. Typical values typical VCC, +25°C. Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation. ICCRQ specification details. Sampled, 100% tested. read program current read program currents. read erase current read erase currents. ICCES specified with flash device deselected. flash device read while erase suspend, current ICCES plus ICCR. VPPLK inhibits erase program operations. VPPL VPPH outside their valid ranges. undershoot -0.4V overshoot VCCQ+0.4V durations less. VIN>VCC input load current increases max. ICCS average current measured over time interval after de-assertion. Refer section Section 8.2, "Automatic Power Savings (APS)" page ICCAPS measurement details.
Table
Voltage Characteristics
Voltage Characteristics
VCCQ= Parameter Note 32/64 Mbit Input Input High Output Output High Lock-Out Lock VCCQ Lock VCCQ VCCQ Mbit VCCQ VCCQ VCCMin VCCQ VCCQMin VCCMin VCCQ VCCQMin -100 Unit Test Conditions
VCCQ
VCCQ
VPPLK VLKO VILKOQ Note:
numbered note references this table, refer notes Table Current Characteristics" page
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Table
Characteristics
Read Operations Lithography
Read Operations Lithography (Sheet
32-Mbit 64-Mbit 128-Mbit Units Notes
Parameter
Asynchronous Specifications tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tELTV tEHTZ Read Cycle Time Address Output Valid Output Valid Output Valid RST# High Output Valid Output Low-Z Output Low-Z High Output High-Z High Output High-Z (OE#) High Output Low-Z Pulse Width High WAIT Valid High WAIT High-Z
Latching Specifications R101 R102 R103 R104 R105 R106 R108 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA Address Setup ADV# High ADV# High ADV# Output Valid ADV# Pulse Width ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/L tCHCL Frequency Period High Time Fall Rise Time
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Table
Read Operations Lithography (Sheet
32-Mbit 64-Mbit 128-Mbit Units Notes
Parameter
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV Address Valid Setup ADV# Setup Setup Output Valid Output Hold from Address Hold from WAIT Valid
Notes: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Address hold synchronous-burst mode defined tCHAX tVHAX, whichever timing specification satisfied first. delayed tELQV tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Applies only subsequent synchronous reads. During initial access synchronous burst read, data from first word might begin driven onto data early first clock edge after tAVQV.
Table
Read Operations Lithography
Read Operations Lithography (Sheet
32-Mbit 64-Mbit 128-Mbit Units Notes
Parameter
Asynchronous Specifications tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ Read Cycle Time Address Output Valid Output Valid Output Valid RST# High Output Valid Output Low-Z Output Low-Z High Output High-Z High Output High-Z
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Table
Read Operations Lithography (Sheet
32-Mbit 64-Mbit 128-Mbit Units Notes
Parameter
tEHEL tELTV tEHTZ
(OE#) High Output Low-Z Pulse Width High WAIT Valid High WAIT High-Z
Latching Specifications R101 R102 R103 R104 R105 R106 R108 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA Address Setup ADV# High ADV# High ADV# Output Valid ADV# Pulse Width ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/L tCHCL Frequency Period High Time Fall Rise Time
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV Address Valid Setup ADV# Setup Setup Output Valid Output Hold from Address Hold from WAIT Valid
Notes: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Address hold synchronous-burst mode defined tCHAX tVHAX, whichever timing specification satisfied first. delayed tELQV- tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Applies only subsequent synchronous reads. During initial access synchronous burst read, data from first word might begin driven onto data early first clock edge after tAVQV.
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Figure
Asynchronous Read Operation Waveform
Address
Valid Address
High High
WAIT
Note
Data [D/Q]
High
Valid Output
RST#
Notes: WAIT shown asserted (RCR[10]=0) ADV# assumed driven this waveform
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Figure
Latched Asynchronous Read Operation Waveform
A[MAX:2]
Valid Address
Valid Address
A[1:0]
R101 R105 R106
Valid Address
Valid Address
ADV#
R104 R103
R102
Data
High
Valid Output
RST#
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Figure
Page-Mode Read Operation Waveform
A[MAX:2]
Valid Address
A[1:0]
R101 R105 R106
Valid Address
Valid Address
Valid Address
Valid Address
ADV#
R104 R103
R102
WAIT
High Valid Output Valid Output Valid Output Valid Output High
Note
R108
High
Data [D/Q]
RST#
Note:
WAIT shown asserted (RCR[10]
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Figure
Single Synchronous Read-Array Operation Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; RCR[10]=0) configured assert either during, data cycle before, valid data. this waveform, x-word burst initiated main array terminated de-assertion after first word burst. this access been done Status, Query reads, asserted (low) WAIT signal would have remained asserted (low) long asserted (low).
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Figure
Synchronous 4-Word Burst Read Operation Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; RCR[10] configured assert either during, data cycle before, valid data.
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Figure
WAIT Functionality EOWL (End-of-Word Line) Condition Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; RCR[10]=0) configured assert either during, data cycle before, valid data. (This example assumes wait delay clocks.)
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
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Figure
WAIT Signal Synchronous Non-Read Array Operation Waveform
Notes: Section 14.2, "First Access Latency Count (RCR[13:11])" page describes insert clock cycles during initial access. WAIT shown asserted (RCR[10]=0).
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Figure
Burst Suspend
R304 Address R101 R105 ADV# WAIT DATA [D/Q] R304 R304 R305 R305 R305
R106
Note:
During Burst Suspend, Clock signal held high low.
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Table
Write Characteristics
Write Characteristics
32-Mbit 64-Mbit 128-Mbit
Parameter
Notes tAVQV
Unit
Notes:
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH tWHEH (tEHWH tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tWHQV tWHAV tWHCV tWHVH
RST# High Recovery (CE#) (WE#) Setup (CE#) (CE#) Write Pulse Width Data Setup (CE#) High Address Setup (CE#) High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High (CE#) Pulse Width High Setup (CE#) High Hold from Valid Hold from Valid Setup (CE#) High Write Recovery before Read High Valid Data High Address Valid High Valid High ADV# High
5,6,7 3,6,10 3,9,10 3,10 3,10
tAVQV
Write timing characteristics during erase suspend same during write-only operations. write operation terminated with either WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from (whichever occurs last) high (whichever occurs first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL tEHEL) defined from high (whichever first) (whichever last). Hence, tWHWL tEHEL tWHEL tEHWL. System designers must take this into account, insert software No-Op instruction delay first read after issuing command. commands other than resume commands. must held VPPL VPPH until block erase program success determined. Applicable during asynchronous reads following write. tWHCH/L tWHVH must when transitioning from write cycle synchronous burst read. tWHCH/L tWHVH both refer address latching event (either rising/falling clock edge rising ADV# edge, whichever occurs first).
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Figure
Write Operations Waveform
Note
Note
Valid Address
Note
Valid Address
Note
Note
Valid Address
Address
R101 R105 R106
ADV#
R104
(WE#) [E(W)]
Note
(CE#) [W(E)]
Note
Data
Data Data
Valid
RST#
VPPH
VPPLK
Notes:
power-up standby. Write Program Erase Setup command. Write valid address data (for program) Erase Confirm command. Automated program/erase delay. Read status register data (SRD) determine program/erase operation completion. must asserted must deasserted read operations. ignored (but kept active/toggling).
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Figure
Asynchronous Read Write Operation Waveform
Address Data [D/Q] RST#
Figure
Asynchronous Write Read Operation
Address
Data [D/Q]
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Figure
Synchronous Read Write Operation
Latency Count R301 R302 R306 R101 Address R105 R106 R102 ADV# R303 WAIT R304 Data [D/Q] R305 R307 R104
Figure
Synchronous Write Read Operation
Latency Count R302 R301 Address ADV# R303 R106 R104 R306
WAIT Data [D/Q RST# R304 R304 R305 R307
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Table
Operation
Erase Program Times
Erase Program Times
Symbol Parameter Description1 VPPL Notes VPPH Unit
Erasing Suspending W500 Erase Time W501 Suspend Latency Programming W200 Program Time W201 W202 tPROG/W tPROG/PB tPROG/MB
tERS/PB tERS/MB tSUSP/P tSUSP/E
4-Kword Parameter Block 32-Kword Main Block Program Suspend Erase Suspend
0.25
W600 W601
Single Word 4-Kword Parameter Block 32-Kword Main Block
0.05
0.03 0.24
0.07
Enhanced Factory Programming W400 Program W401 W402 W403 Operation Latency W404 W405
tEFP/W tEFP/PB tEFP/MB tEFP/SETUP tEFP/TRAN tEFP/VERIFY
Single Word 4-Kword Parameter Block 32-Kword Main Block Setup Program Verify Transition Verify
Notes: Unless noted otherwise, parameters measured nominal voltages, sampled, 100% tested. Excludes external system-level overhead. Exact results might vary based system overhead. W400-Typ calculated delay single programming pulse. W400-Max includes delay when programming within word-line. Some performance degradation might occur block cycling exceeds
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Power Reset Specifications
Intel® Wireless Flash Memory (W30) devices have layered approach power savings that significantly reduce overall system power consumption.
feature reduces power consumption when flash device selected idle. deasserted, memory enters standby mode, where current consumption even
lower.
Asserting RST# provides current savings similar standby mode.
combination these features minimize memory power consumption, therefore, overall system power consumption.
Active Power
With RST# VIH, flash device active mode. Refer Section 6.1, Current Characteristics" page values. When flash device active state, consumes most power from system. Minimizing flash device active current therefore reduces system power consumption, especially battery-powered applications.
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides power operation during read active state. ICCAPS average current measured over time interval, after deasserted. During APS, average current measured over same time interval after following events:
There internal read, program erase activity. asserted. address lines quiescent, VIH.
driven during APS.
Standby Power
When deasserted, flash device deselected placed standby, substantially reducing power consumption. standby, data outputs placed High-Z, independent level placed OE#. Standby current, ICCS, average current measured over time interval, after deasserted. During standby, average current measured over same time interval after deasserted. When flash device deselected (while deasserted) during program erase operation, continues consume active power until program erase operation completes.
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Power-Up/Down Characteristics
flash device protected against accidental block erasure programming during power transitions. Power supply sequencing required connected together; does matter whether powers-up first. connected system supply, then must attain VCCMIN before applying VCCQ VPP. drive flash device inputs before supply voltage VCCQMIN. Power supply transitions occur only when RST# low.
8.4.1
System Reset RST#
RST# during system reset important with automated program/erase flash devices, because system expects read from flash memory when comes reset. reset occurs without flash memory reset, properly initialized, because flash memory might providing status information instead array data.
Note:
allow proper CPU/flash device initialization system reset, connect RST# system RESET# signal. System designers must guard against spurious writes when voltages above VLKO. Because both must command write, driving either signal inhibits writes flash device. architecture provides additional protection, because memory contents altered only after successful completion two-step command sequences. flash device also disabled until RST# brought VIH, regardless control input states. holding flash device reset (RST# connected system PowerGood) during power-up/ down, invalid conditions during power-up masked, providing another level memory protection.
8.4.2
VCC, VPP, RST# Transitions
latches commands issued system software, altered transitions actions. Read-array mode power-up default state after flash device exits from reset mode after transitions above VLKO (Lockout voltage). After completing program block erase operations (even after transitions below PPLK), Read Array command must reset read-array mode flash memory array access desired.
Power Supply Decoupling
When flash device accessed, many internal conditions change. Circuits enabled charge pumps switch voltages. This internal activity produces transient noise. minimize effect this transient noise, device decoupling capacitors required. Transient current magnitudes depend flash device output capacitive inductive loading. Two-line control proper decoupling capacitor selection suppresses these transient voltage peaks.
Note:
Each flash device must have ceramic capacitor connected between each power (VCC, VCCQ, VPP) ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors must close possible package signals.
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Table
Notes:
Reset Specifications
Reset Specifications
Symbol tPLPH tPLRH tVCCPH Parameter1 RST# Reset during Read RST# Reset during Block Erase RST# Reset during Program Power Valid Reset Notes 1,3,4,5,6 Unit
These specifications valid product versions (packages speeds). flash device might reset tPLPH tPLPHMin, this guaranteed. applicable RST# tied VCC. Sampled, 100% tested. RST# tied VCC, flash device ready until tVCCPH occurs after when Min. RST# tied supply/signal with VCCQ voltage levels, RST# input voltage must exceed until Min.
Figure
Reset Operations Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
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Figure
Test Conditions
Input/Output Reference Waveform
VCCQ Input
Note: Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10% 90%) Worst case speed conditions when VCCMin.
VCCQ/2
Test Points
VCCQ/2
Output
Figure
Transient Equivalent Testing Load Circuit
VCCQ
Device Under Test
Note:
Table component values.
Table
Test Configuration Component Values Worst Case Speed Conditions
Test Configuration CCQMin Standard Test Note: includes capacitance. (pF)
Figure
Clock Input Waveform
R201
R202 R203
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Flash Device Capacitance
Symbol Unit Condition
COUT
Input Capacitance Output Capacitance Input Capacitance
VOUT
Sampled, 100% tested.
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Flash Device Operations
This chapter provides overview flash device operations. flash memory device family includes on-chip Write State Machine (WSM) manage block erase program algorithms. Command User Interface (CUI) allows minimal processor overhead with RAM-like interface timings.
Table
Operations
Operations Summary
RST# ADV# WAIT DQ[15:0] Notes
Operation
Asynchronous Read Synchronous Burst Suspend Write Output Disable Standby Reset
Notes:
Running Halted
Asserted Driven Active Asserted Asserted High-Z High-Z
Output Output Output Input High-Z High-Z High-Z
WAIT valid only during synchronous array-read operations. Refer Table "Bus Cycle Definitions" page valid DQ[15:0] during write operation. Don't Care RST# must meet maximum specified power-down current.
9.1.1
Read
flash memory device several read configurations:
Asynchronous page mode read. Synchronous burst mode read outputs four, eight, sixteen, continuous words, from main
blocks parameter blocks. Several read modes available each partition:
Read-array mode: read accesses return flash memory array data from addressed
locations.
Read identifier mode: reads return manufacturer device identifier data, block lock status,
protection register data. Identifier information accessed starting 4-Mbit partition base addresses; flash memory array accessible read identifier mode.
Read query mode: reads return flash device data. information accessed
starting 4-Mbit partition base addresses; flash memory array accessible read query mode.
Read status register mode: reads return status register data from addressed partition.
array data that partition accessible. system processor check status register determine state addressed partition, monitor program erase progress.
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partitions support synchronous burst mode that internally sequences addresses with respect input select supply data outputs. Identifier codes, query data, status register read operations execute single-synchronous asynchronous read cycles. WAIT asserted during these reads. Access modes listed above independent appropriate command places flash device read mode. initial power-up after reset, flash device defaults asynchronous read-array mode. Asserting enables flash device read operations. flash device internally decodes upper address inputs determine which partition accessed.
Asserting ADV# opens internal address latches. Asserting activates outputs, gates selected data onto bus. asynchronous mode, address latched when ADV# deasserted (when flash device
configured ADV#).
synchronous mode, address latched either rising edge ADV# rising
falling) edge while ADV# remains asserted, whichever occurs first. RST# must deasserted during read operations. Note: only asynchronous reads performed your system, must tied valid level, WAIT signal floated, ADV# must tied ground.
9.1.2
Burst Suspend
Burst Suspend feature allows system temporarily suspend synchronous burst operation system needs flash device address data other purposes. Burst accesses suspended during initial latency (before data received) after flash device output data. When burst access suspended, internal array sensing continues previously latched internal data retained. Burst Suspend occurs when asserted, current address been latched (either ADV# rising edge valid edge), halted, deasserted. halted when resume burst access, reasserted restarted. Subsequent edges resume burst sequence where left off. Within flash device, gates WAIT signal. Therefore, during Burst Suspend, WAIT remains asserted does revert high-impedance state when deasserted. This WAIT state cause contention with another flash device attempting control system READY signal during Burst Suspend. System using Burst Suspend feature must connect flash device WAIT signal directly system READY signal. Refer Figure "Burst Suspend" page
9.1.3
Standby
De-asserting deselects flash device places standby mode, substantially reducing flash device power consumption. standby mode, outputs placed high-impedance state independent OE#. deselected during program erase algorithm, flash device consumes active power until program erase operation completes.
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9.1.4
Reset
flash device enters reset mode when RST# asserted. reset mode, internal circuitry turned outputs placed high-impedance state. After returning from reset, time tPHQV required until outputs valid, delay (tPHWV) required before write sequence initiated. After this wake-up interval, normal operation restored. flash device defaults read-array mode, status register 80h, Read Configuration Register defaults asynchronous page-mode reads. RST# asserted during erase program operation, operation aborts memory contents aborted block address invalid. Figure "Reset Operations Waveforms" page detailed information regarding reset timings. automated device, RST# must asserted during system reset. When system comes reset, processor expects read from flash memory array. Automated flash memory devices provide status information when read during program erase operations. reset occurs with flash memory reset, might properly initialized, because flash memory device might providing status information instead array data. Volt Intel Flash memory devices allow proper initialization following system reset through RST# input. this application, RST# controlled same reset signal, RESET#.
9.1.5
Write
write occurs when asserted deasserted. Flash memory control commands written using standard microprocessor write timings. Proper ADV# input needed proper latching addresses. Refer Section 7.3, Write Characteristics" page details. address data latched rising edge WE#. Write operations asynchronous; ignored (but kept active/toggling). does occupy addressable memory location within partition. system processor must access correct address range, depending kind command executed. Programming erasing occur only partition time. Other partitions must read modes erase suspend mode. Table "Command Codes Descriptions" page shows available commands. Appendix "Write State Machine" page provides information about moving between different operating modes using commands.
Flash Device Commands
flash device on-chip manages erase program algorithms. This local (WSM) controls flash device in-system read, program, erase operations. cycles from flash memory device conform standard microprocessor cycles. RST#, CE#, OE#, WE#, ADV# control signals dictate data flow into flash device. WAIT informs valid data during burst reads. Table "Bus Operations Summary" page summarizes operations. select flash device operations, write specific commands into flash device CUI. Table "Command Codes Descriptions" page lists possible command codes descriptions. Table "Bus Cycle Definitions" page lists command definitions. Because commands partition-specific, must issue write commands within target address range.
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Table
Operation
Command Codes Descriptions (Sheet
Code Flash Device Command Description
Read Array Read Status Register Read Identifier
Places selected partition read-array mode. Places selected partition status register read mode. partition enters this mode after Program Erase command issued Places selected partition read identifier mode. Flash device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, protection register data D[15:0]. Places addressed partition read query mode. Flash device reads from partition addresses output information D[7:0]. block lock (SR[1]), (SR[3]), program (SR[4]), erase (SR[5]) status bits status register, cannot clear these bits. SR[5:3,1] cleared only flash device reset through Clear Status Register command. first cycle this preferred program command prepares program operation. second cycle latches address data, executes program algorithm this location. Status register updates occur when toggled. After programming, Read Array command read array data. Equivalent Program Setup command (40h). This program command activates mode. first write cycle sets command. second cycle Confirm command (D0h), subsequent writes provide program data. other commands ignored after mode begins. first command Setup (30h), latches address data, prepares flash device mode. This command prepares Block Erase. flash device erases block that Erase Confirm command addresses. next command Erase Confirm, sets status register bits SR[5:4] indicate command sequence error, places partition read status register mode. first command Erase Setup (20h), latches address data, erases block indicated erase confirm cycle address. During program erase, partition responds only Read Status Register, Program Suspend, Erase Suspend commands. toggle updates status register data. This command, issued flash device address, suspends currently executing program erase operation. Status register data indicates that operation successfully suspended SR[2] (program suspend) SR[6] (erase suspend) SR[7] set. remains suspended state regardless control signal states (except RST#). This command, issued flash device address, resumes suspended program erase operation.
Read
Read Query
Clear Status Register
Word Program Setup
Program
Alternate Setup
Setup
Confirm
Erase
Erase Setup
Erase Confirm
Suspend
Program Suspend Erase Suspend Suspend Resume
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Table
Operation
Command Codes Descriptions (Sheet
Code Flash Device Command Description
Lock Setup
This command prepares lock configuration. next command Lock Block, Unlock Block, Lock-Down, sets SR[5:4] indicate command sequence error. previous command Lock Setup (60h), locks addressed block. previous command Lock Setup (60h), latches address unlocks addressed block. previously locked-down, operation effect. previous command Lock Setup (60h), latches address locks-down addressed block. This command prepares protection register program operation. second cycle latches address data, starts protection register program lock algorithm. Toggling updates flash device status register data. read array data after programming, issue Read Array command. This command prepares flash device configuration. Configuration Register next command, sets SR[5:4] indicate command sequence error. previous command Configuration Setup (60h), latches address writes data from A[15:0] into configuration register. Subsequent read operations access array data.
Block Locking
Lock Block
Unlock Block
Lock-Down
Protection
Protection Program Setup
Configuration
Configuration Setup Configuration Register
Note:
unassigned commands. Intel reserves right redefine these codes future functions.
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Table
Operation
Cycle Definitions
Command Cycles First Cycle Oper Addr Data2,3 Second Cycle Oper Addr1 Data2,3
Read Array/Reset Read Identifier
Read
Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
40h/10h
Read Read Read Read
Read Address PBA+IA PBA+QA
Array Data
Read Query Read Status Register Clear Status Register Block Erase
Write Write Write
Program Erase
Word Program Program/Erase Suspend Program/Erase Resume Lock Block
Write Write Write Write Write Write
FFFDh
Lock
Unlock Block Lock-Down Block Protection Program
Protection
Lock Protection Program
Configuration
Configuration Register
Notes: First-cycle command addresses must same target address operation. Examples: -The first-cycle address Read Identifier command must same Identification code address (IA). -The first-cycle address Word Program command must same word address (WA) programmed. -The first-cycle address Erase/Program Suspend command must same address within block suspended. valid address within flash device. Identification code address. Block Address. address within specific block. Lock Protection Address obtained from (through Read Query command). flash memory device family 0080h. User programmable 4-word protection address. address within specific partition. Partition Base Address. first address particular partition. Query code address. Word address memory location written. Status register data. Data written location Identifier code data. User programmable 4-word protection data. Query code data D[7:0]. Configuration register code data presented flash device addresses A[15:0]. A[MAX:16] address bits select partition. Table "Read Configuration Register Definitions" page configuration register bits descriptions. commands other than those shown above. Other commands reserved Intel future flash device implementations.
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Command Sequencing
When issuing 2-cycle write sequence flash device, read operation occur between write cycles. setup phase 2-cycle write sequence places addressed partition into read-status mode, same partition read before second confirm write cycle issued, status register data returned. Reads from other partitions, however, return actual array data, addressed partition already read-array mode. Figure Figure illustrate these conditions.
Figure
Normal Write Read Cycles
Address Data
Partition
Partition
Partition
Block Erase Setup
Block Erase Conf
Read Array
Figure
Interleaving 2-Cycle Write Sequence with Array Read
Address Data
Partition
Partition
Partition
Partition
Read Array
Erase Setup
Array Data
Read
Erase Conf
contrast, write cycle must interrupt 2-cycle write sequence. Such interruption causes command sequence error appear status register. Figure illustrates command sequence error. Figure Improper Command Sequencing
Address Data [D/Q]
Partition
Partitio
Partition
Partition
Data
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10.0
10.1
Read Operations
Read Array
Read Array command places resets) partition read-array mode used read data from flash memory array. Upon initial flash device power-up, after reset (RST# transitions from VIH), partitions default asynchronous read-array mode. read array data from flash device: Write Read Array command (FFh) specify desired word address. Read from that address.
Note:
partition already read-array mode, need issue Read Array command read from that partition. Read Array command written partition that erasing programming, flash device presents invalid data until program erase operation completes. After program erase finishes that partition, valid array data then read. Erase Suspend Program Suspend command suspends WSM, subsequent Read Array command places addressed partition read-array mode. Read Array command functions independently VPP.
10.2
Read Device
read identifier mode outputs manufacturer/device identifier, block lock status, protection register codes, configuration register data. identifier information contained within separate memory space flash device, accessed along 4-Mbit partition address range supplied Read Identifier command (90h) address. Reads from addresses Table retrieve information. Issuing Read Identifier command partition that programming erasing places outputs that partition read mode while partition continues program erase background.
Table
Flash Device Identification Codes (Sheet
Address1 Item Base Offset Data Description
Manufacturer
Partition
0089h 8852h 8853h
Intel 32-Mbit 32-Mbit 64-Mbit 64-Mbit 128-Mbit 128-Mbit
Device
Partition
8854h 8855h 8856h 8857h
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Table
Flash Device Identification Codes (Sheet
Address1 Item Base Offset Data Description
Block Lock Status(2)
Block
Register Data Lock Data Register Data
Block unlocked Block locked Block locked-down Block locked down
Block Lock-Down Status(2) Configuration Register Protection Register Lock Status Protection Register
Block Partition Partition Partition
Multiple reads required read entire 128-bit Protection Register.
Notes: address constructed from base address plus offset. example, read Block Lock Status block number BPD, address (0F8000h) plus offset (02h), which this example 0F8002h. Then examine data determine whether block locked. Section 13.1.4, "Block Lock Status" page valid lock status.
10.3
Read Query (CFI)
flash memory device contains separate query database that acts on-chip datasheet. access information within flash memory device, issue Read Query command supply specific address. address constructed from base address partition plus particular offset corresponding desired field. Appendix "Common Flash Interface" page shows accessible fields their address offsets. Issuing Read Query command partition that programming erasing puts that partition read query mode while partition continues program erase background.
10.4
Read Status Register
flash device status register displays program erase operation status. status partition read after writing Read Status Register command location within address range that partition. Read-status mode default read mode following Program, Erase, Lock Block command sequence. Subsequent single reads from that partition return partition status until another valid command written. read-status mode supports single synchronous single asynchronous reads only; does support burst reads. first falling edge latches updates Status Register data. operation does affect modes other partitions. Because Status Register bits wide, only [7:0] contain valid status register data; [15:8] contain zeros. Table "Status Register Definitions" page Table "Status Register Descriptions" page
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Each 4-Mbit partition contains status register. Bits SR[6:0] unique each partition, SR[7], Device Status (DWS) bit, pertains entire flash memory device. SR[7] provides program erase status entire flash device. contrast, Partition Status (PWS) bit, SR[0], provides program erase status addressed partition only. Status register bits SR[6:1] present information about partition-specific program, erase, suspend, block-lock states. Table "Status Register Device Partition Write Status Description" page describes (SR[7]) (SR[0]) combinations. Table
Status Register Definitions
VPPS
Table
Status Register Descriptions
Name State Description
Device Status
Device Busy Device Ready
SR[7] indicates erase program completion flash device. SR[6:1] invalid while SR[7] Table valid SR[7] SR[0] combinations. After issuing Erase Suspend command, halts sets SR[7] SR[6]. SR[6] remains until flash device receives Erase Resume command. SR[5] attempted erase failed. Command Sequence Error indicated when SR[7,5:4] set. SR[4] failed program word. indicates level after program erase completes. SR[3] does provide continuous feedback guaranteed when VPPVPPL/VPPH After receiving Program Suspend command, halts execution sets SR[7] SR[2]. These bits remain until Resume command received. erase program operation attempted locked block VIL), sets SR[1] aborts operation. addressed partition erasing programming. mode, SR[0] indicates that data-stream word finished programming verifying, depending particular phase. Table valid SR[7] SR[0] combinations.
Erase Suspend Status
Erase progress/completed Erase suspended Erase successful Erase error Program successful Program error detect, operation aborted Program progress/completed Program suspended Unlocked Aborted erase/program attempt locked block This partition busy, only SR[7]=0 Another partition busy, only SR[7]=0
Erase Status
Program Status VPPS
Status
Program Suspend Status
Device Protect Status
Partition Write Status
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Table
(SR[7])
Status Register Device Partition Write Status Description
(SR[0]) Description
addressed partition performing program/erase operation. EFP: flash device finished programming verifying data, ready data. partition other than currently addressed performing program/erase operation. EFP: flash device either programming verifying data. program/erase operation progress partition. Erase Program suspend bits (SR[6,2]) indicate whether other partitions suspended. EFP: flash device exited mode. Does occur standard program erase modes. EFP: this combination does occur.
10.5
Clear Status Register
Clear Status Register command clears status register leaves partition output states unchanged. status register bits clear bits SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they cleared only Clear Status Register command. allowing system software reset these bits, several operations (such cumulatively programming several addresses erasing multiple blocks sequence) performed before reading status register determine whether error occurred. error detected, Status Register must cleared before beginning another command sequence. Flash device reset (RST# also clears status register. This command functions independently VPP.
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11.0
11.1
Program Operations
Word Program
When Word Program command issued, executes sequence internally timed events program word desired address, verify that bits sufficiently programmed. Programming flash memory array changes specifically addressed bits bits change memory cell contents. Programming occur only partition time. other partitions must either read mode erase suspend mode. Only partition erase suspend mode time. examine status register examined program progress, read address within partition that busy programming. However, while most status register bits partition-specific, Device Status bit, SR[7], device-specific. That status register read from other partition, SR[7] indicates program status entire flash memory device. This status permits system monitor program progress while reading status other partitions. toggle (during polling) updates status register. Several commands issued partition that programming: Read Status Register, Program Suspend, Read Identifier, Read Query. Read Array command also issued, read data indeterminate. After programming completes, three status register bits signify various possible error conditions:
SR[4] indicates program failure set. SR[3] set, could execute Word Program command, because
outside acceptable limits.
SR[1] set, program aborted, because attempted program locked
block. After status register data examined, clear using Clear Status Register command before issuing command. partition remains status register mode until another command written that partition. command issued after status register indicates program completion. deasserted while flash device programming, flash devices enter standby mode until program operation completes.
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Figure
Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Command Operation Write Program Setup Data Comments Data Addr Location program (WA) Data Data program (WD) Addr Location program (WA) Read Toggle update Check SR[7] ready busy
Write 40h, Word Address Write Data Word Address
Write
Read Read Status Register
Suspend Program Loop Suspend Program
Standby
SR[7]
Repeat subsequent programming operations. Full status register check done after each program after sequence program operations.
Full Program Status Check desired) Program Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status Register Command Operation Standby SR[3]
Comments Check SR[3] error Check SR[4] Data program error Check SR[1] Attempted program locked block Program aborted
Range Error Standby Program Error
SR[4]
Standby
SR[1]
Device Protect Error
SR[3] MUST cleared before will allow further program attempts Only Clear Staus Register command clears SR[4:3,1]. error detected, clear status register before attempting program retry other error recovery.
Program Successful
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11.2
Factory Programming
standard factory programming mode uses same commands algorithm Word Program mode (40h/10h). When VPPL, program erase currents drawn through VCC. driven logic signal, must remain above VPPLMin value perform in-system flash memory modifications. When connected power supply, flash device draws program erase current directly from VPP, which eliminates need external switching transistor control voltage. Figure "Examples Power Supply Configurations" page shows examples flash device power supply usage various configurations. 12-V mode enhances programming performance during short time period typically found manufacturing processes. However, this mode intended extended use.12 applied during program erase operations specified Section 5.2, "Operating Conditions" page connected total tPPH hours maximum. Stressing flash device beyond these limits might cause permanent damage.
11.3
Enhanced Factory Program (EFP)
substantially improves flash device programming performance through number enhancements conventional 12-Volt word program algorithm. more efficient algorithm eliminates traditional overhead delays conventional word program mode both host programming system flash device. Changes conventional word programming flowchart internal routine were developed because today's beat-ratesensitive manufacturing environments; balance between programming speed cycling performance attained. host programmer writes data flash device checks Status Register determine when data completed programming. This modification cuts write cycles approximately half.
Following each internal program pulse, increments flash device address
next physical location.
Programming equipment then sequentially stream program data throughout entire block
without having setup present each address. combination, these enhancements reduce much host programmer overhead, enabling more data streaming approach flash device programming. further speeds programming performing internal code verification. With this feature, PROM programmers rely flash device verify that been programmed properly. From flash device side, streamlines internal overhead eliminating delays previously associated with switching voltages between programming verify levels each memory-word location. consists four phases: setup, program, verify, exit. Refer Figure "Enhanced Factory Program Flowchart" page detailed graphical representation implement EFP.
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11.3.1
Table
Requirements Considerations
Requirements Considerations
Requirements Considerations
Ambient temperature: within specified operating range within specified VPPH range Target block unlocked
Block cycling below erase cycles supported2 programs block time cannot suspended
Recommended optimum performance. Some degradation performance might occur this limit exceeded, internal algorithm will continue work properly. Code data cannot read from another partition during EFP.
11.3.2
Setup
After receiving Setup (30h) Confirm (D0h) command sequence, SR[7] transitions from indicating that busy with algorithm startup. delay before checking SR[7] required allow time perform setups checks (VPP level block lock status). error detected, status register bits SR[4], SR[3], and/or SR[1] set, operation terminates.
Note:
After Setup Confirm command sequence, reads from flash device automatically output status register data. issue Read Status Register command, because this command interpreted data program WA0.
11.3.3
Program
After setup completion, host programming system must check SR[0] determine data-stream ready status (SR[0]=0). Each subsequent write after this check program-data write flash memory array. Each cell within memory word programmed receives pulse; additional pulses, required, occur verify phase. SR[0]=1 indicates that busy applying program pulse. host programmer must poll flash device status register program done state after each data-stream write. SR[0]=0 indicates that appropriate cell(s) within accessed memory location have received their single program pulse, that flash device ready next word. Although host check full status errors time, this check necessary only block basis, after exit. Addresses must remain within target block. Supplying address outside target block immediately terminates program phase; then enters verify phase.
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address either remain constant increment. flash device compares incoming address address stored from setup phase (WA0).
addresses match, programs data word next sequential memory
location.
addresses differ, jumps address location.
program phase concludes when host programming system writes different block address. data supplied must FFFFh. Upon program phase completion, flash device enters verify phase.
11.3.4
Verify
high percentage flash memory bits program first pulse. However, internal verification identifies cells that completely program their first attempt, applies additional pulses required. verify phase identical flow program phase, except that instead programming incoming data, compares verify-stream data data that previously programmed into block.
data compares correctly, host programmer proceeds next word. data does match, host waits while applies more additional
pulses. host programmer must reset initial verify-word address same starting location supplied during program phase. then reissues each data word same order during program phase. Like programming, host write each subsequent data word increment through block addresses. verification phase concludes when interfacing programmer writes different block address. data supplied must FFFFh. Upon completion verify phase, flash device enters exit phase.
11.3.5
Exit
SR[7]=1 indicates that flash device returned normal operating conditions. Perform full status check this time, verify that entire block programmed successfully. After exit, valid command issued.
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Figure
Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE Setup
Start
Program
Read Status Register
Verify
Read Status Register
Exit
Read Status Register
Unlock Block
SR[0]=1=N
Data Stream Ready? SR[0] =0=Y Write Data Address
SR[0]=1=N
Verify Stream Ready? SR[0] =0=Y Write Data Address
SR[7]=0=N
Exited? SR[7]=1=Y Full Status Check Procedure
Write Address
Write Address SR[0]=1=N
setup time
SR[7]=0=Y
Read Status Register
Program Done? SR[0]=0=Y
SR[0]=1=N
Read Status Register
Read Status Register
Operation Complete
Verify Done? SR[0]=0=Y
Setup Done? SR[7]=1=N Check Lock errors (SR[3,1])
Last Data? Write FFFFh Address
Last Data? Write FFFFh Address
Exit
Setup
State Write Write Write Standby Read Standby Setup Done? Unlock Block Setup Comments Unlock block Data Address State Read Standby Write (note Read Standby
Program
Comments Status Register Data Stream Ready? Check SR[0] Ready data ready data Data Data program Address Status Register Check SR[0] Program Program done Done? Program done Last Data? Device automatically increments address. State Read Standby Write (note Read Standby (note Standby
Verify
Comments Status Register Verify Stream Ready? Check SR[0] Ready verify ready verify Data Word verify Address Status Register Verify Done? Last Data? Exit Verify Phase Check SR[0] Verify done Verify done Device automatically increments address. Data FFFFh Address within same Status Register Exited? Check SR[7] Exit finished Exit completed
Data Confirm Address setup time Status Register Check SR[7] ready ready
Standby
SR[7] Error Check SR[3,1] Standby Condition SR[3] error Check SR[1] locked block
Write
Exit Data FFFFh Program Address within same Phase
Write
Exit
first Word Address programmed within target block. (Block Base Address) must remain constant throughout program phase data stream; held constant first address location, written sequence through addresses within block. Writing equal that block currently being written terminates program phase, instructs device enter verify phase. proper verification occur verify data stream must presented device same sequence that program phase data stream. Writing equal terminates verify phase, instructs device exit Bits that fully program with single pulse program phase receive additional program-pulse attempts during verify phase. device will report program failure setting SR[4]=1; this check performed during full status check after been exited that block, will indicate error within entire data stream. Read Standby
Repeat subsequent operations. After exit, Full Status Check determine program error occurred. Full Status Check procedure Word Program flowchart.
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12.0
12.1
Program Erase Operations
Program/Erase Suspend Resume
Program Suspend Erase Suspend commands halt in-progress program erase operation. command issued flash device address. partition corresponding address command remains previous state. suspend command allows data accessed from memory locations other than location being programmed block being erased.
program operation suspended only perform read operation. erase operation suspended perform either program read operation within
block, except block that erase suspended.
program command nested within suspended erase subsequently suspended read
another location. Once program erase process starts, Suspend command requests that suspends program erase sequence predetermined points algorithm. partition that actually suspended continues output status register data after Suspend command written. operation suspended when status bits SR[7] SR[6] and/or SR[2] set. read data from blocks within partition (other than erase-suspended block), write Read Array command. Block erase cannot resume until program operations initiated during erase suspend complete.
Read Array, Read Status Register, Read Identifier (ID), Read Query, Program Resume
valid commands during Program Erase Suspend.
Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block,
Unlock Block, Lock-Down Block valid commands during erase suspend. read data from block partition that programming erasing, operation does need suspended.
other partition already read array, Query mode, issuing valid address returns
corresponding data.
other partition read mode, read commands must issued
partition before data read. During suspend, places flash device standby state, which reduces active current. must remain program level must remain unchanged while suspend mode. resume command instructs continue programming erasing, clears status register bits SR[2] SR[6]) SR[7]. Resume command written partition. When read partition that programming erasing, flash device outputs data corresponding last mode that partition. status register error bits set, status register cleared before issuing next instruction. RST# must remain VIH. Figure "Program Suspend Resume Flowchart" page Figure "Erase Suspend Resume Flowchart" page
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suspended partition placed Read Array, Read Status Register, Read Identifier (ID), Read Query during suspend, flash device remains that mode, outputs data corresponding that mode after program erase operation resumes. After resuming suspended operation, issue read command appropriate read operation. read status after resuming suspended operation, issue Read Status Register command (70h) return suspended partition status mode. Figure Program Suspend Resume Flowchart
PROGRAM SUSPEND RESUME PROCEDURE
Start Command Operation Write Comments
Write Address Write Same Partition Read Status Register
Data Program Addr address within programming Suspend partition Read Status Data Addr address same partition Read Toggle update Addr address same partition Check SR[7] ready busy Check SR[2] Program suspended Program completed Read Array Data Addr device address (except word being programmed) Read array data from block other than being programmed Program Resume Data Addr device address
Write
Read
SR[7]
Standby
SR[2]
Program Completed
Standby
Write
Write Susp Partition Read Read Array Data
Write
Done Reading
suspended partition placed Read Array mode: Write Write Pgm'd Partition Read Array Data Read Status Return partition status mode: Data Addr address within same partition
Write Address Program Resumed Write Same Partition
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Figure
Erase Suspend Resume Flowchart
ERASE SUSPEND RESUME PROCEDURE
Start Command Operation Write Comments
Write Address Write Same Partition
Erase Data Suspend Addr address Read Status Data Addr address same partition Read Toggle update Addr address same partition Check SR[7] ready busy Check SR[6] Erase suspended Erase completed Data Read Array Addr device address (except Program block being erased) Read array program data from/to block other than being erased Erase Data Resume Addr address suspended partition placed Read Array mode Program Loop:
Write
Read Read Status Register Standby SR[7]
Standby Erase Completed Write Read Write Write
SR[6]
Read
Read Program?
Program
Read Array Data
Program Loop
Done?
Write Address
Write Erased Partition Read Array Data
Write
Read Status
Return partition status mode: Data Addr Address within same partition
Erase Resumed
Write Same Partition
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12.2
Block Erase
2-cycle block erase command sequence, consisting Erase Setup (20h) Erase Confirm (D0h), initiates block erase addressed block. Only partition erase mode time; other partitions must read mode. Erase Confirm command internally latches address block erase. Erase forces bits within block SR[7] cleared while erase executes. After writing Erase Confirm command, selected partition placed read status register mode. Reads performed that partition return current status data. address given during Erase Confirm command does need same address used Erase Setup command. example, Erase Confirm command given partition then selected block partition erased, even Erase Setup command partition 2-cycle erase sequence cannot interrupted with write operation. example, execute properly, Erase Setup command must immediately followed Erase Confirm command. different command issued between setup confirm commands, following occurs:
partition placed read-status mode. status register signals command sequence error. subsequent erase commands that partition ignored until status register cleared.
detect block erase completion, analyzes SR[7] that partition. error (SR[5,3,1]) flagged, status register cleared issuing Clear Status Register command before attempting next operation. partition remains read-status mode until another command written CUI. instruction follow after erasing completes. read-array mode prevent inadvertent status register reads.
June 2005
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
Figure
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Command Comments Operation Block Data Write Erase Addr Block erased (BA) Setup Write Write Block Address Read Read Status Register
Write Block Address
Erase Confirm
Data Addr Block erased (BA) Read Toggle update Check SR[7] ready busy
Suspend Erase Loop Suspend Erase
Standby
SR[7]
Repeat subsequent block erasures. Full status register check done after each block erase after sequence block erasures.
Full Erase Status Check desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register Range Error Standby
Command Operation Standby Check SR[3] error
Comments
SR[3]
Check SR[5:4] Both Command sequence error Check SR[5] Block erase error
SR[5:4]
Command Sequence Error Block Erase Error Erase Locked Block Aborted
Standby
SR[5]
SR[1]
Check SR[1] Attempted erase locked block Erase aborted SR[3,1] must cleared before will allow further erase attempts. Standby Only Clear Status Register command clears SR[5:3,1]. error detected, clear Status register before attempting erase retry other error recovery.
Block Erase Successful
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
June 2005
28F640W30, 28F320W30, 28F128W30
12.3
Read-While-Write Read-While-Erase
Intel® Wireless Flash Memory (W30) supports flexible multi-partition dual-operation architecture. dividing flash memory into many separate partitions, flash device read from partition while programing (Read-While-Write) erasing (Read-While-Eras) another partition. Both these features greatly enhance data storage performance. flash memory device does support simultaneous program erase operations. Attempting perform operations such these results command sequence error. Only partition programming erasing while another partition reading. However, partition erase suspend mode while second partition performing program operation, another partition executing read command. Table "Command Codes Descriptions" page describes command codes available functions.
June 2005
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
13.0
Security Modes
flash memory device offers both hardware software security features protect flash memory data.
software security feature, execute Lock Block command. hardware security feature, execute Lock-Down Block command assert
signal. Refer Figure "Block Locking State Diagram" page state diagram flash device security features. Also Figure "Locking Operations Flowchart" page
13.1
Block Lock Operations
Individual instant block locking protects code data allowing block locked unlocked with latency. This locking scheme offers levels protection:
Software-only control block locking (useful frequently changed data blocks). Hardware interaction before locking changed (protects infrequently changed code
blocks). following sections discuss locking system operation. term state [abc] specifies locking states, such state [001]. this syntax:
value. block lock-down status Block Lock status register
Figure "Block Locking State Diagram" page defines possible locking states. following summarizes locking functionality.
blocks power-up locked state. Unlock commands unlock these blocks, lock commands lock them again. Lock-Down command locks block prevents from being unlocked when
asserted. Locked-down blocks unlocked locked with commands long deasserted. When asserted, previously locked-down blocks return lock-down. lock-down status clears only when flash device reset powered-down. Block lock registers affected level. These registers modified read even PPLK. locking status each block locked, unlocked, lock-down, described following sections. Figure "Locking Operations Flowchart" page
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
June 2005
28F640W30, 28F320W30, 28F128W30
Figure
Block Locking State Diagram
Power-Up/Reset
Locked [X01]
Locked Down [011]
Hardware Locked [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control Notes: [a,b,c] represents [WP#, D0]. Don't Care. indicates block Lock -down status. Lock -down been issued this block Lock -down been issued this block indicates block lock status. block unlocked. block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked -Down states. B5070
13.1.1
Lock
blocks default locked (state [x01]) after initial power-up reset. Locked blocks fully protected from alteration. Attempted program erase operations locked block return error SR[1].
lock unlocked blocks, Lock Block command sequence. change status locked block unlocked lock-down, appropriate software
commands.
13.1.2
Unlock
Unlocked blocks (states [x00] [110]) programmed erased. unlocked blocks return locked state when flash device reset powered-down.
change status unlocked block locked locked-down state,
appropriate software commands.
unlock locked block, write Unlock Block command sequence block
locked-down.
June 2005
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
28F640W30, 28F320W30, 28F128W30
13.1.3
Lock-Down
Locked-down blocks (state [011]) offer additional level write protection beyond protection regular locked block. block locked-down, software cannot change state block asserted.
lock-down locked unlocked block, write Lock-Down Block command sequence. block locked-down, then later changed unlocked, issue Lock-down
command before asserting WP#, that block back locked-down state.
When deasserted, locked-down blocks change locked state, then
unlocked using Unlock Block command.
13.1.4
Block Lock Status
lock status every block read read identifier mode.
Note:
enter this mode, issue Read Identifier command flash device. Subsequent reads output lock status that block. example, read block lock status block address sent flash device must 50002h (for top-parameter device). lowest data bits read data, DQ0, represent lock status.
indicates block lock status. This using Lock Block command cleared
using Block Unlock command. also when entering lock-down state.
indicates lock-down status using Lock-Down command.
lock-down status cannot cleared software-only flash device reset power-down. Table Table Write Protection Truth Table
RST# Write Protection
Device inaccessible Word program block erase prohibited lock-down blocks locked lock-down blocks unlocked
Intel® Wireless Flash Memory (W30) Order Number: 290702, Revision:
June 2005
28F640W30, 28F320W30, 28F128W30
13.1.5
Lock During Erase Suspend
Block lock configurations performed during erase suspend operation, using standard locking command sequences unlock, lock, lock-down block. This feature useful when another block requires immediate updating. change block locking during erase operation: Write Erase Suspend command. Check SR[6] determine that erase operation suspended. Write desired lock command sequence block. lock status changes. After completing lock, unlock, read, program operations, resume erase operation with Erase Resume command (D0h). block locked locked-down during suspended erase same block, locking status bits change immediately. When erase operation resumes, completes normally. Locking operations cannot occur during program suspend. Appendix "Write State Machine" page shows valid commands during erase suspend.
13.1.6
Status Register Error Checking
Using nested locking program command sequences during erase suspend introduce ambiguity into status re
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