28F640L30, 28F128L30, 28F256L30 High performance Read-While-Write
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Intel StrataFlash® Wireless Memory (L30)
28F640L30, 28F128L30, 28F256L30
High performance Read-While-Write/Erase initial access with zero wait state, clock-todata output synchronous-burst mode asynchronous-page mode 16-, continuous-word burst mode Burst suspend Programmable WAIT configuration Buffered Enhanced Factory Programming (BEFP) µs/byte (Typ) low-power buffered programming µs/byte (Typ) Architecture Asymmetrically-blocked architecture Multiple 8-Mbit partitions: 64-Mbit 128Mbit devices Multiple 16-Mbit partitions: 256-Mbit devices Four 16-Kword parameter blocks: bottom configurations 64-Kword main blocks Dual-operation: Read-While-Write (RWW) Read-While-Erase (RWE) Status register partition device status Power (core) VCCQ (I/O) Standby current: (Typ) 256-Mbit 4-Word synchronous read current: (Typ) Automatic Power Savings mode
Security space: unique factory device identifier bits user-programmable bits Additional 2048 user-programmable bits Absolute write protection: Power-transition erase/program lockout Individual zero-latency block locking Individual block lock-down Software (Typ) program suspend (Typ) erase suspend Intel® Flash Data Integrator (FDI) optimized Basic Command (BCS) Extended Command (ECS) compatible Common Flash Interface (CFI) capable Quality Reliability Expanded temperature: -25° +85° Minimum 100,000 erase cycles block ETOXVIII process technology (0.13 Density Packaging 64-, 128-, 256-Mbit density packages 128/0 256/0 Density Stacked-CSP 16-bit wide data
Intel StrataFlash® wireless memory (L30) product latest generation Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. provides high performance synchronous-burst read mode asynchronous read mode using lowvoltage, multi-level cell (MLC) technology. multiple-partition architecture enables background programming erasing occur partition while code execution data reads take place another partition. This dual-operation architecture also allows system interleave code operations while program erase operations take place background. device manufactured using Intel® 0.13 ETOXVIII process technology. available industry-standard chip scale packaging.
Order Number: 251903, Revision: April 2005
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April 2005
Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
Intel StrataFlash® Wireless Memory (L30)
Contents
Introduction
Nomenclature Acronyms Conventions
Functional Overview Package Information
Packages SCSP Packages Signal Ballout 4.1.1 Package Ballout 4.1.2 SCSP Package Ballout.16 Signal Descriptions.17 4.2.1 Package Signal Descriptions.17 4.2.2 128/0 256/0 SCSP Package Signal Descriptions Memory Absolute Maximum Ratings.23 Operating Conditions.23 Current Characteristics Voltage Characteristics Test Conditions Capacitance Read Specifications 64-Mbit 128-Mbit Densities.28 Read Specifications 256-Mbit Density Write Specifications Program Erase Characteristics Power Down Reset Specifications Power Supply Decoupling Automatic Power Saving Operations. 9.1.1 Reads 9.1.2 Writes 9.1.3 Output Disable.43 9.1.4 Standby
Ballout Signal Descriptions
Maximum Ratings Operating Conditions
Electrical Specifications
Characteristics
Power Reset Specifications
Device Operations
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Intel StrataFlash® Wireless Memory (L30)
9.1.5 Reset Device Commands Command Definitions Asynchronous Page-Mode Read Synchronous Burst-Mode Read 10.2.1 Burst Suspend. Read Configuration Register (RCR). 10.3.1 Read Mode. 10.3.2 Latency Count 10.3.3 WAIT Polarity 10.3.3.1WAIT Signal Function. 10.3.4 Data Hold 10.3.5 WAIT Delay 10.3.6 Burst Sequence. 10.3.7 Clock Edge 10.3.8 Burst Wrap 10.3.9 Burst Length Word Programming 11.1.1 Factory Word Programming Buffered Programming Buffered Enhanced Factory Programming 11.3.1 Buffered Requirements Considerations 11.3.2 Buffered Setup Phase 11.3.3 Buffered Program/Verify Phase. 11.3.4 Buffered Exit Phase. Program Suspend Program Resume Program Protection Block Erase Erase Suspend. Erase Resume. Erase Protection. Block Locking 13.1.1 Lock Block 13.1.2 Unlock Block. 13.1.3 Lock-Down Block. 13.1.4 Block Lock Status. 13.1.5 Block Locking During Suspend Protection Registers 13.2.1 Reading Protection Registers. 13.2.2 Programming Protection Registers 13.2.3 Locking Protection Registers.
10.0
Read Operations
10.1 10.2 10.3
11.0
Programming Operations
11.1 11.2 11.3
11.4 11.5 11.6
12.0
Erase Operations.
12.1 12.2 12.3 12.4
13.0
Security Modes
13.1
13.2
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14.0
Dual-Operation Considerations.68
14.1 14.2 Memory Partitioning Read-While-Write Command Sequences 14.2.1 Simultaneous Operation Details 14.2.2 Synchronous Asynchronous Characteristics Waveforms 14.2.2.1Write operation asynchronous read transition 14.2.2.2Write synchronous read operation transition 14.2.2.3Write Operation with Clock Active 14.2.3 Read Operation During Buffered Programming Flowchart.70 Simultaneous Operation Restrictions Read Status Register 15.1.1 Clear Status Register Read Device Identifier Query
14.3
15.0
Special Read States
15.1 15.2 15.3
Appendix Appendix Appendix Appendix Appendix
Write State Machine (WSM) Flowcharts Common Flash Interface Additional Information .100 Ordering Information.101
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Intel StrataFlash® Wireless Memory (L30)
Revision History
Revision Date 10/14/02 02/08/03 Revision -001 -002 Initial Release Revised 256-Mbit Partition Size Revised 256-Mbit Memory Changed WAIT function de-assert during Asynchronous Operations (Asynchronous Reads Writes) Changed WAIT function active during Synchronous Non-Array Read Updated Waveforms reflect WAIT function Revised Section 8.2.2 Added Synchronous Read Write transition Section Added specs: R15, R16, R17, R111, R311, R312, W21, Various text edits Improved 85ns from 90ns Improved Frequency 52MHz from 50MHz Added SCSP 128/0 256/0 Ball-out Mechanical Drawing Changed ICCS ICCR values Added 256-Mbit Speed Changed Program Erase Spec Combined Buffered Programming Flow Chart Read While Buffered programming Flow Chart Revised Read While Buffered Programming Flow Chart Revised Appendix Write State Machine Revised Table Identification Various text edits EMTS format Added Table "Bus Operations Summary" page following part number line items were added Table "L30 SCSP Package Order Numbers" page 102: RD48F2000L0ZTQ0, RD48F2000L0ZBQ0 PF48F3000L0ZTQ0, PF48F3000L0ZBQ0 RD48F4000L0ZTQ0, RD48F4000L0ZBQ0 PF48F4000L0ZTQ0, PF48F4000L0ZBQ0 Removed Frequency Support Tables Renamed 256-Mbit UT-SCSP 256-Mbit SCSP Expanded Operating Conditions VPPL Updated Ordering Info Minor text edits Converted datasheet template Table "Bottom Parameter Memory Map" page corrected 256-Mbit address range from 100000 10FFFF 800000 80FFFF Section E.2, "Ordering Information SCSP" page 102, corrected package designators leaded lead-free packages from RD/PF NZ/JZ Description
04/11/03
-003
08/04/03
-004
12/12/03 9/02/04
-005 -007
04/22/05
-008
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Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
Intel StrataFlash® Wireless Memory (L30)
Introduction
This document provides information about Intel StrataFlash® wireless memory (L30) device describes Intel StrataFlash® Wireless Memory (L30) features, operation, specifications.
Nomenclature
voltage range (except where noted) Range: VCCQ voltage range voltage range Block: group bits, bytes words within flash memory array that erase simultaneously when Erase command issued device. Intel StrataFlash® Wireless Memory (L30) block sizes: 16-Kword, 64-Kword. Main block: array block that usually used store code and/or data. Main blocks larger than parameter blocks. Parameter block: array block that usually used store frequently changing data small system parameters that traditionally would stored EEPROM. parameter device: Previously referred top-boot device, device with parameter partition located highest physical address memory map. Parameter blocks within parameter partition located highest physical address parameter partition. Bottom parameter device: Previously referred bottom-boot device, device with parameter partition located lowest physical address memory map. Parameter blocks within parameter partition located lowest physical address parameter partition. Partition: group blocks that share common program/erase circuitry. Blocks within partition also share common status register. block within partition being programmed erased, only status register data (rather than array data) available when address within that partition read. Main partition: partition containing only main blocks. Parameter partition: partition containing parameter blocks main blocks.
Acronyms
CUI: Command User Interface MLC: Multi-Level Cell OTP: One-Time Programmable PLR: Protection Lock Register Protection Register RCR: Read Configuration Register RFU: Reserved Future Status Register WSM: Write State Machine
Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
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Intel StrataFlash® Wireless Memory (L30)
Conventions
VCC: signal voltage connection VCC: signal voltage level hexadecimal number prefix binary number prefix SR[4]: Denotes individual register bit. A[15:0]: Denotes group similarly named signals, such address data bus. Denotes element signal group membership, such address. bit: binary unit byte: eight bits word: bytes, sixteen bits Kbit: 1024 bits KByte: 1024 bytes Kword: 1024 words Mbit: 1,048,576 bits MByte: 1,048,576 bytes MWord: 1,048,576 words
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Intel StrataFlash® Wireless Memory (L30)
Functional Overview
This section provides overview features capabilities device. device provides read-while-write read-while-erase capability with density upgrades through 256-Mbit. This family devices provides high performance voltage 16-bit data bus. Individually erasable memory blocks sized optimum code data storage. Each device density contains parameter partition several main partitions. flash memory array grouped into multiple 8-Mbit 16-Mbit partitions. dividing flash memory into partitions, program erase operations take place same time read operations. Although each partition write, erase burst read capabilities, simultaneous operation limited write erase partition while other partitions read mode. Intel StrataFlash® Wireless Memory (L30) allows burst reads that cross partition boundaries. User application code responsible ensuring that burst reads don't cross into partition that programming erasing. Upon initial power return from reset, device defaults asynchronous page-mode read. Configuring Read Configuration Register enables synchronous burst-mode reads. synchronous burst mode, output data synchronized with user-supplied clock signal. WAIT signal provides easy CPU-to-flash memory synchronization. addition enhanced architecture interface, device incorporates technology that enables fast factory program erase operations. Designed low-voltage systems, Intel StrataFlash® Wireless Memory (L30) supports read operations with erase program operations with Buffered Enhanced Factory Programming (Buffered EFP) provides fastest flash array programming performance with Volt, which increases factory throughput. With tied together simple, ultra power design. addition voltage flexibility, dedicated connection provides complete data protection when less than VPPLK. Command User Interface (CUI) interface between system processor internal operations device. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase program. Status Register indicates erase program completion errors that have occurred. industry-standard command sequence invokes program erase automation. Each erase operation erases block. Erase Suspend feature allows system software pause erase cycle read program data another block. Program Suspend allows system software pause programming read other locations. Data programmed word increments. Intel StrataFlash® Wireless Memory (L30) offers power savings through Automatic Power Savings (APS) mode standby mode. device automatically enters following read-cycle completion. Standby initiated when system deselects device deasserting asserting RST#. Combined, these features significantly reduce power consumption. Intel StrataFlash® Wireless Memory (L30)'s protection register allows unique flash device identification that used increase system security. Also, individual Block Lock feature provides zero-latency block locking unlocking.
Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
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Intel StrataFlash® Wireless Memory (L30)
Figure
Index Mark
Package Information
Packages
128-Mbit, 56-Ball Package Drawing Dimensions
Index Mark
View Ball Side Down
Bottom View Ball Side
Seating Plane
Note: Drawing scale
Side View
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length (64Mb, 128Mb) Package Body Width (64Mb, 128Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along
Symbol
0.150 0.325 7.600 8.900
Millimeters 1.000 0.665 0.375 7.700 9.000 0.750 1.225 2.250
Notes
0.0059
Inches
0.0394
0.425 7.800 9.100
0.0128 0.2992 0.3504
0.0262 0.0148 0.3031 0.3543 0.0295 0.0482 0.0886
0.0167 0.3071 0.3583
1.125 2.150
0.100 1.325 2.350
0.0443 0.0846
0.0039 0.0522 0.0925
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Figure
Index Mark
256-Mbit, 79-Ball Package Drawing Dimensions
Index Mark
View Ball Side Down
Bottom View Ball Side
Seating Plane
Side View
Dimensions Table
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length (256Mb) Package Body Width (256Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along Symbol 0.150 0.325 10.900 8.900 0.665 0.375 11.000 9.000 0.750 1.000 2.250 0.425 11.100 9.100 Millimeters Notes 1.000
Drawing scale
0.0059 0.0128 0.4291 0.3504
Inches
0.0394
0.0262 0.0148 0.4331 0.3543 0.0295 0.0394 0.0886
0.0167 0.4370 0.3583
0.900 2.150
0.100 1.100 2.350
0.0354 0.0846
0.0039 0.0433 0.0925
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Intel StrataFlash® Wireless Memory (L30)
Figure
SCSP Packages
128-Mbit, 88-ball (80-active ball) SCSP Drawing Dimensions (8x10x1.2
8x10x1.2Q
Index Mark
View Ball Down
Bottom View Ball
Drawing scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along
Symbol
0.200 0.325 9.900 7.900
illimeters 1.200 0.860 0.375 10.000 8.000 0.800 1.200 0.600
Notes
0.0079
Inches
0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
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Figure
256-Mbit, 88-ball (80-active ball) SCSP Drawing Dimensions (8x11x1.0
Index Mark
View Ball Down
Bottom View Ball
Drawing scale.
Note: Dimensions preliminary
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along Corner Ball Distance Along Symbol 0.117 0.300 10.900 7.900 0.740 0.350 11.00 8.00 0.80 1.200 1.100 0.400 11.100 8.100 Millimeters 1.00 Notes 0.0046 0.0118 0.4291 0.3110 0.0291 0.0138 0.4331 0.3150 0.0315 0.0472 0.0433 0.0157 0.4370 0.3189 Inches 0.0394
1.100 1.000
0.100 1.300 1.200
0.0433 0.0394
0.0039 0.0512 0.0472
Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
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Intel StrataFlash® Wireless Memory (L30)
Ballout Signal Descriptions
Signal Ballout
This section includes signal ballouts following packages:
Package Ballout SCSP Package Ballout 4.1.1 Package Ballout
Intel StrataFlash® Wireless Memory (L30) available package with 0.75 ball-pitch. Figure shows ballout 64-Mbit 128-Mbit devices 56-ball package with active-ball matrix. Figure shows device ballout 256-Mbit device 63-ball package with active-ball matrix. Both package densities ideal space-constrained board applications Figure Active-Ball Matrix 64-, 128-Mbit Densities Packages
VCCQ
RST#
RST#
ADV#
ADV#
WAIT
WAIT
VCCQ
VSSQ
VCCQ
VSSQ
VSSQ
VCCQ
VSSQ
VFBGA View Ball Side Down
VFBGA Bottom View Ball Side
Note:
lower-density devices, upper-address balls treated (e.g., 64-Mbit density, will
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Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
Intel StrataFlash® Wireless Memory (L30)
Figure
Active-Ball Matrix 256-Mbit Density Package
VCCQ VSSQ VCCQ View VSSQ VSSQ VCCQ VSSQ VCCQ WAIT WAIT ADV# ADV# RST# RST#
Ball Side Down-
Bottom View
Ball Side
Note:
lower density devices upper address balls treated RFUs. (A24 512-Mbit 1-Gbit densities). ball locations populated.
Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
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Intel StrataFlash® Wireless Memory (L30)
4.1.2
SCSP Package Ballout
wireless memory QUAD+ ballout device available 88-ball (80-active ball) Stacked Chip Scale Package (SCSP) 128- 256-Mbit devices. Mechanical Information, refer Section 3.0, "Package Information" page
Figure
88-Ball (80-Active Ball) SCSP Package Ballout
R-LB#
Legend: ific
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Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
Intel StrataFlash® Wireless Memory (L30)
Signal Descriptions
This section includes signal descriptions following packages:
Package Signal Descriptions SCSP Package Signal Descriptions 4.2.1 Package Signal Descriptions
Table describes active signals used Intel StrataFlash® Wireless Memory (L30), package. Table
Symbol A[MAX:0] DQ[15:0]
Signal Descriptions (Sheet
Type Input Input/ Output Name Function ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]. DATA INPUT/OUTPUTS: Inputs data commands during write cycles; outputs data during memory, Status Register, Protection Register, Read Configuration Register reads. Data balls float when deasserted. Data internally latched during writes. ADDRESS VALID: Active-low input. During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. asynchronous mode, address latched when ADV# going high continuously flows through ADV# held low. CHIP ENABLE: Active-low input. CE#-low selects device. CE#-high deselects device, placing standby, with DQ[15:0] WAIT High-Z. CLOCK: Synchronizes device with system's frequency synchronous-read mode increments internal address generator. During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. OUTPUT ENABLE: Active-low input. OE#-low enables device's output data buffers during read cycles. OE#-high places data outputs High-Z WAIT High-Z. RESET: Active-low input. RST# resets internal automation inhibits write operations. This provides data protection during power transitions. RST#-high enables normal operation. Exit from reset places device asynchronous read array mode. WAIT: Indicates data valid synchronous array non-array burst reads. Configuration Register (RCR[10], determines polarity when asserted. With VIL, WAIT's active output when asserted. WAIT high-Z VIH. synchronous array non-array read modes, WAIT indicates invalid data when asserted valid data when deasserted. asynchronous page mode, write modes, WAIT deasserted. WRITE ENABLE: Active-low input. controls writes device. Address data latched rising edge WE#. WRITE PROTECT: Active-low input. WP#-low enables lock-down mechanism. Blocks lock-down cannot unlocked with Unlock command. WP#-high overrides lock-down function enabling blocks erased programmed using software commands.
ADV#
Input
Input
Input
Input
RST#
Input
WAIT
Output
Input
Input
Intel StrataFlash® Wireless Memory (L30) Order Number: 251903, Revision:
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Intel StrataFlash® Wireless Memory (L30)
Table
Symbol
Signal Descriptions (Sheet
Type Name Function Erase Program Power: valid voltage this allows erasing programming. Memory contents cannot altered when VPPLK. Block erase program invalid voltages should attempted.
Power/ lnput
in-system program erase operations. accommodate resistor diode drops from system supply, level VPPLmin. must remain above VPPLmin perform in-system program erase. during read operations. VPPH applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. connected cumulative total exceed hours. Extended this derate flash performance/behavior.
VCCQ VSSQ
Power Power Power Power
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes flash array inhibited when VLKO. Operations invalid voltages should attempted. OUTPUT POWER SUPPLY: Output-driver source voltage. Ground: Ground reference device logic voltages. Connect system ground. Ground: Ground reference device output voltages. Connect system ground. Use: this ball. This ball should connected power supplies, signals other balls, must left floating. Connect: internal connection; driven floated. Reserved Future Use: Reserved Intel future device functionality enhancement.
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Intel StrataFlash® Wireless Memory (L30)
4.2.2
128/0 256/0 SCSP Package Signal Descriptions
Table describes active signals used 128/0 256/0 SCSP.
Table
Symbol
Device Signal Descriptions S-CSP (Sheet
Type Description ADDRESS INPUTS: Inputs addresses during read write operations.
A[Max:0]
Input
128-Mbit Die: A[Max] 256-Mbit Die: A[Max]
DQ[15:0]
Input/ Output
DATA INPUTS/OUTPUTS: Inputs data commands during write cycles, outputs data during read cycles. Data signals float when device outputs deselected. Data internally latched during writes. FLASH CHIP ENABLE: Low-true: selects associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, sense amplifiers active. When deasserted, associated flash deselected, power reduced standby levels, data WAIT outputs placed high-Z state. F1-CE# selects flash die. F2-CE# F3-CE# available stacked combinations with three flash dies else they RFU. They each tied high VCCQ through 10K-ohm resistor future design flexibility. SRAM CHIP SELECTS: When both SRAM chip selects asserted, SRAM internal control logic, input buffers, decoders, sense amplifiers active. When either/both SRAM chip selects deasserted (S-CS1# S-CS2 VIL), SRAM deselected power reduced standby levels. Treat this signal Connect) this device. PSRAM CHIP SELECT: Low-true; when asserted, PSRAM internal control logic, input buffers, decoders, sense amplifiers active. When deasserted, PSRAM deselected power reduced standby levels. Treat this signal Connect) this device. FLASH OUTPUT ENABLE: Low-true; OE#-low enables flash output buffers. OE#-high disables flash output buffers, places flash outputs High-Z. F2-OE# available stacked combinations with three flash dies else RFU. pulled high VCCQ through 10K-ohm resistor future design flexibility. OUTPUT ENABLE: Low-true; R-OE#-low enables selected output buffers. R-OE#-high disables output buffers, places selected outputs High-Z. Treat this signal Connect) this device. FLASH WRITE ENABLE: Low-true; controls writes selected flash die. Address data latched rising edge WE#. WRITE ENABLE: Low-true; R-WE# controls writes selected die. Treat this signal Connect) this device. FLASH CLOCK: Synchronizes device with system's frequency synchronous-read mode increments internal address generator. During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. FLASH WAIT: Indicates data valid synchronous array non-array burst reads. Configuration Register (RCR[10], determines polarity when asserted. With VIL, WAIT's active output when asserted. WAIT high-Z VIH. synchronous array non-array read modes, WAIT indicates invalid data when asserted valid data when deasserted. asynchronous page mode, write modes, WAIT deasserted.
F1-CE# F2-CE# F3-CE# Input
S-CS1# S-CS2
Input
P-CS#
Input
F1-OE# F2-OE#
Input
R-OE#
Input
R-WE#
Input Input
Input
WAIT
Output
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Intel StrataFlash® Wireless Memory (L30)
Table
Device Signal Descriptions S-CSP (Sheet
Input FLASH WRITE PROTECT: Low-true; enables/disables lock-down protection mechanism selected flash die. WP#-low enables lock-down mechanism locked down blocks cannot unlocked with software commands. WP#-high disables lock-down mechanism, allowing locked down blocks unlocked with software commands. FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses latched rising edge ADV#, next valid edge with ADV# low, whichever occurs first. asynchronous mode, address latched when ADV# going high continuously flows through ADV# held low.
ADV#
Input
R-UB# R-LB# RST#
Input
UPPER LOWER BYTE ENABLES: Low-true; During reads, R-UB#-low enables high order bytes DQ[15:8], R-LB#-low enables low-order bytes DQ[7:0]. Treat this signal Connect) this device. FLASH RESET: Low-true; RST#-low initializes flash internal circuitry disables flash operations. RST#-high enables flash operation. Exit from reset places flash asynchronous read array mode. PSRAM MODE: Low-true; P-MODE used program configuration register, enter/exit power mode. Treat this signal Connect) this device. FLASH PROGRAM ERASE POWER: valid voltage this allows erasing programming. Memory contents cannot altered when VPPLK. Block erase program invalid voltages should attempted.
Input
P-Mode
Input
VPP, VPEN
Power/ Input
in-system program erase operations. accommodate resistor diode drops from system supply, level VPPLmin. must remain above VPPLmin perform in-system flash modification. during read operations. VPPH applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. connected cumulative total exceed hours. Extended this reduce block cycling capability VPEN (Erase/Program/Block Lock Enables) available products. FLASH LOGIC POWER: F1-VCC supplies power core logic flash F2-VCC supplies power core logic flash Write operations inhibited when VLKO. Device operations invalid voltages should attempted. SRAM Power Supply: Supplies power SRAM operations. Treat this signal Connect) this device. PSRAM Power SUpply: Supplies power PSRAM operations. Treat this signal Connect) this device. Flash Power: Supply power input output buffers. Ground: Connect system ground. float connection. Reserved Future Use: Reserve future device functionality/ enhancements. Contact Intel regarding their future use. Use: connect other signal, power supply; must left floating. Connect: internal connection; driven floated.
F1-VCC F2-VCC S-VCC P-VCC VCCQ
Power
Power Power Power Power
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Memory
Table "Top Parameter Memory Map" page Table "Bottom Parameter Memory Map" page memory array divided into multiple partitions; parameter partition several main partitions:
64-Mbit device. This contains eight partitions: 8-Mbit parameter partition, seven 8-Mbit
main partitions.
128-Mbit device. This contains sixteen partitions: 8-Mbit parameter partition, fifteen 8Mbit main partitions.
256-Mbit device. This contains sixteen partitions: 16-Mbit parameter partition, fifteen 16Mbit main partitions. Table Parameter Memory
Size (KW) 8-Mbit Parameter Partition Seven Partitions
64-Mbit 8-Mbit Parameter Partition 3FC000-3FFFFF 3F8000-3FBFFF 3F4000-3F7FFF 3F0000-3F3FFF 3E0000-3EFFFF 380000-38FFFF 370000-37FFFF
Size (KW) Fifteen Partitions
128-Mbit 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF 000000-00FFFF
Partition
8-Mbit Main Partition
000000-00FFFF 256-Mbit FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF
8-Mbit Main Partitions
Partition
Size (KW) 16-Mbit Parameter Partition Seven Partitions
Partition
F00000-FFFFFF EF0000-EFFFFF
16-Mbit Main Partitions
800000-80FFFF
Eight Partitions
7F0000-7FFFFF
000000-00FFFF
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Table
Bottom Parameter Memory
Size (KW) 8-Mbit Main Partitions Seven Partitions 64-Mbit 3F0000-3FFFFF 8-Mbit Main Partitions Size (KW) Fifteen Partitions 128-Mbit
7F0000-7FFFFF 080000-08FFFF 070000-07FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
080000-08FFFF 070000-07FFFF
8-Mbit Parameter Partition
8-Mbit Parameter Partition
Partition
010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
Partition
Size (KW) 16-Mbit Main Partitions Eight Partitions
256-Mbit
FF0000-FFFFFF
800000-80FFFF
Seven Partitions
7F0000-7FFFFF
100000-10FFFF 0F0000-0FFFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
16-Mbit Parameter Partition
Partition
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Warning:
Maximum Ratings Operating Conditions
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability
Parameter Temperature under bias Storage temperature Voltage signal (except VCC, VPP) voltage voltage VCCQ voltage Output short circuit current Maximum Rating +125 -0.5 +3.8 -0.2 -0.2 +2.5 -0.2 +3.8 1,2,3 Notes
Notes: Voltages shown specified with respect VSS. Minimum voltage -0.5 input/output signals -0.2 VCC, VCCQ, VPP. During transitions, this level undershoot -2.0 periods Maximum voltage +0.5 which, during transitions, overshoot +2.0 periods Maximum voltage input/output signals VCCQ VCCQ +0.5 which, during transitions, overshoot VCCQ +2.0 periods Maximum voltage overshoot +14.0 periods Program/erase voltage typically applied hours maximum total, blocks 1000 cycles maximum. program/erase voltage reduce block cycling capability. Output shorted more than second. more than output shorted time.
Operating Conditions
Symbol VCCQ VPPL VPPH tPPH Block Erase Cycles Operating Temperature Supply Voltage Supply Voltage Voltage Supply (Logic Level) Factory word programming Maximum Hours Main Parameter Blocks Main Blocks Parameter Blocks VPPH VPPH VPPH Parameter 100,000 1000 2500 Cycles Hours Units Notes
NOTES: Case Temperature typical operation, program voltage VPPL. connected 1000 cycles main blocks 2500 cycles parameter blocks.
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Electrical Specifications
Current Characteristics
Parameter VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax VCCQ RST# VCCQ (for ICCS) RST# (for ICCD) VCCMax VCCQ VCCQMax VSSQ RST# VCCQ inputs rail rail (VCCQ VSSQ). Asynchronous Single-Word 5MHz CLK) Page-Mode Read CLK) 4-Word Read Burst length Burst length Burst length Burst length Continuous Burst length Burst length Burst length Burst Length Continuous VCCMax Inputs: Unit Test Conditions Notes
Input Load Current Output Leakage Current
DQ[15:0], WAIT 64-Mbit 128-Mbit 256-Mbit 64-Mbit 128-Mbit
ICCS ICCD
Standby, Power Down
256-Mbit
ICCAPS
ICCR
Average Read Current
Synchronous Burst Read 40MHz
Synchronous Burst Read 52MHz
ICCW, Program Current, ICCE Erase Current ICCWS, Program Suspend Current, ICCES Erase Suspend Current IPPS, Standby Current, IPPWS, Program Suspend Current, IPPES Erase Suspend Current 64-Mbit 128-Mbit 256-Mbit
VPPL, program/erase progress VPPH, program/erase progress VCCQ; suspend progress
1,3,4, 1,3,5, 1,6,3
VPPL, suspend progress
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Parameter VCCQ
0.10 0.10 VPPL, program progress VPPH, program progress VPPL, erase progress VPPH, erase progress Unit Test Conditions Notes
IPPR IPPW IPPE Notes:
Read Program Current Erase Current
0.05 0.05
currents unless noted. Typical values typical VCC, +25°C. ICCS average current measured over time interval after deasserted. Sampled, 100% tested. read program current read program currents. read erase current read erase currents. ICCES specified with device deselected. device read while erase suspend, current ICCES plus ICCR. ICCW, ICCE measured over typical times specified Section 7.6, "Program Erase Characteristics" page
Voltage Characteristics
VCCQ VCCMin VCCQ VCCQMin VCCMin VCCQ VCCQMin -100 Unit Test Condition Notes
Parameter
VCCQ
Input Voltage Input High Voltage Output Voltage
VCCQ
Output High Voltage
VCCQ
VPPLK Lock-Out Voltage VLKO Lock Voltage
VLKOQ VCCQ Lock Voltage
NOTES: undershoot -0.4 overshoot VCCQ durations less. VPPLK inhibits erase program operations. VPPL VPPH outside their valid ranges.
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Figure
Characteristics
Test Conditions
Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Note:
Test Points
VCCQ/2 Output
IO_REF.WMF
test inputs driven VCCQ Logic Logic "0." Input/output timing begins/ends VCCQ/2. Input rise fall times (10% 90%) Worst case speed occurs VCCMin.
Figure
Transient Equivalent Testing Load Circuit
Device Under Test
NOTES: following table component values. Test configuration component value worst case speed conditions. includes capacitance
Table
Test configuration component value worst case speed conditions
Test Configuration Standard Test (pF)
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Figure
Clock Input Waveform
R201
R202 R203
Table
Capacitance
Capacitance
Symbol Parameter Signals Unit Condition temp= temp VCC=VCCQ=(0-1.95) Silicon Note Address, CE#, WE#, OE#, Input Capacitance RST#, CLK, ADV#, Output Capacitance Data, WAIT
COUT NOTES: Sampled, 100% tested. Silicon capacitance only, discrete packages.
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Read Specifications 64-Mbit 128-Mbit Densities
Symbol Parameter Speed 1,2,3 Units Notes
Asynchronous Specifications
tAVAV Read cycle time Address output valid output valid output valid RST# high output valid output low-Z output low-Z high output high-Z high output high-Z Output hold from first occurring address, CE#, change pulse width high WAIT valid high WAIT high WAIT valid WAIT low-Z high WAIT high-Z
tAVQV tELQV tGLQV
tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tELTV tEHTZ tGLTV
tGLTX tGHTZ
Latching Specifications
R101 R102 R103 R104 R105 R106 R108 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA tphvh fCLK tCLK tCH/CL tFCLK/RCLK Address setup ADV# high ADV# high ADV# output valid ADV# pulse width ADV# pulse width high Address hold from ADV# high Page address access RST# high ADV# high
Clock Specifications
R200 R201 R202 R203 frequency period high/low time fall/rise time 19.2
Synchronous Specifications
R301 R302 R303 R304 R305 R306 R307 R311 R312 tAVCH/L tVLCH/L tELCH/L tCHQV tCLQV tCHQX tCHAX tCHTV tCHVL tCHTX Address setup ADV# setup setup output valid Output hold from Address hold from WAIT valid Valid ADV# Setup WAIT Hold from 1,4,5
NOTES: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. delayed tELQV tGLQV after CE#'s falling edge without impact tELQV. Sampled, 100% tested. Address hold synchronous burst mode tCHAX tVHAX, whichever timing specification satisfied first. Applies only subsequent synchronous reads.
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Read Specifications 256-Mbit Density
Symbol Parameter Speed
Units
Notes
Asynchronous Specifications
tAVAV Read cycle time
tAVQV tELQV tGLQV
tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tELTV tEHTZ tGLTV
tGLTX tGHTZ
Address output valid
output valid output valid RST# high output valid output low-Z output low-Z high output high-Z high output high-Z
1,2,3
Output hold from first occurring address, CE#, change pulse width high WAIT valid high WAIT high WAIT valid WAIT low-Z high WAIT high-Z
Latching Specifications
R101 R102 R103 R104 R105 R106 R108 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA tphvh fCLK tCLK tCH/CL tFCLK/RCLK Address setup ADV# high ADV# high ADV# output valid ADV# pulse width ADV# pulse width high Address hold from ADV# high Page address access RST# high ADV# high
Clock Specifications
R200 R201 R202 R203 frequency period high/low time fall/rise time 19.2
Synchronous Specifications
R301 R302 R303 R304 R305 R306 R307 tAVCH/L tVLCH/L tELCH/L tCHQV tCLQV tCHQX tCHAX tCHTV Address setup ADV# setup setup output valid Output hold from Address hold from WAIT valid 1,4,5
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R311 R312
Symbol tCHVL tCHTX
Parameter Valid ADV# Setup WAIT Hold from
Speed
Units
Notes
NOTES: Figure Input/Output Reference Waveform" page timing measurements allowable input slew rate. delayed tELQV tGLQV after CE#'s falling edge without impact tELQV. Sampled, 100% tested. Address hold synchronous burst mode tCHAX tVHAX, whichever timing specification satisfied first. Applies only subsequent synchronous reads.
Figure
Asynchronous Single-Word Read (ADV# Low)
Address ADV# WAIT Data [D/Q] RST#
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
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Figure
Asynchronous Single-Word Read (ADV# Latch)
Address A[1:0][A] R101 R105 ADV# WAIT Data [D/Q] R106
Note:
WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
Figure
Asynchronous Page-Mode Read Timing
A[Max:2] A[1:0] R101 R105 ADV# WAIT DATA [D/Q] R108
R106
Note:
WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low)
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Figure
Synchronous Single-Word Array Non-array Read Timing
R301 R306
Address R101 R105 R104 ADV# R303 R102 WAIT R304 Data [D/Q] R305 R307 R312 R106
Notes: WAIT driven assertion during synchronous array non-array read, configured assert either during data cycle before valid data. This diagram illustrates case which n-word burst initiated flash memory array terminated deassertion after first word burst.
Figure
Continuous Burst Read, showing Output Delay Timing
R301 R302 R306 R304 R304 R304
R101 Address R106 R105 ADV# R303 R102 WAIT R304 Data [D/Q] R305 R305 R305 R305 R307 R312
Notes: WAIT driven assertion during synchronous array non-array read. WAIT asserted during initial latency deasserted during valid data (RCR[10] Wait asserted low). Word Line; delay incurred when burst access crosses 16-word boundary starting address 4-word boundary aligned.
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Figure
Synchronous Burst-Mode Four-Word Read Timing
Latency Count R302 R301 R306
Address R101 R105 R102 ADV# R303 WAIT Data [D/Q] R304 R304 R305 R307 R106
Note:
WAIT driven assertion during synchronous array non-array read. WAIT asserted during initial latency deasserted during valid data (RCR[10] Wait asserted low).
Figure
Burst Suspend Timing
R304
R305
R305
Address R101 R105 ADV# WAIT DATA [D/Q] R304 R304 R312
R106
Notes: stopped either high state. WAIT driven assertion during synchronous array non-array read. WAIT asserted during initial latency deasserted during valid data (RCR[10] Wait asserted low).
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Write Specifications
Nbr. Symbol Parameter Units Notes
Notes:
tPHWL tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH tQVVL tQVBL tBHWH tWHGL tWHQV tWHAV
RST# high recovery setup write pulse width Data setup high Address setup high hold from high Data hold from high Address hold from high pulse width high setup high hold from Status read hold from Status read setup high high high read valid high Address valid
tAVQV
1,2,3 1,2,3 1,2,4
1,2,5 1,2,3,7 1,2,3,7 1,2,9 1,2,3,6,10 1,2,3,6
Write Asynchronous Read Specifications Write Synchronous Read Specifications tWHCH/L high Clock valid tWHVH tVHWL tCHWL high ADV# high ADV# high Clock high 1,2,3,6,10
Write Specifications with Clock Active 1,2,3,11
Write timing characteristics during erase suspend same write-only operations. write operation terminated with either WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from (whichever occurs last) high (whichever occurs first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL tEHEL) defined from high (whichever occurs first) (whichever occurs last). Hence, tWHWL tEHEL tWHEL tEHWL). tWHVH tWHCH/L must when transitioning from write cycle synchronous burst read. should valid level until erase program success determined. This specification only applicable when transitioning from write cycle asynchronous read. spec synchronous read. When doing Read Status operation following command that alters Status Register, write operations results block lock status change, subsequent read operation reflect this change. These specs required only when device synchronous mode clock active during address setup phase.
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Figure
Write Write Timing
Address Data [D/Q] RST#
Figure
Asynchronous Read Write Timing
Address WAIT Data [D/Q] RST#
Note:
WAIT deasserted during asynchronous read during write. WAIT High-Z during write deasserted.
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Figure
Write Asynchronous Read Timing
Address ADV# WAIT Data [D/Q] RST#
Figure
Synchronous Read Write Timing
Latency Count R301 R302 R306
R101 Address R105 R102 ADV# R303 WAIT R304 Data [D/Q] R305 R307 R312 R106 R104
Note:
WAIT shown deasserted High-Z deassertion during write operation (RCR[10]=0 Wait asserted low). Clock ignored during write operation.
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Figure
Write Synchronous Read Timing
Latency Count R302 R301
Address R106 R104 ADV# R303 R306
WAIT Data [D/Q] RST# R304 R305 R304 R307
Note:
WAIT shown deasserted High-Z deassertion during write operation (RCR[10]=0 Wait asserted low).
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Program Erase Characteristics
VPPL Conventional Word Programming Single word Program W200 tPROG/W Time Single cell Buffered Programming Single word W200 tPROG/W Program Time Buffer words) W251 tBUFF Buffered Enhanced Factory Programming Single word W451 tBEFP/W Program tBEFP/ W452 Buffered Setup
Setup
Nbr.
Symbol
Parameter
VPPH
Units Notes
Erasing Suspending W500 tERS/PB 16-KWord Parameter Erase Time W501 tERS/MB 64-KWord Main W600 tSUSP/P Suspend Program suspend Latency Erase suspend W601 tSUSP/E Notes: Typical values measured nominal voltages. Performance numbers valid speed versions. Excludes system overhead. Sampled, 100% tested. Averaged over entire device.
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Power Reset Specifications
Power Down
Power supply sequencing required VCC, VCCQ, connected together; VCCQ and/or connected supply, then should attain VCCMIN before applying VCCQ VPP. Device inputs should driven before supply voltage equals VCCMIN. Power supply transitions should only occur when RST# low. This protects device from accidental programming erasure during power transitions.
Reset Specifications
Asserting RST# during system reset important with automated program/erase devices because systems typically expect read from flash memory when coming reset. reset occurs without flash memory reset, proper initialization occur. This because flash memory providing status information, instead array data expected. Connect RST# same active-low reset signal used initialization. Also, because device disabled when RST# asserted, ignores control inputs during power-up/down. Invalid conditions masked, providing level memory protection. System designers should guard against spurious writes when voltages above VLKO. Because both must asserted write operation, deasserting either signal inhibits writes device. Command User Interface (CUI) architecture provides additional protection because alteration memory contents only occur after successful completion two-step command sequence (see Section 9.2, "Device Commands" page 44).
Nbr. Symbol tPLPH tPLRH
Parameter RST# pulse width RST# device reset during erase RST# device reset during program Power valid RST# deassertion (high)
Unit
Notes 1,2,3,4 1,3,4,7 1,3,4,7 1,4,5,6
tVCCPH Notes: These specifications valid device versions (packages speeds). device reset tPLPH tPLPHmin, this guaranteed. applicable RST# tied Vcc. Sampled, 100% tested. RST# tied supply, device will ready until tVCCPH after VCCmin. RST# tied supply/signal with VCCQ voltage levels, RST# input voltage must exceed until VCCmin. Reset completes within tPLPH RST# asserted while erase program operation executing.
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Figure
Reset Operation Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are: standby current levels; active current levels; transient peaks produced when asserted deasserted. When device accessed, many internal conditions change. Circuits within device enable charge-pumps, internal logic states change high speed. these internal activities produce transient signals. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control correct de-coupling capacitor selection suppress transient voltage peaks. Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, VCCQ, each power connection should have ceramic capacitor connected corresponding ground connection. High-frequency, inherently low-inductance capacitors should placed close possible package leads. Additionally, every eight devices used system, electrolytic capacitor should placed between power ground close devices. bulk capacitor meant overcome voltage droop caused trace inductance.
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Automatic Power Saving
Automatic Power Saving (APS) provides power operation during read's active state. ICCAPS average current measured over time interval, after deasserted. During APS, average current measured over same time interval after following events happen: there internal read, program erase operations cease; asserted; address lines quiescent VSSQ VCCQ. also driven during APS.
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Device Operations
This section provides overview device operations. system provides control insystem read, write, erase operations device system bus. on-chip Write State Machine (WSM) manages block-erase word-program algorithms. Device commands written Command User Interface (CUI) control flash memory device operations. does occupy addressable memory location; mechanism through which flash device controlled.
Operations
CE#-low RST# high enable device read operations. device internally decodes upper address inputs determine accessed partition. ADV#-low opens internal address latches. OE#-low activates outputs gates selected data onto bus. asynchronous mode, address latched when ADV# goes high continuously flows through ADV# held low. synchronous mode, address latched first either rising ADV# edge next valid edge with ADV# (WE# RST# must VIH; must VIL). cycles to/from device conform standard microprocessor operations. Table summarizes operations logic levels that must applied device control signal inputs.
Table
Operations Summary
RST# Running Halted ADV# WAIT Deasserted Driven High-Z High-Z High-Z High-Z High-Z DQ[15:0] Output Output Output Input High-Z High-Z High-Z Notes
Operation Asynchronous Read Synchronous Burst Suspend Write Output Disable Standby Reset
Notes: Refer Table "Command Cycles" page valid DQ[15:0] during write operation. Don't Care RST# must meet maximum specified power-down current.
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9.1.1
Reads
perform read operation, RST# must deasserted while asserted. device-select control. When asserted, enables flash memory device. data-output control. When asserted, addressed flash memory data driven onto bus. Section 10.0, "Read Operations" page details available read modes, Section 15.0, "Special Read States" page details regarding available read states. Automatic Power Savings (APS) feature provides power operation following reads during active mode. After data read from memory array address lines quiescent, automatically places device into standby. APS, device current reduced ICCAPS (see Section 6.1, Current Characteristics" page 24).
9.1.2
Writes
perform write operation, both asserted while RST# deasserted. During write operation, address data latched rising edge CE#, whichever occurs first. Table "Command Cycles" page shows cycle sequence each supported device commands, while Table "Command Codes Definitions" page describes each command. Section 7.0, Characteristics" page signaltiming details.
Note:
Write operations with invalid and/or voltages produce spurious results should attempted.
9.1.3
Output Disable
When deasserted, device outputs DQ[15:0] disabled placed high-impedance (High-Z) state, WAIT also placed High-Z.
9.1.4
Standby
When deasserted device deselected placed standby, substantially reducing power consumption. standby, data outputs placed High-Z, independent level placed OE#. Standby current, ICCS, average current measured over time interval, after deasserted. During standby, average current measured over same time interval after deasserted. When device deselected (while deasserted) during program erase operation, continues consume active power until program erase operation completed.
9.1.5
Reset
with automated device, important assert RST# when system reset. When system comes reset, system processor attempts read from flash memory system boot device. reset occurs with flash memory reset, improper initialization occur because flash memory providing status information rather than array data. Flash memory devices from Intel allow proper initialization following system reset through RST# input. RST# should controlled same low-true reset signal that resets system CPU.
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After initial power-up reset, device defaults asynchronous Read Array, Status Register 0x80. Asserting RST# de-energizes internal circuits, places output drivers High-Z. When RST# asserted, device shuts down operation progress, process which takes minimum amount time complete. When RST# been deasserted, device reset asynchronous Read Array state. Note: RST# asserted during program erase operation, operation terminated memory contents aborted location (for program) block (for erase) longer valid, because data have been only partially written erased. When returning from reset (RST# deasserted), minimum wait required before initial read access outputs valid data. Also, minimum delay required after reset before write cycle initiated. After this wake-up interval passes, normal operation restored. Section 7.0, Characteristics" page details about signal-timing.
Device Commands
Device operations initiated writing specific device commands Command User Interface (CUI). Table "Command Cycles" page Several commands used modify array data including Word Program Block Erase commands. Writing either command initiates sequence internally-timed functions that culminate completion requested task. However, operation aborted either asserting RST# issuing appropriate suspend command.
Table
Mode
Command Cycles (Sheet
Command Read Array Read Device Identifier Cycles First Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 Data2 0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0xE8 0x80 0x20 0xB0 0xD0 0x60 0x60 0x60 Write Write Write 0x01 0xD0 0x2F Write Write Write Write 0xD0 0xD0 Read Read Read PBA+IA Second Cycle Oper Addr1 Data2
Read
Query Read Status Register Clear Status Register Word Program
PnA+QA
Program
Buffered Program3 Buffered Enhanced Factory Program (Buffered EFP)4
Erase Suspend
Block Erase Program/Erase Suspend Program/Erase Resume
Block Locking/ Unlocking
Lock Block Unlock Block Lock-down Block
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Table
Mode
Command Cycles (Sheet
Command Program Protection Register Cycles First Cycle Oper Write Write Write Addr1 Data2 0xC0 0xC0 0x60 Second Cycle Oper Write Write Write Addr1 Data2 0x03
Protection Program Lock Register Configuration Program Read Configuration Register
Notes: First command cycle address should same operation's target address. Address within partition. Partition base address. Identification code address offset. Query address offset. Address within block. Word address memory location written. Protection Register address. Lock Register address. valid address within device. Identifier data. Query data DQ[15:0]. Status Register data. Word data. Word count data loaded into write buffer. Protection Register data. Protection Register data. Lock Register data. Read Configuration Register data A[15:0]. A[MAX:16] select partition. second cycle Buffered Program Command word count data loaded into write buffer. This followed words data.Then confirm command (0xD0) issued, triggering array programming operation. confirm command (0xD0) followed buffer data.
Command Definitions
Valid device command codes descriptions shown Table
Table
Mode
Command Codes Definitions (Sheet
Code Device Mode 0xFF Read Array Read Status 0x70 Register Read Device 0x90 Configuration Register 0x98 Read Query 0x50 Clear Status Register Description Places addressed partition Read Array mode. Array data output DQ[15:0]. Places addressed partition Read Status Register mode. partition enters this mode after program erase command issued. Status Register data output DQ[7:0]. Places addressed partition Read Device Identifier mode. Subsequent reads from addresses within partition outputs manufacturer/device codes, Configuration Register data, Block Lock status, Protection Register data DQ[15:0]. Places addressed partition Read Query mode. Subsequent reads from partition addresses output Common Flash Interface information DQ[7:0]. only Status Register error bits. Clear Status Register command used clear error bits.
Read
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Table
Mode
Command Codes Definitions (Sheet
Code Device Mode Description First cycle 2-cycle programming command; prepares write operation. next write cycle, address data latched executes programming algorithm addressed location. During program operations, partition responds only Word Program Read Status Register Program Suspend commands. must toggled Setup update Status Register asynchronous read. ADV# must toggled update Status Register Data synchronous Non-array read. Read Array command must issued read array data after programming finished. Alternate Word Program Equivalent Word Program Setup command, 0x40. Setup Buffered This command loads variable number bytes buffer size words onto Program program buffer. Buffered confirm command Issued after data streaming writing into buffer done. This Program instructs perform Buffered Program algorithm, writing data from buffer Confirm flash memory array. Buffered First cycle 2-cycle command; initiates Buffered Enhanced Factory Program mode Enhanced (Buffered EFP). then waits Buffered Confirm command, 0xD0, that Factory initiates Buffered algorithm. other commands ignored when Buffered mode Programming begins. Setup Buffered previous command Buffered Setup (0x80), latches address Confirm data, prepares device Buffered mode. First cycle 2-cycle command; prepares block-erase operation. Block Erase performs erase algorithm block addressed Erase Confirm command. Setup next command Erase Confirm (0xD0) command, sets Status Register bits SR[4] SR[5], places addressed partition read status register mode. first command Block Erase Setup (0x20), latches address data, erases addressed block. During block-erase operations, partition responds Block Erase only Read Status Register Erase Suspend commands. must toggled Confirm update Status Register asynchronous read. ADV# must toggled update Status Register Data synchronous Non-array read. This command issued device address initiates suspend currently-executing Program program block erase operation. Status Register indicates successful suspend operation Erase setting either SR[2] (program suspended) SR[6] (erase suspended), along with SR[7] Suspend (ready). Write State Machine remains suspend mode regardless control signal states (except RST# asserted). Suspend This command issued device address resumes suspended program block-erase Resume operation. First cycle 2-cycle command; prepares block lock configuration changes. Lock Block next command Block Lock (0x01), Block Unlock (0xD0), Block Lock-Down (0x2F), Setup sets Status Register bits SR[4] SR[5], indicating command sequence error. Lock Block previous command Block Lock Setup (0x60), addressed block locked. previous command Block Lock Setup (0x60), addressed block unlocked. Unlock Block addressed block lock-down state, operation effect. Lock-Down previous command Block Lock Setup (0x60), addressed block locked down. Block Program First cycle 2-cycle command; prepares device Protection Register Lock Protection Register program operation. second cycle latches register address data, starts Register programming algorithm Setup Read First cycle 2-cycle command; prepares device read configuration. Configuration Read Configuration Register command (0x03) next command, sets Status Register Register bits SR[4] SR[5], indicating command sequence error. Setup Read previous command Read Configuration Register Setup (0x60), latches Configuration address writes A[15:0] Read Configuration Register. Following Configure Read Register Configuration Register command, subsequent read operations access array data.
0x40
0x10 Write 0xE8 0xD0
0x80
0xD0
0x20 Erase 0xD0
0xB0 Suspend 0xD0 0x60 Block 0x01 Locking/ Unlocking 0xD0 0x2F
Protection 0xC0
0x60 Configuration 0x03
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10.0
Read Operations
device supports read modes: asynchronous page mode synchronous burst mode. Asynchronous page mode default read mode after device power-up reset. Read Configuration Register must configured enable synchronous burst reads flash memory array (see Section 10.3, "Read Configuration Register (RCR)" page 48). Each partition device four read states: Read Array, Read Identifier, Read Status Read Query. Upon power-up, after reset, partitions device default Read Array. change partition's read state, appropriate read command must written device (see Section 9.2, "Device Commands" page 44). Section 15.0, "Special Read States" page details regarding Read Status, Read Query modes. following sections describe read-mode operations detail.
10.1
Asynchronous Page-Mode Read
Following device power-up reset, asynchronous page mode default read mode partitions Read Array. However, perform array reads after other device operation (e.g. write operation), Read Array command must issued order read from flash memory array.
Note:
Asynchronous page-mode reads only performed when Read Configuration Register RCR[15] (see Section 10.3, "Read Configuration Register (RCR)" page 48). perform asynchronous page-mode read, address driven onto A[MAX:0], ADV# asserted. RST# must already have been deasserted. WAIT deasserted during asynchronous page mode. ADV# driven high latch address, must held throughout read cycle. used asynchronous page-mode reads, ignored. only asynchronous reads performed, should tied valid level, WAIT signal floated ADV# must tied ground. Array data driven onto DQ[15:0] after initial access time tAVQV delay. (see Section 7.0, Characteristics" page 26). asynchronous page mode, four data words "sensed" simultaneously from flash memory array loaded into internal page buffer. buffer word corresponding initial address A[MAX:0] driven onto DQ[15:0] after initial access delay. Address bits A[MAX:2] select 4-word page. Address bits A[1:0] determine which word 4-word page output from data buffer given time.
10.2
Synchronous Burst-Mode Read
Section 10.3, "Read Configuration Register (RCR)" page 48continuous-wordsTo perform synchronous burst- read, initial address driven onto A[MAX:0], ADV# asserted. RST# must already have been deasserted. ADV# asserted, then deasserted latch address. Alternately, ADV# remain asserted throughout burst access, which case address latched next valid edge while ADV# asserted.
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During synchronous array non-array read modes, first word output from data buffer next valid edge after initial access latency delay (see Section 10.3.2, "Latency Count" page 50). Subsequent data output valid edges following minimum delay. However, synchronous non-array read, same word data will output successive clock edges until burst length requirements satisfied.
10.2.1
Burst Suspend
Burst Suspend feature device reduce eliminate initial access latency incurred when system software needs suspend burst sequence that progress order retrieve data from another device same system bus. system processor resume burst sequence later. Burst suspend provides maximum benefit non-cache systems. Burst accesses suspended during initial access latency (before data received) after device output data. When burst access suspended, internal array sensing continues previously latched internal data retained. burst sequence suspended resumed without limit long device operation conditions met. Burst Suspend occurs when asserted, current address been latched (either ADV# rising edge valid edge), halted, deasserted. halted when VIL. WAIT High-Z during deassertion. resume burst access, reasserted, restarted. Subsequent edges resume burst sequence. Within device, gate WAIT. Therefore, during Burst Suspend WAIT placed high-impedance state when deasserted resumed active when re-asserted. Figure "Burst Suspend Timing" page
10.3
Read Configuration Register (RCR)
used select read mode (synchronous asynchronous), defines synchronous burst characteristics device. modify settings, Configure Read Configuration Register command (see Section 9.2, "Device Commands" page 44). contents examined using Read Device Identifier command, then reading from <partition base address> 0x05 (see Section 15.2, "Read Device Identifier" page 73).
shown Table following sections describe each bit.
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Table
Read Configuration Register Description
Read Configuration Register (RCR)
Read Mode Latency Count WAIT Polarity Data Hold WAIT Delay Burst Edge Burst Wrap Burst Length
13:11
LC[2:0]
BL[2:0]
Name Read Mode (RM) Reserved Latency Count (LC[2:0])
Description Synchronous burst-mode read Asynchronous page-mode read (default) Reserved bits should cleared =Code =Code =Code =Code =Code =Code (default) (Other settings reserved) =WAIT signal active =WAIT signal active high (default) =Data held 1-clock data cycle =Data held 2-clock data cycle (default) =WAIT deasserted with valid data =WAIT deasserted data cycle before valid data (default) =Reserved =Linear (default) Falling edge Rising edge (default) Reserved bits should cleared =Wrap; Burst accesses wrap within burst length BL[2:0] Wrap; Burst accesses wrap within burst length (default) =4-word burst =8-word burst =16-word burst =Continuous-word burst (default) (Other settings reserved)
Wait Polarity (WP) Data Hold (DH) Wait Delay (WD) Burst Sequence (BS) Clock Edge (CE) Reserved Burst Wrap (BW) Burst Length (BL[2:0])
Note:
Latency Code Data Hold 2-clock data cycle Wait must deasserted with valid data Latency Code Data Hold 2-cock data cycle (DH=1) Wait deasserted data cycle before valid data combination supported.
10.3.1
Read Mode
Read Mode (RM) selects synchronous burst-mode asynchronous page-mode operation device. When set, asynchronous page mode selected (default). When cleared, synchronous burst mode selected.
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10.3.2
Latency Count
Latency Count bits, LC[2:0], tell device many clock cycles must elapse from rising edge ADV# from first valid clock edge after ADV# asserted) until first data word driven onto DQ[15:0]. input clock frequency used determine this value. Figure shows data output latency different settings LC[2:0]. Synchronous burst with Latency Count setting Code will result zero WAIT state; however, Latency Count setting Code will cause WAIT state (Code will cause WAIT states, Code will cause WAIT states) after every four words, regardless whether 16-word boundary crossed. RCR[9] (Data Hold) (data hold clocks) this WAIT condition will occur because enough clocks elapse during each burst cycle eliminate subsequent WAIT states. Refer Table Frequency Support (tAVQV/tCHQV ns)" page Latency Code Settings.
Figure
First-Access Latency Count
Valid Address
Address
ADV# Code (Reserved) DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q]
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Code
(Reserved
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Valid Output
Code
Valid Output
Valid Output
Code
Valid Output
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Table
Frequency Support (tAVQV/tCHQV
VCCQ Latency Count Settings Frequency Support (MHz)
Figure "Example Latency Count Setting using Code
Figure
Example Latency Count Setting using Code
tData
ADV# A[MAX:0]
Code Address
D[15:0]
High-Z
Data
R103
10.3.3
WAIT Polarity
WAIT Polarity (WP), RCR[10] determines asserted level (VOH VOL) WAIT. When set, WAIT asserted-high (default). When cleared, WAIT asserted-low. WAIT changes state valid clock edges during active cycles (CE# asserted, asserted, RST# deasserted).
10.3.3.1
WAIT Signal Function
WAIT signal indicates data valid when device operating synchronous mode (RCR[15]=0). WAIT signal only "deasserted" when data valid bus. When device operating synchronous non-array read mode, such read status, read read query WAIT signal also "deasserted" when data valid bus. WAIT behavior during synchronous non-array reads word line works correctly only first data access.
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When device operating asynchronous page mode, asynchronous single word read mode, write operations, WAIT deasserted state determined RCR[10]. Figure "Asynchronous Single-Word Read (ADV# Latch)" page Figure "Asynchronous Page-Mode Read Timing" page Table WAIT Functionality Table
Condition WAIT Notes
`1', `X', ='0', Synchronous Array Reads Synchronous Non-Array Reads Asynchronous Reads Writes
High-Z
Active Active Active Deasserted High-Z
Notes: Active: WAIT asserted until data becomes valid, then deasserts When during writes, WAIT High-Z
10.3.4
Data Hold
burst read operations, Data Hold (DH) determines whether data output remains valid DQ[15:0] clock cycles. This period time called "data cycle". When set, output data held clocks (default). When cleared, output data held clock (see Figure 26). processor's data setup time flash memory's clock-to-data output delay should considered when determining whether hold output data clocks. method determining Data Hold configuration shown below: device clock data hold subsequent reads, following condition must satisfied: tCHQV (ns) tDATA (ns) Period (ns) tDATA Data Clock (defined CPU) example, with clock frequency MHz, clock period Assuming tCHQV tDATA 4ns. Applying these values formula above: equation satisfied data will available every clock period with data hold setting clock. tCHQV (ns) tDATA (ns) Period (ns), data hold setting clock periods must used.
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Figure
Data Hold Timing
Data Hold Data Hold
Valid Output Valid Output Valid Output
D[15:0]
D[15:0]
Valid Output
Valid Output
10.3.5
WAIT Delay
WAIT Delay (WD) controls WAIT assertion-delay behavior during synchronous burst reads. WAIT asserted either during data cycle before valid data output DQ[15:0]. When set, WAIT deasserted data cycle before valid data (default). When cleared, WAIT deasserted during valid data.
10.3.6
Burst Sequence
Burst Sequence (BS) selects linear-burst sequence (default). Only linear-burst sequence supported. Table shows synchronous burst sequence burst lengths, well effect Burst Wrap (BW) setting.
Table
Burst Sequence Word Ordering
Start Addr. (DEC) Burst Addressing Sequence (DEC) Burst Wrap (RCR[3]) 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 4-Word Burst (BL[2:0] 0b001) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-Word Burst (BL[2:0] 0b010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 16-Word Burst (BL[2:0] 0b011) 0-1-2-3-4.14-15 1-2-3-4-5.15-0 2-3-4-5-6.15-0-1 3-4-5-6-7.15-0-1-2 4-5-6-7-8.15-0-1-2-3 5-6-7-8-9.15-0-1-2-3-4 6-7-8-9-10.15-0-1-2-3-4-5 7-8-9-10.15-0-1-2-3-4-5-6 14-15-0-1-2.12-13 15-0-1-2-3.13-14 0-1-2-3-4.14-15 1-2-3-4-5.15-16 2-3-4-5-6.16-17 3-4-5-6-7.17-18 4-5-6-7-8.18-19 5-6-7-8-9.19-20 6-7-8-9-10.20-21 7-8-9-10-11.21-22 14-15-16-17-18.28-29 15-16-17-18-19.29-30 Continuous Burst (BL[2:0] 0b111) 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13. 14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-. 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13. 14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-.
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10.3.7
Clock Edge
Clock Edge (CE) selects either rising (default) falling clock edge CLK. This clock edge used start burst cycle, output synchronous data, assert/deassert WAIT.
10.3.8
Burst Wrap
Burst Wrap (BW) determines whether 4-word, 8-word, 16-word burst length accesses wrap within selected word-length boundaries cross word-length boundaries. When set, burst wrapping does occur (default). When cleared, burst wrapping occurs. When performing synchronous burst reads with wrap), output delay occur when burst sequence crosses first device-row (16-word) boundary. burst sequence's start address 4-word aligned, then delay occurs. start address 4-word boundary, worst case output delay clock cycle less than first access Latency Count. This delay take place only once, doesn't occur burst sequence does cross device-row boundary. WAIT informs system this delay when occurs.
10.3.9
Burst Length
Burst Length (BL[2:0]) selects linear burst length synchronous burst reads flash memory array. burst lengths 4-word, 8-word, 16-word, continuous word. Continuous-burst accesses linear only, wrap within word length boundaries (see Table "Burst Sequence Word Ordering" page 53). When burst cycle begins, device outputs synchronous burst data until reaches "burstable" address space.
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11.0
Programming Operations
device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), Buffered Enhanced Factory Programming (Buffered EFP) (80h, D0h). Section 9.0, "Device Operations" page details various programming commands issued device. Successful programming requires addressed block unlocked. block locked down, must deasserted block must unlocked before attempting program block. Attempting program locked block causes program error (SR[4] SR[1] set) termination operation. Section 13.0, "Security Modes" page details locking unlocking blocks. following sections describe device programming detail.
11.1
Word Programming
Word programming operations initiated writing Word Program Setup command device (see Section 9.0, "Device Operations" page 42). This followed second write device with address data programmed. partition accessed during both write cycles outputs Status Register data when read. partition accessed during second cycle (the data cycle) program command sequence location where data written. Figure "Word Program Flowchart" page Programming occur only partition time; other partitions must read state erase suspend. must above VPPLK, within specified VPPL min/max values (nominally During programming, Write State Machine (WSM) executes sequence internally-timed events that program desired data bits addressed location, verifies that bits sufficiently programmed. Programming flash memory array changes "ones" "zeros." Memory array bits that zeros changed ones only erasing block (see Section 12.0, "Erase Operations" page 61). Status Register examined programming progress errors reading address within partition that being programmed. partition remains Read Status Register state until another command written that partition. Issuing Read Status Register command another partition address sets that partition Read Status Register state, allowing programming progress monitored that partition's address. Status Register SR[7] indicates programming status while sequence executes. Commands that issued programming partition during programming Program Suspend, Read Status Register, Read Device Identifier, Query, Read Array (this returns unknown data). When programming finished, Status Register SR[4] (when set) indicates programming failure. SR[3] set, could perform word programming operation because outside acceptable limits. SR[1] set, word programming operation attempted program locked block, causing operation abort.
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Before issuing command, Status Register contents should examined then cleared using Clear Status Register command. valid command follow, when word programming completed.
11.1.1
Factory Word Programming
Factory word programming similar word programming that uses same commands programming algorithms. However, factory word programming enhances programming performance with VPPH. This enable faster programming times during manufacturing processes. Factory word programming intended extended use. Section 5.2, "Operating Conditions" page limitations when VPPH.
Note:
When VPPL, device draws programming current from supply. driven logic signal, VPPL must remain above VPPL program device. When VPPH, device draws programming current from supply. Figure "Example Supply Connections" page shows examples device power supply configurations.
11.2
Buffered Programming
device features 32-word buffer enable optimum programming performance. Buffered Programming, data first written on-chip write buffer. Then buffer data programmed into flash memory array buffer-size increments. This improve system programming performance significantly over non-buffered programming. When Buffered Programming Setup command issued (see Section 9.2, "Device Commands" page 44), Status Register information updated reflects availability buffer. SR[7] indicates buffer availability: set, buffer available; cleared, buffer available. retry, issue Buffered Programming Setup command again, re-check SR[7]. When SR[7] set, buffer ready loading. (see Figure "Buffer Program Flowchart" page 84). next write, word count written device buffer address. This tells device many data words will written buffer, maximum size buffer. next write, device start address given along with first data written flash memory array. Subsequent writes provide additional device addresses data. data addresses must within start address plus word count. Optimum programming performance lower power usage obtained aligning starting address beginning 32-word boundary (A[4:0] 0x00). Crossing 32-word boundary during programming will double total programming time. After last data written buffer, Buffered Programming Confirm command must issued original block address. begins program buffer contents flash memory array. command other than Buffered Programming Confirm command written device, command sequence error occurs Status Register bits SR[7,5,4] set. error occurs while writing array, device stops programming, Status Register bits SR[7,4] set, indicating programming failure. Reading from another partition allowed while data being programmed into array from write buffer (see Figure "Buffer Program Flowchart" page 84). When Buffered Programming completed, additional buffer writes initiated issuing another Buffered Programming Setup command repeating buffered program sequence. Buffered programming performed with VPPL VPPH (see Section 5.2, "Operating Conditions" page limitations when operating device with VPPH).
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attempt made program past erase-block boundary using Buffered Program command, device aborts operation. This generates command sequence error, Status Register bits SR[5,4] set. Buffered programming attempted while below VPPLK, Status Register bits SR[4,3] set. errors detected that have Status Register bits, Status Register should cleared using Clear Status Register command.
11.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds Multi-Level Cell (MLC) flash programming today's beat-rate-sensitive manufacturing environments. enhanced programming algorithm used Buffered eliminates traditional programming elements that drive overhead device programmer systems. Buffered consists three phases: Setup, Program/Verify, Exit (see Figure "Buffered Flowchart" page 85). uses write buffer spread program performance across data words. Verification occurs same phase programming accurately program flash memory cell correct state. single two-cycle command sequence programs entire block data. This enhancement eliminates three write cycles buffer: commands word count each data words. Host programmer cycles fill device's write buffer followed status check. SR[0] indicates when data from buffer been programmed into sequential flash memory array locations. Following buffer-to-flash array programming sequence, Write State Machine (WSM) increments internal addressing automatically select next 32-word array boundary. This aspect Buffered saves host programming equipment address-bus setup overhead. With adequate continuity testing, programming equipment rely WSM's internal verification ensure that device programmed properly. This eliminates external postprogram verification associated overhead.
11.3.1
Buffered Requirements Considerations
Buffered requirements:
Ambient temperature: 25°C, ±5°C within specified operating range. driven VPPH. Target block unlocked before issuing Buffered Setup Confirm commands. first-word address (WA0) block programmed must held constant from setup phase through data streaming into target block, until transition exit phase desired.
must align with start array buffer boundary1.
Buffered considerations:
optimum performance, cycling must limited below erase cycles block2.
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Buffered programs block time; buffer data must fall within single block3. Buffered cannot suspended. Programming flash memory array occur only when buffer full4. Read operation while performing Buffered supported.
NOTES: Word buffer boundaries array determined A[4:0] (0x00 through 0x1F). alignment start point A[4:0] 0x00. Some degradation performance occur this limit exceeded, internal algorithm continues work properly. internal address counter increments beyond block's maximum address, addressing wraps around beginning block. number words less than remaining locations must filled with 0xFFFF.
11.3.2
Buffered Setup Phase
After receiving Buffered Setup Confirm command sequence, Status Register SR[7] (Ready) cleared, indicating that busy with Buffered algorithm startup. delay before checking SR[7] required allow enough time perform setups checks (Block-Lock status, level, etc.). error detected, SR[4] Buffered operation terminates. block found locked, SR[1] also set. SR[3] error occurred incorrect level.
Note:
Reading from device after Buffered Setup Confirm command sequence outputs Status Register data. issue Read Status Register command; will interpreted data loaded into buffer.
11.3.3
Buffered Program/Verify Phase
After Buffered Setup Phase completed, host programming system must check SR[7,0] determine availability write buffer data streaming. SR[7] cleared indicates device busy Buffered program/verify phase activated. SR[0] indicates write buffer available. basic sequences repeat this phase: loading write buffer, followed buffer data programming array. Buffered EFP, count value buffer loading always maximum buffer size words. During buffer-loading sequence, data stored sequential buffer locations starting address 0x00. Programming buffer contents flash memory array starts soon buffer full. number words less than remaining buffer locations must filled with 0xFFFF.
Caution:
buffer must completely filled programming occur. Supplying address outside current block's range during buffer-fill sequence causes algorithm exit immediately. data previously loaded into buffer during fill cycle programmed into array. starting address data entry must buffer size aligned, Buffered algorithm will aborted program fail (SR[4]) flag will set. Data words from write buffer directed sequential memory locations flash memory array; programming continues from where previous buffer sequence ended. host programming system must poll SR[0] determine when buffer program sequence completes. SR[0] cleared indicates that buffer data been transferred flash array; SR[0] indicates that buffer available next fill cycle. host system check full
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status errors time, only necessary block basis after Buffered exit. After buffer fill cycle, write cycles should issued device until SR[0] device ready next buffer fill. Note: spurious writes ignored after buffer fill operation when internal program proceeding. host programming system continues Buffered algorithm providing next group data words written buffer. Alternatively, terminate this phase changing block address outside current block's range. Program/Verify phase concludes when programmer writes different block address; data supplied must 0xFFFF. Upon Program/Verify phase completion, device enters Buffered Exit phase.
11.3.4
Buffered Exit Phase
When SR[7] set, device returned normal operating conditions. full status check should performed partition being programmed this time ensure entire block programmed successfully. When exiting Buffered algorithm with block address change, read mode both programmed addressed partition will change. After Buffered exit, valid command issued device.
11.4
Program Suspend
Issuing Program Suspend command while programming suspends programming operation. This allows data accessed from memory locations other than being programmed. Program Suspend command issued device address; corresponding partition affected. program operation suspended perform reads only. Additionally, program operation that running during erase suspend suspended perform read operation (see Figure "Program Suspend/Resume Flowchart" page 83). When programming operation executing, issuing Program Suspend command requests suspend programming algorithm predetermined points. partition that suspended continues output Status Register data after Program Suspend command issued. Programming suspended when Status Register bits SR[7,2] set. Suspend latency specified Section 7.6, "Program Erase Characteristics" page read data from blocks within suspended partition, Read Array command must issued that partition. Read Array, Read Status Register, Read Device Identifier, Query, Program Resume valid commands during program suspend. program operation does need suspended order read data from block another partition that programming. other partition already Read Array, Read Device Identifier, Query state, issuing valid address returns corresponding read data. other partition read mode, read commands must issued partition before data read. During program suspend, deasserting places device standby, reducing active current. must remain programming level, must remain unchanged while program suspend. RST# asserted, device reset.
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11.5
Program Resume
Resume command instructs device continue programming, automatically clears Status Register bits SR[7,2]. This command written partition. When read partition that's programming, device outputs data corresponding partition's last state. error bits set, Status Register should cleared before issuing next instruction. RST# must remain deasserted (see Figure "Program Suspend/Resume Flowchart" page 83).
11.6
Program Protection
When VIL, absolute hardware write protection provided device blocks. below VPPLK, programming operations halt SR[3] indicating VPP-level error. Block lock registers affected voltage level VPP; they still programmed read, even less than VPPLK.
Figure
Example Supply Connections
PROT
Factory Programming with VPPH Complete write/Erase Protection when VPPLK
Low-voltage Programming only Logic Control Device Protection
VPP=VPPH
Voltage Factory Programming
Voltage Programming Only Full Device Protection Unavailable
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12.0
Erase Operations
Flash erasing performed block basis. entire block erased each time erase command sequence issued, only block erased time. When block erased, bits within that block read logical ones. following sections describe block erase operations detail.
12.1
Block Erase
Block erase operations initiated writing Block Erase Setup command address block erased (see Section 9.2, "Device Commands" page 44). Next, Block Erase Confirm command written address block erased. Erasing occur only partition time; other partitions must read state. device placed standby (CE# deasserted) during erase operation, device completes erase operation before entering standby.VPP must above VPPLK block must unlocked (see Figure "Block Erase Flowchart" page 86). During block erase, Write State Machine (WSM) executes sequence internally-timed events that conditions, erases, verifies bits within block. Erasing flash memory array changes "zeros" "ones." Memory array bits that ones changed zeros only programming block (see Section 11.0, "Programming Operations" page 55). Status Register examined block erase progress errors reading address within partition that being erased. partition remains Read Status Register state until another command written that partition. Issuing Read Status Register command another partition address sets that partition Read Status Register state, allowing erase progress monitored that partition's address. SR[0] indicates whether addressed partition another partition erasing. partition's Status Register SR[7] upon erase completion. Status Register SR[7] indicates block erase status while sequence executes. When erase operation finished, Status Register SR[5] indicates erase failure set. SR[3] would indicate that could perform erase operation because outside acceptable limits. SR[1] indicates that erase operation attempted erase locked block, causing operation abort. Before issuing command, Status Register contents should examined then cleared using Clear Status Register command. valid command follow once block erase operation completed.
12.2
Erase Suspend
Issuing Erase Suspend command while erasing suspends block erase operation. This allows data accessed from memory locations other than being erased. Erase Suspend command issued device address; corresponding partition affected. block erase operation suspended perform word buffer program operation, read operation within block except block that erase suspended (see Figure "Program Suspend/Resume Flowchart" page 83).
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When block erase operation executing, issuing Erase Suspend command requests suspend erase algorithm predetermined points. partition that suspended continues output Status Register data after Erase Suspend command issued. Block erase suspended when Status Register bits SR[7,6] set. Suspend latency specified Section 7.6, "Program Erase Characteristics" page read data from blocks within suspended partition (other than erase-suspended block), Read Array command must issued that partition first. During Erase Suspend, Program command issued block other than erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, Query, Erase Resume valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, Block Lock-Down valid commands during Erase Suspend. read data from block partition that erasing, erase operation does need suspended. other partition already Read Array, Read Device Identifier, Query, issuing valid address returns corresponding data. other partition read state, read commands must issued partition before data read. During erase suspend, deasserting places device standby, reducing active current. must remain valid level, must remain unchanged while erase suspend. RST# asserted, device reset.
12.3
Erase Resume
Erase Resume command instructs device continue erasing, automatically clears status register bits SR[7,6]. This command written partition. When read partition that's erasing, device outputs data corresponding partition's last state. status register error bits set, Status Register should cleared before issuing next instruction. RST# must remain deasserted (see Figure "Program Suspend/Resume Flowchart" page 83).
12.4
Erase Protection
When VIL, absolute hardware erase protection provided device blocks. below VPPLK, erase operations halt SR[3] indicating VPP-level error.
April 2005
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Intel StrataFlash® Wireless Memory (L30)
13.0
Security Modes
device features security modes used protect information stored flash memory array. following sections describe each security mode detail.
13.1
Block Locking
Individual instant block locking used protect user code and/or data within flash memory array. blocks power locked state protect array data from being altered during power transitions. block locked unlocked with latency. Locked blocks cannot programmed erased; they only read. Software-controlled security implemented using Block Lock Block Unlock commands. Hardware-controlled security implemented using Block Lock-Down command along with asserting WP#. Also, data security used inhibit program erase operations (see Section 11.6, "Program Protection" page Section 12.4, "Erase Protection" page 62).
13.1.1
Lock Block
lock block, issue Lock Block Setup command. next command must Lock Block command issued desired block's address (see Section 9.2, "Device Commands" page Figure "Block Lock Operations Flowchart" page 88). Read Configuration Register command issued after Block Lock Setup command, device configures instead. Block lock unlock operations affected voltage level VPP. block lock bits modified and/or read even below VPPLK.
13.1.2
Unlock Block
Unlock Block command used unlock blocks (see Section 9.2, "Device Commands" page 44). Unlocked blocks read, programmed, erased. Unlocked blocks return locked state when device reset powered down. block lock-down state, must deasserted before unlocked (see Figure "Block Locking State Diagram" page 64).
13.1.3
Lock-Down Block
locked unlocked block locked-down writing Lock-Down Block command sequence (see Section 9.2, "Device Commands" page 44). Blocks lock-down state cannot programmed erased; they only read. However, unlike locked blocks, their locked state cannot changed software commands alone. locked-down block only unlocked issuing Unlock Block command with deasserted. return unlocked block lockeddown state, Lock-Down command must issued prior changing VIL. Locked-down blocks revert locked state upon reset power device (see Figure "Block Locking State Diagram" page 64).
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Intel StrataFlash® Wireless Memory (L30)
13.1.4
Block Lock Status
Read Device Identifier command used determine block's lock status (see Section 15.2, "Read Device Identifier" page 73). Data bits DQ[1:0] display addressed block's lock status; addressed block's lock bit, while addressed block's lock-down bit.
Figure
Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown [011]
Hardware Locked [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control
Notes:
[a,b,c] represents [WP#, DQ1, DQ0]. Don't Care. indicates Block Lock-Down status. `0', Lock-Down been issued this block. `1', Lock-Down been issued this block. indicates block lock status. `0', block unlocked. `1', block locked. Locked-down Hardware Software locked. [011] states should tracked system software determine difference between Hardware Locked Locked-Down states.
13.1.5
Block Locking During Suspend
Block lock unlock changes performed during erase suspend. change block locking during erase operation, first issue Erase Suspend command. Monitor Status Register until SR[7] SR[6] set, indicating device suspended ready accept another command. Next, write desired lock command sequence block, which changes lock state that block. After completing block lock unlock operations, resume erase operation using Erase Resume command.
Note:
Lock Block Setup command followed command other than Lock Block, Unlock Block, Lock-Down Block produces command sequence error Status Register bits SR[4] SR[5]. command sequence error occurs during erase suspend, SR[4] SR[5] remains set, even after erase operation resumed. Unless Status Register cleared using Clear Status Register command before resuming erase operation, possible erase errors masked command sequence error.
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Intel StrataFlash® Wireless Memory (L30)
block locked locked-down during erase suspend same block, lock status bits change immediately. However, erase operation completes when resumed. Block lock operations cannot occur during program suspend. Appendix "Write State Machine (WSM)" page which shows valid commands during erase suspend.
13.2
Protection Registers
device contains Protection Registers (PRs) that used implement system security measures and/or device identification. Each Protection Register individually locked. first 128-bit Protection Register comprised 64-bit (8-word) segments. lower 64bit segment pre-programmed factory with unique 64-bit number. other 64-bit segment, well other sixteen 128-bit Protection Registers, blank. Users program these registers needed. When programmed, users then lock Protection Register(s) prevent additional programming (see Figure "Protection Register Map" page 66). user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot erased. Each Protection Register accessed multiple times program individual bits, long register remains unlocked. Each Protection Register associated Lock Register bit. When Lock Register programmed, associated Protection Register only read; longer programmed. Additionally, because Lock Register bits themselves OTP, when programmed, Lock Register bits cannot erased. Therefore, when Protection Register locked, cannot unlocked
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Figure
Protection Register
0x109 128-bit Protection Register (User-Programmable) 0x102
0x91 128-bit Protection Register (User-Programmable) 0x8A Lock Register 0x89
0x88 64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0x80
128-Bit Protection Register 64-bit Segment (Factory-Programmed)
13.2.1
Reading Protection Registers
Protection Registers read from within partition's address space. read Protection Register, first issue Read Device Identifier command partitions' address place that partition Read Device Identifier state (see Section 9.2, "Device Commands" page 44). Next, perform read operation that partition's base address plus address offset corresponding register read. Table "Device Identifier Information" page shows address offsets Protection Registers Lock Registers. Register data read bits time.
Note:
program erase operation occurs within device while reading Protection Register, certain restrictions apply. Table "Simultaneous Operation Restrictions" page details.
April 2005
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13.2.2
Programming Protection Registers
program Protection Registers, first issue Program Protection Register command parameter partition's base address plus offset desired Protection Register (see Section 9.2, "Device Commands" page 44). Next, write desired Protection Register data same Protection Register address (see Figure "Protection Register Map" page 66). device programs 64-bit 128-bit user-programmable Protection Register data bits time (see Figure "Protection Register Programming Flowchart" page 89). Issuing Program Protection Register command outside Protection Register's address space causes program error (SR[4] set). Attempting program locked Protection Register causes program error (SR[4] set) lock error (SR[1] set).
Note:
program erase operation occurs when programming Protection Register, certain restrictions apply. Table "Simultaneous Operation Restrictions" page details.
13.2.3
Locking Protection Registers
Each Protection Register locked programming respective lock Lock Register. lock Protection Register, program corresponding Lock Register issuing Program Lock Register command, followed desired Lock Register data (see Section 9.2, "Device Commands" page 44). physical addresses Lock Registers 0x80 register 0x89 register These addresses used when programming lock registers (see Table "Device Identifier Information" page 74). Lock Register already programmed factory, locking lower, pre-programmed 64-bit region first 128-bit Protection Register containing unique identification number device. Lock Register programmed user lock user-programmable, 64-bit region first 128-bit Protection Register. other bits Lock Register used. Lock Register controls locking upper sixteen 128-bit Protection Registers. Each bits Lock Register correspond each upper sixteen 128-bit Protection Registers. Programming Lock Register locks corresponding 128-bit Protection Register.
Caution:
After being locked, Protection Registers cannot unlocked.
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14.0
Dual-Operation Considerations
multi-partition architecture device allows background programming erasing) occur partition while data reads code execution) take place another partition.
14.1
Memory Partitioning
flash memory array divided into multiple 8-Mbit partitions, which allows simultaneous read-while-write operations. Simultaneous program erase allowed. Only partition time program erase mode. flash device supports read-while-write operations with cycle granularity command granularity. other words, assumed that both cycles cycle command erase command example) will always occur back back cycles flash device. practice, code fetches (reads) interspersed between write cycles flash device, they will likely directed different partition than being written. This especially true when processor executing code from partition that instructs processor program erase another partition.
14.2
Read-While-Write Command Sequences
When issuing commands device, read operation occur between 2-cycle Write command'
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