High-Performance 16-Bit Microcontrollers 2005 Microchip Technolog
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PIC24H Family Overview
High-Performance 16-Bit Microcontrollers
2005 Microchip Technology Inc.
DS70166A
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance WiperLock trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2005, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS70166A-page
2005 Microchip Technology Inc.
PIC24H
PIC24H High-Performance 16-Bit Overview
Operating Range
MIPS MIPS 3.0-3.6V, -40° +85°C) Industrial temperature range (-40° +85°C)
Interrupt Controller
5-cycle latency interrupt vectors available interrupt sources, external interrupts programmable priority levels processor exceptions
High-Performance
Modified Harvard architecture compiler optimized instruction 16-bit wide data path 24-bit wide instructions Linear program memory addressing instruction words Linear data memory addressing Kbytes base instructions: mostly word/1 cycle Sixteen 16-bit general-purpose registers Flexible powerful addressing modes Software stack integer multiply operations 32/16 16/16 divide operations Single-cycle multiply 16-bit shifts
Digital
programmable digital pins Wake-up/Interrupt-on-Change pins Output pins drive from 3.0V 3.6V digital input pins tolerant sink source pins
On-Chip Flash SRAM
Flash program memory, Kbytes Data SRAM Kbytes): Includes
System Management
Flexible clock options: External, crystal, resonator, internal Fully integrated Extremely jitter Power-up timer Oscillator Start-up Timer/Stabilizer Watchdog timer with oscillator Fail-Safe Clock Monitor Reset multiple sources
Direct Memory Access (DMA)
8-channel hardware Allows data transfer between peripheral while executing code cycle stealing) dual-ported buffer area (DMA RAM) store data transferred Most peripherals support
Power Management
On-chip 2.5V voltage regulator Switch between clock sources real time Idle, Sleep Doze modes with fast wake-up
2005 Microchip Technology Inc.
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PIC24H
Timers/Capture/Compare/PWM
Timer/Counters: nine 16-bit timers: pair make four 32-bit timers timer runs Real-Time Clock with external oscillator Programmable prescaler Input Capture channels): Capture down both edges 16-bit capture input functions 4-deep FIFO each capture Output Compare channels): Single Dual 16-Bit Compare mode 16-Bit Glitchless mode
Analog-to-Digital Converters (ADC)
10-bit 12-bit modules device 10-bit Msps 12-bit Msps conversion: simultaneous samples input channels with auto-scanning Conversion start manual synchronized with trigger sources Conversion possible Sleep mode integral nonlinearity differential nonlinearity
CMOS Flash Technology
Low-power, high-speed Flash technology Fully static design 3.3V (+/- 10%) operating voltage Industrial temperature Low-power consumption
Communication Modules
3-wire SPI(up modules): Framing supports interface simple codecs Supports 8-bit 16-bit data Supports serial clock formats sampling modes 8-word FIFO buffers I2C(up modules): Full Multi-Master Slave mode support 7-bit 10-bit addressing collision detection arbitration Integrated signal conditioning Address masking UART modules): Interrupt-on-address detect Wake-up-on-Start from Sleep mode 4-character FIFO buffers support IrDA® encoding decoding hardware High-Speed Baud mode Enhanced 2.0B active modules): transmit receive buffers receive filters masks Loopback, Listen Only Listen Messages modes diagnostics monitoring Wake-up message FIFO mode using
Packaging:
100-pin TQFP (14x14x1 12x12x1 64-pin TQFP (10x10x1 Note: Table exact peripheral features device.
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2005 Microchip Technology Inc.
PIC24H
PIC24H PRODUCT FAMILIES
General-Purpose Family
PIC24H General-purpose Family (Table 1-1) ideal wide variety 16-bit embedded applications. variants with codec interfaces well-suited audio applications.
TABLE 1-1:
PIC24H GENERAL-PURPOSE FAMILY VARIANTS
Output Compare Std. Pins (Max)(2) Channels Input Capture Timer 16-bit Codec Interface RAM(1) (KB) UART SPI
I2C
Device
Pins
Program Flash Memory (KB)
Packages
24HJ64GP206 24HJ64GP210 24HJ64GP506 24HJ64GP510 24HJ128GP206 24HJ128GP210 24HJ128GP506 24HJ128GP510 24HJ128GP306 24HJ128GP310 24HJ256GP206 24HJ256GP210 24HJ256GP610 Note
ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC, ADC,
size inclusive RAM. Maximum count includes pins shared peripheral functions.
2005 Microchip Technology Inc.
DS70166A-page
PIC24H
PRODUCT IDENTIFICATION SYSTEM
Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Count Tape Reel Flag applicable) Temperature Range Package Pattern
Examples:
dsPIC24HJ64GP610I/PT: General Purpose dsPIC24H, program memory, 100-pin, Industrial temp., TQFP package. dsPIC24HJ64GP206I/PT-ES: Motor Control dsPIC24H, program memory, 64-pin, Industrial temp., TQFP package, Engineering Sample.
Architecture
16-bit Microcontroller
Flash Memory Family
Flash program memory, 3.3V, high-speed
Program Memory Size
Kbytes Kbytes Kbytes
Product Group
General Purpose family General Purpose family General Purpose family General Purpose family
Tape Reel
Applicable Blank applicable
Count
64-pin 100-pin
Temperature Range
-40°C +85°C (Industrial)
Package Pattern
10x10 12x12 TQFP (Thin Quad Flatpack) 14x14 TQFP (Thin Quad Flatpack)
Three-digit QTP, SQTP, Code Special Requirements (blank otherwise) Engineering Sample
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2005 Microchip Technology Inc.
PIC24H
PIC24H DEVICE FAMILY OVERVIEW
Further, Direct Memory Access (DMA) enables overhead-free transfer data between several peripherals dedicated RAM. Reliable, field programmable Flash program memory ensures scalability applications that PIC24H devices. Figure shows sample device block diagram typical PIC24H product family.
PIC24H device family employs powerful 16-bit microcontroller (MCU). resulting functionality ideal applications that rely high-speed, repetitive computations, well control. Flexible deterministic interrupt handling, coupled with powerful array peripherals, renders PIC24H devices suitable control applications.
FIGURE 2-1:
PIC24H DEVICE BLOCK DIAGRAM
X-Data <16-bit>
Shifter
Multiplier
Data SRAM Kbytes Ports
Register Array Memory Mapped
Program Flash Memory Data Access
Program Counter bits> Divide Control Instruction Prefetch Decode STATUS Register
Flash Program Memory Kbytes
Peripherals
16-bit Legend: MCU/DSP X-Data Path Address Path
Dual Port Kbytes
Controller
2005 Microchip Technology Inc.
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PIC24H
ARCHITECTURE
Overview
FIGURE 3-1:
PROGRAM SPACE MEMORY
Reset GOTO Instruction Reset Target Address Reserved Osc. Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Error Vector Reserved Vector Reserved Vector 000000 000002 000004
PIC24H module 16-bit (data) modified Harvard architecture with enhanced instruction set. 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses bits user program memory space. actual amount program memory implemented, illustrated Figure 3-1, varies from device another. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instruction, which interruptible point. PIC24H devices have sixteen 16-bit working registers programmer's model. Each working registers serve data, address address offset register. 16th working register (W15) operates software Stack Pointer (SP) interrupts calls. PIC24H instruction includes many addressing modes designed optimum compiler efficiency.
000014 Interrupt Vector Table 0000FE 000100 000104 0001FE 000200 User Flash Program Memory (87552 24-bit) 02ABFE 02AC00
User Memory Space
Reserved Alternate Vector Table
Reserved
7FFFFE 800000
3.1.1
DATA MEMORY OVERVIEW
data space addressed words Kbytes. Reads writes performed using Address Generation Unit (AGU), which accesses entire memory linear data space.
Configuration Memory Space
upper Kbytes data space memory optionally mapped into program space program word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program-to-data space mapping feature lets instruction access program space were data space. data space includes Kbytes RAM, which primarily used data transfers, used general-purpose RAM.
Reserved
Device Configuration Registers 8-bit)
F7FFFE F80000 F80016 F80018
Reserved
Device 16-bit) Reserved
FEFFFE FF0000 FF0002 FF0004 FFFFFE
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Vector Tables
PIC24H
3.1.2 ADDRESSING MODES OVERVIEW 3.1.5
supports Inherent operand), Relative, Literal, Memory Direct, Register Direct Register Indirect Addressing modes. Each instruction associated with predefined addressing mode group depending upon functional requirements. many addressing modes supported each instruction. most instructions, PIC24H capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing operations executed single cycle.
FEATURES ENHANCE COMPILER EFFICIENCY
architecture possesses several features that lead more efficient (code size speed) compiler. most instructions, three-parameter instructions supported, allowing operations executed single cycle. Instruction addressing modes extremely flexible meet compiler needs. working register array consists 16-bit registers, each which data, address offset registers. working register (W15) operates software Stack Pointer interrupts calls. Linear indirect access data space possible, plus memory direct address range Kbytes. This capability, together with addition 16-bit direct address MOV-based instructions, provided contiguous linear addressing space. Linear indirect access word Kbyte) pages within program space possible, using working register table read write instructions. Part data space mapped into program space, allowing constant data accessed were data space.
3.1.3
SPECIAL FEATURES
PIC24H features 17-bit 17-bit, single-cycle multiplier. multiplier perform signed, unsigned mixed-sign multiplication. Using 17-bit 17-bit multiplier 16-bit 16-bit multiplication allows perform mixed-sign multiplication. PIC24H supports 16/16 32/16 divide operations, both fractional integer. divide instructions iterative operations. They must executed within REPEAT loop, resulting total execution time instruction cycles. divide operation interrupted during those cycles without loss data. 40-bit data shifter used perform 16-bit left right shift single cycle.
3.1.4
INTERRUPT OVERVIEW
PIC24H vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels.
2005 Microchip Technology Inc.
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PIC24H
Programmer's Model
programmer's model, shown Figure 3-2, consists 16-bit working registers through W15), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), REPEAT count register (RCOUNT) Program Counter (PC). working registers data, address offset registers. registers memory mapped. register instructions that perform file register addressing. Some these registers have shadow register associated with them (see legend Figure 3-2). shadow register used temporary holding register transfer contents from host register upon some event occurring single cycle. None shadow registers accessible directly. When byte operation performed working register, only Least Significant Byte (LSB) target register affected. However, benefit memory mapped working registers that both Least Most Significant Bytes (MSBs) manipulated through byte-wide data memory space accesses. dedicated software Stack Pointer (SP). automatically modified exception processing subroutine calls returns. However, referenced instruction same manner other registers. This simplifies reading, writing manipulation Stack Pointer (e.g., creating stack frames). been dedicated Stack Frame Pointer, defined ULNK instructions. However, referenced instruction same manner other registers. Stack Pointer always points first available free word grows from lower addresses towards higher addresses. pre-decrements stack pops (reads) post-increments stack pushes (writes).
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PIC24H
FIGURE 3-2: PROGRAMMER'S MODEL
W0/WREG Result Registers W14/Frame Pointer W15*/Stack Pointer *W15 SPLIM shadowed Stack Pointer Limit Register Working Registers
PUSH.S Shadow
Legend:
SPLIM*
Program Counter
TABPAG TBLPAG
Data Table Page Address
PSVPAG
Program Space Visibility Page Address
RCOUNT
REPEAT Loop Counter
CORCON
Core Configuration Register
IPL2 IPL1 IPL0
STATUS Register
2005 Microchip Technology Inc.
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PIC24H
Data Address Space
3.3.3 DATA ALIGNMENT
data space accessed unified linear address range (for instructions). data space accessed using Address Generation Unit (AGU). Effective Addresses (EAs) bits wide point bytes within data space. Therefore, data space address range Kbytes words, though implemented memory locations vary from device another. help maintain backward compatibility with PICmicro® devices improve data space memory usage efficiency, PIC24H instruction supports both word byte operations. Data aligned data memory registers words, data space resolve bytes. Data byte reads will read complete word which contains byte, using Least Significant (LSb) determine which byte select. consequence this byte accessibility, Effective Address calculations internally scaled. example, core would recognize that Post-Modified Register Indirect Addressing mode, [Ws++], will result value byte operations word operations. word accesses must aligned even address. Misaligned word data fetches supported. Should misaligned read write attempted, trap will then executed, allowing system and/or user examine machine state prior execution address Fault.
3.3.1
Every PIC24H device contains Kbytes located data space. Memory locations space accessible simultaneously Controller module. utilized Controller store data transferred various peripherals using DMA, well data transferred from various peripherals using DMA. When Controller attempt concurrently write same location, hardware ensures that given precedence accessing location. Therefore, provides reliable means transferring data without ever having stall CPU.
3.3.2
DATA SPACE WIDTH
core data width bits. internal registers organized 16-bit wide words. Data space memory organized byte addressable, 16-bit wide blocks. Figure depicts sample data space memory PIC24H device with Kbytes RAM.
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PIC24H
FIGURE 3-3: SAMPLE DATA SPACE MEMORY
Most Significant Byte Address 2-Kbyte Space 8-Kbyte Data Space 0x1FFF 0x0001 0x07FF 0x0801 Data 0x1FFE Space Least Significant Byte Address 0x0000 0x07FE 0x0800
Bits
0x3FFF 0x4001 0x47FF 0x4801 Unimplemented 0x8001
0x3FFE 0x4000 0x47FE 0x4800
0x8000
Optionally Mapped into Program Memory 0xFFFF 0xFFFE
Note:
This data memory largest memory PIC24H device. Data memory maps other devices vary.
2005 Microchip Technology Inc.
DS70166A-page
PIC24H
DIRECT MEMORY ACCESS
Direct Memory Access (DMA) very efficient mechanism copying data between peripheral SFRs (e.g., UART Receive register, Input Capture buffer) buffers variables stored with minimal intervention. Controller automatically copy entire blocks data, without user software having read write peripheral Special Function Registers (SFRs) every time peripheral interrupt occurs. exploit capability, corresponding user buffers variables must located space. Controller features eight identical data transfer channels, each with control status registers. UART, SPI, DCI, Input Capture, Output Compare, ECANtechnology modules utilize DMA. Each channel configured copy data either from buffers stored peripheral SFRs from peripheral SFRs buffers RAM. Each channel supports following features: Word byte-sized data transfers Transfers from peripheral peripheral Indirect addressing locations with without automatic post-increment Peripheral Indirect Addressing some peripherals, read/write addresses partially derived from peripheral One-Shot Block Transfers Terminating transfer after block transfer Continuous Block Transfers Reloading buffer start address after every block transfer complete Ping-Pong Mode Switching between start addresses between successive block transfers, thereby filling buffers alternately Automatic manual initiation block transfers Each channel select from possible sources data sources destinations each channel, interrupt request generated when block transfer complete. Alternatively, interrupt generated when half block been filled. Additionally, error trap generated either following Fault conditions: data write collision between peripheral Peripheral data write collision between Controller
FIGURE 4-1:
LEVEL SYSTEM ARCHITECTURE USING DEDICATED TRANSACTION
Peripheral Indirect Address Controller
Control
SRAM
PORT PORT
Channels
Ready Peripheral
SRAM X-Bus
Peripheral
Non-DMA Ready Peripheral
Ready Peripheral
Ready Peripheral
Note: address buses shown clarity.
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PIC24H
EXCEPTION PROCESSING
PIC24H four processor exceptions (traps) sources interrupts, which must arbitrated based priority scheme. processor core responsible reading Interrupt Vector Table (IVT) transferring address contained interrupt vector Program Counter. Interrupt Vector Table (IVT) Alternate Interrupt Vector Table (AIVT) placed near beginning program memory (0x000004) ease debugging. interrupt controller hardware pre-processes interrupts before they presented CPU. interrupts traps enabled, prioritized controlled using centralized Special Function Registers. Each individual interrupt source vector address individually enabled prioritized user software. Each interrupt source also status flag. This independent control monitoring interrupt eliminates need poll various status flags determine interrupt source Table contains information about interrupt vector. Certain interrupts have specialized control bits features like edge level triggered interrupts, interrupton-change, etc. Control these features remains within peripheral module, which generates interrupt. special DISI instruction used disable processing interrupts priorities lower certain number instruction cycles, during which DISI remains set.
TABLE 5-1:
Vector Number
INTERRUPT VECTORS
Address 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x000030 0x000032 0x000034 0x000036 0x000038 0x00003A 0x00003C 0x00003E 0x000040 0x000042 0x000044 0x000046 0x000048 0x00004A 0x00004C 0x00004E 0x000050 0x000052 AIVT Address 0x000114 0x000116 0x000118 0x00011A 0x00011C 0x00011E 0x000120 0x000122 0x000124 0x000126 0x000128 0x00012A 0x00012C 0x00012E 0x000130 0x000132 0x000134 0x000136 0x000138 0x00013A 0x00013C 0x00013E 0x000140 0x000142 0x000144 0x000146 0x000148 0x00014A 0x00014C 0x00014E 0x000150 0x000152 Interrupt Source INT0 External Interrupt Input Compare Output Compare Timer1 DMA0 Channel Input Capture Output Compare Timer2 Timer3 SPI1E SPI1 Error SPI1 SPI1 Transfer Done U1RX UART1 Receiver U1TX UART1 Transmitter ADC1 DMA1 Channel Reserved I2C1S I2C1 Slave Event I2C1M I2C1 Master Event Reserved Change Notification Interrupt INT1 External Interrupt ADC2 Input Capture Input Capture DMA2 Channel Output Compare Output Compare Timer4 Timer5 INT2 External Interrupt U2RX UART2 Receiver U2TX UART2 Transmitter
2005 Microchip Technology Inc.
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PIC24H
TABLE 5-1:
Vector Number 65-68 70-72 80-125
INTERRUPT VECTORS (CONTINUED)
Address AIVT Address Interrupt Source
0x000054 0x000154 SPI2E SPI2 Error 0x000056 0x000156 SPI1 SPI1 Transfer Done 0x000058 0x000158 C1RX ECAN1 Receive Data Ready 0x00005A 0x00015A ECAN1 Event 0x00005C 0x00015C DMA3 Channel 0x00005E 0x00015E Input Capture 0x000060 0x000160 Input Capture 0x000062 0x000162 Input Capture 0x000064 0x000164 Input Capture 0x000066 0x000166 Output Compare 0x000068 0x000168 Output Compare 0x00006A 0x00016A Output Compare 0x00006C 0x00016C Output Compare 0x00006E 0x00016E Reserved 0x000070 0x000170 DMA4 Channel 0x000072 0x000172 Timer6 0x000074 0x000174 Timer7 0x000076 0x000176 I2C2S I2C2 Slave Event 0x000078 0x000178 I2C2M I2C2 Master Event 0x00007A 0x00017A Timer8 0x00007C 0x00017C Timer9 0x00007E 0x00017E INT3 External Interrupt 0x000080 0x000180 INT4 External Interrupt 0x000082 0x000182 C2RX ECAN2 Receive Data Ready 0x000084 0x000184 ECAN2 Event 0x000086-0x00008C 0x000186-0x00018C Reserved 0x00008E 0x00018E DMA5 Channel 0x000090-0x000094 0x000190-0x000194 Reserved 0x000096 0x000196 UART1 Error 0x000098 0x000198 UART2 Error 0x00009A 0x00019A Reserved 0x00009C 0x00019C DMA6 Channel 0x00009E 0x00019E DMA7 Channel 0x0000A0 0x0001A0 C1TX ECAN1 Transmit Data Request 0x0000A2 0x0001A2 C2TX ECAN2 Transmit Data Request 0x0000A40x0001A4Reserved 0x0000FE 0x0001FE
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PIC24H
Interrupt Priority Traps
Each interrupt source user-assigned priority levels, through Levels represent highest lowest maskable priorities, respectively. priority level disables interrupt. Since more than interrupt request source assigned user-specified priority level, means provided assign priority within given level. This method called "Natural Order Priority". Natural Order Priority interrupt numerically identical vector number. Natural Order Priority scheme highest priority lowest priority. ability user assign every interrupt eight priority levels implies that user assign very high overall priority level interrupt with Natural Order Priority, thereby providing much flexibility designing applications that large number peripherals. Traps considered non-maskable, nestable interrupts that adhere fixed priority structure. Traps intended provide user means correct erroneous operation during debug when operating within application. user does intend take corrective action event trap error condition, these vectors must loaded with address software routine that will reset device. Otherwise, trap vector programmed with address service routine that will correct trap condition. PIC24H five implemented sources non-maskable traps: Oscillator Failure Trap Address Error Trap Stack Error Trap Math Error Trap Error Trap
Interrupt Nesting
Interrupts, default, nestable. that progress interrupted another source interrupt with higher user-assigned priority level. Interrupt nesting optionally disabled setting NSTDIS control (INTCON1<15>). When NSTDIS control set, interrupts progress will force priority level setting IPL<2:0> 111. This action will effectively mask other sources interrupt until RETFIE instruction executed. When interrupt nesting disabled, user-assigned interrupt priority levels will have effect, except resolve conflicts between simultaneous pending interrupts. IPL<2:0> bits become read-only when interrupt nesting disabled. This prevents user software from setting IPL<2:0> lower value, which would effectively re-enable interrupt nesting.
Many these trap conditions only detected when they happen. Consequently, instruction that caused trap allowed complete before exception processing begins. Therefore, user have correct action instruction that caused trap. Each trap source fixed priority defined position IVT. oscillator failure trap highest priority, while arithmetic error trap lowest priority. Table contains information about trap vector.
Generating Software Interrupt
available interrupt manually generated user software (even corresponding peripheral disabled), simply enabling interrupt then setting interrupt flag when required.
TABLE 5-2:
TRAP VECTORS
Address 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 0x000012 AIVT Address 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000092 Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Error Trap Reserved Reserved
Vector Number
2005 Microchip Technology Inc.
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PIC24H
SYSTEM INTEGRATION
System management services provided PIC24H device family include: Control clock options oscillators Power-on Reset Oscillator Start-up Timer/Stabilizer Watchdog Timer with oscillator Fail-Safe Clock Monitor Reset multiple sources defines operating speed device, speeds supported PIC24H architecture. PIC24H oscillator system provides: Various external internal oscillator options clock sources on-chip scale internal operating frequency required system clock frequency internal oscillator also used with PLL, thereby allowing full-speed operation without external clock generation hardware Clock switching between various clock sources Programmable clock postscaler system power savings Fail-Safe Clock Monitor (FSCM) that detects clock failure takes fail-safe measures Clock Control register (OSCCON) Nonvolatile Configuration bits main oscillator selection. simplified block diagram oscillator system shown Figure 6-1.
Clock Options Oscillators
There clock options provided PIC24H: Oscillator Oscillator with Primary (XT, Oscillator Primary Oscillator with Secondary (LP) Oscillator LPRC Oscillator
(Fast internal oscillator runs nominal frequency 7.37 MHz. user software tune frequency. User software specify factor which this clock frequency scaled. primary oscillator following clock source: (Crystal): Crystals ceramic resonators range MHz. crystal connected OSC1 OSC2 pins. (High-Speed Crystal): Crystals range MHz. crystal connected OSC1 OSC2 pins. (External Clock): External clock signal range MHz. external clock signal directly applied OSC1 pin.
secondary (LP) oscillator designed power uses crystal ceramic resonator. oscillator uses SOSCI SOSCO pins. LPRC (Low-Power internal oscIllator runs nominal frequency 32.768 kHz. Another scaled reference clock used Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM). clock signals generated primary oscillators optionally applied on-chip Phase Locked Loop (PLL) provide wide range output frequencies device operation. input range MHz, Phase Detector Input Divider, Multiplier Ratio Voltage Controlled Oscillator (VCO) individually configured user software generate output frequencies range MHz. output oscillator output mode been selected) divided generate device instruction clock (FCY).
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PIC24H
FIGURE 6-1:
OSC1 OSC2
OSCILLATOR SYSTEM BLOCK DIAGRAM
Primary Oscillator Module Primary Internal Fast (FRC) Oscillator
Secondary SOSCO SOSCI Secondary Oscillator
Clock Switching Control Block
FOSC
Divide
Internal Low-Power (LPRC) Oscillator
Timer1
Power-on Reset (POR)
Watchdog Timer (WDT)
When supply voltage applied device, Power-on Reset (POR) generated. Power-on Reset event generated supply voltage falls below device threshold voltage (VPOR). internal pulse generated when rising supply voltage crosses circuit threshold voltage.
primary function Watchdog Timer (WDT) reset processor event software malfunction. free-running timer that runs on-chip LPRC oscillator, requiring external component. continues operate even main processor clock (e.g., crystal oscillator) fails. Watchdog Timer "Enabled" "Disabled" either through Configuration (FWDTEN) Configuration register, through (SWDTEN). device programmer capable programming dsPIC® devices (such Microchip's MPLAB® Programmer) allows programming this other Configuration bits desired state. enabled, increments until overflows "times out". time-out forces device Reset (except during Sleep).
Oscillator Start-up Timer/Stabilizer (OST)
Oscillator Start-up Timer (OST) included ensure that crystal oscillator ceramic resonator) started stabilized. simple, 10-bit counter that counts 1024 TOSC cycles before releasing oscillator clock rest system. timeout period designated TOST. TOST time involved every time oscillator restart (i.e., Power-on Reset wake-up from Sleep). Oscillator Start-up Timer applied oscillator, modes (upon wake-up from Sleep, Brown-out Reset (BOR)) primary oscillator.
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PIC24H
Fail-Safe Clock Monitor (FSCM) Reset System
Fail-Safe Clock Monitor (FSCM) allows device continue operate even event oscillator failure. FSCM function enabled programming. FSCM function enabled, LPRC internal oscillator runs times (except during Sleep mode) subject control Watchdog Timer. event oscillator failure, FSCM generates clock failure trap event switches system clock over oscillator. application program then either attempt restart oscillator, execute controlled shutdown. trap treated warm Reset simply loading Reset address into oscillator fail trap vector. Reset system combines Reset sources controls device Master Reset signal. Device Reset sources include: POR: Power-on Reset BOR: Brown-out Reset SWR: RESET Instruction EXTR: MCLR Reset WDTR: Watchdog Timer Time-out Reset TRAPR: Trap Conflict IOPUWR: Attempted execution Illegal Opcode, Indirect Addressing, using Uninitialized register
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PIC24H
DEVICE POWER MANAGEMENT
processor exits (wakes from Sleep these events: interrupt source that individually enabled form device Reset time-out Power management services provided PIC24H devices include: Real-Time Clock Source Switching Power-Saving Modes
7.2.2
IDLE MODE
Real-Time Clock Source Switching
When device enters Idle mode: stops executing instructions automatically cleared System clock source remains active Peripheral modules, default, continue operate normally from system clock source Peripherals, optionally, shut down Idle mode using their `stop-in-idle' control bit. FSCM enabled, LPRC also remains active processor wakes from Idle mode these events: interrupt that individually enabled source device Reset time-out Upon wake-up from Idle, clock re-applied instruction execution begins immediately starting with instruction following PWRSAV instruction, first instruction Interrupt Service Routine (ISR).
Configuration bits determine clock source upon Power-on Reset (POR) Brown-out Reset (BOR). Thereafter, clock source changed between permissible clock sources. OSCCON register controls clock switching reflects system clock related status bits. reduce power consumption, user switch slower clock source.
Power-Saving Modes
PIC24H devices have reduced power modes that entered through execution PWRSAV instruction. Sleep Mode: CPU, system clock source peripherals that operate system clock source disabled. This lowest power mode device. Idle Mode: disabled system clock source continues operate. Peripherals continue operate optionally disabled. Doze Mode: clock temporarily slowed down relative peripheral clock user-selectable factor. These modes provide effective reduce power consumption during periods when use.
7.2.3
DOZE MODE
7.2.1
SLEEP MODE
Doze mode provides user software ability temporarily reduce processor instruction cycle frequency relative peripheral frequency. Clock frequency ratios 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64 1:128 supported. example, suppose device operating MIPS module been configured kbps rate based this device operating speed. device placed Doze mode with clock frequency ratio 1:4, module will continue communicate required rate kbps, starts executing instructions frequency MIPS. This feature further reduces power consumption during periods where relatively less activity required. When device operating Doze mode, hardware ensures that there loss synchronization between peripheral events accesses CPU.
When device enters Sleep mode: System clock source shut down. on-chip oscillator used, turned off. Device current consumption minimum provided that sourcing current. Fail-Safe Clock Monitor (FSCM) does operate during Sleep mode because system clock source disabled. LPRC clock continues Sleep mode enabled. circuit, enabled, remains operative during Sleep mode WDT, enabled, automatically cleared prior entering Sleep mode. Some peripherals continue operate Sleep mode. These peripherals include pins that detect change input signal, peripherals that external clock input. peripheral that operating system clock source disabled Sleep mode.
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PIC24H PERIPHERALS
Digital Signal Controller (DSC) family 16-bit devices provides integrated functionality many peripherals. Specific peripheral functions include: Analog-to-Digital Converters (ADC) 10-bit High-Speed 12-bit High-Resolution General-purpose 16-Bit Timers Motor Control module Quadrature Encoder Interface module Input Capture module Output Compare/PWM module Data Converter Interface Serial Peripheral Interface (SPITM) module UART module I2Cmodule Controller Area Network (CAN) module pins Integral Nonlinearity (INL) (3.3V ±10%) on-chip sample hold amplifiers each (enables simultaneous sampling analog inputs) Automated channel scanning Single-supply operation: 3.0-3.6V Msps Msps sampling rate 3.0V Ability convert during Sleep Idle modes Conversion start manual synchronized with trigger sources (automatic, Timer3 external interrupt, period match) buffer storage
General-Purpose Timer Modules
Analog-to-Digital Converters
General-Purpose (GP) timer modules provide time base elements input capture output compare/PWM. They configured Real-Time Clock operation well various timer/counter modes. timer modes count pulses internal time base, whereas counter modes count external pulses that appear timer clock pin. PIC24H device supports nine 16-bit timers (Timer1 through Timer9). Eight 16-bit timers configured four 32-bit timers (Timer2/3, Timer4/5, Timer6/7 Timer8/9). Each timer several selectable operating modes.
Analog-to-Digital Converters provide analog inputs with both single-ended differential inputs. These modules offer on-board sample hold circuitry. minimize control loop errors finite update times (conversion plus computations), high-speed low-latency required. addition, several hardware features have been included peripheral interface improve real-time performance typical DSP-based application. Result alignment options Automated sampling Automated channel scanning Dual port data buffer External conversion start control
8.2.1
TIMER1
Timer1 module (Figure 8-1) 16-bit timer that serve time counter asynchronous RealTime Clock, operate free-running interval timer/ counter. 16-bit timer following modes: 16-Bit Timer 16-Bit Synchronous Counter 16-Bit Asynchronous Counter Further, following operational characteristics supported: Timer gated external pulse Selectable prescaler settings Timer operation during Idle Sleep modes Interrupt 16-Bit Period register match falling edge external gate signal
configured user application either following configurations: 10-bit, Msps module (2.2 Msps conversion using modules) 12-bit, ksps module Msps conversion using modules) features module include: 10-bit 12-bit resolution Unipolar differential sample/hold amplifiers input channels Selectable voltage reference sources (external VREF+ VREF- pins available) Differential Nonlinearity (DNL) (3.3V ±10%)
Timer1, when operating Real-Time Clock (RTC) mode, provides time event time-stamping capabilities. operational features are: Operation from oscillator 8-bit prescaler power Real-Time Clock interrupts
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FIGURE 8-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Equal
Comparator
TSYNC Sync
Reset T1IF Event Flag TGATE
TMR1
TGATE
TGATE
SOSCO/ T1CK LPOSCEN SOSCI Gate Sync
TCKPS<1:0> Prescaler
8.2.2
TIMER2/3
8.2.3
TIMER4/5, TIMER6/7, TIMER8/9
Timer2/3 module 32-bit timer (which configured 16-bit timers) with selectable operating modes. These timers used other peripheral modules, such Input Capture Output Compare/Simple Timer2/3 following modes: independent 16-bit timers (Timer2 Timer3) with Timer Synchronous Counter modes Single 32-Bit Timer Single 32-Bit Synchronous Counter Further, following operational characteristics supported: conversion start trigger 32-bit timer gated external pulse Selectable prescaler settings Timer counter operation during Idle Sleep modes Interrupt 32-Bit Period register match Timer2/3 buffer storage
Timer4/5, Timer6/7 Timer8/9 modules similar operation Timer2/3 module. Differences include: These modules support event trigger feature These modules used other peripheral modules, such input capture output compare
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Input Capture Module
input capture module useful applications requiring frequency (period) pulse measurement. PIC24H devices support eight input capture channels. input capture module captures 16-bit value selected time base register when event occurs pin. events that cause capture event listed below three categories: Simple Capture Event modes Capture timer value every falling edge input Capture timer value every rising edge input Capture timer value every edge (rising falling) Prescaler Capture Event modes Capture timer value every rising edge input Capture timer value every 16th rising edge input PIC24H device have eight output compare channels, designated through OC8. Refer specific device data sheet number channels available particular device. output compare channels functionally identical. Each output compare channel selectable time bases. time base selected using OCTSEL (OCxCON<3>). pin, register name denotes specific output compare channel. Refer device data sheet specific timers that used with each output compare channel number. Each output compare module following modes operation: Single Compare Match mode Dual Compare Match mode generating Single Output Pulse Continuous Output Pulses Simple Pulse-Width Modulation mode With Fault Protection Input Without Fault Protection Input Output compare channels, OC2, support data transfers.
Each input capture channel select between 16-bit timers (Timer2 Timer3) time base. selected timer either internal external clock. Other operational features include: Device wake-up from capture during Sleep Idle modes Interrupt input capture event 4-word FIFO buffer capture values Interrupt optionally generated after buffer locations filled Input capture also used provide additional sources external interrupts. Input capture channels support data transfers.
Module
Serial Peripheral Interface (SPI) module synchronous serial interface communicating with other peripheral microcontroller devices such serial EEPROMs, shift registers, display drivers, ADC, etc. compatible with Motorola® SIOP interfaces. This module includes modes. Frame Synchronization mode also included support voice band codecs. Four pins make serial interface: SDI, Serial Data Input; SDO, Serial Data Output; SCK, Shift Clock Input Output; Active-Low Slave Select, which also serves FSYNC (Frame Synchronization Pulse). device master provides serial communication clock signal pin. series clock pulses (depending mode) shift bits (depending whether byte word being transferred) simultaneously shift bits data from pin. interrupt generated when transfer complete. Slave select synchronization allows selective enabling slave devices, which particularly useful when single master connected multiple slaves. SPI1 SPI2 modules support data transfers.
Output Compare/PWM Module
output compare module features quite useful applications that require controlled timing pulses modulated pulse streams. output compare module ability compare value selected time base with value compare registers (depending operation mode selected). Furthermore, ability generate single output pulse, repetitive sequence output pulses, compare match event. Like most PIC24H peripherals, also ability generate interrupts compare match events.
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UART Module
UART full-duplex asynchronous system that communicate with peripheral devices, such personal computers, RS-232 RS-485 interfaces. PIC24H devices have more UARTs. features UART module are: Full-duplex operation with 9-bit data Even, parity options (for 8-bit data) Stop bits Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates range from Mbps down MIPS 4-character deep transmit data buffer 4-character deep receive data buffer Parity, framing buffer overrun error detection Full IrDA® support, including hardware encoding decoding IrDA® messages support Auto wake-up from Sleep Idle mode Start detect Auto-baud detection Break character support Support interrupt address detect (9th Separate transmit receive interrupts transmission characters reception characters Loopback mode diagnostics
Controller Area Network (CAN) Module
Controller Area Network (CAN) module serial interface useful communicating with other modules microcontroller devices. This interface/ protocol designed allow communications within noisy environments. module communication controller implementing protocol, defined BOSCH specification. module supports 1.2, 2.0A, 2.0B Passive 2.0B Active versions protocol. Details these protocols found BOSCH specification. module features: Implementation protocol 1.2, 2.0A 2.0B Standard extended data frames Data lengths bytes Programmable rate Mbit/sec Automatic response remote frames receive buffers FIFO Buffer mode messages deep) full (standard/extended identifier) acceptance filters full acceptance filter masks transmit buffers used transmission reception Programmable wake-up functionality with integrated low-pass filter Programmable Loopback mode supports self-test operation Signaling interrupt capabilities receiver transmitter error states Programmable clock source Programmable link timer module time-stamping network synchronization Low-power Sleep Idle mode module consists protocol engine message buffering/control. protocol engine handles functions receiving transmitting messages bus. Messages transmitted first loading appropriate data registers. Status errors checked reading appropriate registers. message detected checked errors then matched against filters should received stored receive registers.
UART1 UART2 modules support data transfers.
Module
Inter-Integrated Circuit (I2C) module synchronous serial interface, useful communicating with other peripheral microcontroller devices. These peripheral devices serial EEPROMs, shift registers, display drivers, ADC, etc. module offers full hardware support both slave multi-master operations. features module are: slave operation supports 10-bit address master operation supports 10-bit address port allows bidirectional transfers between master slaves Serial clock synchronization port used handshake mechanism suspend resume serial transfer (serial clock stretching) supports multi-master operation; detects collision will arbitrate accordingly Slew rate control speeds mode, clock data. module will override data direction bits these pins.
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Pins
pins have following features: Schmitt Trigger input CMOS output drivers Weak internal pull-up pins configured digital inputs accept signals. This provides degree compatibility with external signals different voltage levels. However, digital outputs analog pins only generate voltage levels 3.6V. input change notification module gives PIC24H devices ability generate interrupt requests processor response change state selected input pins. This module capable detecting input changes state, even Sleep mode, when clocks disabled. There external signals (CN0 through CN23) that selected (enabled) generating interrupt request change state. Each pins also optional weak pull-up feature. Some pins functions multiplexed with alternate function peripheral features device. general, when peripheral enabled, that used general-purpose pin. port pins have three registers directly associated with operation port pin. Data Direction register determines whether input output. Port Data Latch register provides latched output data pins. Port register provides visibility logic state pins. Reading Port register provides logic state, while writes Port register write data Port Data Latch register. port pins have latch bits (Port Data Latch register). This register, when read, yields contents latch when written, modifies contents latch, thus modifying value driven corresponding Data Direction register configured output. This used read-modify-write instructions that allow user modify contents Port Data Latch register, regardless status corresponding pins.
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PIC24H INSTRUCTION
Introduction
9.2.1
MULTI-CYCLE INSTRUCTIONS
PIC24H instruction provides broad suite instructions which supports traditional microcontroller applications, class instructions which supports math-intensive applications. Since almost functionality PICmicro instruction been maintained, this hybrid instruction allows friendly migration path users already familiar with PICmicro microcontroller.
instruction summary tables show, most instructions execute single cycle with following exceptions: Instructions MOV.D, POP.D, PUSH.D, TBLRDH, TBLRDL, TBLWTH TBLWTL require cycles execute. Instructions DIVF, DIV.S, DIV.U singlecycle instructions, which should executed consecutive times target REPEAT instruction. Instructions that change Program Counter also require cycles execute, with extra cycle executed NOP. Skip instructions, which skip over 2-word instruction, require instruction cycles execute with cycles executed NOP. RETFIE, RETLW RETURN special cases instructions that change Program Counter. These execute cycles unless exception pending, then they execute cycles. Note: Instructions that access program memory data, using Program Space Visibility, incur some cycle count overhead.
Instruction Overview
PIC24H instruction contains instructions which grouped into functional categories shown Table 9-1. Table defines symbols used instruction summary tables, Table through Table 9-11. These tables define syntax, description, storage execution requirements each instruction. Storage requirements represented 24-bit instruction words execution requirements represented instruction cycles. Most instructions have several different addressing modes execution flows which require different instruction variants. instance, there unique instructions each instruction variant instruction encoding.
9.2.2
MULTI-WORD INSTRUCTIONS
TABLE 9-1:
PIC24H INSTRUCTION GROUPS
Summary Table Table Table Table Table Table Table Table Table 9-10 Table 9-11
Functional Group Move Instructions Math Instructions Logic Instructions Rotate/Shift Instructions Instructions Compare/Skip Instructions Program Flow Instructions Shadow/Stack Instructions Control Instructions
instruction summary tables show, almost instructions consume instruction word bits), with exception CALL GOTO instructions, which flow instructions listed Table 9-9. These instructions require words memory because their opcodes embed large literal operands.
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TABLE 9-2:
Symbol bit4 Expr lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 Slit4 Slit6 Slit10 Slit16 Wm*Wm Wm*Wn WREG Literal operand designation 4-bit wide position (0:15) Absolute address, label expression (resolved linker) File register address 1-bit literal (0:1) 4-bit literal (0:15) 5-bit literal (0:31) 8-bit literal (0:255) 10-bit literal (0:255 Byte mode, 0:1023 Word mode) 14-bit literal (0:16383) 16-bit literal (0:65535) 23-bit literal (0:8388607) Signed 4-bit literal (-8:7) Signed 6-bit literal (-16:16) Signed 10-bit literal (-512:511) Signed 16-bit literal (-32768:32767) Top-of-Stack Base working register Destination working register (direct indirect addressing) Working register divide pair (dividend, divisor) Working register multiplier pair (same source register) Working register multiplier pair (different source registers) Both source destination working register (direct addressing) Destination working register (direct addressing) Source working register (direct addressing) Default working register Source working register (direct indirect addressing)
SYMBOLS USED SUMMARY TABLES
Description
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TABLE 9-3:
Assembly EXCH MOV.b MOV.D MOV.D SWAP TBLRDH TBLRDL TBLWTH TBLWTL Note:
MOVE INSTRUCTIONS
Syntax Wns,Wnd {,WREG} WREG,f f,Wnd Wns,f #lit8,Wnd #lit16,Wnd [Ws+Slit10],Wnd Wns,[Wd+Slit10] Ws,Wd Ws,Wnd Wns,Wd Ws,Wd Ws,Wd Ws,Wd Ws,Wd Description Swap Move destination Move WREG Move Move Move 8-bit literal Move 16-bit literal Move signed 10-bit offset] Move signed 10-bit offset] Move Move double Wnd:Wnd Move double Wns:Wns byte nibble swap Read high program word Read program word Write high program word Write program word Words Cycles
When optional {,WREG} operand specified, destination instruction WREG. When {,WREG} specified, destination instruction file register
Note:
Table through Table 9-11 present base instruction syntax PIC24H. These instructions include available addressing modes. example, some instructions show Byte Addressing mode others not.
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TABLE 9-4:
Assembly ADDC ADDC ADDC ADDC DAW.B DEC2 DEC2 DIV.S DIV.SD DIV.U DIV.UD DIVF INC2 INC2 MUL.SS MUL.SU MUL.SU MUL.US MUL.UU MUL.UU SUBB SUBB SUBB SUBB SUBBR SUBBR
MATH INSTRUCTIONS
Syntax {,WREG} #lit10,Wn Wb,#lit5,Wd Wb,Ws,Wd {,WREG} #lit10,Wn Wb,#lit5,Wd Wb,Ws,Wd {,WREG} Ws,Wd {,WREG} Ws,Wd Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wm,Wn {,WREG} Ws,Wd {,WREG} Ws,Wd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,Ws,Wnd Ws,Wnd {,WREG} #lit10, Wb,#lit5,Wd Wb,Ws,Wd {,WREG} #lit10, Wb,#lit5,Wd Wb,Ws,Wd {,WREG} Wb,#lit5,Wd Description Destination WREG lit10 lit5 Destination WREG lit10 lit5 decimal adjust Destination Destination Signed 16/16-bit integer divide* Signed 32/16-bit integer divide* Unsigned 16/16-bit integer divide* Unsigned 32/16-bit integer divide* Signed 16/16-bit fractional divide* Destination Destination W3:W2 WREG {Wnd 1,Wnd} sign(Wb) sign(Ws) {Wnd 1,Wnd} sign(Wb) unsign(lit5) {Wnd 1,Wnd} sign(Wb) unsign(Ws) {Wnd 1,Wnd} unsign(Wb) sign(Ws) {Wnd 1,Wnd} unsign(Wb) unsign(lit5) {Wnd 1,Wnd} unsign(Wb) unsign(Ws) sign-extended Destination WREG lit10 lit5 Destination WREG lit10 lit5 Destination WREG lit5 Words Cycles
SUBBR Wb,Ws,Wd SUBR {,WREG} Destination WREG SUBR Wb,#lit5,Wd lit5 SUBR Wb,Ws,Wd Ws,Wnd zero-extended Divide instructions interruptible cycle-by-cycle basis. Also, divide instructions must accompanied REPEAT instruction, which adds extra cycle.
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TABLE 9-5:
Assembly SESESEXOR Note:
LOGIC INSTRUCTIONS
Syntax {,WREG} #lit10,Wn Wb,#lit5,Wd Wb,Ws,Wd WREG {,WREG} Ws,Wd {,WREG} #lit10,Wn Wb,#lit5,Wd Wb,Ws,Wd {,WREG} Ws,Wd WREG {,WREG} #lit10,Wn Wb,#lit5,Wd Wb,Ws,Wd Description Destination .AND. WREG lit10 .AND. .AND. lit5 .AND. 0x0000 WREG 0x0000 0x0000 Destination Destination .IOR. WREG lit10 .IOR. .IOR. lit5 .IOR. Destination 0xFFFF WREG 0xFFFF 0xFFFF Destination .XOR. WREG lit10 .XOR. .XOR. lit5 .XOR. Words Cycles
When optional {,WREG} operand specified, destination instruction WREG. When {,WREG} specified, destination instruction file register
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TABLE 9-6:
Assembly RLNC RLNC RRNC RRNC Note:
ROTATE/SHIFT INSTRUCTIONS
Syntax {,WREG} Ws,Wd Wb,#lit4,Wnd Wb,Wns,Wnd {,WREG} Ws,Wd Wb,#lit4,Wnd Wb,Wns,Wnd {,WREG} Ws,Wd {,WREG} Ws,Wd {,WREG} Ws,Wd {,WREG} Ws,Wd {,WREG} Ws,Wd Wb,#lit4,Wnd Wb,Wns,Wnd Description Destination arithmetic right shift arithmetic right shift arithmetic right shift lit4 arithmetic right shift Destination logical right shift logical right shift logical right shift lit4 logical right shift Destination rotate left through Carry rotate left through Carry Destination rotate left Carry) rotate left Carry) Destination rotate right through Carry rotate right through Carry Destination rotate right Carry) rotate right Carry) Destination left shift left shift left shift lit4 left shift Words Cycles
When optional {,WREG} operand specified, destination instruction WREG. When {,WREG} specified, destination instruction file register
TABLE 9-7:
Assembly BCLR BCLR BSET BSET BSW.C BSW.Z BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS.C BTSTS.Z FBCL FF1L FF1R Note:
INSTRUCTIONS
Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wnd Ws,Wnd Ws,Wnd clear clear Write Ws<Wb> Write Ws<Wb> toggle toggle test test test test Ws<Wb> test Ws<Wb> test then test then test then Find change from left (MSb) side Find first from left (MSb) side Find first from right (LSb) side Description Words Cycles
positions specified bit4 (0:15) word operations.
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TABLE 9-8:
BTSC BTSC BTSS BTSS CPSEQ CPSGT CPSLT CPSNE Note
COMPARE/SKIP INSTRUCTIONS
Description test skip clear test skip clear test skip test skip Compare WREG) Compare lit5) Compare Compare 0x0000) Compare 0x0000) Compare with Borrow WREG Compare with Borrow lit5 Compare with Borrow Compare with Skip Equal Signed Compare with Skip Greater Than Signed Compare with Skip Less Than Signed Compare with Skip Equal Words Cycles f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Wb,#lit5 Wb,Ws Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn
Assembly Syntax
positions specified bit4 (0:15) word operations. Conditional skip instructions execute cycle skip taken, cycles skip taken over one-word instruction cycles skip taken over two-word instruction.
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TABLE 9-9:
Assembly CALL CALL GOTO GOTO RCALL RCALL REPEAT REPEAT RETFIE RETLW RETURN Note #lit10,Wn
PROGRAM FLOW INSTRUCTIONS
Syntax Expr C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OA,Expr OB,Expr OV,Expr SA,Expr SB,Expr Z,Expr Expr Expr Expr #lit14 Computed branch Branch Carry Borrow) Branch greater than equal Branch unsigned greater than equal Branch greater than Branch unsigned greater than Branch less than equal Branch unsigned less than equal Branch less than Branch unsigned less than Branch Negative Branch Carry (Borrow) Branch Negative Branch Overflow Branch Zero Branch Accumulator Overflow Branch Accumulator Overflow Branch Overflow Branch Accumulator Saturate Branch Accumulator Saturate Branch Zero Call subroutine Call indirect subroutine address address indirectly Relative call Computed call Repeat next instruction (lit14 times Repeat next instruction times Return from interrupt enable Return with lit10 Return from subroutine Description Branch unconditionally Words Cycles
Conditional branch instructions execute cycle branch taken, cycles branch taken. RETURN normally executes cycles; however, executes cycles interrupt pending.
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TABLE 9-10:
Assembly POP.D POP.S PUSH PUSH PUSH.D PUSH.S ULNK
SHADOW/STACK INSTRUCTIONS
Description Link Frame Pointer Double from Wnd:Wnd shadow registers Push Push Push double Wns:Wns Push shadow registers Unlink Frame Pointer Words Cycles
Syntax #lit14
TABLE 9-11:
Assembly CLRWDT DISI NOPR PWRSAV RESET
CONTROL INSTRUCTIONS
Description Clear Watchdog Timer Words Cycles
Syntax
#lit14
Disable interrupts (lit14 instruction cycles operation operation
#lit1
Enter Power-Saving mode lit1 Software device Reset
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10.0 MICROCHIP DEVELOPMENT TOOL SUPPORT
Microchip offers comprehensive development tools libraries support dsPIC30F, dsPIC33F PIC24H architectures. addition, company partnering with many third party tools manufacturers additional device support. Table 10-1 lists development tools that support PIC24H family. paragraphs that follow describe each tools more detail.
TABLE 10-1:
PIC24H DEVELOPMENT TOOLS
Development Tool Description Integrated Development Environment Part SW007002 From Microchip
MPLAB® (see Section 10.1 MPLAB Integrated Development Environment Software) Essential Software Tools MPLAB ASM30 (see Section 10.2 MPLAB ASM30 Assembler/Linker/Librarian) MPLAB (see Section 10.3 MPLAB Software Simulator) MPLAB (see Section 10.4 MPLAB Visual Device Initializer) MPLAB (see Section 10.5 MPLAB Compiler/Linker/Librarian) Essential Hardware Tools MPLAB (see Section 10.6 MPLAB In-Circuit Debugger) MPLAB (see Section 10.7 MPLAB Universal Device Programmer) Determined
Assembler (included MPLAB IDE)
SW007002
Microchip
Software Simulator (Included MPLAB IDE)
SW007002
Microchip
Visual Device Initializer PIC24H (included MPLAB IDE) ANSI Compiler, Assembler, Linker Librarian
SW007002
Microchip
SW006012
Microchip
In-Circuit Debugger Device Programmer
DV164005
Microchip
Full-Featured Device Programmer, Base Unit Socket Module 100L TQFP Devices Socket Module TQFP Devices Socket Module TQFP Devices
DV007004
Microchip Microchip Microchip Microchip
Legend:
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10.1 MPLAB Integrated Development Environment Software
Context sensitive, interactive on-line help Integrated MPLAB instruction simulator User interface MPLAB PICSTART® Plus device programmers (sold separately) User interface MPLAB In-Circuit Debugger (sold separately) MPLAB allows: Editing source files either assembly One-touch compiling downloading dsPIC emulator simulator Debugging using: Source files Machine code Mixed mode source machine code ability MPLAB with multiple development debugging targets provides easy transition from cost-effective simulator MPLAB full-featured emulator with minimal retraining.
MPLAB Integrated Development Environment (IDE) available cost. MPLAB lets user edit, compile emulate from single user interface, depicted Figure 10-1. Code designed developed dsPIC devices same design environment PICmicro microcontrollers. MPLAB 32-bit Windows® operating system-based application that provides many advanced features demanding engineer modern, easy-to-use interface. MPLAB integrates: Full-featured, color coded text editor Easy project manager with visual display Source level debugging Enhanced source level debugging (structures, automatic variables, etc.) Customizable toolbar mapping Dynamic status displays processor condition
FIGURE 10-1:
MPLAB® DESKTOP
Powerful Project Manager handles multiple projects file types
break/trace points with click mouse
Color keyed editor makes source code debug easier
Simply move your mouse over variable view modify
Fully customizable watch windows view modify registers memory locations Status updates single step
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10.2 MPLAB ASM30 Assembler/Linker/ Librarian 10.4 MPLAB Visual Device Initializer
MPLAB Visual Device Initializer (VDI) simplifies task configuring PIC24H. MPLAB software allows configure entire processor graphically (see Figure 10-2). when you're done, mouse click generates your code assembly code. MPLAB performs extensive error checking assignments conflicts pins, memories interrupts, well selection operating conditions. Generated code files integrated seamlessly with rest application code through MPLAB Project. Detailed resource assignment configuration reports simplify project documentation. features MPLAB include: Drag-and-drop feature selection click configuration Extensive error checking Generates initialization code form callable assembly function Integrates seamlessly MPLAB Project Printed reports ease project documentation requirements MPLAB Visual Device Initializer MPLAB plug-in installed independently MPLAB
MPLAB ASM30 full-featured macro assembler. User-defined macros, conditional assembly variety assembler directives make MPLAB ASM30 powerful code generation tool. accompanying MPLAB LINK30 Linker MPLAB LIB30 Librarian modules allow efficient linking, library creation maintenance. Notable features assembler include: Support entire dsPIC instruction Support fixed-point floating-point data Available Windows operating system Command Line Interface Rich Directive Flexible Macro Language MPLAB compatibility
Notable features linker include: Automatic user-defined stack allocation Supports dsPIC Program Space Visibility (PSV) window Available Windows operating systems Command Line Interface Linker scripts dsPIC devices MPLAB compatibility
FIGURE 10-2:
MPLAB® DISPLAY
10.3
MPLAB Software Simulator
MPLAB software simulator provides code development PIC24H family PC-hosted environment simulating PIC24H device instruction level. instruction, examine modify data areas apply stimuli pins from file pressing user-defined key. execution performed Single-Step, Execute-Until-Break Trace mode. MPLAB software simulator fully supports symbolic debugging using MPLAB compiler assembler. software simulator gives flexibility develop debug code outside laboratory environment, making excellent multi-project software development tool. Complex stimuli injected from files, synchronous clocks user-defined keys. Output files register activity sophisticated post analysis. Besides modeling behavior CPU, MPLAB also supports following peripherals: Timers Input Capture 12-Bit 10-Bit Motor Control UART Ports Program Flash
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10.5 MPLAB Compiler/Linker/ Librarian
MPLAB these characteristics: 16-bit native data types Efficient register-based, 3-operand instructions Complex addressing modes Efficient multi-bit shift operations Efficient signed/unsigned comparisons MPLAB comes complete with assembler, linker librarian. These allow Mixed mode assembly programs link resulting object files into single executable file. compiler sold separately. assembler, linker librarian available free with MPLAB C30. MPLAB also includes Math Library, Peripheral Library standard libraries.
Microchip Technology MPLAB Compiler provides language support PIC24H family. This compiler fully ANSI-compliant product with standard libraries. highly optimized PIC24H family takes advantage many PIC24H architecture-specific features help generate very efficient software code. Figure 10-3 illustrates code size efficiency relative several competitors. MPLAB also provides extensions that allow excellent support hardware, such interrupts peripherals. fully integrated with MPLAB high-level source debugging.
FIGURE 10-3:
RELATIVE CODE SIZE BYTES)
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PIC24H
10.6 MPLAB In-Circuit Debugger
MPLAB In-Circuit Debugger powerful, low-cost, run-time development tool that uses in-circuit debugging capability built into PIC24H Flash devices. This feature, along with Microchip's In-Circuit Serial Programming(ICSPTM) protocol, gives cost-effective, in-circuit debugging from graphical user interface MPLAB IDE. lets develop debug source code watching variables, singlestepping setting breakpoints, well running full speed test hardware real time. MPLAB these features: Full-speed operation range device Serial connector USB-powered from interface noise power (VPP VDD) with analog other noise sensitive applications Operation down 2.0V used debugger inexpensive serial programmer Some device resources required bytes pins) MPLAB programmer designed with programmable socket pins therefore, each socket module configured support many different devices. result, fewer socket modules required support entire line Microchip parts. socket modules multi-pin connectors high reliability quick interchange. When connected host system, MPLAB programmer seamlessly integrated with MPLAB Integrated Development Environment (IDE), providing user-friendly programming interface. features MPLAB Programmer include: RS-232 interface Integrated In-Circuit Serial Programming (ICSP) interface Fast programming time Three operating modes: Host mode full control Safe mode secure data Stand-Alone mode programming without Complete line interchangeable socket modules support Microchip devices package options (sold separately) SQTPSM serialization programming unique serial numbers while Host mode. alternate command line interface batch control Large easy-to-read display Field upgradeable firmware allows quick device support Secure Digital (SD) Multimedia Card (MMC) external memory support Buzzer notification noisy environments
FIGURE 10-4:
MPLAB® IN-CIRCUIT DEBUGGER
FIGURE 10-5:
MPLAB® DEVICE PROGRAMMER
10.7
MPLAB Universal Device Programmer
MPLAB Universal Device Programmer easy with stand-alone unit, program Microchip's entire line PICmicro devices well latest PIC24H devices. MPLAB features large bright unit (128 pixels) display easy menus, programming statistics status information. MPLAB programmer exceptional programming speed high production throughput, especially important large memory devices. also includes Secure Digital/Multimedia Card slot easy secure data storage transfer.
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11.0 PIC24H DEVELOPMENT TOOLS APPLICATION LIBRARIES
Table 11-1 summarizes available planned PIC24H software tools libraries. Microchip also provides value added services, such skilled/certified technical application contacts, reference designs hardware software developers. (Contact Microchip DSCD Marketing availability.)
Microchip offers comprehensive tools libraries help with rapid development PIC24H device-based application(s).
TABLE 11-1:
MICROCHIP SOFTWARE DEVELOPMENT TOOLS APPLICATION LIBRARIES
Description Double Precision Floating-Point Library (ASM, Wrapper) Peripheral Initialization, Control Utility Routines Part SW300020 SW300021 SW300023
Development Tool Math Library (see Section 11.1 Math Library) Peripheral Library (see Section 11.2 Peripheral Driver Library)
dsPICworksTool (see Section 11.3 Graphical Data Analysis Conversion Tool Algorithms dsPICworksData Analysis Tool Software) TCP/IP Library (see Section 11.4 Microchip TCP/IP Connectivity Protocol Support TCP/IP Stack)
SW300024
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11.1 Math Library
TABLE 11-2:
PIC24H Math Library compiled version math library that distributed with highly optimized, ANSI-compliant PIC24H MPLAB Compiler (SW006012). contains advanced single doubleprecision floating-point arithmetic trigonometric functions from standard header file (math.h). library delivers small program code size data size, reduced cycles high accuracy. Features math library callable from either MPLAB PIC24H assembly language. functions IEEE-754 compliant, with signed zero, signed infinity, (Not Number) denormal support operated "Round Nearest" mode. Compatible with MPLAB ASM30 MPLAB LINK30, which available charge from Microchip's site. Table 11-2 shows memory usage performance Math Library. Table 11-3 lists math functions that included.
MEMORY USAGE PERFORMANCE
5250
Memory Usage (bytes)(1,2) Code size Data size
Performance (cycles)(1,3) sqrt Note Results based using PIC24H MPLAB Compiler (SW006012), version 1.20. Maximum "Memory Usage" when functions library loaded. Most applications will less. Average 32-bit floating-point performance results.
TABLE 11-3:
MATH FUNCTIONS
Single Double-Precision Floating-Point Functions add, subtract, multiply, divide, remainder pow, sqrt acos, asin, atan, atan2, cos, cosh, sin, sinh, tan, tanh exp, log, log10, frexp, ldexp ceil, floor fabs fmod, modf comparison, integer floating-point conversions
Arithmetic Functions Root Power Functions Trigonometric Hyperbolic Functions Logarithmic Exponential Functions Rounding Functions Absolute Value Functions Modular Arithmetic Functions Comparison Conversions
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11.2 Peripheral Driver Library 11.3
Microchip offers free peripheral driver library that supports setup control PIC24H hardware peripherals, including, limited Analog-to-Digital Converter UART General-purpose Timers Input Capture Output Compare/Simple Ports External Interrupts Reset
dsPICworksData Analysis Tool Software
dsPICworks tool free data analysis signal processing package with Microsoft® Windows® Windows NT®, Windows 2000 Windows platforms. provides extensive number functions encompassing: Wide variety Signal Generators Sine, Square, Triangular, Window Functions, Noise Extensive Functions FFT, DCT, Filtering, Convolution, Interpolation Extensive Arithmetic Functions Algebraic Expressions, Data Scaling, Clipping, etc. 1-D, Displays Multiple Data Quantization Saturation Options Multi-Channel Data Support Automatic "Script File"-based Execution Options available user-defined sequence dsPICworks Tool Functions File Import/Export interoperable with MPLAB Digital Filtering Options support Filters generated dsPIC Filter Design ASM30 Assembler File Option export Data Tables into PIC24H
addition hardware peripherals, library supports software generated peripherals, such standard drivers, which support Hitachi style controller. peripheral library consist more than functions, well several macros simple tasks such enabling disabling interrupts. peripheral driver routines developed optimized using MPLAB Compiler. Electronic documentation accompanies peripheral library help become familiar with implement library functions. features PIC24H Peripheral Library include: library file each individual device from PIC24H family, including functions corresponding peripherals present that particular device. include files that take advantage predefined constants passing parameters various library functions. There include file each peripheral module. Since functions form precompiled libraries, they called from user application program written either MPLAB Compiler PIC24H assembly language. Included source code allows customize peripheral functions suit your specific application requirements. Predefined constants include files eliminate need refer details structure every Special Function Register while initializing peripherals checking status bits.
FIGURE 11-1:
dsPICworksDATA
ANALYSIS TOOL SOFTWARE
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PIC24H
11.3.1 SIGNAL GENERATION 11.3.4
dsPICworks Data Analysis Tool Software support extensive signal generators, including basic sine, square triangle wave generators, well advanced generators window functions, unit step, unit sample, sine, exponential noise functions. Noise, with specified distribution, added signal. Signals generated 32-bit floating-point, 16-bit fractional fixed-point values, desired sampling rate. length generated signal limited only available disk space. Signals imported exported from MPLAB file register windows. Multi-channel data created multiplexing functions.
FILE IMPORT/EXPORT MPLAB MPLAB ASM30 SUPPORT
dsPICworks Data Analysis Tool Software allow data imported from external world form ASCII text binary files. Conversely, also allows data exported form files. dsPICworks tool supports file formats supported MPLAB import/export table. This feature allows user bring real-world data from MPLAB into dsPICworks tool analysis. dsPICworks tool also create ASM30 assembler files that included into MPLAB workspace.
11.4
Microchip TCP/IP Stack
11.3.2
DIGITAL SIGNAL PROCESSING (DSP) ARITHMETIC OPERATIONS
dsPICworks Data Analysis Tool Software have wide range arithmetic functions that applied signals. Standard functions include transform operations: DCT, convolution correlation, signal decimation, signal interpolation sample rate conversion digital filtering. Digital filtering important part dsPICworks tool. uses filters designed sisterapplication, dsPIC Filter Design, applies them synthesized imported signals. dsPICworks tool also features special operations, such signal clipping, scaling quantization, which vital real practical analysis algorithms.
free Microchip TCP/IP Stack suite programs that provide services standard (HTTP Server, Mail Client, etc.) custom TCP/IP-based applications. Users need expert TCP/IP specifications only need specific knowledge TCP/IP accompanying HTTP Server application. This stack implemented modular fashion, with services creating highly abstracted layers, each layer accessing services from more layers directly below stack optimized size designed PIC24H using dsPICDEM.netDevelopment Board; however, easily retargeted hardware equipped with PIC24H. HTML pages generated PIC24H viewed with standard browser such Microsoft Internet Explorer. features Microchip TCP/IP Stack include: Out-of-box support Microchip Compiler Implements complete state machine Multiple sockets with simultaneous connection/management Includes modules supporting various standard protocols: MAC, SLIP, ARP, ICMP, TCP, SNMP, UDP, DHCP, FTP, Gleaning, HTTP, MPFS (Microchip File System) used part HTTP Server (included) custom TCP/IP-based application RTOS independent
11.3.3
DISPLAY MEASUREMENT
dsPICworks Data Analysis Tool Software have wide variety display measurement options. Frequency domain data plotted form 2-dimensional `spectrogram' 3-dimensional `waterfall' options. signals measured accurately simple mouse click. window shows current cursor coordinates, well derived values, such difference from last position signal frequency. Signal strength measured over particular range frequencies. Special support also exists displaying multi-channel multiplexed data. Graphs allow zoom options. user choose from color scheme options customize display settings.
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12.0 THIRD PARTY DEVELOPMENT TOOLS APPLICATION LIBRARIES
Besides providing development tools application libraries PIC24H products, Microchip also partners with third party tool manufacturers develop quality hardware software tools support PIC24H product family. Details various third party development tools will provided shortly.
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13.0 PIC24H HARDWARE DEVELOPMENT BOARDS
In-Circuit Debugger (ICD tool cost-effective debugging programming PIC24H devices. These boards shown Table 13-1. Microchip plans offer additional hardware development boards support PIC24H product family. Contact Microchip DSCD Marketing additional information.
Microchip initially offers hardware development boards that help quickly prototype validate aspects your design. Each board features various PIC24H peripherals supports Microchip's MPLAB
TABLE 13-1:
Development Boards Reference Designs
HARDWARE DEVELOPMENT BOARDS
Description dsPICDEM80-Pin Starter Development Board Explorer Development Board Part DM300019 DM240001 From Microchip Microchip
Development Tool General-purpose Development Board
Plug-in Samples
Plug-in Sample (see Section 13.3 Plug-in Modules) Acoustic Accessory (see Section 13.3 Plug-in Modules)
board with 100-pin PIC24H sample; with DM240001 development board. board with 100-pin PIC24H sample; with DM300019 development board. Accessory includes: audio cable, headset, oscillators, microphone, speaker, RS-232 cable, DB9M-DB9M Null Modem Adapter used library evaluation.
AC300030
Microchip Microchip Microchip
Accessory Kits
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PIC24H
13.1 dsPICDEM80-Pin Starter Development Board 13.2 Explorer Development Board
This development board offers very economical evaluate both PIC24H General-purpose Motor Control Family devices, well PIC24F devices. This board ideal prototyping tool help quickly develop validate design requirements. Some features attributes Explorer Development Board include: Includes 100-pin PIC24H plug-in module Includes 100-pin PIC24 plug-in module Power input from supply Modular design plug-in demonstration boards, expansion header JTAG connection reprogramming protocol translation support through PIC18F4450 RS-232 connection with firmware driver support bank general indication Serial EEPROM alphanumeric Temperature sensor Terminal interface program menu programs
This development board offers very economical evaluate both dsPIC30F PIC24H Generalpurpose Motor Control Family devices. This board ideal prototyping tool help quickly develop validate design requirements. Some features attributes dsPICDEM 80-Pin Starter Development Board include: Includes 80-pin dsPIC30F6014A plug-in module (MA300014) Power input from supply Selectable voltage regulator outputs 3.3V LEDs, switches, potentiometer, UART interface input filter circuit speech band signal input On-board filter speech band signal output Circuit prototyping area Assembly language demonstration program tutorial accommodate 80-pin adapter PIC24H plug-in module
FIGURE 13-1:
dsPICDEM80-PIN STARTER DEVELOPMENT BOARD
FIGURE 13-2:
EXPLORER DEVELOPMENT BOARD
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13.3 Plug-in Modules 13.4 Acoustic Accessory
various PIC24H development boards plug-in modules PIC24H silicon devices. Since boards contain device header pins PCB, they also used provide flexibility replacement PIC24H silicon. Plug-in sample types will provided, supporting 64-pin 100pin TQFP package types General-purpose device samples. plug-in samples considered interim development board mechanization. Acoustic Accessory includes following accessories targeted towards acoustics-oriented application development support: Stereo Audio Cable Stereo Headset 14.7456 Oscillators Clip-on Microphone Fold-up Speaker RS-232 Cable DB9M-DB9M Null Modem Adapter
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APPENDIX DEVICE PINOUTS FUNCTIONS GENERALPURPOSE FAMILY
Table provides brief description device pinouts functions that multiplexed port pin. Multiple functions exist port pin. When multiplexing occurs, peripheral module's functional requirements force override data direction port pin.
TABLE A-1:
Name AN0-AN31 AVDD AVSS CLKI CLKO
PINOUT DESCRIPTIONS GENERAL-PURPOSE FAMILY
Type Input Buffer Type Analog ST/CMOS Analog input channels. Positive supply analog module. Ground reference analog module. External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. Input change notification inputs. software programmed internal weak pull-ups inputs. Data Converter Interface frame synchronization pin. Data Converter Interface serial clock input/output pin. Data Converter Interface serial data input pin. Data Converter Interface serial data output pin. ECAN1 receive pin. ECAN1 transmit pin. ECAN2 receive pin. ECAN2 transmit pin. Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Capture inputs through External interrupt External interrupt External interrupt External interrupt External interrupt Master Clear (Reset) input programming voltage input. This active-low Reset device. Compare Fault input (for Compare Channels Compare Fault input (for Compare Channels Compare outputs through Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. PORTA bidirectional port. Description
CN0-CN23 COFS CSCK CSDI CSDO C1RX C1TX C2RX C2TX PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3 IC1-IC8 INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OC1-OC8 OSC1 OSC2 RA0-RA7 RA9-RA10 RA12-RA15 RB0-RB15 Legend:
ST/CMOS
PORTB bidirectional port.
CMOS CMOS compatible input output; Analog Analog input Schmitt Trigger input with CMOS levels; Output; Input; Power
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TABLE A-1:
Name RC1-RC4 RC12-RC15 RD0-RD15 RE0-RE9 RF0-RF8 RF12-RF13 RG0-RG3 RG6-RG9 RG12-RG15 SCK1 SDI1 SDO1 SCK2 SDI2 SDO2 SCL1 SDA1 SCL2 SDA2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDDCORE VREF+ VREFLegend:
PINOUT DESCRIPTIONS GENERAL-PURPOSE FAMILY (CONTINUED)
Type Input Buffer Type ST/CMOS Analog Analog Description PORTC bidirectional port. PORTD bidirectional port. PORTE bidirectional port. PORTF bidirectional port. PORTG bidirectional port.
Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization. Synchronous serial clock input/output SPI2. SPI2 data SPI2 data out. SPI2 slave synchronization. Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. Synchronous serial clock input/output I2C2. Synchronous serial data input/output I2C2. low-power oscillator crystal input; CMOS otherwise. low-power oscillator crystal output. JTAG Test mode select pin. JTAG test clock input/output pin. JTAG test data input pin. JTAG test data output pin. Timer1 external clock Timer2 external clock Timer3 external clock Timer4 external clock Timer5 external clock Timer6 external clock Timer7 external clock Timer8 external clock Timer9 external clock input. input. input. input. input. input. input. input. input.
UART1 clear send. UART1 ready send. UART1 receive. UART1 transmit. UART2 clear send. UART2 ready send. UART2 receive. UART2 transmit. Positive supply peripheral logic pins. logic filter capacitor connection. Ground reference logic pins. Analog voltage reference (high) input. Analog voltage reference (low) input.
CMOS CMOS compatible input output; Analog Analog input Schmitt Trigger input with CMOS levels; Output; Input; Power
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Diagrams (Continued)
64-Pin TQFP
RG13 RG12 RG14 VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0
PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ256GP206
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
Note:
PIC24HJ64GP206 device does have SCL2 SDA2 pins.
2005 Microchip Technology Inc.
PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/CN17/RF4 U2TX/CN18/RF5
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Diagrams (Continued)
64-Pin TQFP
RG13 RG12 RG14 VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0
PIC24HJ128GP306
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5
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Diagrams (Continued)
64-Pin TQFP
CSDO/RG13 CSDI/RG12 CSCK/RG14 C1TX/RF1 C1RX/RF0 VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
COFS/RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0
PIC24HJ64GP506 PIC24HJ128GP506
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
2005 Microchip Technology Inc.
PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5
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Diagrams (Continued)
100-Pin TQFP
AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 TMS/RA0 AN20/INT1/RE8 AN21/INT2/RE9 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ256GP210
PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5
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Diagrams (Continued)
100-Pin TQFP
AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C1TX/RF1 C1RX/RF0 VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 TMS/RA0 AN20/INT1/RE8 AN21/INT2/RE9 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24HJ64GP510 PIC24HJ128GP510
2005 Microchip Technology Inc.
PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5
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Diagrams (Continued)
100-Pin TQFP
AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 TMS/RA0 AN20/INT1/RE8 AN21/INT2/RE9 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24HJ256GP610
PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5
DS70166A-page
2005 Microchip Technology Inc.
PIC24H
NOTES:
2005 Microchip Technology Inc.
DS70166A-page
WORLDWIDE SALES SERVICE
AMERICAS
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08/24/05
DS70166A-page
2005 Microchip Technology Inc.
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