File Number 4897 16A, 100V, 0.090 Ohm, N-Channel, UltraFET®

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File Number 4897 16A, 100V, 0.090 Ohm, N-Channel, UltraFET®

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HUF75617D3, HUF75617D3S
File Number
4897
16A, 100V, 0.090 Ohm, N-Channel, UltraFET® Power MOSFETs Packaging
JEDEC TO-251AA JEDEC TO-252AA
Features
Ultra On-Resistance rDS(ON) 0.090, Simulation Models Temperature Compensated PSPICE® SABERElectrical Models Spice SABER Thermal Impedance Models www.intersil.com Peak Current Pulse Width Curve Rating Curve
SOURCE DRAIN GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
GATE SOURCE
HUF75617D3
HUF75617D3S
Symbol
Ordering Information
PART NUMBER HUF75617D3 PACKAGE TO-251AA TO-252AA BRAND 75617D 75617D
HUF75617D3S
NOTE: When ordering, entire part number. suffix obtain variant tape reel, e.g., HUF75617D3ST.
Absolute Maximum Ratings
25oC, Unless Otherwise Specified HUF75617D3, HUF75617D3S UNITS
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous 25oC, 10V) (Figure Continuous 100oC, 10V) (Figure Pulsed Drain Current .IDM Pulsed Avalanche Rating .UIS Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief TB334 Tpkg NOTE: 25oC 150oC.
Figure Figures 0.43
W/oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. PSPICE® registered trademark MicroSim Corporation. SABERis trademark Analogy, Inc. UltraFET® registered trademark Intersil Corporation. 1-888-INTERSIL 321-724-7143 Intersil Design trademark Intersil Corporation. Copyright Intersil Corporation 2000
HUF75617D3
Electrical Specifications
PARAMETER STATE SPECIFICATIONS Drain Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS 250µA, (Figure 95V, 90V, 150oC Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient TO-251, TO-252 2.34
oC/W oC/W
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
±100
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 16A, (Figure
0.080
0.090
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Gate Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure Qg(TOT) Qg(10) Qg(TH) 50V, 16A, Ig(REF) 1.0mA (Figures td(ON) td(OFF) tOFF 50V, 10V, (Figures
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage SYMBOL Reverse Recovery Time Reverse Recovered Charge 16A, dISD/dt 100A/µs 16A, dISD/dt 100A/µs TEST CONDITIONS 1.25 1.00 UNITS
HUF75617D3 Typical Performance Curves
POWER DISSIPATION MULTIPLIER
DRAIN CURRENT
CASE TEMPERATURE (oC)
CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
THERMAL IMPEDANCE ZJC, NORMALIZED
DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01
NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 RECTANGULAR PULSE DURATION 10-1
SINGLE PULSE 0.01 10-5 10-4
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT
25oC TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-5 10-4 10-3 10-2 PULSE WIDTH 10-1
FIGURE PEAK CURRENT CAPABILITY
HUF75617D3 Typical Performance Curves
(Continued)
AVALANCHE CURRENT
DRAIN CURRENT
SINGLE PULSE RATED 25oC
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD)
100µs
STARTING 25oC
OPERATION THIS AREA LIMITED rDS(ON)
10ms
STARTING 150oC
VDS, DRAIN SOURCE VOLTAGE
0.001
0.01
tAV, TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE FORWARD BIAS SAFE OPERATING AREA
DRAIN CURRENT
PULSE DURATION 80µs DUTY CYCLE 0.5%
DRAIN CURRENT
VDS, DRAIN SOURCE VOLTAGE PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC
25oC 175oC -55oC
VGS, GATE SOURCE VOLTAGE
FIGURE TRANSFER CHARACTERISTICS
FIGURE SATURATION CHARACTERISTICS
NORMALIZED DRAIN SOURCE RESISTANCE
PULSE DURATION 80µs DUTY CYCLE 0.5% NORMALIZED GATE THRESHOLD VOLTAGE VDS, 250µA
10V,
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
HUF75617D3 Typical Performance Curves
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE
(Continued)
2000
250µA
1000 CAPACITANCE (pF)
1MHz
CISS COSS CRSS
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
GATE SOURCE VOLTAGE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER:
GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
HUF75617D3 Test Circuits Waveforms
(Continued)
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
Ig(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE SWITCHING TIME WAVEFORM
HUF75617D3 PSPICE Electrical Model
.SUBCKT HUF75617d3
9.9e-10 1.0e-9 5.4e-10 DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD
24May 2000
LDRAIN DPLCAP RLDRAIN DBREAK EBREAK MWEAK MMED MSTRO LSOURCE RSOURCE RLSOURCE RVTHRES VBAT RBREAK RVTEMP SOURCE DRAIN RSLC1 ESLC RDRAIN EVTHRES
RSLC2
LGATE GATE RLGATE EVTEMP RGATE
LDRAIN 1.0e-9 LGATE 5.24e-9 LSOURCE 4.25e-9 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 3.9e-2 RGATE 2.45 RLDRAIN RLGATE 52.4 RLSOURCE 42.5 RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 3.2e-2 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
VBAT ESLC .MODEL DBODYMOD 6.0e-13 11.0e-3 TRS1 1.1e-3 TRS2 7.1e-6 6.5e-10 4.1e-8 0.54) .MODEL DBREAKMOD 5.6e-1 TRS1 8.0e-4 TRS2 3.0e-6) .MODEL DPLCAPMOD (CJO 7.0e-10 1e-30 0.89 .MODEL MMEDMOD NMOS (VTO 3.10 1e-30 2.45) .MODEL MSTROMOD NMOS (VTO 3.64 1e-30 .MODEL MWEAKMOD NMOS (VTO 2.68 0.02 1e-30 24.5) .MODEL RBREAKMOD (TC1 1.05e-3 -5.0e-7) .MODEL RDRAINMOD (TC1 1.20e-2 3.00e-5) .MODEL RSLCMOD (TC1 3.2e-3 1.0e-6) .MODEL RSOURCEMOD (TC1 1e-3 1e-6) .MODEL RVTHRESMOD (TC1 -2.2e-3 -9.0e-6) .MODEL RVTEMPMOD (TC1 -2.4e-3 -1.8e-6) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF -5.9 VOFF= -3.1) -3.1 VOFF= -5.9) -0.6 VOFF= 0.5) VOFF= -0.6)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
EBREAK 117.8 EVTHRES EVTEMP
DBODY
HUF75617D3 SABER Electrical Model
2000 template huf75617d3 n2,n1,n3 electrical n2,n1,n3 iscl dp.model dbodymod (isl 6.0e-13, 11.0e-3, 4.5, trs1 1.1e-3, trs2 7.1e-6, 6.5e-10, 4.1e-8, 0.54) dp.model dbreakmod 5.6e-1, trs1 8.0e-4, trs2 3.0e-6) dp.model dplcapmod (cjo 7.0e-10, 10e-30, 0.89, m.model mmedmod (type=_n, 3.10, 1e-30, m.model mstrongmod (type=_n, 3.64, 1e-30, m.model mweakmod (type=_n, 2.68, 0.02, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, -5.9, voff -3.1) DPLCAP sw_vcsp.model s1bmod (ron 1e-5, roff 0.1, -3.1, voff -5.9) sw_vcsp.model s2amod (ron 1e-5, roff 0.1, -0.6, voff 0.5) sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 0.5, voff -0.6) RSLC1 c.ca 9.9e-10 c.cb 1.0e-9 c.cin 5.4e-10 dp.dbody model=dbodymod dp.dbreak model=dbreakmod dp.dplcap model=dplcapmod i.it l.ldrain 1.0e-9 l.lgate 5.24e-9 l.lsource 4.25e-9
GATE RLGATE LGATE EVTEMP RGATE MSTRO EVTHRES RSLC2 ISCL RDRAIN MWEAK MMED EBREAK RSOURCE RLSOURCE RVTHRES VBAT RBREAK RVTEMP DBODY DBREAK
LDRAIN DRAIN RLDRAIN
LSOURCE
m.mmed model=mmedmod, l=1u, w=1u m.mstrong model=mstrongmod, l=1u, w=1u m.mweak model=mweakmod, l=1u, w=1u res.rbreak 1.05e-3, -5.0e-7 res.rdrain 3.9e-2, 1.20e-2, 3.00e-5 res.rgate 2.45 res.rldrain res.rlgate 52.4 res.rlsource 42.5 res.rslc1 1e-6, 3.2e-3, 1.0e-6 res.rslc2 res.rsource 3.2e-2, 1e-3, 1e-6 res.rvtemp -2.4e-3, 1.8e-6 res.rvthres -2.2e-3, -9.0e-6 spe.ebreak 117.8 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat dc=1 equations (n51->n50) +=iscl iscl: v(n51,n50) 3.5))
SOURCE
HUF75617D3 SPICE Thermal Model
2000
JUNCTION
HUF75617D CTHERM1 1.00e-3 CTHERM2 4.00e-3 CTHERM3 4.00e-3 CTHERM4 3.60e-3 CTHERM5 7.00e-3 CTHERM6 5.00e-2 RTHERM1 1.59e-2 RTHERM2 3.96e-2 RTHERM3 1.12e-1 RTHERM4 4.27e-1 RTHERM5 6.45e-1 RTHERM6 7.00e-1
RTHERM1
CTHERM1
RTHERM2
CTHERM2
SABER Thermal Model
SABER thermal model HUF75617D template thermal_model thermal_c ctherm.ctherm1 1.00e-3 ctherm.ctherm2 4.00e-3 ctherm.ctherm3 4.00e-3 ctherm.ctherm4 3.60e-3 ctherm.ctherm5 7.00e-3 ctherm.ctherm6 5.00e-2 rtherm.rtherm1 1.59e-2 rtherm.rtherm2 3.96e-2 rtherm.rtherm3 1.12e-1 rtherm.rtherm4 4.27e-1 rtherm.rtherm5 6.45e-1 rtherm.rtherm6 7.00e-1
RTHERM3 CTHERM3
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
HUF75617D3 TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
SEATING PLANE
TERM.
0.265 (6.7)
SYMBOL
INCHES 0.086 0.094 0.018 0.023 0.028 0.033 0.033 0.045 0.205 0.215 0.190 0.018 0.023 0.270 0.295 0.250 0.265 0.090 0.180 0.035 0.050 0.040 0.045 0.100 0.115 0.020 0.025 0.170 0.040
MILLIMETERS 2.19 2.38 0.46 0.58 0.72 0.84 0.84 1.14 5.21 5.46 4.83 0.46 0.58 6.86 7.49 6.35 6.73 2.28 4.57 0.89 1.27 1.02 1.14 2.54 2.92 0.51 0.64 4.32 1.01
NOTES
0.265 (6.7)
0.070 (1.8) 0.118 (3.0) BACK VIEW 0.063 (1.6) 0.090 (2.3) MINIMUM SIZE RECOMMENDED SURFACE-MOUNTED APPLICATIONS
NOTES: These dimensions within allowable dimensions Rev. JEDEC TO-252AA outline dated 9-88. dimensions establish minimum mounting surface terminal Solder finish uncontrolled this area. Dimension (without solder). typically 0.002 inches (0.05mm) solder plating. terminal length soldering. Position lead measured 0.090 inches (2.28mm) from bottom dimension Controlling dimension: Inch. Revision dated 5-00.
1.5mm DIA. HOLE
4.0mm USER DIRECTION FEED 2.0mm 1.75mm
TO-252AA
16mm TAPE REEL
16mm
8.0mm
COVER TAPE
22.4mm
13mm 330mm 50mm
GENERAL INFORMATION 2500 PIECES REEL. ORDER MULTIPLES FULL REELS ONLY. MEETS EIA-481 REVISION SPECIFICATIONS.
16.4mm
HUF75617D3 TO-251AA
LEAD JEDEC TO-251AA PLASTIC PACKAGE
TERM. SEATING PLANE
INCHES SYMBOL
MILLIMETERS 2.19 0.46 0.72 0.84 5.21 0.46 6.86 6.35 2.38 0.58 0.84 1.14 5.46 0.58 7.49 6.73 NOTES
0.086 0.018 0.028 0.033 0.205 0.018 0.270 0.250
0.094 0.023 0.033 0.045 0.215 0.023 0.295 0.265
0.090 0.180 0.035 0.040 0.355 0.075 0.050 0.045 0.375 0.090
2.28 4.57 0.89 1.02 9.02 1.91 1.27 1.14 9.52 2.28
NOTES:
These dimensions within allowable dimensions Rev. JEDEC TO-251AA outline dated 9-88. Solder finish uncontrolled this area. Dimension (without solder). typically 0.002 inches (0.05mm) solder plating. Position lead measured 0.250 inches (6.35mm) from bottom dimension Position lead measured 0.100 inches (2.54mm) from bottom dimension Controlling dimension: Inch. Revision 4dated 5-00.
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site www.intersil.com
Sales Office Headquarters
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File Number 4897 16A, 100V, 0.090 Ohm, N-Channel, UltraFET®

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