File Number 4720.2 33A, 100V, 0.040 Ohm, N-Channel, UltraFET

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File Number 4720.2 33A, 100V, 0.040 Ohm, N-Channel, UltraFET

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HUF75631P3, HUF75631S3S
File Number
4720.2
33A, 100V, 0.040 Ohm, N-Channel, UltraFET Power MOSFET Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE
JEDEC TO-263AB
DRAIN (FLANGE)
Features
Ultra On-Resistance rDS(ON) 0.040, Simulation Models Temperature Compensated PSPICE® SABERElectrical Models Spice SABER Thermal Impedance Models www.intersil.com Peak Current Pulse Width Curve Rating Curve
DRAIN (FLANGE)
GATE SOURCE
HUF75631P3
HUF75631S3S
Symbol
Ordering Information
PART NUMBER PACKAGE TO-220AB TO-263AB BRAND 75631P 75631S HUF75631P3 HUF75631S3S
NOTE: When ordering, entire part number. suffix obtain variant tape reel, e.g., HUF75631S3ST.
Absolute Maximum Ratings
25oC, Unless Otherwise Specified HUF75631P3 HUF75631S3S Figure Figures 0.80 UNITS
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note .VDGR Gate Source Voltage Drain Current Continuous (TC= 25oC, 10V) (Figure Continuous (TC= 100oC, 10V) (Figure Pulsed Drain Current Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case 10s. Package Body 10s, Techbrief TB334 .Tpkg NOTE: 25oC 150oC.
W/oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
CAUTION: These devices sensitive electrostatic discharge. Follow proper Handling Procedures. UltraFET® registered trademark Intersil Corporation. PSPICE® registered trademark MicroSim Corporation. SABERis trademark Analogy, Inc. 1-888-INTERSIL 321-724-7143 Intersil Design trademark Intersil Corporation. Copyright Intersil Corporation 2000
HUF75631P3, HUF75631S3S
Electrical Specifications
PARAMETER STATE SPECIFICATIONS Drain Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS 250µA, (Figure 95V, 90V, 150oC Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient TO-220, TO-263 1.25
oC/W oC/W
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
±100
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 33A, (Figure
0.033
0.040
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Gate Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 1220 Qg(TOT) Qg(10) Qg(TH) 50V, 33A, Ig(REF) 1.0mA (Figures td(ON) td(OFF) tOFF 50V, 10V, (Figures
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage SYMBOL Reverse Recovery Time Reverse Recovered Charge 33A, dISD/dt 100A/µs 33A, dISD/dt 100A/µs TEST CONDITIONS 1.25 1.00 UNITS
HUF75631P3, HUF75631S3S Typical Performance Curves
POWER DISSIPATION MULTIPLIER CASE TEMPERATURE (oC)
DRAIN CURRENT
CASE TEMPERATURE (oC)
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01 NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 RECTANGULAR PULSE DURATION 10-1
SINGLE PULSE 0.01 10-5 10-4
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
25oC TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS:
IDM, PEAK CURRENT
TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-5 10-4 10-3 10-2 PULSE WIDTH 10-1
FIGURE PEAK CURRENT CAPABILITY
HUF75631P3, HUF75631S3S Typical Performance Curves
SINGLE PULSE RATED 25oC IAS, AVALANCHE CURRENT
(Continued)
(L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED BVDSS VDD)
DRAIN CURRENT
100µs
STARTING 25oC
OPERATION THIS AREA LIMITED rDS(ON)
STARTING 150oC
10ms
VDS, DRAIN SOURCE VOLTAGE
0.001
0.01
tAV, TIME AVALANCHE (ms)
NOTE: Refer Intersil Application Notes AN9321 AN9322. FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE FORWARD BIAS SAFE OPERATING AREA
PULSE DURATION 80µs DUTY CYCLE 0.5%
DRAIN CURRENT
DRAIN CURRENT
175oC -55oC 25oC VGS, GATE SOURCE VOLTAGE
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC VDS, DRAIN SOURCE VOLTAGE
FIGURE TRANSFER CHARACTERISTICS
FIGURE SATURATION CHARACTERISTICS
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs DUTY CYCLE 0.5%
10V, NORMALIZED GATE THRESHOLD VOLTAGE
VDS, 250µA
JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
HUF75631P3, HUF75631S3S Typical Performance Curves
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA
(Continued)
4000 1MHz
CAPACITANCE (pF)
1000
CISS COSS
CRSS
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
GATE SOURCE VOLTAGE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER: GATE CHARGE (nC)
NOTE: Refer Intersil Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
HUF75631P3, HUF75631S3S Test Circuits Waveforms
(Continued)
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
Ig(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE SWITCHING TIME WAVEFORM
HUF75631P3, HUF75631S3S PSPICE Electrical Model
.SUBCKT HUF75631
1.95e-9 1.90e-9 1.12e-9
LDRAIN DPLCAP
July 1999
DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD EBREAK 112.8 EVTHRES EVTEMP LDRAIN 1.0e-9 LGATE 6.19e-9 LSOURCE 2.18e-9 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 2.00e-2 RGATE 1.77 RLDRAIN RLGATE RLSOURCE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 6.5e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
GATE RLGATE LGATE
RLDRAIN DBREAK EBREAK
RSLC1 ESLC
DRAIN
RSLC2
EVTEMP RGATE EVTHRES
MSTRO LSOURCE RSOURCE RLSOURCE RBREAK RVTEMP SOURCE
VBAT ESLC .MODEL DBODYMOD 1.20e-12 4.2e-3 TRS1 1.3e-3 TRS2 8.0e-6 1.50e-9 7.47e-8 0.63) .MODEL DBREAKMOD 4.2e-1 TRS1 8e-4 TRS2 3e-6) .MODEL DPLCAPMOD (CJO 1.45e-9 1e-30 0.82) .MODEL MMEDMOD NMOS (VTO 3.11 1e-30 1.77) .MODEL MSTROMOD NMOS (VTO 3.57 33.5 1e-30 .MODEL MWEAKMOD NMOS (VTO 2.68 0.09 1e-30 17.7 .MODEL RBREAKMOD (TC1 =1.05e-3 -5e-7) .MODEL RDRAINMOD (TC1 9.40e-3 2.93e-5) .MODEL RSLCMOD (TC1 3.5e-3 2.0e-6) .MODEL RSOURCEMOD (TC1 1e-3 1e-6) .MODEL RVTHRESMOD (TC1 -1.8e-3 -8.6e-6) .MODEL RVTEMPMOD (TC1 -3.0e-3 =1.5e-7) .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF -6.2 VOFF= -3.1) -3.1 VOFF= -6.2) -1.0 VOFF= 0.5) VOFF= -1.0)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
RDRAIN
DBODY
MWEAK MMED
VBAT
RVTHRES
HUF75631P3, HUF75631S3S SABER Electrical Model
July 1999 template huf75631 n2,n1,n3 electrical n2,n1,n3 iscl d.model dbodymod 1.20e-12, 1.50e-9, 7.47e-8, 0.63) d.model dbreakmod d.model dplcapmod (cjo 1.45e-9, 1e-30, 0.82) m.model mmedmod (type=_n, 3.11, 1e-30, m.model mstrongmod (type=_n, 3.57, 33.5, 1e-30, m.model mweakmod (type=_n, 2.68, 0.09, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, -6.2, voff -3.1) DPLCAP sw_vcsp.model s1bmod (ron =1e-5, roff 0.1, -3.1, voff -6.2) sw_vcsp.model s2amod (ron 1e-5, roff 0.1, -1.0, voff 0.5) sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 0.5, voff -1.0) c.ca 1.95e-9 c.cb 1.90e-9 c.cin 1.12e-9 d.dbody model=dbodymod d.dbreak model=dbreakmod d.dplcap model=dplcapmod i.it l.ldrain 1e-9 l.lgate 6.19e-9 l.lsource 2.18e-9
GATE RLGATE LGATE RSLC2 ISCL
LDRAIN RLDRAIN RDBREAK DBREAK MWEAK MMED MSTRO EBREAK RDBODY DRAIN RSLC1
EVTEMP RGATE EVTHRES
RDRAIN
DBODY
m.mmed model=mmedmod, l=1u, w=1u m.mstrong model=mstrongmod, l=1u, w=1u m.mweak model=mweakmod, l=1u, w=1u res.rbreak 1.05e-3, -5.0e-7 res.rdbody 4.2e-3, 1.30e-3, 8.0e-6 res.rdbreak 4.2e-1, 8.0e-4, 3.0e-6 res.rdrain 2.00e-2, 9.40e-3, 2.93e-5 res.rgate 1.77 res.rldrain res.rlgate res.rlsource res.rslc1 1e-6, 3.5e-3, 2.0e-6 res.rslc2 res.rsource 6.5e-3, 1e-3, 1e-6 res.rvtemp -3.0e-3, 1.5e-7 res.rvthres -1.8e-3, -8.6e-6 spe.ebreak 112.8 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat dc=1 equations (n51->n50) +=iscl iscl: v(n51,n50) 3.5))
LSOURCE RLSOURCE
SOURCE
RSOURCE RBREAK RVTEMP
VBAT
RVTHRES
HUF75631P3, HUF75631S3S SPICE Thermal Model
July 1999 HUF75631T CTHERM1 2.60e-3 CTHERM2 8.85e-3 CTHERM3 7.60e-3 CTHERM4 7.65e-3 CTHERM5 1.22e-2 CTHERM6 8.70e-2 RTHERM1 9.00e-3 RTHERM2 1.80e-2 RTHERM3 9.15e-2 RTHERM4 2.43e-1 RTHERM5 3.10e-1 RTHERM6 3.21e-1
RTHERM1 CTHERM1 JUNCTION
RTHERM2
CTHERM2
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF75631T
template thermal_model thermal_c ctherm.ctherm1 2.60e-3 ctherm.ctherm2 8.85e-3 ctherm.ctherm3 7.60e-3 ctherm.ctherm4 7.65e-3 ctherm.ctherm5 1.22e-2 ctherm.ctherm6 8.70e-2 rtherm.rtherm1 9.00e-3 rtherm.rtherm2 1.80e-2 rtherm.rtherm3 9.15e-2 rtherm.rtherm4 2.43e-1 rtherm.rtherm5 3.10e-1 rtherm.rtherm6 3.21e-1
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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File Number 4720.2 33A, 100V, 0.040 Ohm, N-Channel, UltraFET

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