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Fusion Design Flow Tutorial
Actel Corporation, Mountain View, 94043
2005 Actel Corporation. rights reserved. Printed United States America Part Number: 502-00064-0 Release: December 2005 part this document copied reproduced form means without prior written consent Actel. Actel makes warranties with respect this documentation disclaims implied warranties merchantability fitness particular purpose. Information this document subject change without notice. Actel assumes responsibility errors that appear this document. This document contains confidential proprietary information that disclosed unauthorized person without prior written consent Actel Corporation.
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Actel Actel logo registered trademarks Actel Corporation. Adobe Acrobat Reader registered trademarks Adobe Systems, Inc. other products brand names mentioned trademarks registered trademarks their respective holders.
Table Contents
Fusion Design Flow Tutorial
Fusion Design Flow Overview Application Overview Fusion Design Flow Libero
Special Notes
Customer Service Actel Customer Technical Support Center Actel Technical Support Website Contacting Customer Technical Support Center
Product Support
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Based upon successful Actel ProASIC3/E architecture, Actel Fusion devices integrate configurable 12-bit successive approximation register (SAR) analog digital converter (ADC) with frequencies ksps. flexible analog block supports metal-oxide semiconductor fieldeffect transistor (MOSFET) gate driver output multiple analog inputs from volts volts, with optional prescaler, thus enabling direct connection control wide variety analog systems. monitor voltage, enable differential current monitor, monitor temperature. analog inputs outputs, ADC, related soft compose Analog System. Actel Fusion Programmable System Chip (PSC) family only programmable logic solution that includes embedded Flash memory-up Mbyte device. Flash memory offers 60-nanosecond random access very fast access read-ahead mode. high performance Flash memory offers configurable data supporting x16, widths. memory also offers error correction circuitry (ECC) with single-bit error correct, double-bit error-detect capabilities. Pseudo EEPROM achieved with available endurance extender from Actel. Further, Actel Fusion PSCs enable reconfigure analog block settings simply downloading data from embedded Flash memory. Fusion uses static dynamic power, includes sleep stand-by modes. addition both oscillator crystal oscillator circuit eliminates need expensive external clock sources. power features, combined with Fusion's Real-Time Counter, offer wide variety functionality: sleep, standby, periodic wake-up, low-speed/power operations.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Fusion Design Flow Overview
general Fusion design flow (Figure 1-1) starts when create Analog System Flash Block System, then instantiate sub-macros into top-level netlist, synthesis, then place-and-route simulation each step.
Create Libero Project Fusion
there Flash Block Client Design?
there Analog System Design?
Synthesis
PostSynthesis Simulation
Generate Analog System Using SmartGen Generate Flash Block with Analog Client using SmartGen
Backannotation Simulation
Generate Flash Block with nonAnalog Client using Smartgen
Create Level Connect Macros
Generate Programming File
Generate Testbench File
Simulation Meet Requirements? Program Fusion Device
Simulation
Figure 1-1. Fusion Design Flow Diagram
Fusion Design Flow Tutorial User's Guide
Application Overview
Application Overview
Power management term widely used industry describe managing powerup power-down behavior electronic components. Power management features often used save power protect components during abnormal conditions. Fusion power management example described this tutorial monitors power supply voltage, load side voltage, current provided from supply side load side. Based preset voltage current thresholds, MOSFET between supply side load side controlled Fusion gate driver enable disable power load side. power management example contains Analog System (configured with voltage current monitors), 12-bit analog digital converter (ADC), system frequency (Figure page example monitors three analog signals (AV33V, AC33V, AV33VLOAD) configures multiple threshold flags. Additional logic blocks implemented Fusion FPGA fabric.
Supply Side AV33V
AC33VC V33MON I33MON
AFS600
V33GD VL33MON Load Side AV33VLOAD AV33V_ON
Figure 1-2. Power Management Example Block Diagram
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Fusion Design Flow Libero
Step Initiate Libero Project
Invoke Libero IDE. From File menu, choose Project. Enter PwrM Project Name field, select type VHDL (the sample Libero project VHDL) Verilog, then click Next (Figure 1-3).
Figure 1-3. Create Libero Project
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Select Family Fusion, AFS600, Package FBGA (Figure 1-4).
Figure 1-4. Select Fusion Device Family
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Click Finish. Libero creates project, shown Figure 1-5.
Figure 1-5. Libero Project Window Note: working other Fusion projects, must consider following conditions. your design does include Analog System Flash Block client (i.e., only includes regular FPGA macros, such gate, gate, NGMUX SmartGen generated counters), follow regular Libero project design flow. more information, refer Libero Online Help. your design only implements Flash Block related applications (such Initialization Client) does contain portion Analog System, skip Step Step start from Step directly. your design uses Fusion Analog System, follow Step
Step Configure Generate Analog System SmartGen
Invoke SmartGen Libero Design Flow window.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Invoke Analog System Builder from Core Varieties Fusion Family window (Figure 1-6) Enter following: System Clock: 20.000 Resolution: bits
Select Current Monitor from Available Peripherals list.
Figure 1-6. Analog System Builder Window Click System configure Current Monitor Peripheral. Current Monitor configuration, create Current Monitor AC33V well Voltage Monitor AV33V. Note: current channel must used together with adjacent voltage channel pair Current Monitor. also adjacent voltage channel Voltage Monitor monitor voltage connected this channel. Check Voltage Monitor checkbox enable Voltage Monitor Current Monitor Configuration window. check this box, voltage channel will still used Current Monitor cannot used other voltage monitoring purpose. configuring pure Voltage Monitor, refer Step item Enter following parameters, shown Figure page Digital filtering factor Acquisition time 10.000
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Enter threshold flag values Current Monitor AC33V shown Table 1-1. Table 1-1. Current Monitor Values AC33V Flag Name OVER1P0A OVER1P5A UNDER0P2A UNDER0P5A Flag Type OVER OVER UNDER UNDER Threshold Assert Samples De-Assert Samples
Enter threshold flag values Voltage Monitor AV33V shown Table Table 1-2. Voltage Monitor Values AV33V Flag Name OVER3P6 OVER4P0 UNDER2P5 UNDER3P3 Flag Type OVER OVER UNDER UNDER Threshold Assert Samples De-Assert Samples
External resistor 0.100 Maximum voltage 6.000
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Note: more information about these settings parameters, refer SmartGen Online Help.
Figure 1-7. Current Monitor Configuration
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Click Analog System Builder lists current monitor your system peripherals (Figure 1-8)
Figure 1-8. Analog System with Current Monitor Added Note: select package current channel from Package column. associated voltage channel package automatically selected SmartGen after select current channel package pin. have another separate voltage channel, temperature channel, gate driver, also select their package from Package column. Select Voltage Monitor configure Voltage Monitor peripheral shown Figure page Voltage Monitor configuration, create Voltage Monitor AV33VLOAD. Digital filtering factor Acquisition time 10.000 Maximum voltage 6.000
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Enter threshold flag values Voltage Monitor AV33V shown Table Figure 1-9. Table 1-3. Voltage Monitor Values AV33VLOAD Flag Name OVER3P3 OVER3P75 UNDER2P5 UNDER3P0 Flag Type OVER OVER UNDER UNDER Threshold 3.75 Assert Samples De-Assert Samples
Figure 1-9. Voltage Monitor Configuration
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Click displays your voltage monitor shown Figure 1-10.
Figure 1-10. Analog System with Current/Voltage Monitors Added After configuring voltage current monitors with multiple analog input channels, need define sample sequencer parameters allocate time slots sampling different channels. Click Modify Sample Sequence window change sample sequence (Figure 1-11 page 17). operations available Sample Sequencer are: SAMPLE Sample channel that added system SAMPLE_RESET0 Sample channel reset Slot RESET0 Reset Slot CALIBRATE Calibrate ADC. operation. your sample sequence shown Figure 1-11. SLOT0 SAMPLE AV33V; SLOT1 SAMPLE AC33V; SLOT2 SAMPLE AV33VLOAD, SLOT3 RESET0. Click return main window.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Note: also Jump sequences with jump triggers built your coding. reserve time slots jump sequences, specify number "Use slots jump sequences". more information jump sequences, refer SmartGen Online Help.
Figure 1-11. Modify Sampling Sequence must gate driver control external MOSFET pass transistor between supply side load side (Figure 1-12 page 18). Based threshold values, create turnon/off conditions gate driver order control power supply load side. Select Gate Driver from Available Peripherals list. Click System. Enter following Gate Driver parameters: Gate Driver Polarity: Negative Signal Name: AV33V_ON Enable Signal Name: AV33V_ENABLE
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Source/Sink Current: 1.000 (default)
Figure 1-12. Gate Driver Configuration Click Your configured with Gate Driver, shown Figure 1-13.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
more information about Gate Driver settings, refer SmartGen Online Help.
Figure 1-13. Analog System with Current/Voltage Monitors Gate Driver Added
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Click Generate. Enter core name AS_PwrM, click (Figure 1-14).
Figure 1-14. Generate AS_PwrM Core Close Analog System Builder. Analog System saved Pwr_M Libero project created. reopen reconfiguration from SmartGen Cores folder Libero File Manager invoke from SmartGen double-clicking core name Configured Core View window. After reconfiguration, generate Analog System again. detailed information about available settings specific tool usage, refer SmartGen Online Help.
Step Configure Generate Flash Memory System with Analog System Client Using SmartGen
After generate Analog System, must create corresponding Analog System client Flash Memory. During Analog System generation, file created record Analog System configuration this file must imported into Flash Memory System generation tool shown Figure 1-15 page 21). detailed instructions creating Flash Memory System, refer SmartGen Online Help. Invoke SmartGen Libero Design Flow window (skip this step SmartGen already open).
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Invoke Flash Memory System builder from Core Varieties Fusion Family window. Select Analog System from Available Client Types list, then click System. Analog System Client window appears, shown Figure 1-15.
Figure 1-15. Analog System Client Select As_PwrM from Analog System core pull-down menu. Note: core looking visible, make sure pressed Generate button Analog System builder.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Click Analog System Client added your Flash Memory System (Figure 1-16).
Figure 1-16. Flash Memory System with Analog System Client Added Click Generate complete design. Enter Core name nvm_sysm click SmartGen creates Flash Block system netlist memory files. Close Flash Memory System Builder.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
have generated AS_PwrM (Analog System) nvm_sysm (Flash Memory System), shown Figure 1-17.
Figure 1-17. SmartGen with Analog System Flash Memory System Generated Close SmartGen. Note: this particular design, after generating Flash Memory System, jump Step working other Fusion projects with additional Flash Memory System clients, proceed Step
Step Configure Generate Flash Memory System Using SmartGen
Note: this section working other Fusion projects with additional Flash Memory System clients. Invoke Flash Memory System builder from SmartGen Initialization Client Data Storage Client into Flash Memory System. Initialization Client Data Storage Client into Flash Memory System, select target client from Available Client Types window, then click Add.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Enter your parameters shown Figure 1-18 page 24). Memory Content File content Embedded Flash initialize this client. specified supported memory formats (Binary, Intel_Hex, MotorolaS, Simple_Hex). manually generate sample memory file following supported file formats.
more information Initialization Client Data Storage Client, refer SmartGen Online Help.
Figure 1-18. Initialization/Data Storage Client Dialog Boxes
Step Create Level Netlist
must create top-level VHDL (the sample project VHDL) Verilog netlist instantiate connect sub-blocks, just hierarchical designs. complete top-level VHDL code sample Libero project, under \hdl folder Power_Management.vhd. import VHDL file, from File menu, choose Import. Then navigate Power_Management.vhd file click Import. Libero imports top-level netlist. After import create top-level netlist, right-click file Design Hierarchy window Libero select Root. sample top-level VHDL code below shows basic architecture level. will Analog System Flash Block system instantiated gate driver turn-on/off conditions coded.
library ieee; ieee.std_logic_1164.all;
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
library fusion; entity Power_Management level entity port(.); Power_Management; architecture DEF_ARCH Power_Management component AS_PwrM is-Analog System generated SmartGen port(. INIT_ADDR std_logic_vector(8 downto INIT_DATA std_logic_vector(8 downto INIT_DONE, INIT_ACM_WEN, INIT_ASSC_WEN, INIT_EV_WEN, INIT_TR_WEN std_logic component; component nvm_sysm Flash Memory System generated SmartGen port(INIT_CLK, SYS_RESET, INIT_POWER_UP std_logic; INIT_DONE std_logic; INIT_DATA std_logic_vector(8 downto INIT_ADDR std_logic_vector(8 downto INIT_ACM_WEN, INIT_ASSC_WEN, INIT_EV_WEN, INIT_TR_WEN std_logic); component; begin INIT_DONE<=INIT_DONE_net;
nvm_system_inst:nvm_sysm-Flash Memory System instantiation port INIT_CLK=>SYS_CLK, SYS_RESET=>SYS_RESET, INIT_POWER_UP=>INIT_POWER_UP, INIT_DONE=>INIT_DONE_net, INIT_ACM_WEN=>INIT_ACM_WEN, INIT_ASSC_WEN=>INIT_ASSC_WEN, INIT_EV_WEN=>INIT_EV_WEN,
Fusion Design Flow Tutorial User's Guide
INIT_TR_WEN=>INIT_TR_WEN analog_system_inst AS_PwrM Analog System Instantiation port INIT_DATA INIT_DATA_to_INIT_DATA, INIT_ADDR INIT_ADDR_to_INIT_ADDR, INIT_DONE INIT_DONE_net, INIT_ACM_WEN INIT_ACM_WEN, INIT_ASSC_WEN INIT_ASSC_WEN, INIT_EV_WEN INIT_EV_WEN, INIT_TR_WEN INIT_TR_WEN AV33V_ON_ON (not AV33V_UNDER2P5) (not AV33V_OVER4P0) (not AC33V_OVER1P5A) (not AV33VLOAD_OVER3P75); -Gate Driver Turn-ON/OFF condition DEF_ARCH;
Fusion Design Flow Libero
Connectivity Between Analog System Flash Memory System
following Analog System Flash Memory ports connected Power_Management.vhd file included tutorial. Power_Management.vhd file provided example, must connect following Analog Flash memory system ports manually, according example used code above. ports listed Table 1-4. Table 1-4. Internal Ports Between Analog System Flash Memory System
Flash Memory System (from)
INIT_ADDR INIT_DATA INIT_DONE INIT_ACM_WEN INIT_ASSC_WEN INIT_EV_WEN INIT_TR_WEN
Analog System (to)
INIT_ADDR INIT_DATA INIT_DONE INIT_ACM_WEN INIT_ASSC_WEN INIT_EV_WEN INIT_TR_WEN
Size
9-11 bits 9-11 bits
Gate Driver Turn-ON/OFF Conditions
write your top-level code, must code below (substituting your threshold flag names). Power_Management.vhd file have additional code. Here example turn-on/off condition gate driver based thresholds analog system configuration Step Using these conditions, control power supply load well protect load voltage current limit. AV33V then gate driver enable signal (AV33V_ON_ON) HIGH gate driver (AV33V_ON) will AC33V then gate driver enable signal (AV33V_ON_ON) gate driver (AV33V_ON) will OFF. AV33VLOAD 3.75 then gate driver enable signal (AV33V_ON_ON) gate driver (AV33V_ON) will OFF. Sample VHDL code:
AV33V_ON_ON_int (not AV33V_UNDER2P5_int) (not AV5V_OVER4_int) (not AC33V_OVER1P5A_int) (not AV33VLOAD_OVER3P75_int);
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
customize gate driver turn-on/off conditions based your threshold values.
Step Create Testbench
must have testbench file order simulation. either create manually, import sample testbench file (tb_new_pwr_1.vhd) included sample Libero project. Actel special function Fusion library that enables manually code testbench analog signals. Manually coding testbench that includes analog signals requires that special function; example included testbench file tb_new_pwr_1.vhd sample Libero project. Analog signals must pre-processed before they used digital simulation. drive_analog_input function enables simulation tool simulate analog signals from Analog System Builder. Here sample VHDL code that includes drive_analog_input function analog signals (there other special simulation requirements Fusion besides these analog input):
process begin wait <analog_input_name>; drive_analog_input real (<analog_input_name>), <converted_digital_value> process
import testbench file from sample project, from File menu, choose Import, select Stimulus Files from dropdown menu. must navigate stimulus directory sample project import file tb_new_pwr_1.vhd. Click Import continue.
Step Simulation
After generating Analog System, Flash Memory System, top-level netlist creating testbench, proceed with simulation. top-level netlist must Root before simulation. right-click top-level netlist Design Hierarchy window Libero choose Root from Right-click menu. must associate stimulus before simulation. right-click top-level netlist Libero Design Hierarchy window choose Organize Stimulus.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Select stimulus file your project (tb_new_pwr_1.vhd filename example project) click button your projects' Associated files list. ready Simulation. Invoke ModelSim® from Libero project. simulation Verify threshold flags with respect analog input signals testbench file (Figure 1-19 page 29).
simulation does meet your requirements, need change Analog System parameters. redo steps Refer SmartGen Cores Reference guide more information adjusting parameters will change results. Once simulation passes, continue step more information regarding simulation, refer Libero online help.
Figure 1-19. Simulation Result
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Updating Level Netlist When Macros Changed
made changes Analog System (step Flash Memory System (step then need make following corresponding changes: changed Analog System parameters configuration changes signal names threshold flag names), Flash Memory System must regenerated loading from latest Analog System. changes required level netlist this change Analog System. changed Analog System signal names and/or threshold flag names, Flash Memory System must regenerated loading from latest Analog System. Also, must alter top-level netlist this change Analog System. changed client name and/or parameters Flash Memory System client, corresponding netlist changed. must regenerate Flash Memory System change corresponding port names top-level netlist. Note: Client Name prefixed before select enable signal names group control signals that client together.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Libero
Step Synthesis
Invoke Synplify® from Libero Design Hierarchy window click Synthesis icon Design Flow window (Figure 1-20).
Figure 1-20. Synthesis Accept default implementation, make sure AFS600 selected this particular design, then click execute synthesis. more information about Synthesis, refer Libero Online Help.
Step Post-Synthesis Simulation
After synthesis, click Simulation icon Libero continue with post-synthesis. Verify threshold flags with respect analog input signals testbench file. more information about Post-Synthesis Simulation, refer Libero Online Help.
Fusion Design Flow Tutorial User's Guide
Fusion Design Flow Tutorial
Step Place-and-Route
Click Place-and-Route invoke Designer from Libero Design Flow window, then follow instructions Device Selection Wizard select appropriate device. this particular design, select AFS600, 256FBGA, speed, Voltage (Figure 1-21).
Figure 1-21. Place-and-Route After Compile Layout complete, click Back-Annotate icon generate back-annotated VHDL netlist timing information. more information about place-and-route, refer Libero online help.
Step Back-Annotation Simulation
After Back-Annotation, continue with post-layout simulation clicking Simulation icon Libero Design Flow window. Verify threshold flags with respect analog input signals testbench file. more information about Back-Annotation Simulation, refer Libero online help.
Fusion Design Flow Tutorial User's Guide
Special Notes
file shows system configuration.
file records System parameter settings after configuring generating systems from SmartGen. This gives advanced users capability explore details system provides guidance fine-tuning system.
Pre-defined Soft Applets speed design process.
Pre-defined Soft (included with SmartGen) implemented particular application. This reduces development time. also have flexibility implement your (such Core8051 replace that bundled with SmartGen). user-defined application module, Applets, archived re-used other applications. example, could archive file power management system reuse your next project.
have multiple versions Analog System, make sure corresponding Flash Memory System used project.
stated step make sure that Analog Flash Memory System used level match each other have generated several versions Analog System Flash Memory System.
Fusion Design Flow Tutorial User's Guide
Product Support
Actel backs products with various support services including Customer Service, Customer Technical Support Center, site, site, electronic mail, worldwide sales offices. This appendix contains information about contacting Actel using these support services.
Customer Service
Contact Customer Service non-technical product support, such product pricing, product upgrades, update information, order status, authorization. From Northeast North Central U.S.A., call 650.318.4480 From Southeast Southwest U.S.A., call 650. 318.4480 From South Central U.S.A., call 650.318.4434 From Northwest U.S.A., call 650.318.4434 From Canada, call 650.318.4480 From Europe, call 650.318.4252 1276 From Japan, call 650.318.4743 From rest world, call 650.318.4743 Fax, from anywhere world 650.318.8044
Actel Customer Technical Support Center
Actel staffs Customer Technical Support Center with highly skilled engineers help answer your hardware, software, design questions. Customer Technical Support Center spends great deal time creating application notes answers FAQs. before contact please visit online resources. very likely have already answered your questions.
Actel Technical Support
Visit Actel Customer Support website more information support. Many answers available searchable resource include diagrams, illustrations, links other resources Actel site.
Website
browse variety technical non-technical information Actel's home page, www.actel.com.
Fusion Design Flow Tutorial User's Guide
Contacting Customer Technical Support Center
Highly skilled engineers staff Technical Support Center from 7:00 A.M. 6:00 P.M., Pacific Time, Monday through Friday. Several ways contacting Center follow:
communicate your technical questions email address receive answers back email, fax, phone. Also, have design problems, email your design files receive assistance. constantly monitor email account throughout day. When sending your request please sure include your full name, company name, your contact information efficient processing your request. technical support email address tech@actel.com.
Phone
Technical Support Center answers calls. center retrieves information, such your name, company name, phone number your question, then issues case number. Center then forwards information queue where first available application engineer receives data returns your call. phone hours from 7:00 A.M. 6:00 P.M., Pacific Time, Monday through Friday. Technical Support numbers are:
650.318.4460 800.262.1060
Customers needing assistance outside time zones either contact technical support email (tech@actel.com) contact local sales office. Sales office listings found
Fusion Design Flow Tutorial User's Guide
more information about Actel's products, visit website http://www.actel.com
Actel Corporation 2061 Stierlin Court Mountain View, 94043 Customer Service: 650.318.1010 Customer Applications Center: 800.262.1060 Actel Europe Ltd. Dunlop House, Riverside Camberley, Surrey GU15 United Kingdom Phone 1276 1276 Actel Japan EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Phone +81.03.3445.7671 +81.03.3445.7668 www.jp.actel.com Actel Hong Kong Suite 2114, Pacific Place Queensway, Admiralty Hong Kong Phone +852 2185 6460 +852 2185 6488 www.actel.com.cn
502-00064-0/12.05
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