Gigabit Ethernet Single Chip Features Specification Revision comp

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Gigabit Ethernet Single Chip Features Specification Revision comp

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IP1000M
Gigabit Ethernet Single Chip
Features Specification Revision compliant 32-bit, 33/66MHz master capability Efficient operation maximizes band-width utilization Terabyte bit) address space Scatter, gather transmit/receive Transmit "interrupt-less" mode operation Receive frame priority interrupts Receive interrupt coalescing FIFO Features external memory required Receive FIFO flow control thresholds Configurable TX/RX FIFO Features IEEE 802.3z, 802.3x compliant IEEE 802.1p, 802.1Q compliant 1000Mbps, 100Mbps, 10Mbps triple speed, half/full duplex operation Transmit receive back back frames full wire speed Half duplex carrier extension packet bursting Asymmetric/symmetric flow control VLAN insertion/removal VLAN tagged frame filtering IPV4, TCP, checksum calculation/verification 802.3 statistic register sets 64-bit hash table multicast frame filtering Jumbo frame support transmit receive Big-endian Phsical Layer Features Fully integrated IEEE 802.3ab compliant 1000BASE-T, 100BASE-TX 10BASE-T port receiver includes feed-forward equalizer, decision feedback equalizer, echo canceller, crosstalk canceller, baseline wander correction 802.3ab compliant Auto-Negotiation automatic speed, duplex, master/slave configuration Automatic MDI/MDI-X crossover function polarity correction
Confidential. Copyright 2003, Plus Corp.
Automatic pair skew adjustment management registers Smart Cable Analyzer (SCATM) Smart speed downshift APS(Auto Power Saving) Power Saving with Link status detecting Keep only alive through software setting
Power Management, EEPROM Package WakeOnLAN support ACPI Revision compliant 1.8/3.3V CMOS with tolerant EEPROM 24C02 support 128-pin LQFP package
General Description
IP1000M truly 10/100/1000Mbps Gigabit Ethernet single chip which incorporates 32-bit interface with master support. manufactured using standard digital CMOS process contains active circuitry required implement physical layer functions transmit receive data standard CAT5 unshielded twisted pair cable. IP1000M designed variety applications including workstation NICs, other systems utilizing bus. IP1000M includes 32-bit interface, IEEE 802.3 compliant MAC, transmit receive FIFO buffers, IEEE 802.3 compliant 10BASE-T, 100BASE-TX PHY, IEEE 802.3z compliant 1000 BASE-T PHY, serial EEPROM interface drivers. IP1000M supports features "Green PCs" systems where control over system power consumption desired. IP1000M supports several power down states, ability issue system "wake event" reception unique, user defined Ethernet frames. addition, IP1000M assert wake event response changes Ethernet link status.
Jul. 2003 IP1000M-PB-R01
IP1000M
Block Diagram
VDET INTAN RSTN PMEN FRAMEN TRDYN IRDYN STOPN DEVSELN IDSEL PCICLK PERRN SERRN REQN GNTN CBEN[3:0] AD[31:0] ANALOG MISC HSDAC_P CTRL_REGD CTRL_REGA RSET MAIN CLOCK POWER GROUND AVCCH AVCC AVSS VCC2 VCC1 VSS2 VSS1 Segment -ation IP/TCP/UDP Checksum Generation Transmit Flow Control Master IP/TCP/UDP Checksum Verification Receive Flow Control Physical Media Access Control (MAC) Layer (PCS, PMA, PMD) TP_MDI[3:0]+ TP_MDI[3:0]EEPROM VPD_DATA VPD_CLK LED_LINK10N LED_LINK100N LED_LINK1000N LED_DUPLEXN LED_RXN LED_TXN LED_STANT
Dual Queue Controller Interface Dual Queue Controller
FIFO
FIFO
Plus Corp.
Headquarters 10F, No.47, Lane Kwang-Fu Road, Sec. Hsin-Chu City, Taiwan 300, R.O.C. 886-3-575-0275 886-3-575-0475 Website: www.icplus.com.tw
Confidential. Copyright 2003, Plus Corp.
Sales Office 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. 886-2-2696-1669 886-2-2696-2220
Jul. 2003 IP1000M-PB-R01

Gigabit Ethernet Single Chip Features Specification Revision comp

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