DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR differential LVDS

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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR differential LVDS

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ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
differential LVDS outputs designed meet exceed requirements ANSI TIA/EIA-644 Selectable differential clock inputs CLKx, nCLKx pairs accept following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Output frequency range: 31.25MHz 700MHz Input frequency range: 31.25MHz 700MHz range: 250MHz 700MHz External feedback "zero delay" clock regeneration with configurable frequencies Programmable dividers allow following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, Cycle-to-cycle jitter: 25ps (maximum) Output skew: 35ps (maximum) Static phase offset: 50ps 150ps 3.3V supply voltage 70°C ambient operating temperature Industrial temperature information available upon request
GENERAL DESCRIPTION
ICS8745 highly versatile LVDS clock generator member HiPerClockSHiPerClockSfamily High Performance Clock Solutions from ICS. ICS8745 fully integrated configured zero delay buffer, multiplier divider, output frequency range 31.25MHz 700MHz. Reference Divider, Feedback Divider Output Divider each programmable, thereby allowing following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. external feedback allows device achieve "zero delay" between input clock output clocks. PLL_SEL used bypass system test debug purposes. bypass mode, reference clock routed around into internal output dividers.
BLOCK DIAGRAM
PLL_SEL ÷16, ÷32, CLK1 nCLK1 CLK_SEL FB_IN nFB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
ASSIGNMENT
PLL_SEL SEL3 VDDO VDDA
CLK0 nCLK0
SEL0 SEL1 CLK0
nFB_IN FB_IN SEL2 VDDO
VDDO
nCLK0 CLK1 nCLK1 CLK_SEL
ICS8745
SEL0 SEL1 SEL2 SEL3
32-Lead LQFP 1.4mm package body Package View
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Type Description
TABLE DESCRIPTIONS
Number Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL nFB_IN FB_IN SEL2 nQ0, VDDO nQ1, nQ2, nQ3, nQ4, SEL3 VDDA PLL_SEL Input Input Input Input Input Input Input Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input Pullup Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, internal dividers reset. Pulldown When LOW, Master Reset disabled. LVCMOS LVTTL interface levels. Core supply pins. Pullup Feedback input phase detector regenerating clocks with "zero delay". Pulldown Feedback input phase detector regenerating clocks with "zero delay". Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Power supply ground. Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Analog supply pin. Selects between reference clock input dividers. When LOW, selects reference clock. LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL Enable Mode Q0:Q4, nQ0:nQ4
TABLE CONTROL INPUT FUNCTION TABLE
Inputs SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* 62.5 31.25 87.5 62.5 -700 62.5 31.25 87.5 62.5 31.25 87.5 31.25 87.5
*NOTE: frequency range configurations above 700MHz.
TABLE BYPASS FUNCTION TABLE
Inputs SEL3
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SEL2
SEL1
SEL0
Outputs PLL_SEL Bypass Mode Q0:Q4, nQ0:nQ4
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
4.6V -0.5V -0.5V VDDO 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol VDDA VDDO IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Core Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage Input High Current CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, SEL0, SEL1, SEL2, SEL3 Input Current PLL_SEL 3.465V 3.465V 3.465V, 3.465V, -150 Test Conditions Minimum -0.3 Typical Maximum Units
TABLE DIFFERENTIAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol Parameter VCMR Input High Current Input Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions 3.465V 3.465V 3.465V, 3.465V, -150 0.15 0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE
NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK0, nCLK0 CLK1, nCLK1 0.3V.
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 1.125 Typical 1.25 -3.5 -3.5 1.34 1.06 Maximum 1.375 Units
TABLE LVDS CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol IOSD IOFF Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change Differential Output Shor Circuit Current Output Shor Circuit Current Power Leakage Output Voltage High Output Voltage
TABLE INPUT FREQUENCY CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL PLL_SEL Minimum 31.25 Typical Maximum Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE Static Phase Offset; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter; NOTE Phase Jitter; NOTE Output Pulse Width Lock Time Output Rise Time; NOTE Output Fall Time; NOTE 155.5MHz 155.5MHz 155.5MHz 155.5MHz tcycle/2 tcycle/2 PLL_SEL 700MHz PLL_SEL 3.3V -100 Test Conditions Minimum Typical Maximum tcycle/2 Units
tsk(o) tjit(cc) tjit()
parameters measured fMAX unless noted otherwise. NOTE Measured from differential input crossing point differential output crossing point. NOTE Defined time difference between input reference clock averaged feedback input signal across conditions, when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE Phase jitter dependent input source used. NOTE This parameter defined accordance with JEDEC Standard NOTE Characterized frequency 622MHz. NOTE Measured from points. Guaranteed characterization. production tested.
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE LVDS
3.3V±5% POWER SUPPLY
Float
3.3V OUTPUT LOAD TEST CIRCUIT
VDDO
nCLK0, nCLK1 CLK0, CLK1
Cross Points
DIFFERENTIAL INPUT LEVEL
tsk(o)
OUTPUT SKEW
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
SWING
Clock Outputs
OUTPUT RISE
FALL TIME
nCLK0, nCLK1
CLK0, CLK1
nQ0:nQ4 Q0:Q4
PROPAGATION DELAY
nCLK0, nCLK1 CLK0, CLK1
nFB_IN FB_IN
mean Phase Jitter
(where random sample, mean average sampled cycles measured controlled edges)
PHASE JITTER
nQ0:nQ4
Q0:Q4
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mean Static Phase Offset
STATIC PHASE OFFSET
Pulse Width
PERIOD
tPERIOD
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ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
DVOS SETUP
Input
LVDS
VOD/
DVOD SETUP
Input
LVDS
IOSD SETUP
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Input
LVDS
VOS/
IOSD
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ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Input
LVDS
SETUP
LVDS
IOFF
IOFF SETUP
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ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
CLK_IN V_REF 0.1uF
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
LAYOUT GUIDELINE
schematic ICS8745 layout example shown Figure ICS8745 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stacking P.C. board.
Space (i.e. intstalled)
CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 PLL_SEL SEL3 VDDA 0.01u
(77.76 MHz)
VDDO
LVDS_input
3.3V
(155.5 MHz)
SEL0 SEL1
PLL_SEL VDDA SEL3 VDDO
CLK_SEL 3.3V PECL Driver
8745
nFB_IN FB_IN SEL2 VDDO
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL
VDDO
VDD=3.3V VDDO=3.3V
SEL[3:0] 0101, Divide
SEL2
Decoupling capacitor located near power pins
(U1-9)
0.1uF
(U1-32)
0.1uF
(U1-22)
0.1uF
VDDO
(U1-28)
0.1uF
(U1-16)
0.1uF
FIGURE ICS8745 LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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following component footprints used this layout example: resistors capacitors size 0603.
ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace
VDDO
VDDA
Traces
FIGURE BOARD LAYOUT ICS8745
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ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8745 3050
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
TABLE ORDERING INFORMATION
Part/Order Number ICS8745AY ICS8745AYT Marking ICS8745AY ICS8745AY Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8745AY
REV. OCTOBER 2002
ICS8745
DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description Change Updated Block Diagram. Changed Reference Zero Delay Static Phase Offset. Added note bottom table. Added Note Revised Block Diagram. Changed inputs from LVDS interface levels LVCMOS interface levels. Revised VCMR from "VDD 0.5" Minimum "GND 0.5" Minimum Updated Block Diagram. Revised Feature notes. Characteristics revised first line notes. Descriptions, revised description. Updated Output Rise/Fall Diagram. Characteristics Table Revised Rise/Fall Time read: tR/tF min. 150ps 550ps Test Conditions 155.5MHz. tR/tF min. 50ps 450ps Test Conditions >155.5MHz. Changed description from Positive supply Core supply pin. Updated LVDS Zero Delay Buffer Schematic Example. Date 11/5/01 11/20/01 11/27/01 11/29/01 11/30/01 1/25/02 5/10/02 5/15/02 8/15/02 9/11/02 10/3/02
Table
Page
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DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR differential LVDS

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