700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL outputs Selectable crystal oscillator interface LVCMOS TEST_CLK Output frequency range: 72.5MHz 700MHz Crystal input frequency range: 14MHz 40MHz range: 580MHz 700MHz Parallel serial interface programming counter output dividers Cycle-to-cycle jitter: 12ps (typical) period jitter: 2.5ps (typical) phase jitter 155.52MHz, using 38.88MHz crystal (12KHz 20MHz): 2.5ps (typical) Phase noise: 155.52MHz (typical) Offset Noise Power 100Hz -90.5 dBc/Hz 1KHz -114.2 dBc/Hz 10KHz -123.6 dBc/Hz 100KHz -128.1 dBc/Hz 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS84320-01 general purpose, dual output Crystal-to-3.3V Differential LVPECL High FreHiPerClockSquency Synthesizer member HiPerClockSfamily High Performance Clock Solutions from ICS. ICS84320-01 selectable TEST_CLK crystal inputs. operates frequency range 580MHz 700MHz. frequency programmed steps equal value input reference crystal frequency. output frequency programmed using serial parallel interfaces configuration logic. phase noise characteristics ICS84320-01 make ideal clock source Gigabit Ethernet, SONET, Serial Attached SCSI applications.
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL1 XTAL2
ASSIGNMENT
VCO_SEL nP_LOAD XTAL2
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
XTAL1 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
PHASE DETECTOR
FOUT0 nFOUT0 FOUT1 nFOUT1
ICS84320-01
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz crystal. Valid loop divider values different crystal input frequencies defined Input Frequency Characteristics, Table NOTE
ICS84320-01 features fully integrated therefore requires external components setting loop bandwidth. fundamental crystal used input on-chip oscillator. output oscillator into phase detector. 25MHz crystal provides 25MHz phase detector reference frequency. operates over range 580MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS84320-01 support input modes, programmable divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode, nP_LOAD input initially LOW. data inputs through passed directly divider output divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition nP_LOAD until serial event occurs. result, bits hardwired divider output divider specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, crystal frequency divider defined follows: fVCO fxtal value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock 25MHz reference defined frequency defined follows: FOUT fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data Output divider CMOS Fout
SERIAL LOADING
S_DATA
S_CLOCK
*NULL
S_LOAD
M0:M8, N0:N1
PARALLEL LOADING
nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE: NULL timing slot must observed.
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Input Pulldown Pullup divider inputs. Data latched LOW-to-HIGH transition Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function Table. LVCMOS LVTTL interface levels. connect. Negative supply pins. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Differential output synthesizer. LVPECL interface levels. Output supply pin. Differential output synthesizer. LVPECL interface levels. Master Reset. When logic HIGH, forces outputs (Fout0 Fout1 LOW; nFout0 nFout1 HIGH). When logic LOW, outputs enabled. Asser tion does affect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled rising edge S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition data from shift register into dividers. LVCMOS LVTTL interface levels. Analog supply pin. Selects between ystal test inputs reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS LVTTL interface levels. Test clock input. LVCMOS LVTTL interface levels. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL1, XTAL2 nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown
ystal oscillator inputs. Parallel load input. Determines when data present M8:M0 Pulldown loaded into divider, when data present N1:N0 sets output divider value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE PARALLEL
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. Forces outputs LOW. Data inputs passed directly divider output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
nP_LOAD
Data Data
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Divide
NOTE These divide values resulting frequencies correspond crystal TEST_CLK input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs Divider Value Output Frequency (MHz) Minimum 72.5 Maximum 87.5
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V -0.5V VCCO 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, VCCO Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA VCCO ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage VCO_SEL, XTAL_SEL, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD XTAL_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD XTAL_SEL, VCO_SEL Output High Voltage Output Voltage TEST; NOTE TEST; NOTE Test Conditions Minimum -0.3 -0.3 3.465V 3.465V 3.465V, 3.465V, Typical Maximum Units
Input Voltage
Input High Current
Input Current
-150
NOTE Outputs terminated with VCCO/2.
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Output High Voltage; NOTE Output Voltage; NOTE
Peak-to-Peak Output Voltage Swing VSWING NOTE Outputs terminated with VCCO "Parameter Measurement Information" section, figure "3.3V Output Load Test Circuit".
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter TEST_CLK; NOTE Input Frequency XTAL1, XTAL2; NOTE Test Conditions Minimum Typical Maximum Units
S_CLOCK NOTE input ystal TEST_CLK frequency range, value must operate within 580MHz 700MHz range. Using minimum input frequency 14MHz, valid values Using maximum frequency 40MHz, valid values
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Test Conditions Minimum Typical Maximum 38.88 Units Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise Time Output Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Output Duty Cycle Output Pulse Width tPERIOD/2 tPERIOD/2 fVCO 350MHz fOUT 100MHz Test Conditions Minimum Typical Maximum Units
tjit(cc) tjit(per) tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE Jitter performance using XTAL inputs. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE 155.52MHZ
USING 38.88MHZ QUARTZ CRYSTAL
-100 -110 -120 -130 -140 -150 -160 -170 -180
Jitter Source Process Result 100.000 40.000M 155.520M
Start Freq.
OC-48 Sonet Bandpass Filter
Stop Freq. Freq. carrier Mode
Noise Spurs sec. Plot
Integral 2.38p
phase noise data
Execute
TYPICAL PHASE NOISE 622.08MHZ
USING 38.88MHZ QUARTZ CRYSTAL
Phase noise result adding Sonet Bandpass Filter data
100k
100M
-100 -110 -120 -130 -140 -150 -160 -170 -180
84320AY-01
Jitter Source Process Result 100.000 40.000M 622.080M
Start Freq. Stop Freq. Freq. carrier
OC-48 Sonet Bandpass Filter
Mode
Noise Spurs sec. Plot
Integral 2.48p
phase noise data
Execute
Phase noise result adding Sonet Bandpass Filter data
100k
100M
REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
LVPECL
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
nFOUTx FOUTx
nFOUTy FOUTy
tsk(o)
OUTPUT SKEW
SWING
Clock Outputs
OUTPUT RISE
FALL TIME
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ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
nFOUTx FOUTx
Pulse Width
PERIOD
PERIOD
odc, tPERIOD
Vref
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Period Jitter
nFOUTx
FOUTx
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
Cycle-to-Cycle Jitter
84320AY-01
tcycle
REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATIONS INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS84320-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF VCCA .01µF
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
crystal characterized either series parallel mode operation. ICS84320-01 built-in crystal oscillator circuit. This interface accept either series parallel crystal without additional components generate frequencies with accuracy suitable most applications. Additional accuracy achieved adding small capacitors shown Figure Typical results using parallel 18pF crystals shown Table
18pF Parallel Crystal
XTAL2
XTAL1 ICS84320-01
Figure CRYSTAL INPUt INTERFACE
Table TYPICAL RESULTS Crystal Frequency (MHz) 14.31818 15.00 16.66 19.44 24.00 25.00
84320AY-01
CRYSTAL INPUT INTERFACE FREQUENCY FINE TUNING (pF) Measured Output Frequency (MHz) 25.000129
(pF)
Accuracy (PPM)
REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TERMINATION LVPECL OUTPUTS
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
FOUT
3.3V
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
schematic ICS84320-01 layout example used this layout guideline shown Figure ICS84320-01 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stack P.C. board.
ICS84320-01
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
VCO_SEL nP_LOAD XTAL2
FOUT FOUTN
FIGURE SCHEMATIC
84320AY-01
0.1u
FIGURE LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
REF_IN XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
XTAL1 T_CLK nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
0.01u
0.1u
RECOMMENDED LAYOUT
REV. OCTOBER 2002
following component footprints used this layout example: resistors capacitors size 0603.
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
POWER
GROUNDING
Place decoupling capacitors C15, close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VCCA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces.
CRYSTAL
crystal should located close possible pins (XTAL1) (XTAL2). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
VCCA
Close input pins receiver
TL1N
TL1N
TL1, TL21N traces equal length
FIGURE BOARD LAYOUT
84320AY-01
ICS84320-01
REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS84320-01. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS84320-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 110mA 381.2mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 60.4mW
Total Power_MAX (3.465V, with outputs switching) 381.2mW 60.4mW 441.6mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.441W 42.1°C/W 88.6°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
84320AY-01
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50) 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50) 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
84320AY-01
REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS84320-01 3776
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REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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REV. OCTOBER 2002
ICS84320-01
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Marking ICS84320AY-01 ICS84320AY-01 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS84320AY-01 ICS84320AY-01T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 84320AY-01
REV. OCTOBER 2002
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