3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT TOLERANT BUS-HOLD

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3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT TOLERANT BUS-HOLD

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IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT TOLERANT BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion
IDT74LVCH16501A
DESCRIPTION
This 18-bit registered transceiver built using advanced dual metal CMOS technology. This high-speed, power 18-bit registered transceiver combines D-type latches D-type flip-flops allow data flow transparent latched clocked modes. Data flow each direction controlled output-enable (OEAB OEBA), latch enable (LEAB LEBA) clock (CLKAB CLKBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held high logic level. LEAB low, data stored latch/flip-flop low-to-high transition CLKAB. OEAB performs output enable function port. Data flow from port port similar requires using OEBA, LEBA CLKBA. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. LVCH16501A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. LVCH16501A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features LVCH16501A: High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
Functional Block Diagram
OEAB LKBA
LEBA OEBA LKAB LEAB
NELS
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-3688/1
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
CONFIGURATION
OEAB LEAB OEBA LEBA SO56-1 SO56-2 SO56-3
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Unit
Link
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
NOTE: applicable device type.
FUNCTION TABLE
OEAB LEAB Inputs CLKAB
Outputs B(3) B(4)
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names OEAB OEBA LEAB LEBA CLKAB CLKBA Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1)
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
1998 Integrated Device Technology, Inc.
NOTES: HIGH Voltage Level Voltage Level Don't Care High Impedance LOW-to-HIGH Transition A-to-B data flow shown. B-to-A data flow similar uses OEBA, LEBA, CLKBA. Output level before indicated steady-state input conditions were established. Output level before indicated steady-state input conditions were established, provided that CLKAB HIGH before LEAB went LOW.
DSC-123456
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance transceiver Outputs enabled Power Dissipation Capacitance transceiver Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Propagation Delay LEBA LEAB Propagation Delay CLKBA CLKAB Output Enable Time OEBA OEAB Output Disable Time OEBA OEAB Set-up Time, HIGH CLKAB, CLKBA Hold Time, HIGH CLKAB, CLKBA Set-up Time Clock HIGH LEAB, Clock LEBA HIGH Hold Time HIGH LEAB, LEBA LEAB LEBA Pulse Width HIGH CLKAB CLKBA Pulse Width HIGH Output Skew(2)
2.7V Min. Max. 3.3V±0.3V Min. Max. Unit
tSK(o)
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT
ORDERING INFORMATION
Bus-Hold Family XXXX Device Type Package Temp. ange
501A
Shrink Outline Package (SO56-1) Thin Shrink Outline Package (SO56-2) Thin Very Outline Package (SO56-3) 18-bit Registered Transceiver Double-Density with Resistors, ±12m
Bus-hold -40°C +85°C
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3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH VOLT TOLERANT BUS-HOLD

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