Handbook HBD855/D Rev. Jun-2005 SCILLC, 2005 Previous Editio
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Thyristor Theory Design Considerations
Handbook
HBD855/D Rev. Jun-2005
SCILLC, 2005 Previous Edition 2000 Excerpted from DL137/D "All Rights Reserved''
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ABOUT THYRISTORS
Thyristors take many forms, they have certain things common. them solid state switches which open circuits capable withstanding rated voltage until triggered. When they triggered, thyristors become low-impedance current paths remain that condition until current either stops drops below minimum value called holding level. Once thyristor been triggered, trigger current removed without turning device. Silicon controlled rectifiers (SCRs) triacs both members thyristor family. SCRs unidirectional devices where triacs bidirectional. designed switch load current direction, while triac designed conduct load current either direction. Structurally, thyristors consist several alternating layers opposite silicon, with exact structure varying with particular kind device. load applied across multiple junctions trigger current injected them. trigger current allows load current flow through device, setting regenerative action which keeps current flowing even after trigger removed. These characteristics make thyristors extremely useful control applications. Compared mechanical switch, thyristor very long service life very fast turn turn times. Because their fast reaction times, regenerative action resistance once triggered, thyristors useful power controllers transient overvoltage protectors, well simply turning devices off. Thyristors used motor controls,
incandescent lights, home appliances, cameras, office equipment, programmable logic controls, ground fault interrupters, dimmer switches, power tools, telecommunication equipment, power supplies, timers, capacitor discharge ignitors, engine ignition systems, many other kinds equipment. Although thyristors sorts generally rugged, there several points keep mind when designing circuits using them. most important respect devices' rated limits rate change voltage current (dv/dt di/dt). these exceeded, thyristor damaged destroyed. other hand, important provide trigger pulse large enough fast enough turn gate quickly completely. Usually gate trigger current should least percent greater than maximum rated gate trigger current. Thyristors driven many different ways, including directly from transistors logic families, power control integrated circuits, optoisolated triac drivers, programmable unijunction transistors (PUTs) SIDACs. These other design considerations covered this manual. interest too, line Thyristor Surge Suppressors surface mount package covering surge currents amps, with breakover voltages from volts. These Thyristor Surge Protection devices prevent overvoltage damage sensitive circuits lightening, induction, power line crossing. They breakover triggered crowbar protectors with turn occurring when surge current falls below holding current value.
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CHAPTER Theory Applications
Sections thru
Page Section Symbols Terminology Section Theory Thyristor Operation Basic Behavior Switching Characteristics False Triggering Theory Power Control Triac Theory Methods Control Zero Point Switching Techniques Section Thyristor Drivers Triggering Pulse Triggering SCRs Effect Temperature, Voltage Loads Using Negative Bias Shunting Snubbing Thyristors Using Sensitive Gate SCRs Drivers: Programmable Unijunction Transistors Section SIDAC, High Voltage Bilateral Trigger Section Characteristics Turn-Off Characteristics Turn-Off Mechanism Turn-Off Time Parameters Affecting Characterizing SCRs Crowbar Applications Switches Line-Type Modulators Parallel Connected SCRs Suppression Thyristor Circuits Section Applications Phase Control with Thyristors Motor Control Phase Control with Trigger Devices Cycle Control with Optically Isolated Triac Drivers Power Control with Solid-State Relays Triacs Inductive Loads Inverse Parallel SCRs Power Control Page Interfacing Digital Circuits Thyristor Controlled Loads Motor Control with Thyristors Programmable Unijunction Transistor (PUT) Applications Triac Zero-Point Switch Applications AN1045 Series Triacs High Voltage Switching Circuits AN1048 Snubber Networks Thyristor Power Control Transient Suppression AND8005 Automatic Line Voltage Selector AND8006 Electronic Starter Flourescent Lamps AND8007 Momentary Solid State Switch Split Phase Motors AND8008 Solid State Control Solutions Three Phase Motor AND8015 Long Life Incandescent Lamps using SIDACs AND8017 Solid State Control Bi-Directional Motors Section Mounting Techniques Thyristors Mounting Surface Considerations Thermal Interface Insulation Considerations Fastening Techniques Insulated Packages Surface Mount Devices Thermal System Evaluation Section Reliability Quality Using Transient Thermal Resistance Data High Power Pulsed Thyristor Applications Thyristor Construction In-Process Controls Inspections Reliability Tests Stress Testing Environmental Testing Section Appendices
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SECTION SYMBOLS TERMINOLOGY
SYMBOLS
following most commonly used schematic symbols Thyristors:
Name Device
Silicon Controlled Rectifier (SCR)
Symbol
Triac
Thyristor Surge Protective Devices Sidac
Programmable Unijunction Transistor (PUT)
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THYRISTOR TERMINOLOGY (The following terms used TRIAC specifications.)
Symbol di/dt
Terminology CRITICAL RATE RISE ON-STATE CURRENT
Definition maximum rate change current device will withstand after switching from off-state on-state when using recommended gate drive. other words, maximum value rate rise on-state current which Triac withstand without damage. ability Triac turn itself when driving inductive load resultant commutating dv/dt condition associated with nature load. Also, commonly called static dv/dt. minimum value rate rise forward voltage which will cause switching from off-state on-state with gate open. maximum value current which will flow VDRM specified temperature when Triac off-state. Frequently referred leakage current forward off-state blocking mode. maximum peak gate current which safely applied device cause conduction. maximum value gate current required switch device from off-state on-state under specified conditions. designer should consider maximum gate trigger current minimum trigger current value that must applied device order assure proper triggering. minimum current that must flowing (MT1 MT2; cathode anode) keep device regenerative on-state condition. Below this holding current value device will return blocking state, condition. minimum current that must applied through main terminals Triac cathode anode SCR) order turn from off-state on-state while being correctly applied. maximum value current which will flow VRRM specified temperature when Triac reverse mode, off-state. Frequently referred leakage current reverse off-state blocking mode. maximum average on-state current device safely conduct under stated conditions without incurring damage.
(di/dt)c
RATE CHANGE COMMUTATING CURRENT (Triacs)
dv/dt
CRITICAL RATE RISE OFF-STATE VOLTAGE
IDRM
PEAK REPETITIVE BLOCKING CURRENT
FORWARD PEAK GATE CURRENT (SCR) PEAK GATE CURRENT (Triac) GATE TRIGGER CURRENT
HOLDING CURRENT
LATCHING CURRENT
IRRM
PEAK REPETITIVE REVERSE BLOCKING CURRENT
IT(AV)
AVERAGE ON-STATE CURRENT (SCR)
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THYRISTOR TERMINOLOGY (The following terms used TRIAC specifications.)
Symbol I
Terminology PEAK REPETITIVE ON-STATE CURRENT (SCR) (also called PEAK DISCHARGE CURRENT)
Definition Peak discharge current capability thyristor useful when connected discharge peak current usually from capacitor. This rarely specified parameter. (See MCR68 MCR69 data sheets, examples where specified.) maximum value on-state current that applied device through main terminals Triac cathode anode SCR) continuous basis. maximum allowable non-repetitive surge current device will withstand specified pulse width, usually specified maximum forward non-repetitive overcurrent capability that device able handle without damage. Usually specified one-half cycle operation. maximum allowable value gate power, averaged over full cycle, that dissipated between gate cathode terminal (SCR), main terminal Triac. maximum instantaneous value gate power dissipation between gate cathode terminal between gate main terminal Triac, short pulse duration. thermal resistance (steady-state) from device case ambient. thermal resistance (steady-state) from semiconductor junction(s) ambient. thermal resistance (steady-state) from semiconductor junction(s) stated location case. thermal resistance (steady-state) from semiconductor junction(s) stated location mounting surface. temperature measured below device environment substantially uniform temperature, cooled only natural currents materially affected radiant reflective surfaces. temperature device case under specified conditions.
IT(RMS)
ON-STATE CURRENT
ITSM
PEAK NON-REPETITIVE SURGE CURRENT
CIRCUIT FUSING CONSIDERATIONS (Current squared time)
PG(AV)
FORWARD AVERAGE GATE POWER (SCR) AVERAGE GATE POWER (Triac)
FORWARD PEAK GATE POWER (SCR) PEAK GATE POWER (Triac)
THERMAL RESISTANCE, CASE-TO-AMBIENT THERMAL RESISTANCE, JUNCTION-TO-AMBIENT THERMAL RESISTANCE, JUNCTION-TO-CASE THERMAL RESISTANCE, JUNCTION-TO-MOUNTING SURFACE
AMBIENT TEMPERATURE
CASE TEMPERATURE
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THYRISTOR TERMINOLOGY (The following terms used TRIAC specifications.)
Symbol
Terminology TURN-ON TIME (SCR) (Also called Gate Controlled Turn-on Time)
Definition time interval between specified point beginning gate pulse instant when device voltage dropped specified value during switching from state state gate pulse. junction temperature device level result ambient load conditions. other words, junction temperature must operated within this range prevent permanent damage. time interval between instant when current decreased zero after external switching voltage circuit instant when thyristor capable supporting specified wave form without turning minimum maximum temperature which device stored without harm with electrical connections. maximum allowed value repetitive forward voltage which applied switch Triac damage thyristor. maximum rated operational temperature, specified main terminal off-state voltage applied, this parameter specifies maximum voltage that applied gate still switch device from off-state on-state. maximum peak value voltage allowed between gate cathode terminals with these terminals forward biased SCR. Triac, bias condition between gate main terminal MT1. gate voltage required produce gate trigger current. dielectric withstanding voltage capability thyristor between active portion device heat sink. Relative humidity specified condition. maximum allowable peak reverse voltage applied gate SCR. Measured specified which reverse gate current. maximum allowed value repetitive reverse voltage which applied switch Triac damage thyristor.
OPERATING JUNCTION TEMPERATURE
TURN-OFF TIME (SCR)
Tstg
STORAGE TEMPERATURE
VDRM
PEAK REPETITIVE OFF-STATE FORWARD VOLTAGE
GATE NON-TRIGGER VOLTAGE
FORWARD PEAK GATE VOLTAGE (SCR) PEAK GATE VOLTAGE (Triac)
GATE TRIGGER VOLTAGE
V(Iso)
ISOLATION VOLTAGE
VRGM
PEAK REVERSE GATE BLOCKING VOLTAGE (SCR)
VRRM
PEAK REPETITIVE REVERSE OFF-STATE VOLTAGE
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THYRISTOR TERMINOLOGY (The following terms used TRIAC specifications.)
Symbol V
Terminology PEAK FORWARD ON-STATE VOLTAGE (SCR) PEAK ON-STATE VOLTAGE (Triac)
Definition maximum voltage drop across main terminals stated conditions when devices on-state (i.e., when thyristor conduction). prevent heating junction, measured short pulse width duty cycle. transient thermal impedance from semiconductor junction(s) ambient. transient thermal impedance from semiconductor junction(s) stated location case.
ZJA(t)
TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-AMBIENT TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE
ZJC(t)
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Thyristor Surge Protector Devices (TSPD) Sidac Terminology*
Symbol
Terminology BREAKOVER CURRENT
Definition breakover current corresponding parameter defining condition, that where breakdown occurring. maximum value current which will flow specific voltages (VD1 VD2) when TSPD clearly off-state. Frequently referred leakage current. maximum pulse surge capability TSPD (non-repetitive) under double exponential decay waveform conditions. Defines instantaneous peak power dissipation when TSPD (thyristor surge suppressor devices) subjected specified surge current conditions. effective switching resistance usually under sinusoidal, condition. peak voltage point where device switches on-state condition. voltage where breakdown occurs. Usually given typical value reference Design Engineer. maximum off-state voltage prior TSPD going into characteristic similar avalanche mode. When transient line signal exceeds VDM, device begins avalanche, then immediately begins conduct. maximum voltage drop across terminals stated conditions when TSPD devices on-state (i.e., conduction). prevent overheating, measured short pulse width duty cycle.
ID1,
OFF-STATE CURRENT (TSPD)
Ipps
PULSE SURGE SHORT CIRCUIT CURRENT NON-REPETITIVE (TSPD)
INSTANTANEOUS PEAK POWER DISSIPATION (TSPD)
SWITCHING RESISTANCE (Sidac)
BREAKOVER VOLTAGE
V(BR)
BREAKDOWN VOLTAGE (TSPD)
OFF-STATE VOLTAGE (TSPD)
ON-STATE VOLTAGE (TSPD)
definitions this page ones that were already previously defined under Triac terminology.
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SECTION THEORY THYRISTOR OPERATION
Edited Updated
successfully apply thyristors, understanding their characteristics, ratings, limitations imperative. this chapter, significant thyristor characteristics, basis their ratings, their relationship circuit design discussed. Several different kinds thyristors shown Table 2.1. Silicon Controlled Rectifiers (SCRs) most widely used power control elements; triacs quite popular lower current (under power applications. Diacs, SUSs SBSs most commonly used gate trigger devices power control elements.
Table 2.1. Thyristor Types
*JEDEC Titles Reverse Blocking Diode Thyristor Reverse Blocking Triode Thyristor Reverse Conducting Diode Thyristor Reverse Conducting Triode Thyristor Bidirectional Triode Thyristor Popular Names, Types Four Layer Diode, Silicon Unilateral Switch (SUS) Silicon Controlled Rectifier (SCR) Reverse Conducting Four Layer Diode Reverse Conducting Triac
JEDEC acronym Joint Electron Device Engineering Councils, industry standardization activity co-sponsored Electronic Industries Association (EIA) National Electrical Manufacturers Association (NEMA). generally available.
Before considering thyristor characteristics detail, brief review their operation based upon common two-transistor analogy order. BASIC BEHAVIOR bistable action thyristors readily explained analysis structure SCR. This analysis essentially same operating quadrant triac because triac considered parallel SCRs oriented opposite directions. Figure 2.1(a) shows
schematic symbol SCR, Figure 2.1(b) shows P-N-P-N structure symbol represents. two-transistor model shown Figure 2.1(c), interconnections transistors such that regenerative action occurs. Observe that current injected into model, gain transistors sufficiently high) causes this current amplified another leg. order regeneration occur, necessary common base current gains transistors exceed unity. Therefore, because junction leakage currents relatively small current gain designed leakage current level, PNPN device remains unless external current applied. When sufficient trigger current applied gate, example, case SCR) raise loop gain unity, regeneration occurs on-state principal current limited primarily external circuit impedance. initiating trigger current removed, thyristor remains state, providing current level high enough meet unity gain criteria. This critical current called latching current. order turn thyristor, some change current must occur reduce loop gain below unity. From model, appears that shorting gate cathode would accomplish this. However actual structure, gate area only fraction cathode area very little current diverted short. practice, principal current must reduced below certain level, called holding current, before gain falls below unity turn-off commence. fabricating practical SCRs Triacs, "shorted emitter" design generally used which, schematically, resistor added from gate cathode gate MT1. Because current diverted from N-base through resistor, gate trigger current, latching current holding current increase. principal reasons shunt resistance improve dynamic performance high temperatures. Without shunt, leakage current most high current thyristors could initiate turn-on high temperatures.
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Sensitive gate thyristors employ high resistance shunt none all; consequently, their characteristics altered dramatically external resistance. external resistance minor effect most shorted emitter designs.
ANODE ANODE
GATE CATHODE ANODE GATE CATHODE CATHODE GATE
Figure 2.1. Two-transistor analogy SCR: schematic symbol SCR; P-N-P-N structure represented schematic symbol; two-transistor model SCR.
from leakage, avalanche breakdown blocking junction. result, breakover voltage thyristor varied controlled injection current gate terminal. Figure shows interaction gate current voltage SCR. When gate current zero, applied voltage must reach breakover voltage before switching occurs. value gate current increased, however, ability thyristor support applied voltage reduced there certain value gate current which behavior thyristor closely resembles that rectifier. Because thyristor turn-on, result exceeding breakover voltage, produce high instantaneous power dissipation non-uniformly distributed over area during switching transition, extreme temperatures resulting failure occur unless magnitude rate rise principal current (di/dt) restricted tolerable levels. normal operation, therefore, SCRs triacs operated applied voltages lower than breakover voltage, made switch state gate signals high enough assure complete turn-on independent applied voltage. other hand, diacs other thyristor trigger devices designed triggered anode breakover. Nevertheless they also have di/dt peak current limits which must adhered
Junction temperature primary variable affecting thyristor characteristics. Increased temperatures make thyristor easier turn keep Consequently, circuit conditions which determine turn-on must designed operate lowest anticipated junction temperatures, while circuit conditions which turn thyristor prevent false triggering must designed operate maximum junction temperature. Thyristor specifications usually written with case temperatures specified with electrical conditions such that power dissipation enough that junction temperature essentially equals case temperature. incumbent upon user properly account changes characteristics caused circuit operating conditions different from test conditions. TRIGGERING CHARACTERISTICS Turn-on thyristor requires injection current raise loop gain unity. current take form current applied gate, anode current resulting
Figure 2.2. Thyristor Characteristics Illustrating Breakover Function Gate Current
triac works same general both positive negative voltage. However since triac switched either polarity gate signal regardless voltage polarity across main terminals, situation somewhat more complex than SCR. various combinations gate main terminal polarities shown Figure 2.3. relative sensitivity depends physical structure particular triac, rule, sensitivity highest quadrant quadrant generally considerably less sensitive than others.
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MT2(+) QUADRANT MT2(+), G(-) G(-) QUADRANT MT2(+), G(+) G(+)
QUADRANT MT2(-), G(-)
QUADRANT MT2(-), G(+)
MT2(-)
Figure 2.3. Quadrant Definitions Triac
Gate sensitivity triac function temperature shown Figure 2.4.
IGT, GATE TRIGGER CURRENT (mA) OFF-STATE VOLTAGE QUADRANTS
Although criteria turn-on have been described terms current, more basic consider thyristor being charge controlled. Accordingly, duration trigger pulse reduced, amplitude must correspondingly increased. Figure shows typical behavior various pulse widths temperatures. gate pulse width required trigger thyristor also depends upon time required anode current reach latching value. necessary maintain gate signal throughout conduction period applications where load highly inductive where anode current swing below holding value within conduction period. When triggering with current, excess leakage reverse direction normally occurs trigger signal maintained during reverse blocking phase anode voltage. This happens because operates like remote base transistor having gain which generally about 0.5. When high gate drive currents used, substantial dissipation could occur significant current could flow load; therefore, some means usually must provided remove gate signal during reverse blocking phase.
PEAK GATE CURRENT (mA) OFF-STATE VOLTAGE
QUADRANT JUNCTION TEMPERATURE (°C)
-55°C 25°C 100°C PULSE WIDTH
Figure 2.4. Typical Triac Triggering Sensitivity Four Trigger Quadrants
Since both junction leakage currents current gain "transistor" elements increase with temperature, magnitude required gate trigger current decreases temperature increases. gate which regarded diode exhibits decreasing voltage drop temperature increases. Thus important that gate trigger circuit designed deliver sufficient current gate lowest anticipated temperature. also advisable observe maximum gate current, well peak average power dissipation ratings. Also negative direction, maximum gate ratings should observed. Both positive negative gate limits often given data sheets they indicate that protective devices such voltage clamps current limiters required some applications. generally inadvisable dissipate power reverse direction.
Figure 2.5. Typical Behavior Gate Trigger Current Pulse Width Temperature Varied
LATCH HOLD CHARACTERISTICS order thyristor remain state when trigger signal removed, necessary have sufficient principal current flowing raise loop gain unity. principal current level required latching current, Although triacs show some dependency gate current quadrant latching current primarily affected temperature shorted emitter structures. order allow turn off, principal current must reduced below level latching current. current level where turn occurs called holding current, Like latching current, holding current affected temperature also depends gate impedance.
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Reverse voltage gate markedly increases latch hold levels. Forward bias thyristor gates significantly lower values shown data sheets since those values normally given with gate open. Failure take this into account cause latch hold problems when thyristors being driven from transistors whose saturation voltages tenths volt. Thyristors made with shorted emitter gates obviously sensitive gate circuit conditions devices which have built-in shunt. SWITCHING CHARACTERISTICS When triacs SCRs triggered gate signal, turn-on time consists stages: delay time, rise time, shown Figure 2.6. total gate controlled turn-on time, tgt, usually defined time interval between percent point leading edge gate trigger voltage percent point principal current. rise time time interval required principal current rise from percent maximum value. resistive load usually specified.
POINT PRINCIPAL VOLTAGE POINT
PRINCIPAL CURRENT GATE CURRENT
POINT POINT
POINT
(WAVESHAPES SENSITIVE LOAD)
Figure 2.6. Waveshapes Illustrating Thyristor Turn-On Time Resistive Load
Delay time decreases slightly peak off-state voltage increases. primarily related magnitude
gate-trigger current shows relationship which roughly inversely proportional. rise time influenced primarily off-state voltage, high voltage causes increase regenerative gain. major importance rise time interval relationship between principal voltage current flow through thyristor di/dt. During this time dynamic voltage drop high current density possible rapid rate change produce localized spots die. This permanently degrade blocking characteristics. Therefore, important that power dissipation during turn-on restricted safe levels. Turn-off time property associated only with SCRs other unidirectional devices. triacs bidirectional devices reverse voltage cannot used provide circuit-commutated turn-off voltage because reverse voltage applied half structure would forward-bias voltage other half.) turn-off times SCRs, recovery period consists stages, reverse recovery time gate forward blocking recovery time, shown Figure 2.7. When forward current reduced zero conduction period, application reverse voltage between anode cathode terminals causes reverse current flow SCR. current persists until time that reverse current decreases leakage level. Reverse recovery time (trr) usually measured from point where principal current changes polarity specified point reverse current waveform indicated Figure 2.7. During this period anode cathode junctions being swept free charge that they support reverse voltage. second recovery period, called gate recovery time, tgr, must elapse charge stored forward-blocking junction recombine that forward-blocking voltage reapplied successfully blocked SCR. gate recovery time usually much longer than reverse recovery time. total time from instant reverse recovery current begins flow start forward-blocking voltage referred circuit- commutated turn-off time Turn-off time depends upon number circuit conditions including on-state current prior turn-off, rate change current during forward-to-reverse transition, reverse-blocking voltage, rate change reapplied forward voltage, gate bias, junction temperature. Increasing junction temperature state current both increase turn-off time have more
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significant effect than other factors. Negative gate bias will decrease turn-off time.
REAPPLIED dv/dt
PRINCIPAL VOLTAGE
FORWARD
REVERSE
di/dt FORWARD
PRINCIPAL CURRENT
REVERSE
Figure 2.7. Waveshapes Illustrating Thyristor Turn-Off Time
applications which used control power, during entire negative half sine wave reverse voltage applied. Turn easily accomplished most devices frequencies kilohertz. applications which used control output full-wave rectifier bridge, however, there reverse voltage available turn-off, complete turn-off accomplished only bridge output reduced close zero such that principal current reduced value lower than device holding current sufficiently long time. Turn-off problems occur even frequency particularly inductive load being controlled. triacs, rapid application reverse polarity voltage does cause turn-off because main blocking junctions common both halves device. When first triac structure (SCR-1) conducting state, quantity charge accumulates N-type region result principal current flow. principal current crosses zero reference point, reverse current established result charge remaining N-type region, which common both halves device. Consequently, reverse recovery current
becomes forward current second half triac. current resulting from stored charge causes second half triac into conducting state absence gate signal. Once current conduction been established application gate signal, therefore, complete loss power control occur result interaction within N-type base region triac unless sufficient time elapses rate application reverse polarity voltage slow enough allow nearly charge recombine common N-type region. Therefore, triacs generally limited low-frequency applications. Turn-off commutation triacs more severe with inductive loads than with resistive loads because phase between voltage current associated with inductive loads. Figure shows waveforms inductive load with lagging current power factor. time current reaches zero crossover (Point half triac conduction begins commutate when principal current falls below holding current. instant conducting half triac turns off, applied voltage opposite current polarity applied across triac terminals (Point Because this voltage forward bias second half triac, suddenly reapplied voltage conjunction with remaining stored charge high-voltage junction reduces over-all device capability support voltage. result loss power control load, device remains conducting state absence gate signal. measure triac turn-off ability rate rise opposite polarity voltage handle without remaining called commutating dv/dt (dv/dt[c]). Circuit conditions temperature affect dv/dt(c) manner similar affected SCR. imperative that some means provided restrict rate rise reapplied voltage value which will permit triac turn-off under conditions inductive load. commonly accepted method keeping commutating dv/dt within tolerable levels snubber network parallel with main terminals triac. Because rate rise applied voltage triac terminals function load impedance snubber network, circuit evaluated under worst-case conditions operating case temperature maximum principal current. values resistance capacitance snubber area then adjusted that rate rise commutating dv/dt stress within specified minimum limit under conditions mentioned above. value snubber resistance should high enough limit snubber capacitance discharge currents during turn-on dampen oscillation during commutation. combination snubber values having highest resistance lowest capacitance that provides satisfactory operation generally preferred.
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Figure 2.8. Inductive Load Waveforms
FALSE TRIGGERING Circuit conditions cause thyristors turn absence trigger signal. False triggering result from: high rate rise anode voltage, (the dv/dt effect). Transient voltages causing anode breakover. Spurious gate signals. Static dv/dt effect: When source voltage suddenly applied thyristor which state, switch from state conducting state. thyristor controlling alternating voltage, false turn-on resulting from transient imposed voltage limited more than one-half cycle applied voltage because turn-off occurs during zero current crossing. However, principal voltage voltage, transient cause switching state turn-off could then achieved only circuit interruption. switching from state caused rapid rate rise anode voltage result internal capacitance thyristor. voltage wavefront impressed across terminals thyristor causes capacitance-charging current flow through device which function rate rise applied off-state voltage dv/dt). rate rise voltage exceeds critical value, capacitance charging current exceeds gate triggering current causes device turn-on. Operation elevated junction temperatures reduces thyristor ability support steep rising voltage dv/dt because increased sensitivity. dv/dt ability improved quite markedly sensitive gate devices some extent shorted emitter designs resistance from gate cathode MT1) however reverse bias voltage even more effective SCR. More commonly, snubber network used keep dv/dt within limits thyristor when gate open. TRANSIENT VOLTAGES: Voltage transients which occur electrical systems result disturbance line caused various sources such energizing transformers, load switching, solenoid closure, contractors like generate voltages which
above ratings thyristors. Thyristors, general, switch from state state whenever breakover voltage device exceeded, energy then transferred load. However, unless thyristor specified breakover mode, care should exercised ensure that breakover does occur, some devices incur surface damage with resultant degradation blocking characteristics. good practice when thyristors exposed heavy transient environment provide some form transient suppression. applications which low-energy, long-duration transients encountered, advisable thyristors that have voltage ratings greater than highest voltage transient expected system. voltage clipping cells (MOV Zener) also effective method hold transient below thyristor ratings. "snubber" circuit effective reducing effects high-energy short-duration transients more frequently encountered. snubber commonly required prevent static dv/dt limits from being exceeded, often satisfactory limiting amplitude voltage transients well. applications, dv/dt limits exceeded. This minimum value rate rise off-state voltage applied immediately MT1-MT2 terminals after principal current opposing polarity decreased zero. SPURIOUS GATE SIGNALS: noisy electrical environments, possible enough energy cause gate triggering coupled into gate wiring stray capacitance electromagnetic induction. therefore advisable keep gate lead short have common return directly cathode MT1. extreme cases, shielded wire required. Another commonly used connect capacitance order 0.01 across gate cathode terminals. This added advantage increasing thyristor dv/dt capability, since forms capacitance divider with anode gate capacitance. gate capacitor also reduces rate application gate trigger current which cause di/dt failures high inrush load present. THYRISTOR RATINGS insure long life proper operation, important that operating conditions restrained from exceeding thyristor ratings. most important fundamental ratings temperature voltage which interrelated some extent. voltage ratings applicable only maximum temperature ratings particular part number. temperature rating chosen manufacturer insure satisfactory voltage ratings, switching speeds, dv/dt ability.
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OPERATING CURRENT RATINGS Current ratings independently established rule. values chosen such that practical case temperature power dissipation will cause junction temperature rating exceeded. Various manufacturers chose different criteria establish ratings. Semiconductors, made thermal response semiconductor worst case values on-state voltage thermal resistance, guarantee junction temperature below rated value. Values shown data sheets consequently differ somewhat from those computed from standard formula:
TC(max) where (max) (rated) (rated) PD(AV) Maximum allowable case temperature Rated junction temperature maximum rated case temperature with zero principal current rated blocking voltage applied. Junction case thermal resistance Average power dissipation
PD(AV)
triac, current waveform used rating full sine wave. Multicycle surge curves used select proper circuit breakers series line impedances prevent damage thyristor event equipment fault. subcycle overload subcycle surge rating curve called because time duration rating usually from about eight milliseconds which less than time cycle power source. Overload peak current often given curve form function overload duration. This rating also applies following rated load condition neither off-state reverse blocking capability required part thyristor immediately following overload current. subcycle surge current rating used select proper current-limiting fuse protection thyristor event equipment fault. Since this rating common, manufacturers simply publish rating place subcycle current overload curve because fuses commonly rated terms i2t. rating approximated from single cycle surge rating (ITSM) using:
I2TSM
above formula generally suitable estimating case temperature situations covered data sheet information. Worst case values should used thermal resistance power dissipation. OVERLOAD CURRENT RATINGS Overload current ratings divided into types: non-repetitive repetitive. Non-repetitive overloads those which part normal application device. Examples such overloads faults equipment which devices used accidental shorting load. Non-repetitive overload ratings permit device exceed maximum operating junction temperature short periods time because this overload rating applies following rated load condition. case reverse blocking thyristor SCR, device must block rated voltage reverse direction during current overload. However, type thyristor required block off-stage voltage time during immediately following overload. Thus, case triac, device need block either direction during immediately following overload. Usually only approximately hundred such current overloads permitted over life device. These non-repetitive overload ratings just described divided into types: multicycle (which include single cycle) subcycle. SCR, multicycle overload current rating, surge current rating commonly called, generally presented curve giving maximum peak values half sine wave on-state current function overload duration measured number cycles frequency.
where time time base overload, i.e., 8.33 frequency. Repetitive overloads those which intended part application such motor drive application. Since this type overload occur large number times during life thyristor, rated maximum operating junction temperature must exceeded during overload long thyristor life required. Since this type overload have complex current waveform duty-cycle, current rating analysis involving transient thermal impedance characteristics often only practical approach. this type analysis, thyristor junction-to-case transient thermal impedance characteristic added user's heat dissipator transient thermal impedance characteristic. Then superposition power waveforms conjunction with composite thermal impedance curve, overload current rating obtained. exact calculation procedure found power semiconductor literature. THEORY POWER CONTROL most common form power control phase control. this mode operation, held condition portion positive half cycle then triggered into condition time half cycle determined control circuitry which circuit current limited only load entire line voltage except nominal volt drop across applied load).
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alone control only half cycle waveform. full wave control, SCRs connected inverse parallel (the anode each connected cathode other, Figure 2.9a). full wave control, methods possible. SCRs used bridge rectifier (see Figure 2.9b) placed series with diode bridge (see Figure 2.9c). Figure 2.10 shows voltage waveform along with some common terms used describing operation. Delay angle time, measured electrical degrees, during which blocking line voltage. period during which called conduction angle. important note that voltage controlling device. load power source determine circuit current. arrive problem. Different loads respond different characteristics waveform. Some loads sensitive peak voltage, some average voltage some voltage. Figures 2.11(b) 2.12(b) show various characteristic voltages plotted against conduction angle half wave full wave circuits. These voltages have been normalized applied voltage. determine actual peak, average voltage conduction angle, simply multiply normalized voltage value applied line voltage. (These normalized curves also apply current resistive circuit.) Since greatest majority circuits either volt power, curves have been redrawn these voltages Figures 2.11(a) 2.12(a). relative power curve been added Figure 2.12 constant impedance loads such heaters. (Incandescent lamps motors follow this curve precisely since their relative impedance changes with applied voltage.) curves, find full wave rated power load, then multiply fraction associated with phase angle question. example, 180° conduction angle half wave circuit provides full wave full-conduction power. interesting point illustrated power curves. conduction angle provides only three cent full power full wave circuit, conduction angle 150° provides cent full power. Thus, control circuit provide cent full power control with pulse phase variation only 120°. Thus, becomes pointless many cases obtain conduction angles less than greater than 150°.
CONTROL CHARACTERISTICS
simplest most common control circuit phase control relaxation oscillator. This circuit shown diagrammatically would used with Figure 2.13. capacitor charged through resistor from voltage current source until breakover voltage trigger device reached. that time, trigger device changes state, capacitor discharged through gate SCR. Turn-on thus accomplished with short, high current pulse. Commonly used trigger devices programmable unijunction transistors, silicon bilateral switches, SIDACs, optically coupled thyristors, power control integrated circuits. Phase control obtained varying time constant charging circuit that trigger device turn-on occurs varying phase angles within controlled half cycle. relaxation oscillator operated from pure source, capacitor voltage-time characteristic shown Figure 2.14. This shows capacitor voltage rises supply voltage through several time constants. Figure 2.14(b) shows charge characteristic first time constant greatly expanded. this portion capacitor charge characteristic which most often used Triac control circuits. Generally, design starting point selection capacitance value which will reliably trigger thyristor when capacitor discharged. Gate characteristics ratings, trigger device properties, load impedance play part selection. Since important parameters this selection completely specified, experimental determination often best method. Low-current loads strongly inductive circuits sometimes cause triggering difficulty because gate current pulse goes away before principal thyristor current achieves latching value. series gate resistor used introduce discharge time constant gate circuit lengthen trigger pulse duration allowing more time main terminal current rise latching value. Small thyristors will require series gate resistance avoid exceeding gate ratings. discharge time constant snubber, used, also latching. duration these capacitor discharge duration currents estimated tw10 where tw10 time current decay peak.
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LINE CONTROL CIRCUIT
LINE
LOAD CONTROL CIRCUIT LOAD
Control
Control Figure 2.9. Connections Various Methods Phase Control
FULL WAVE RECTIFIED OPERATION VOLTAGE APPLIED LOAD
LINE
CONTROL CIRCUIT
LOAD
DELAY ANGLE CONDUCTION ANGLE
Control
Figure 2.10. Sine Wave Showing Principles Phase Control
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NORMALIZED SINE WAVE VOLTAGE POWER FRACTION FULL CONDUCTION
HALF WAVE PEAK VOLTAGE
APPLIED VOLTAGE VOLTAGE
HALF WAVE
PEAK VOLTAGE
POWER
CONDUCTION ANGLE
CONDUCTION ANGLE
Figure 2.11. Half-Wave Characteristics Thyristor Power Control
NORMALIZED SINE WAVE VOLTAGE POWER FRACTION FULL CONDUCTION
FULL WAVE PEAK VOLTAGE
APPLIED VOLTAGE VOLTAGE
FULL WAVE
PEAK VOLTAGE
POWER
CONDUCTION ANGLE
CONDUCTION ANGLE
Figure 2.12. Full-Wave Characteristics Thyristor Power Control
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many recently proposed circuits cost operation, timing capacitor relaxation oscillator charged through rectifier resistor using power line source. Calculations charging time with this circuit become exceedingly difficult, although they still necessary circuit design. curves Figure 2.14 simplify design immensely. These curves show voltage-time characteristic capacitor charged from half cycle sine wave. Voltage
normalized value sine wave convenience use. parameter curves term, ratio time constant period half cycle, denoted Greek letter most easily calculated from equation
2RCf. Where: resistance Ohms capacitance Farads frequency Hertz.
CAPACITOR VOLTAGE FRACTION SUPPLY VOLTAGE CAPACITOR VOLTAGE FRACTION SUPPLY VOLTAGE TIME CONSTANTS
TIME CONSTANTS
Figure 2.13(a). Capacitor Charging From Source
Figure 2.13(b). Expanded Scale
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1.80 1.40 NORMALIZED VOLTAGE FRACTION CHARGING SOURCE VOLTAGE 1.20 0.80 0.707 0.60 0.40 0.20 CAPACITOR VOLTAGE, APPLIED VOLTAGE,
DELAY ANGLE DEG. CONDUCTION ANGLE DEG.
Figure 2.14(a). Capacitor Voltage When Charged
0.35 NORMALIZED VOLTAGE FRACTION CHARGING SOURCE VOLTAGE 0.30 0.25 0.20 0.15 0.10 0.05
DELAY ANGLE DEG. CONDUCTION ANGLE DEG.
Figure 2.14(b). Expansion Figure 2.15(a).
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NORMALIZED VOLTAGE FRACTION CHARGING SOURCE VOLTAGE
0.09 0.08 0.0696 0.07 0.06 0.05 0.04 0.03 0.02 0.01
12.5
CHARGING SOURCE VOLTAGE
DELAY ANGLE DEG. CONDUCTION ANGLE DEG.
Figure 2.14(c). Expansion Figure 2.14(b)
curves when starting capacitor charge from zero each half cycle, line drawn horizontally across curves relative voltage level trigger breakdown compared sine wave voltage. determined maximum minimum conduction angles limits found from equation example will again clarify picture. Consider same problem previous example, except that capacitor charging source Vac, power line. ratio trigger diode breakover voltage charging voltage then
8/115 69.6 10-3.
prevented selecting lower value resistor larger capacitor. available current determined from Figure 2.14(a). vertical line drawn from conduction angle intersects applied voltage curve 0.707. instantaneous current breakover then
(0.707 115-8)/110
line drawn 0.0696 ordinate Figure 2.14(c) shows that conduction angle 30°, conduction angle 150°, 0.8. Therefore, since /(2CF)
Rmax 2(1.0 ohms, 6)60
Rmin
6667 ohms. 10-6
When conduction angle greater than 90°, triggering takes place before peak sine wave. current thru does exceed switching current moment breakover, triggering still take place predicted time because additional delay rising line voltage drive current switching level. Usually long conduction angles associated with value timing resistors making this problem less likely. current moment breakover determined same method described trailing edge. advisable shunt gate-cathode resistor across sensitive gate SCR's provide path leakage currents insure that firing causes turn-on trigger device discharge gate circuit capacitor. TRIAC THEORY triac three-terminal semiconductor switch which triggered into conduction when low-energy signal applied gate. Unlike silicon controlled rectifier SCR, triac will conduct current either direction when turned triac also differs from that either positive negative gate signal will trigger triac into conduction. triac thought complementary SCRs parallel.
These values would require potentiometer series with minimum fixed resistance. timing resistor must capable supplying highest switching current allowed specification switching voltage. When conduction angle less than 90°, triggering takes place along back power line sine wave maximum firing current thru start breakover. this current does equal exceed "ls" will fail trigger phase control will lost. This
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triac offers circuit designer economical versatile means accurately controlling power. several advantages over conventional mechanical switches. Since triac positive "on" zero current "off" characteristic, does suffer from contact bounce arcing inherent mechanical switches. switching action triac very fast compared conventional relays, giving more accurate control. triac triggered rectified pulses. Because energy required triggering triac, control circuit many low-cost solid-state devices such transistors, bilateral switches, sensitive- gate SCRs triacs, optically coupled drivers integrated circuits. CHARACTERISTICS TRIAC Figure 2.15(a) shows triac symbol relationship typical package. Since triac bilateral device, terms "anode" "cathode" used unilateral devices have meaning. Therefore, terminals simply designated MT1, MT2, where current-carrying terminals, gate terminal used triggering triac. avoid confusion, become standard practice specify currents voltages using reference point. basic structure triac shown Figure 2.15(b). This drawing shows symbol adopted triac consists complementary SCRs with common gate. triac five-layer device with region between being P-N-P-N switch (SCR) parallel with N-P-N-P switch (complementary SCR). Also, structure gives some insight into triac's ability triggered with either positive negative gate signal. region between consists complementary diodes. positive negative gate signal will forward-bias these diodes causing same transistor action found SCR. This action breaks down blocking junction regardless polarity MT1. Current flow between then causes device provide gate current internally. will remain until this current flow interrupted. voltage-current characteristic triac shown Figure 2.16 where, previously stated, used reference point. first quadrant, Q-I, region where positive with respect quadrant opposite case. Several terms used characterizing triac shown figure. VDRM breakover voltage device highest voltage triac allowed block either
direction. this voltage exceeded, even transiently, triac into conduction without gate signal. Although triac damaged this action current limited, this situation should avoided because control triac lost. triac particular application should have VDRM least high peak waveform applied reliable control maintained. holding current (IH) minimum value current necessary maintain conduction. When current goes below triac ceases conduct reverse blocking state. IDRM leakage current triac with VDRM applied from several orders magnitude smaller than current rating device. figure shows characteristic triac without gate signal applied should noted that triac triggered into state value voltage VDRM application gate signal. This important characteristic makes triac very useful. Since triac will conduct either direction triggered with either positive negative gate signal there four possible triggering modes (Figure 2.3): Quadrant MT2(+), G(+), positive voltage positive gate current. Quadrant MT2(+), G(-), positive voltage negative gate current. Quadrant III; MT2(-), G(-), negative voltage negative gate current. Quadrant MT2(-), G(+), negative voltage positive gate current. Present triacs most sensitive quadrants III, slightly less quadrant much less sensitive quadrant Therefore recommended quadrant unless special circumstances dictate important fact remember that since triac conduct current both directions, only brief interval during which sine wave current passing through zero recover revert blocking state. this reason, reliable operation present triacs limited line frequency lower frequencies. inductive loads, phase-shift between current voltage means that time current falls below triac ceases conduct, there exists certain voltage which must appear across triac. this voltage appears rapidly, triac will resume conduction control lost. order achieve control with certain inductive loads, rate rise voltage (dv/dt) must limited series network across triac. capacitor will then limit dv/dt across triac. resistor necessary limit surge current from capacitor when triac fires, damp ringing capacitance with load inductance.
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PHASE CONTROL
GATE
Figure 2.15. Triac Structure Symbol
ON-STATE
IDRM
VDRM
VDRM
MT2+ BLOCKING STATE
effective widely-used method controlling average power load through triac phase control. Phase control method utilizing triac apply supply load controlled fraction each cycle. this mode operation, triac held open condition portion each positive negative cycle, then triggered into condition time half cycle determined control circuitry. condition, circuit current limited only load i.e., entire line voltage (less forward drop triac) applied load. Figure 2.17 shows voltage waveform along with some common terms used describing triac operation. Delay angle angle, measured electrical degrees, during which triac blocking line voltage. period during which triac called conduction angle. important note that triac either (blocking voltage) fully (conducting). When condition, circuit current determined only load power source. might expect, spite usefulness, phase control without disadvantages. main disadvantage using phase control triac applications generation electro-magnetic interference (EMI). Each time triac fired load current rises from zero load-limited current value very short time. resulting di/dt generates wide spectrum noise which interfere with operation nearby electronic equipment unless proper filtering used.
ZERO POINT SWITCHING
BLOCKING STATE QIII ON-STATE
IDRM
Figure 2.16. Triac Voltage-Current Characteristic
METHODS CONTROL
SWITCH
useful application triac direct replacement mechanical relay. this application, triac furnishes on-off control power-regulating ability triac utilized. control circuitry this application usually very simple, consisting source gate signal some type small current switch, either mechanical electrical. gate signal obtained from separate source directly from line voltage terminal triac.
addition filtering, minimized zero-point switching, which often preferable. Zero- point switching technique whereby control element this case triac) gated instant sine wave voltage goes through zero. This reduces, eliminates, turn-on transients EMI. Power load controlled providing bursts complete sine waves load shown Figure 2.18. Modulation random basis with on-off control, proportioning basis with proper type proportional control. order zero-point switching effective, must indeed zero point switching. triac turned with little volts across into load few-hundred watts, sufficient will result nullify advantages adopting zero-point switching first place. BASIC TRIAC SWITCHES Figure 2.19 shows methods using triac on-off switch. These circuits useful applications where simplicity reliability important. previously stated, there arcing with triac, which very important some applications. circuits resistive loads shown require addition dv/dt network across triac inductive loads.
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Figure 2.19(a) shows low-voltage control triac. When switch closed, gate current supplied triac from volt battery. order reduce surge current failures during turn (ton), this current should times maximum gate current (IGT) required trigger triac. triac turns remains until opened. This circuit switches zero current except initial turn very-low-current switch because carries only triac gate current. Figure 2.19(b) shows triac switch with same characteristics circuit Figure 2.19(a) except need battery been eliminated. gate signal obtained from voltage triac prior turn circuit shown Figure 2.19(c) modification Figure 2.19(b). When switch position one, triac receives gate current non-conducting. With position two, circuit operation same that Figure 2.19(b). position three, triac receives gate current only positive half cycles. Therefore, triac conducts only positive half cycles power load half wave. Figure 2.19(d) shows control triac. pulse transformer coupled isolate power control circuits. Peak current should times IGT(max) time constant should times ton(max). high frequency pulse kHz) often used obtain zero point switching.
VOLTAGE APPLIED LOAD
applied load shown Figure 2.20. This type switching primarily used control power resistive loads such heaters. also used controlling speed motors duty cycle modulated having short bursts power applied load load characteristic primarily inertial rather than frictional. Modulation random basis with on-off control, proportioning basis with proper type proportioning control. order zero-point switching effective, must true zero-point switching. turned with anode voltage volts load just hundred watts, sufficient will result nullify advantages going zero-point switching first place. thyristor turned must receive gate drive exactly zero crossing applied voltage. most successful method zero-point thyristor control therefore, have gate signal applied before zero crossing. soon zero crossing occurs, anode voltage will supplied thyristor will come This effectively accomplished using capacitor derive leading gate signal from power line source. However, only thyristor controlled from this phase-shifted signal, slaving circuit necessary control other full-wave power control. These basic ideas illustrated Figure 2.21. slaving circuit fires only half cycle after firing master SCR. This guarantees that only complete cycles power will applied load. gate signal master receives control; convenient control method replace switch with low-power transistor, which controlled bridge- sensing circuits, manually controlled potentiometers, various other techniques.
DELAY ANGLE CONDUCTION ANGLE HALF POWER LOAD
LOAD VOLTAGE
Figure 2.17. Sine Wave Showing Principles Phase Control
LINE VOLTAGE
ZERO POINT SWITCHING TECHNIQUES Zero-point switches highly desirable many applications because they generate electro-magnetic interference (EMI). zero-point switch controls sine-wave power such that either complete cycles half cycles power supply voltage
FULL POWER LOAD
Figure 2.18. Sine Wave Showing Principles Zero-Point Switching
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LOAD LOAD VOLTAGE 2N6346 LINE VOLTAGE
(a): Voltage Controlled Triac Switch
Figure 2.20. Load Voltage Line Voltage Duty Cycle
LOAD 2N6342
(b): Triac Static Contactor
LOAD 2N6342
(c): Position Static Switch
LOAD
2N6346
(d): Controlled Triac Switch Figure 2.19. Triac Switches
basic very effective trouble free. However, dissipate considerable power. This must taken into account designing circuit packaging. case triacs, slaving circuit also usually required furnish gate signal negative half cycle. However, triacs slave circuits requiring less power than SCRs shown Figure 2.21. Other considerations being equal, easier slaving will sometimes make triac circuit more desirable than circuit. Besides slaving circuit power dissipation, there another consideration which should carefully checked when using high-power zero-point switching. Since this on-off switching, abruptly applies full load power line every time circuit turns This cause temporary drop voltage which lead erratic operation other electrical equipment line (light dimming, picture shrinkage, etc.). this reason, loads with high cycling rates should powered from same supply lines lights other voltage-sensitive devices. other hand, load cycling rate slow, once half minute, loading flicker objectionable lighting circuits. note caution order here. full-wave zero-point switching control illustrated Figure 2.21 should used half-wave control removing slave SCR. When slave Figure 2.21 removed, master positive gate current flowing over approximately cycle while itself reverse-blocking state. This occurs during negative half cycle line voltage. When this condition exists, will have high leakage current with full voltage applied will therefore dissipating high power. This will cause excessive heating lead failure. desirable such circuit half-wave control, then some means clamping gate signal during negative half cycle must devised inhibit gate current while reverse blocking. circuits shown Figures 2.23 2.24 have this disadvantage used half-wave controls.
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OPERATION
LINE LOAD (MASTER)
(SLAVE)
Figure 2.21. Slave Master SCRs Zero-Point Switching
LINE ON-OFF CONTROL
MAC210A8
LOAD
Figure 2.22. Triac Zero-Point Switch
LINE 1N4004 1N4004 LOAD 0.25 1N5760 1N4004 MCR22-6
Figure 2.23. Sensitive-Gate Switch
LINE 1N4004
0.25 1N4004 1N5760 1N4004
LOAD MCR218-4
Figure 2.24. Zero-Point Switch
zero-point switches shown Figure 2.23 2.24 used insure that control turns start each positive alternation. Figure 2.23 pulse generated before zero crossing provides small amount gate current when line voltage starts positive. This circuit primarily sensitive-gate SCRs. Less-sensitive SCRs, with their higher gate currents, normally require smaller values result high power dissipation these resistors. circuit Figure 2.24 uses capacitor, provide low-impedance path around resistors used with less-sensitive, higher-current SCRs without increasing dissipation. This circuit actually oscillates near zero crossing point provides series pulses assure zero-point switching. basic circuit that shown Figure 2.23. Operation begins when switch closed. positive alternation present, nothing will happen since diode reverse biased. When negative alternation begins, capacitor will charge through resistor toward limit voltage voltage divider consisting resistors negative alternation reaches peak, will have charged about volts. Line voltage will decrease cannot discharge because diode will reverse biased. seen that three-layer diode effectively series with line. When line drops volts, will still volts positive with respect gate this time will about volts will trigger. This allows discharge through gate This discharge current will continue flow line voltage crosses zero will insure that turns start positive alternation. Diode prevents reverse gate-current flow resistor prevents false triggering. circuit Figure 2.24 operates similar manner point where starts discharge into gate. discharge path will from through gate capacitor will quickly charge from this high pulse current. This reduces voltage across causing turn again revert blocking state. will discharge through until voltage again becomes sufficient cause break back. This repetitive exchange charge from causes series gate-current pulses flow line voltage crosses zero. This means that will again turned start each positive alternation desired. Resistor been added limit peak gate current.
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SLAVING CIRCUIT
slaving circuit will provide full-wave control load when control signal available only pair SCRs. slaving circuit commonly used where master controlled zero-point switching. Zero-point switching causes load receive full cycle line voltage whenever control signal applied. duty cycle control signal therefore determines average amount power supplied load. Zero-point switching necessary large loads such electric heaters because conventional phase-shift techniques would generate excessive amount electro-magnetic interference (EMI). This particular slaving circuit important advantages over standard discharge slaving circuits. derives these advantages with practically increase price using low-cost transistor place current-limiting resistor normally used slaving. first advantage that large pulse gate current available zero-crossing point. This means that necessary select sensitive-gate SCRs controlling power. second advantage that this current pulse reduced zero within alternation. This couple good effects operation slaving SCR. prevents gate drive from appearing while reverse-biased, which would produce high power dissipation within device. also prevents slaved from being turned additional half cycles after drive removed from control SCR.
OPERATION
being charged, reverse-biases base-emitter junction thereby holding off. charging time constant, long enough that charges practically entire half cycle. charging rate follows shaped curve, charging slowly first, then faster supply voltage peaks, finally slowly again supply voltage decreases. When supply voltage falls below voltage across diode becomes reverse biased base-emitter becomes forward biased. values shown, this occurs approximately before half cycle conduction base current derived from energy stored This turns discharging through into gate voltage across decreases, base drive decreases somewhat limits collector current. current pulse must last until line voltage reaches magnitude such that latching current will exist values shown will deliver current pulse which peaks magnitude greater than when anode- cathode voltage reaches plus volts. This circuit completely discharges during half cycle that This eliminates possibility being slaved additional half cycles after drive removed from peak current current duration controlled values values chosen provide sufficient drive "shorted emitter" SCRs which typically require fire. particular used must capable handling maximum current requirements load driven; ampere, SCRs shown will handle 1000 watt load.
1000 CONTROL 2N6397 1N4004 2N6397 3638
slaving circuit shown Figure 2.25 provides single power pulse gate each time turns thus turning half cycle following during which therefore turned only when turned load controlled signal connected gate shown schematic. control signal either power pulse. control signal synchronized with power line, this circuit will make excellent zero-point switch. During time that capacitor charged through While
INPUT SIGNAL
*1000 WATT LOAD. TEXT.
Figure 2.25. Slave Circuit
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SECTION THYRISTOR DRIVERS TRIGGERING
Edited Updated
BASE WIDTH DIFFUSION LENGTH COMMON BASE CURRENT GAIN
Triggering thyristor requires meeting gate energy specifications there many ways doing this. general, gate should driven hard fast ensure complete gate turn thus minimize di/dt effects. Usually this means gate current least three times gate turn current with pulse rise less than microsecond pulse width greater than microseconds. gate also driven source long average gate power limits met. Some methods driving gate include: Direct drive from logic families transistors Opto triac drivers Programmable unijunction transistors (PUTs) SIDACs this chapter will discuss these, well some important design application considerations triggering thyristors general. chapter applications, will also discuss some additional considerations relating drivers triggers specific applications. PULSE TRIGGERING SCRs
GATE TURN-ON MECHANISM
10-3
10-2
10-1
(mA/mm2)
EMITTER CURRENT DENSITY
Figure 3.1. Typical Variation Transistor with Emitter Current Density
turn-on PNPN devices been discussed many papers where been shown that condition current amplification factors "transistors.'' However, case connected reverse gate bias, device have still stay blocking state. condition turn-on actually current amplification factor, increases with emitter current; some typical curves shown Figure 3.1. monotonical increase with device blocking state makes regeneration current (i.e., turn-on) possible. switching given (i.e., where
Using transistor analysis, anode current, expressed function gate current,
ICS1 ICS2
Definitions derivations given Appendix Note that anode current, will increase infinity This analysis based upon assumption that majority carrier current flows gate circuit. When such assumption made, condition turn-on given
which corresponds (see Appendix
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ANODE
CATHODE
CURRENT PULSE TRIGGERING Current pulse triggering defined supplying current through gate compensate carriers lost recombination order provide enough current sustain increasing regeneration. gate triggered with current pulse, shorter pulse widths require higher currents shown Figure 3.3(a). Figure 3.3(a) seems indicate there constant amount charge required trigger device when above threshold level. When charge required turn-on plotted versus pulse current pulse width, there optimum range current levels pulse widths which charge minimum, shown region Figure 3.3(b) (c). Region shows that lower current levels (i.e., longer minimum pulse widths) more charge required trigger device. Region shows increasing charge required current gets higher pulse width smaller.
GATE
Figure 3.2. Schematic Structure SCR, Positive Currents Defined Shown Arrows
Current regeneration starts when charge current introduced through gate (Figure 3.2). Electrons injected from cathode across they travel across "base'' region swept collector junction, thrown into base. increase majority carrier electrons region decreases potential region that holes from injected across junction into "base'' region swept across thrown into "base'' region. increase potential region causes more electrons injected into thereby repeating cycle. Since increases with emitter current, increase regeneration takes place until Meanwhile, more carriers collected than emitted from either emitters. continuity charge flow violated there electron build-up side hole build-up side. When inert impurity charges compensated injected majority carriers, junction becomes forward biased. collector emits holes back electrons until steady state continuity charge established. During regeneration process, time takes minority carrier travel across base region transit time, which given approximately
where base width diffusion length
25°C MINIMUM GATE TRIGGER CURRENT (mA)
HIGH UNIT
UNIT
THRESHOLD 0.05
(The subscript "i'' either indicate appropriate base.) time taken from start gate trigger turn-on device will equal some multiple transit time.
PULSE WIDTH (ms)
Figure 3.3(a). Typical Variation Minimum Gate Current Required Trigger
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25°C
25°C HIGH UNIT UNIT
MINIMUM TRIGGER CHARGE (nc) THRESHOLD UNIT
MINIMUM TRIGGER CHARGE (nc)
HIGH UNIT
THRESHOLD
0.05
GATE CURRENT (mA)
MINIMUM PULSE WIDTH (ms)
Figure 3.3(b). Variation Charge versus Gate Current
Figure 3.3(c). Variation Charge versus Minimum Pulse Width
charge characteristic curves explained qualitatively variation current amplification with respect emitter current. typical variation thyristor shown Figure 3.4(a). From Figure 3.4(a), deduced that total current amplification factor, characteristic curve shown Figure 3.4(b). (The data does correspond data Figure they taken different types devices.) gate current levels region Figure correspond emitter anode) currents which slope curve steepest (Figure 3.4(b)). region rate that builds with respect changes high, little charge lost recombination, therefore, minimum charge required turn-on. region Figure 3.3, lower gate current corresponds small which slope well itself, small. takes large change order build this region, turn-on device should large enough flood gate cathode junction nearly instantaneously with
charge supplied through gate lost recombination. charge required turn-on increases markedly gate current decreased threshold level. Below this threshold, device will turn regardless long pulse width becomes. this point, slope equal zero; charge supplied lost completely recombination drained through gate-cathode shunt resistance. qualitative analysis variation charge with pulse width region discussed Appendix region gate current level gets higher pulse width smaller, there effects that contribute increasing charge requirement trigger-on device: decreasing slope and, transit time effect. mentioned previously, takes some multiple transit time turn-on. gate pulse width decreases (tN1 tP2) less, (where positive real number, transit time base transit time base amount current required charge which corresponds high enough give
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N-P-N SECTION
CURRENT AMPLIFICATION FACTOR CURRENT AMPLIFICATION FACTOR
P-N-P SECTION
EMITTER CURRENT (mA)
EMITTER CURRENT (mA)
Figure 3.4(a). Variation with Emitter Current Sections Typical Silicon Controlled Rectifiers
Figure 3.4(b). Typical Variation versus Emitter Current
CAPACITANCE CHARGE TRIGGERING Using gate trigger circuit shown Figure 3.5, charge required turn-on increases with value
capacitance used shown Figure 3.7. reasons account increasing charge characteristics: effect threshold current. effect variation gate spreading resistance.
S)C1
COMMUTATING CIRCUIT
(rG1 RS)C1 SHADED AREA |(rG1 RS)(C1)|(Ithr) SHADED AREA |(rG2 RS)(C2)|(Ithr) |(rG1 RS)(C1)|(Ithr) |(rG2 RS)(C2) |(Ithr)
Figure 3.5. Gate Circuit Capacitance Charge Triggering
Figure 3.6. Gate Current Waveform Capacitance Charge Triggering
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PULSE WIDTH,
Ithr
DV1C DV2C
Consider gate current waveform Figure 3.6; triggering pulse width made large enough such that uutfl; threshold trigger current shown Ithr. charge supplied transient current level less than Ithr lost recombination, shown shaded regions. gate spreading resistance (rG) gate junction varies inversely with peak current; higher peak current, smaller gate spreading resistance. Variation gate spreading resistance measured method Time Domain Reflectometry plotted Figure 3.8. From data Figure 3.7, clear that larger values capacitance lower voltage level required turn-on. peak current spike Figure given smaller smaller Ipk. Smaller turn yields large that dependent value capacitance used capacitance charge triggering. This reasoning confirmed measuring fall time gate trigger voltage calculating transient gate spreading resistance, from: Figure 3.9. expected, increases with increasing values capacitance used. Referring back Figure 3.6, same amount charge larger rG)C time constant current spike, more charge under threshold level lost recombination. Increasing value will increase time constant more rapidly than were invariant. Therefore, increasing value should increase charge lost shown Figure 3.7. Note that order magnitude increase capacitance increased charge less than 3:1.
NORMALIZED GATE SPREADING RESISTANCE
HIGH UNIT 25°C
UNIT
1000
GATE CURRENT (mA)
Figure 3.8. Variation Gate Spreading Resistance versus Gate Peak Current
Results
plotted
EFFECT TEMPERATURE higher temperature, less charge required turn device, shown Figure 3.10. range temperatures where operated life time minority carriers increases with temperature; therefore less charge into gate lost recombination. analyzed Appendix there three components charge involved gate triggering: charge lost recombination, Qdr, charge drained through built-in gate-cathode shunt resistance, Qtr, charge triggering. them temperature dependent. Since temperature coefficient voltage across junction small, considered invariant temperature. temperature range operation, temperature give rise significant impurity gettering, lifetime increases with temperature causing decrease with increasing temperature. Also, decreases with increasing temperature because constant current device blocking state increases with temperature;7 other words, attain elevated temperature, less anode current, hence gate current [see equation Appendix needed; therefore, decreases. input charge, being equal Qtr, Qdr, decreases with increasing temperature. minimum current trigger charge decreases roughly exponentially with temperature. Actual data taken MCR729 deviate somewhat from exponential trend (Figure 3.10). higher temperatures, rate decrease less; also different pulse widths rates decrease different; large pulse widths recombination charge becomes more significant than that small pulse widths. result, expected Figure 3.10 shows that decreases more rapidly with temperature high pulse widths. These effects analyzed
MINIMUM TRIGGER CHARGE, Q(nc) -15°C HIGH UNIT
UNIT
PULSE WIDTH 1000
2000
5000 10,000
CAPACITANCE (pF)
Figure 3.7. Variation Trigger Charge versus Capacitance Used
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Appendix [equation (7), page 235]. theory experiment agree reasonably well.
EFFECT BLOCKING VOLTAGE avalanche mode device; turn-on device multiplication carriers middle collector junction. multiplication factor given empirical equation
25°C GATE SPREADING RESISTANCE
where
Multiplication factor Voltage across middle "collector'' junction (voltage which device blocking prior turn-on)
2.2C
Breakdown voltage middle "collector'' junction Some positive number Note increased, also increases turn increases (the current amplification factor where Emitter efficiency, Base transport factor, Factor recombination).
1000
2000
CAPACITANCE (pF)
Figure 3.9. Variation Transient Base Spreading Resistance versus Capacitance
larger larger would expected minimum gate trigger charge decrease with increasing Experimental results show this effect (see Figure 3.11). MCR729, gate trigger charge only slightly affected voltage which device blocking prior turn-on; this reflects that exponent, equation small. EFFECT GATE CIRCUIT mentioned earlier, turn device, total amplification factor must greater than unity. This means that some current being drained gate which bleeds regeneration current, turn-on will affected. higher gate impedance, less gate trigger charge. Since regenerative current prior turn-on small, gate impedance only slightly affects required minimum trigger charge; case over-driving gate achieve fast switching time, gate circuit impedance will have noticeable effect. EFFECT INDUCTIVE LOAD presence inductive load tends slow down change anode current with time, thereby causing required charge triggering increase with value inductance. long pulse width current triggering, inductive load little effect, effect increases markedly short pulse widths, shown Figure 3.12. increase charge occurs because short pulse widths, trigger signal decreased negligible value before anode current reached level sufficient sustain turn-on.
GATE CURRENT PULSE WIDTH MINIMUM TRIGGER CHARGE (nc)
+105
TEMPERATURE (°C)
Figure 3.10. Variation versus Temperature
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MINIMUM TRIGGER CHARGE (nc)
USING NEGATIVE BIAS SHUNTING Almost SCR's exhibit some degree turn-off gain. normal values anode current, negative gate current will have sufficient effect upon internal feedback loop device cause significant change anode current. However, does have marked effect anode current levels; advantage using modify certain device parameters. Specifically, turn-off time reduced hold current increased. Reduction turn-off time increase hold current useful such circuits inverters full-wave phase control circuits which inductance present. Negative gate current may, course, produced external bias supply. also produced taking advantage fact that during conduction gate positive with respect cathode providing external conduction path such gate-to-cathode resistor. Semiconductor SCR's, with exception sensitive gate devices, constructed with built gate-to-cathode shunt, which produces same effect negative gate current. Further change characteristics produced external shunt. Shunting does produce much change characteristics does negative bias, since negative gate current, even with external short circuit, limited lateral resistance base layer. When using external negative bias current must limited, care must taken avoid driving gate into avalanche region. effects negative gate current shown device specification sheets. curves Figure 3.13 represent measurements made number SCRs, should therefore considered spec limits. They however, show definite trends. example, SCRs showed improvement turn-off time about one-third using negative bias point where further significant improvement obtained. increase hold current external shunt resistor ranged typically between percent, whereas with negative bias, range improvement typically between 2-1/2 times open gate value. Note that holding current curves normalized referred open gate value.
25°C 0.05 CAP. DISCHARGE 1000
VAK, ANODE VOLTAGE
Figure 3.11. Variation Current Trigger Charge versus Blocking Voltage Prior Turn-On
MINIMUM TRIGGER CHARGE (nc)
25°C 1000
MINIMUM PULSE WIDTH (ns)
Figure 3.12. Effect Inductance Load Triggering Charge
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SPREAD DEVICES NORMALIZED HOLDING CURRENT
REDUCING di/dt EFFECT FAILURES Figure 3.14 shows typical structural cross section (not scale). Note that collector transistor base transistor same layer. This also true collector transistor base transistor Although optimum performance base thicknesses great compared normal transistor, nevertheless, base thickness still small compared lateral dimensions. When applying positive bias gate, transverse base resistance, spreading resistance will cause lateral voltage drop which will tend forward bias those parts transistor emitter-junction closest base contact (gate) more heavily, sooner than portions more remote from contact area. Regenerative action, consequently will start area near gate contact, will turn first this area. Once conduction will propagate across entire junction.
LAYER CATHODE
1000 5000
GATE-TO-CATHODE RESISTANCE (OHMS)
Figure 3.13(a). Normalized Holding Current versus Gate-to-Cathode Resistance
SPREAD DEVICES NORMALIZED HOLDING CURRENT
GATE
-2.0
-4.0
-6.0
-8.0
Figure 3.14. Construction Typical
GATE-TO-CATHODE VOLTAGE (VOLTS)
Figure 3.13(b). Normalized Holding Current versus Gate-to-Cathode Voltage
AVERAGE DEVICES TURN-OFF TIME
-5.0 GATE-TO-CATHODE VOLTAGE (VOLTS)
Figure 3.13(c). Turn-Off Time versus Bias
phenomenon di/dt failure related turn-on mechanism. look some external factors involved they contribute. Curve 3.15(a) shows fall anode-to-cathode voltage with time. This fall follows delay time after application gate bias. delay time fall time together called turn-on time, and, depending upon device, will take anywhere from tens nanoseconds microseconds. propagation conduction across entire junction requires considerably longer time. time required propagation equalization conduction represented approximately time required anode-to-cathode voltage fall from percent point steady state value particular value anode current under consideration (neglecting change temperature effects). during interval time between start fall anode-to-cathode voltage final equalization conduction that most susceptible damage from excessive current.
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ANODE
superimpose current curve anode-to- cathode voltage versus time curve better understand this. allow current rise rapidly high value find multiplying current voltage that instantaneous dissipation curve reaches peak which hundreds times steady state dissipation level same value current. same time important remember that dissipation does take place entire junction, confined this time small volume. Since temperature related energy unit volume, since energy into device high current levels very large while volume which concentrated very small, very high spot temperatures achieved. Under such conditions, difficult attain temperatures which sufficient cause localized melting device. Even peak energy levels high enough destructive single-shot basis, must realized that since power dissipation confined small area, power handling capabilities device lessened. pulse service where significant percentage power pulse dissipated during fall-time interval, acceptable extrapolate steady state power dissipation capability duty cycle basis obtain allowable peak pulse power.
ANODE CATHODE VOLTAGE PERCENT MAXIMUM INSTANTANEOUS POWER DISSIPATION ANODE CURRENT
tion useful, however, determining limitations device before entire junction conduction, because they based measurements made with entire junction conduction. present, there known technique making reasonably accurate measurement junction temperature time domain interest. Even were devise method switching sufficiently large current short enough time, would still faced with problem charge storage effects device under test masking thermal effects. Because these other problems, becomes necessary determine device limitations during turn-on interval destructive testing. resultant information published form such maximum allowable current versus time, simply maximum allowable rate rise anode current (di/dt). Understanding di/dt failure mechanism part problem. user, however, possible cure infinitely more important. There three approaches that should considered. Because lateral base resistance portion gate closest gate contact first turned because first forward biased. minimum gate bias cause turn-on device used, spot which conduction initiated will smallest size. increasing magnitude gate trigger pulse several times minimum required, applying with very fast rise time, considerably increase size spot which conduction starts. Figure 3.16(a) illustrates effect gate drive voltage fall time Figure 3.16(b) shows improvement instantaneous dissipation. conclude from this that overdriving gate will improve di/dt capabilities device, reduce stress device doing
ANODE CATHODE VOLTAGE (VOLTS) PEAK ANODE CURRENT
TIME (ms)
Figure 3.15. Typical Conditions Fast-Rise, High Current Pulse
final criterion limit operation junction temperature. reliable operation instantaneous junction temperature must always kept below maximum junction temperature stated manufacturer's data sheet. Some data sheets present include information determine thermal response junction current pulses. This informa-
TIME (ms)
Figure 3.16(a). Effect Gate Drive Fall Time
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very straightforward approach simply slow down rate rise anode current insure that stays within device ratings. This done simply adding some series inductance circuit.
SNUB THYRISTORS Inductive loads (motors, solenoids, etc.) present problem power triac because current phase with voltage. important fact remember that since triac conduct current both directions, only brief interval during which sine wave current passing through zero recover revert blocking state. inductive loads, phase shift between voltage current means that time current power handling triac falls below holding current triac ceases conduct, there exists certain voltage which must appear across triac. this voltage appears rapidly, triac will resume conduction control lost. order achieve control with certain inductive loads, rate rise voltage (dv/dt) must limited series network placed parallel with power triac shown Figure 3.18. capacitor will limit dv/dt across triac. resistor necessary limit surge current from when triac conducts damp ringing capacitance with load inductance Such network commonly referred "snubber.'' Figure 3.19 shows current voltage waveforms power triac. Commutating dv/dt resistive load typically only 0.13 line source 0.063 line source. inductive loads "turn-off'' time commutating dv/dt stress more difficult define affected number variables such back motors ratio inductance resistance (power factor). Although appear from inductive load that rate rise extremely fast, closer circuit evaluation reveals that commutating dv/dt generated restricted some finite value which function load reactance device capacitance still exceed triac's critical commutating dv/dt rating which about V/s. generally good practice snubber network across triac limit rate rise (dv/dt) value below maximum allowable rating. This snubber network only limits voltage rise during commutation also suppresses transient voltages that occur result line disturbances. There easy methods selecting values snubber network. circuit Figure 3.18 damped, tuned circuit comprised minor extent junction capacitance triac. When triac ceases conduct (this occurs every half cycle line voltage when current falls below holding current), triac receives step impulse line voltage which depends power factor load. given load fixes however, circuit designer vary Commutating dV/dt lowered increasing while increased decrease resonant "over ringing'' tuned circuit.
INSTANTANEOUS POWER DISSIPATION (kW)
PEAK ANODE CURRENT
TIME (ms)
Figure 3.16(b). Effect Gate Drive Turn-On Dissipation
application should require rate current rise beyond rated di/dt limit device, then another approach taken. device turned relatively current level sufficient time large part junction into conduction; then current level allowed rise much more rapidly very high levels. This might accomplished using delay reactor shown Figure 3.17. Such reactor would wound square loop core that would have sharp saturation characteristic allow rapid current rise. also possible make separate saturation winding. Under these conditions, delay long enough entire junction into conduction, power handling capabilities device extrapolated duty cycle basis.
DELAY REACTOR
Figure 3.17. Typical Circuit Delay Reactor
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ZERO CROSSING CIRCUIT
LOAD
BASIC CIRCUIT ANALYSIS Figure 3.20 shows equivalent circuit used analysis, which triac been replaced ideal switch. When triac blocking non-conducting state, represented open switch, circuit standard series network driven voltage source. following differential equation obtained summing voltage drops around circuit;
i(t) di(t) c(t) Msin(wt
Figure 3.18. Triac Driving Circuit with Snubber
IF(ON)
IF(OFF) LINE VOLTAGE
CURRENT COMMUTATING dv/dt VOLTAGE ACROSS POWER TRIAC
TIME
RESISTIVE LOAD
IF(ON)
IF(OFF) LINE VOLTAGE
which i(t) instantaneous current after switch opens, qc(t) instantaneous charge capacitor, peak line voltage, phase angle which voltage leads current prior opening switch. After differentiation rearrangement, equation becomes standard second-order differential equation with constant coefficients. With imposition boundary conditions that i(o) qc(o) with selected values equation solved, generally computer. Having determined magnitude time occurrence peak voltage across thyristor, then possible calculate values times voltages peak value. This necessary order compute dv/dt stress defined following equation:
CURRENT THROUGH POWER TRIAC VOLTAGE ACROSS POWER TRIAC
COMMUTATING dv/dt TIME INDUCTIVE LOAD
Figure 3.19. Current Voltage Waveforms During Commutation
where voltage time point voltage time point. Solution differential equation assumed load conditions will give circuit designer starting point selecting Because design snubber contingent load, almost impossible simulate test every possible combination under actual operating conditions. advisable measure peak amplitude rate rise voltage across triac oscilloscope, then make final selection experimentally. Additional comments about circuit values SCRs Triacs made Chapter
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LOAD POWER SOURCE
Figure 3.20. Equivalent Circuit used Analysis
USING SENSITIVE GATE SCRs applications sensitive gate SCRs such Semiconductor 2N6237, gate-cathode resistor, (Figure 3.21) important factor. value affects, varying degrees, such parameters IGT, VDRM, dv/dt, leakage current, noise immunity.
ANODE
Figure 3.22(a) shows construction sensitive gate path taken leakage current flowing through RGK. Large SCRs (Figure 3.22(b)) keep path length small bringing gate layer contact cathode metal. This allows current siphon all-round cathode area. When chip dimensions small there little penalty placing resistor outside package. This gives circuit designer considerable freedom tailoring electrical properties SCR. This great advantage when trigger holding current needed. Still, there trade-offs maximum allowable junction temperature dV/dt immunity that with larger resistor values. Verifying that design adequate prevent circuit upset heat noise important. rated value usually Ohm. Lower values improve blocking turn-off capability.
DIFFUSED CATHODE METAL DIFFUSED BASE DIFFUSED EMITTER SHORTS
GATE CATHODE
Figure 3.21. Gate-Cathode Resistor,
Figure 3.22. Sensitive Gate Construction
CONSTRUCTION initial step making creation, diffusion, P-type layers N-type silicon base material. Prior advent all-diffused SCR, next step form gate-cathode junction alloying gold-antimony foil. This produced silicon junction regrown type over most junction area. However, resistive rather than semiconductor junction would form where molten alloy terminated surface. This formed internal RGK, looking gate-cathode terminals, that reduced "sensitivity'' SCR. Modern practice produce gate-cathode junction masking diffusing, much more controllable process. produces very clean junction over entire junction area with unwanted resistive paths. Good dv/dt performance larger SCRs, however, requires resistive paths distributed over junction area. These diffused emitter shorts naturally desensitize device. Smaller SCRs rely external because lateral resistance gate layer small enough prevent leakage dV/dt induced currents from forward biasing cathode triggering SCR.
sensitive gate SCR, therefore, all-diffused design with emitter shorts. very high impedance path parallel with gate-cathode diode; better process higher this impedance, until very good device cannot block voltage forward direction without external RGK. This because thermally generated leakage currents flowing from anode into gate junction sufficient turn SCR. value usually kilohm presence value affects many other parameters. FORWARD BLOCKING VOLTAGE CURRENT, VDRM IDRM 2N6237 family specified have IDRM, anode-to-cathode leakage current, less than maximum operating junction temperature rated VDRM. This leakage current increases omitted and, fact, device well able regenerate turn Tests were several 2N6239 devices establish dependency leakage current determine relationship with junction temperature, forward voltage (Figure 3.23a).
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CASE CASE (a). SIMPLE CONSTRUCTION (b). SHORTED EMITTER CONSTRUCTION
Figure 3.23(a) plot VAK, forward voltage, versus taken maximum rated operating junction temperature 110°C. With each device leakage current, IAK, then reduced varied re-establish same leakage current. plot shows that leakage current strongly voltage dependent conversely, increased derate. While leakage current voltage dependent, very temperature dependent. plot Figure 3.23(b) junction temperature, versus taken VDRM, maximum forward blocking voltage shows this dependence. each device (2N6329 again) leakage current, IAK, measured maximum operating junction temperature 110°C, then junction temperature reduced varied re-establish that same leakage current. plot shows that leakage current strongly dependent junction temperature. Conversely increased derated temperature. conservative rule thumb that leakage doubles every 10°C. current flows through RGK, triggering will occur until voltage across reaches VGT. This implies allowed doubling resistor every reduction maximum junction temperature. However, this rule should applied with caution. Static dV/dt require smaller resistor than expected. Also leakage current does always follow rule below 70°C because surface effects. summarize, leakage current sensitive gate much more temperature sensitive than voltage sensitive. Operation lower junction temperatures allows increase gate-cathode resistor which makes SCR-resistor combination more "sensitive.''
(VOLTS) 2N6239 110°C CONSTANT
2N6239 VDRM CONSTANT
(OHMS)
Figure 3.23(b). versus (Typical) Constant Leakage Current
dv/dt
Figure 3.23(c). dv/dt Firing
dv/dt, RATE RISE ANODE VOLTAGE (V/m
1,000V/
MCR706-6 110°C PEAK EXPONENTIAL METHOD
100V/
10V/
1,000
10,000
100,000
(OHMS)
Figure 3.23(a). versus (Typical) Constant Leakage Current
Figure 3.23(d). Static dv/dt function Gate-Cathode Resistance devices with different sensitivity.
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RATE-OF-RISE ANODE VOLTAGE, dv/dt SCR's junctions exhibit capacitance separation charge when device blocking state. subjected forward dv/dt, this capacitance couple sufficient current into SCR's gate turn shown Figure 3.23(c). acts diversionary path dv/dt current. larger SCRs, where lateral gate resistance device limits influence RGK, this path provided resistive emitter shorts mentioned previously.) gate-cathode resistor, then, might expected have some effect dv/dt performance SCR. Figure 3.23(d) confirms this behavior. static dV/dt MCR706 devices varies over several powers with changes gate-cathode resistance. Selection external resistor allows designer trade dynamic performance with amount drive current provided resistor-SCR combination. sensitive-gate device with provides performance approaching that equivalent non-sensitive SCR. This strong dependence does exist with conventional shorted emitter SCRs because their internal resistor. conventional cannot made more sensitive, sensitive-gate device attributes reliably with resistor desired point along sensitivity range. values resistance make dV/dt performance more uniform predictable. curves devices with different sensitivity diverge high values resistance because device response becomes more dependent sensitivity. resistor most important factor determining static dV/dt capability product. Reverse biasing gate also improves dV/dt. 2N6241 improved factor with volt bias. GATE CURRENT, total gate current that gating circuit must supply current that device itself requires fire current flowing circuit ground through RGK, shown Figure 3.24. IGT, current required device that fire, usually specified device manufacturer maximum some temperature (for 2N6236 series maximum -40°C). current flowing through defined resistor value gate-to-cathode voltage that needs fire. This maximum -40°C 2N6237 series, example.
ITOT
GATE CURRENT, IGT(min) manufacturers sometimes requests sensitive-gate specified with IGT(min), that maximum gate current that will fire device. This requirement conflicts with basic function sensitive gate SCR, which fire zero very gate current, IGT(max). Production devices with measurable IGT(min) best difficult deliveries sporadic! reason IGT(min) requirement might some measurable off-state gating circuit leakage current, perhaps collector leakage driving transistor. Such current readily bypassed suitably chosen RGK. temperature question estimated from Figure 3.25, Ohm's calculation made, resistor installed define this "won't fire'' current. This repeatable design well control equipment designer.
GATE TRIGGER VOLTAGE, gate-cathode junction silicon junction. gate trigger voltage follows diode roughly same temperature coefficient silicon diode, -2mV/C. Figure 3.25 plot versus temperature typical sensitive gate SCRs. They prone triggering noise coupled through gate circuit because their trigger voltage. smallest noise voltage margin occurs maximum temperature with most sensitive devices.
GATE TRIGGER VOLTAGE (VOLTS) UNIT 300°K HIGH UNIT 300°K
JUNCTION TEMPERATURE (°C)
Figure 3.25. Typical Figure 3.24. "Gate'' Currents
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HOLDING CURRENT, holding current minimum anode current required maintain device state. usually specified maximum series devices (for instance, maximum 25°C 2N6237 series). particular device will turn somewhere between this maximum zero anode current there perhaps 20-to-1 spread each devices. Figure 3.26 shows holding current increasing with decreasing resistor siphons more more regeneratively produced gate current when device latched condition. Note that gate-cathode resistor determines holding current when less than Ohms. sensitivity determining factor when resistor exceeds Ohm. This allows designer holding current over wide range possible values using resistor. Values typical those conventional non-sensitive devices occur when external resistor similar their internal gate-cathode shorting resistance. holding current uniformity also improves when resistor small.
25°C HOLDING CURRENT,
1.62
0.01
1,000
1,000 resistor, between noise current necessary generate enough voltage fire device. Adding capacitor sized between 0.01 creates noise filter improves dV/dt shunting dV/dt displacement current through gate terminal. These components must placed close possible gate cathode terminals prevent lead inductance from making them ineffective. capacitor also requires gate drive circuit supply enough current fire without excessive time delay. This particularly important applications with rapidly rising (di/dtu50 A/s) anode current where fast rise high amplitude gate pulse helps prevent di/dt damage SCR. Reverse gate voltage cause unwanted turn-off SCR. Then works like gate turn-off thyristor. Turn-off gate signal more probable with small SCRs because short distance between cathode gate regions. Whether turn-off occurs depends many variables. Even turn-off does occur, effect high reverse gate current move conduction away from gate, reducing effective cathode area surge capability. Suppressing reverse gate voltage particularly important when gate pulse duration less than microsecond. Then part triggers charge instead current halving gate pulse width requires double gate current. Capacitance coupled gate drive circuits differentiate gate pulse (Figure 3.27) leading reverse gate spike. reverse gate voltage rating should exceeded prevent avalanche damage. This discussion shown that RGK, gate-cathode resistor, many implications. Clear understanding need influence performance sensitive gate will enable designer have better control circuit designs using this versatile part.
RGK, GATE-CATHODE RESISTANCE,
Figure 3.26. 2N5064 Holding Current
NOISE IMMUNITY Changes electromagnetic electrostatic fields coupled into wires printed circuit lines trigger these sensitive devices, logic circuit glitches. result more serious than with transistor since will latch Careful wire harness design (twisted pairs adequate separation from high-power wiring) printed circuit layout (gate return runs adjacent another) minimize potential problems. gate cathode network consisting resistor parallel capacitor also helps. resistor provides static short helpful with noise signals frequency. example, with
OPTIONAL REVERSE GATE SUPPRESSOR DIODE
Figure 3.27. Capacitance Coupled Gate Drive
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DRIVERS: PROGRAMMABLE UNIJUNCTION TRANSISTORS programmable unijunction transistor (PUT) four layer device similar SCR. However, gating with respect anode instead cathode. external resistive voltage divider accurately sets triggering voltage allows adjustment. finds limited application phase control element most often used long duration battery drain timer circuits where high sensitivity permits large timing resistors small capacitors. Like SCR, conductivity modulated device capable providing high current output pulses. OPERATION three terminals, anode (A), gate (G), cathode (K). symbol transistor equivalent circuit shown Figure 3.28. seen from equivalent circuit, device actually anode-gated SCR. This means that gate made negative with respect anode, device will switch from blocking state state.
ANODE GATE
voltages reversed. Negative resistance terminology describes device characteristics because traditional application circuit. external reference voltage must maintained gate terminal. typical relaxation type oscillator circuit shown Figure 3.29(a). voltage divider shown typical obtaining gate reference. this circuit, characteristic curve looking into anode-cathode terminals would appear shown Figure 3.29(b). peak valley points stable operating points either negative resistance region. peak point voltage (VP) essentially same external gate reference, only difference being gate diode drop. Since reference circuit device dependent, varied, this way, programmable. characterizing PUT, convenient speak Thevenin equivalent circuit external gate voltage (VS) equivalent gate resistance (RG). parameters defined terms divider resistors supply voltage follows:
Most device parameters sensitive changes example, decreasing will cause peak valley currents increase. This easy since actually shunts device will cause sensitivity decrease. CHARACTERISTICS Table list typical characteristics Semiconductor's 2N6027/2N6028 programmable unijunction transistors. test circuits test conditions shown essentially same data sheet characteristics. data presented here defines static curve shown Figure 3.29(b) gate reference (VS) with various gate resistances (RG). also indicates leakage currents these devices describes output pulse. Values given 25°C unless otherwise noted.
CATHODE
Figure 3.28(a). Symbol
Figure 3.28(b). Transistor Equivalent
complementary when anode connected like SCR's cathode circuit bias
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PEAK POINT NEGATIVE RESISTANCE REGION VALLEY POINT
OUTPUT
IGAO
Figure 3.29(a). Typical Oscillator Circuit
Figure 3.29(b). Static Characteristics
Table 3.1. Typical Characteristics
Symbol IGAO IGKS Curve Tracer Used 3.33 3.34 Test Circuit Figure 3.30 3.30 Test Conditions (See Figure 3.31) (See Figure 3.32) 2N6027 1.25 2N6028 0.08 0.70 Unit
PEAK POINT CURRENT, (IP) peak point indicated graphically static curve. Reverse anode current flows with anode voltages less than gate voltage (VS) because leakage from bias network charging network. With currents less than device blocking state. With currents above device goes through negative resistance region state. charging current, current through timing resistor, must greater than insure that device will switch from blocking state oscillator circuit. this reason, maximum values given data sheet. These values dependent temperature, Typical curves data sheet indicate this dependence must consulted most applications. test circuit Figure 3.30 sawtooth oscillator which uses 0.01 timing capacitor, supply, adjustable charging current, equal biasing resistors (R). biasing resistors were chosen given equivalent peak point
current measured with device just prior oscillation detected absence output voltage pulse. 2N5270 held effect transistor circuit used current source. variable gate voltage supply used control this current. VALLEY POINT CURRENT, (IV) valley point indicated graphically Figure 3.28. With currents slightly less than device unstable negative resistance state. voltage minimum occurs with higher currents, device stable state. When device used oscillator, charging current current through timing resistor must less than valley point voltage (VV). this reason, minimum values given data sheet With reasonable "low'' devices. When device used latching mode, anode current must greater than Maximum values given with devices have reasonable "high'' with
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PEAK POINT VOLTAGE, (VP) unique feature that peak point voltage determined externally. This programmable feature gives this device ability function voltage controlled oscillators similar applications. triggering peak point voltage approximated
across PUT. Tektronix, Type plug-in used determine this parameter. FORWARD ANODE-GATE VOLTAGE, (VAG) forward anode-to-gate voltage drop affects peak point voltage previously discussed. drop essentially same small signal silicon diode plotted Figure 3.31. voltage decreases current decreases, change voltage with temperature greater currents. temperature coefficient about -2.4 V/°C drops about -1.6 mV/°C This information useful applications where desirable temperature compensate effect this diode. GATE-CATHODE LEAKAGE CURRENT, (IGKS) gate-to-cathode leakage current current that flows from gate cathode with anode shorted cathode. actually open circuit gate-anode gate-cathode leakage currents. shorted leakage represents current that shunted away from voltage divider.
where unloaded divider voltage offset voltage. actual offset voltage will always higher than anode-gate voltage VAG, because flows gate just prior triggering. This makes change will affect both opposite ways. First, increases, decreases causes decrease. Second, since does decrease fast increases, product will increase actual will increase. These second order effects difficult predict measure. Allowing first order approximation gives sufficiently accurate results most applications. peak point voltage tested using circuit Figure 3.30 scope with input impedance
UNDER TEST 2N5270
NOTES: VARIOUS SENSE RESISTORS (RS) USED KEEP SENSE VOLTAGE NEAR Vdc. GATE SUPPLY (VG) ADJUSTED FROM ABOUT -0.5 0.01 OUTPUT PULSE
Figure 3.30. Test Circuit
GATE-ANODE LEAKAGE CURRENT, (IGAO) gate-to-anode leakage current current that flows from gate anode with cathode open. important long duration timers since adds charging current flowing into timing capacitor. typical leakage currents measured shown Figure 3.32. Leakage 25°C approximately current appears double about every 10°C rise temperature.
FORWARD VOLTAGE, (VF) forward voltage (VF) voltage drop between anode cathode when device biased offset voltage drop across some internal dynamic impedance which both tend reduce output pulse. typical data sheet curve shows this impedance less than forward current.
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PEAK OUTPUT VOLTAGE, (VO) peak output voltage only function dynamic impedance, also affected switching speed. This particularly true when small capacitors (less than 0.01 used timing since they lose part their charge during turn interval. relatively large capacitor (0.2 test circuit Figure 3.33 tends minimize this last effect. output voltage measured placing scope across resistor which series with cathode lead. RISE TIME, (tr) Rise time useful parameter pulse circuits that capacitive coupling. used predict amount current that will flow between these circuits. Rise time specified using fast scope measuring between leading edge output pulse. MINIMUM MAXIMUM FREQUENCY actual tests with devices whose parameters known, possible establish minimum maximum values timing resistors that will guarantee oscillation. circuit under discussion conventional relaxation type oscillator. obtain maximum frequency, desirable values capacitance (1000 select devices bias conditions obtain high possible stray capacitance results generall
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