HYB3117800BSJ-50/-60/-70 words 8-bit organization operating tempe

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HYB3117800BSJ-50/-60/-70 words 8-bit organization operating tempe

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8-Bit Dynamic
HYB3117800BSJ-50/-60/-70
words 8-bit organization operating temperature Performance: tRAC tCAC access time access time Access time from address Read/Write cycle time Fast page mode cycle time
Single 0.3V) supply power dissipation max. active (-50 version) max. active (-60 version) max. active (-70 version) standby (LV-TTL) standby (CMOS) Output unlatched cycle allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh test mode Fast page mode capability inputs, outputs clocks fully LVTTL-compatible 2048 refresh cycles Plastic Package: P-SOJ-28-3
Semiconductor Group
1.96
3117800BSJ-50/-60/-70 8-DRAM
3117800BSJ MBit dynamic organized 2097152 words 8-bits. 3117800BSJ utilizes submicron CMOS silicon gate process technology, well advanced circuit techniques provide wide operating margins, both internally system user. Multiplexed address inputs permit 3117800BSJ packaged standard plastic package. These packages provide high system densities compatible with commonly used automatic testing insertion equipment. System-oriented features include single 0.3V) power supply, direct interfacing with high-performance logic device families. Ordering Information Type 3117800BSJ-50 3117800BSJ-60 3117800BSJ-70 Names I/O1-I/O8 Address Inputs Column Address Inputs Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply Ground connected Ordering Code Q67100-Q1147 Q67100-Q1148 Package P-SOJ-28-3 P-SOJ-28-3 P-SOJ-28-3 Descriptions
3.3V DRAM (access time 3.3V DRAM (access time 3.3V DRAM (access time
N.C.
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
P-SOJ-28-3 (400mil)
I/O1 I/O2 I/O3 I/O4 N.C.
I/O8 I/O7 I/O6 I/O5
Configuration
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
I/O1 I/O2
I/O8
Data Buffer
Clock Generator
Data Buffer
Column Address Buffer(10)
Column Decoder
Refresh Controller
Sense Amplifier Gating
Refresh Counter (11)
1024
Address Buffers(11)
Decoder 2048
Memory Array 2048x1024x8
Clock
Generator
Block Diagram
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Absolute Maximum Ratings Operating temperature range Storage temperature range.- Input/output voltage .-0.5 (Vcc+0.5, 4.6) Power supply voltage.-1.0V Power dissipation. Data current (short circuit) Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics 0.3V, Parameter Input high voltage Input voltage LVTTL Output high voltage (IOUT LVTTL Output voltage (IOUT CMOS Output high voltage (IOUT -100 CMOS Output voltage (IOUT Input leakage current,any input 0.3V, other pins Output leakage current disabled, VOUT 0.3V) Average supply current: version version version (RAS, CAS, address cycling, min.) Symbol Limit Values min. max. Vcc+0.5 Vcc-0.2 Unit Test Condition
II(L) IO(L) ICC1
Standby supply current (RAS VIH) ICC2
Average supply current, during RAS-only refresh cycles: version version version (RAS cycling: VIH, min.)
ICC3
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Characteristics (cont'd) 0.3V, Parameter Symbol Limit Values min. Average supply current, ICC4 during fast page mode: version version version (RAS VIL, CAS, address cycling,tPC min.) max. Unit Test Condition
Standby supply current (RAS
Average supply current, during CASbefore-RAS refresh mode: version version version (RAS, cycling, min.)
ICC5 ICC6
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., held low, WE=Vcc-0.2V, Address Din=Vcc-0.2V 0.2V)
ICC7
Capacitance °C,VCC 0.3V, Parameter Input capacitance A10) Input capacitance (RAS, CAS, capacitance (I/O1-I/O8) Symbol Limit Values min. max. Unit
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Characteristics 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
common parameters
Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay time hold time hold time precharge time Transition time (rise fall) Refresh period tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tREF
Read Cycle
Access time from Access time from access time Read command setup time Read command hold time Read command hold time referenced output low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF 8,10
Access time from column address Column address lead time tRAL
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Characteristics (cont'd) 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
Output buffer turn-off delay from Data delay high data delay high data delay
tOEZ tDZO tCDD tODD
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWCS
Write command lead time tRWL Write command lead time tCWL Data setup time Data hold time Data delay tDZC
Read-Modify-Write Cycle
Read-write cycle time delay time delay time command hold time tRWC tRWD tCWD tOEH
Column address delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time precharge time Access time from precharge pulse width precharge Delay tCPA tRAS tRHPC
200k
200k
200k
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Characteristics (cont'd) 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time precharge tPRWC tCPWD
CAS-before-RAS Refresh Cycle
setup time hold time precharge time Write precharge time tCSR tCHR tRPC tWRP
Write hold time referenced tWRH
CAS-before-RAS Counter Test Cycle
precharge time tCPT
Test Mode
hold time Write command setup time Write command hold time tCHRT tWTS tWTH
Self Refresh Cycle
pulse width precharge time hold time tRASS tRPS tCHS 100k 100k 100k
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Notes:
voltages referenced VSS. ICC1, ICC3, ICC4 ICC6 depend cycle rate. ICC1 ICC4 depend output loading. Specified values measured with output open. Address changed once less while VIL. case ICC4 changed once less during fast page mode cycle (tPC). initial pause required after power-up followed cycles which least cycle refresh cycle, before proper device operation achieved. case using internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. measurements assume (min.) (max.) reference levels measuring timing input signals. Transition times also measured between VIL. Measured with load equivalent Voh=2.0 (Ioh -2mA) Vol=0.8V (Iol=2mA). Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only: tRCD greater than specified tRCD (max.) limit, then access time controlled tCAC. 10)Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only: tRAD greater than specified tRAD (max.) limit, then access time controlled tAA. 11)Either tRCH tRRH must satisfied read cycle. 12)tOFF (max.) tOEZ (max.) define time which outputs achieve open-circuit condition referenced output voltage levels. 13)Either tDZC tDZO must satisfied. 14)Either tCDD tODD must satisfied. 15)tWCS, tRWD, tCWD, tAWD tCPWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min.), cycle early write cycle will remain open-circuit (high impedance) through entire cycle; tRWD tRWD (min.), tCWD tCWD (min.), tAWD tAWD (min.) tCPWD tCPWD (min.) cycle read-write cycle pins will contain data read from selected cells. neither above sets conditions satisfied, condition pins access time) indeterminate. 16)These parameters referenced leading edge early write cycles leading edge read-write cycles. 17)When using Self Refresh mode, following refresh operations must performed ensure proper DRAM operation: addresses being refreshed evenly distributed manner over refresh interval using refresh cycles, then only cycle must performed immediately after exit from Self Refresh. addresses being refreshed other manner (ROR Distributed/Burst; CBR-Burst) over refresh interval, then full refreshes must performed immediately before entry immediately after exit from Self Refresh.
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
tRAD tASR tASC tCAH
Column
tASR
Address
tRCH tRAH tRCS tRRH tOEA
tDZC tDZO tODD tCAC tCLZ
tCDD
(Inputs)
tOFF tOEZ
Valid Data
(Outputs)
tRAC
Read Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
tRAD tASR tASC
tASR
Address
tRAH
tWCS
tCWL
tWCH tRWL
(Inputs)
Valid Data
(Outputs)
Write Cycle (Early Write)
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
tRAD tASR tASC tCAH
Column
tASR
Address
tRAH
tCWL tRWL
tOEH
tDZO tDZC
(Inputs)
tODD tOEZ tCLZ tOEA
Valid Data
(Outputs)
Hi-Z
Hi-Z
Write Cycle Controlled Write)
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRWC tRAS
tCSH tRCD tRSH tCAS tCRP
tRAH tASR
tCAH tASC
Column
tASR
Address
tRAD
tAWD tCWD tRWD
tCWL tRWL
tRCS
tOEA
tOEH
tDZO tDZC
(Inputs)
Valid Data
tCLZ tCAC
tODD tOEZ
Data
(Outputs)
tRAC
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRASP
tRCD
tCAS
tCAS
tRHCP tRSH tCAS
tCRP
tCSH tRAH tASR tASC tCAH
Column
tASC
tCAH tASC
tCAH tASR
Column
Address
Column
tRAD tRCH tRCS tRCS tRCS
tRCH
tCPA tOEA
tOEA
tCPA tOEA tDZC tODD tDZO
tRRH
tDZC tDZO tODD
tDZC tDZO
tCDD tODD
(Inputs)
tCAC tRAC tCLZ
tOFF tOEZ
Valid Data
tCAC tCLZ
tOFF tOEZ
Valid Data
tCAC tCLZ
tOFF tOEZ
Valid Data
(Outputs)
FPM1
Fast Page Mode Read Cycle Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tRCD
tRSH tCAS tCAS tCRP
tCAS
tRAH tASR
tRAL tCAH tASC tASC
Column Column
tCAH tASC
tCAH
tASR
Column
Address
Column
tRAD tWCS
tCWL tWCH
tWCS
tCWL tWCH
tWCS
tCWL tRWL tWCH
(Inputs)
Valid Data
Valid Data
Valid Data
(Outputs)
HI-Z
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
tRAS
tCSH tPRWC tCAS tCAS tCRP tCAS tRSH tRCD
Semiconductor Group
tRAD tCAH tASC tASC
Column Column Column Address
tASR tASC
tRAH
tCAH tCAH
tRAL tASR
Address
tRCS tCWL tCWL tAWD tOEA tOEA tAWD tAWD tOEA
tRWD tCWD tCPWD tCWD
tCPWD tCWD
Fast Page Mode Read-Modify-Write Cycle
tRWL tCWL
Data
tDZC tCLZ tDZO tODD
Data
tCPA tDZC tCLZ
tCPA tDZC tCLZ tOEH tCAC tOEZ
Data Data
tODD
Data
(Inputs)
tCAC tRAC tOEZ
Data
tODD
tOEH
tOEH tOEZ
(Outputs)
3117800BSJ-50/-60/-70 8-DRAM
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tCRP tRPC
tRAH tASR
tASR
Address
(Outputs)
HI-Z
RAS-Only Refresh Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tRPC
tCSR tCHR tRPC
tCRP
tWRP tWRH
tOEZ
tCDD
(Inputs)
tODD
(Outputs)VOL
HI-Z
tOFF
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tRAS
tRCD
tRSH tCHR tCRP
tRAD tASC tASR tRAH
tWRP tCAH tWRH tASR
Address
Column
tRCS
tRRH
tOEA
tDZC tDZO
tCDD tODD tCAC tCLZ
(Inputs)
tOFF tOEZ
Valid Data HI-Z
tRAC
(Outputs)
WL11
Hidden Refresh Cycle (Read) Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tRAS
tRCD
tRSH
tCHR
tCRP
tRAD tRAH tASR tASC tCAH
Column
tASR
Address
tWCS
tWCH
tWRP
tWRH
Valid Data
(Input)
(Output)
HI-Z
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRASS
tRPS
tRPC tCSR
tCHS
tCRP
tWRP tWRH
tCDD
(Inputs)
tODD tOEZ
(Outputs)
HI-Z
tOFF
WL13
before Self Refresh Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
Read Cycle:
tCSR
tCHR
tRSH tCAS tRAL
tASC
Address
tCAH tCAC
tASR
Column
tWRP
tRRH tOEA tCDD tOFF tOEZ
Data
tRCH
tWRH
tRCS tDZC tDZO tCLZ
(Inputs)
tODD
(Outputs)
tWRP
Write Cycle:
tWCS
tWCH tWRH
tRWL tCWL
(Inputs) (Outputs)
Data
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
tRAS
tRPC tCSR tCHR tRPC tCRP
tASR tRAH
Address
tWTS
tWTH
(Inputs)
tODD
HI-Z
tCDD tOEZ
(Outputs)
HI-Z
tOFF
WL15
Test Mode Entry
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Test Mode 3117800BSJ organized internally 16-bits, test mode cycle using compression used improve test time. Note that version test time reduced test pattern. test mode "write" data from each written into blocks simultaneously (all test mode "read" each output used indicating test mode result. internal bits equal, would indicate "1". they were equal, would indicate "0". WCBR cycle (WE, before RAS) puts device into test mode. exit from test mode, "CAS before refresh", "RAS only refresh" "Hidden refresh" used. Refresh during test mode operation performed normal read cycles WCBR refresh cylces. addresses through have kept high perform testmode entry cycle. other addresses don't care.
Semiconductor Group
3117800BSJ-50/-60/-70 8-DRAM
Package Outlines
Plastic Package P-SOJ-28-3 (400 mil) (Small Outline J-lead, SMD)
10.16
+0.13
1.27 0.51 -0.13
0.81max
11.18
0.25
0.18
0.18
+0.13
GPJ05699
18.54
-0.25
Index Marking
Does include plastic metal protrusion 0.15 max. side
Semiconductor Group

HYB3117800BSJ-50/-60/-70 words 8-bit organization operating tempe

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