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HYB5117800BSJ-50/-60/-70 words 8-bit organization operating tempe


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8-Bit Dynamic
HYB5117800BSJ-50/-60/-70
words 8-bit organization operating temperature Performance:: tRAC tCAC access time access time Access time from address Read/Write cycle time Fast page mode cycle time
Single supply power dissipation max. active (-50 version) max. active (-60 version) max. active (-70 version) standby (TTL) 5.5. standby (CMOS) Output unlatched cycle allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh, self refresh test mode Fast page mode capability inputs, outputs clocks fully TTL-compatible 2048 refresh cycles Plastic Package: P-SOJ-28-3
Semiconductor Group
1.96
5117800BSJ-50/-60/-70 8-DRAM
5117800BSJ MBit dynamic organized 2097152 words 8-bits. 5117800BSJ utilizes submicron CMOS silicon gate process technology, well advanced circuit techniques provide wide operating margins, both internally system user. Multiplexed address inputs permit 5117800BSJ packaged standard plastic package. These packages provide high system densities compatible with commonly used automatic testing insertion equipment. System-oriented features include single power supply, direct interfacing with high-performance logic device families such Schottky TTL. Ordering Information Type 5117800BSJ-50 5117800BSJ-60 5117800BSJ-70 Names I/O1-I/O8 Address Inputs Column Address Inputs Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply Ground connected Ordering Code Q67100-Q1092 Q67100-Q1093 Q67100-Q1094 Package P-SOJ-28-3 P-SOJ-28-3 P-SOJ-28-3 Descriptions DRAM (access time DRAM (access time DRAM (access time
N.C.
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
P-SOJ-28-3 (400mil)
I/O1 I/O2 I/O3 I/O4 N.C.
I/O8 I/O7 I/O6 I/O5
Configuration
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
I/O1 I/O2
I/O8
Data Buffer
Clock Generator
Data Buffer
Column Address Buffer(10)
Column Decoder
Refresh Controller
Sense Amplifier Gating
Refresh Counter (11)
1024
Address Buffers(11)
Decoder 2048
Memory Array 2048x1024x8
Clock
Generator
Voltage Down Generator
(internal)
Block Diagram
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Absolute Maximum Ratings Operating temperature range Storage temperature range.- Input/output voltage .-0.5 (Vcc+0.5,7.0) Power supply voltage.-1.0V Power dissipation. Data current (short circuit) Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics Parameter Input high voltage Input voltage Output high voltage (IOUT Output voltage (IOUT Input leakage current,any input 0.3V, other pins Output leakage current disabled, VOUT 0.3V) Average supply current: version version version (RAS, CAS, address cycling, min.) Standby supply current (RAS VIH) ICC2 Average supply current, during RAS-only refresh cycles: version version version (RAS cycling: VIH, min.) Symbol Limit Values min. max. Vcc+0.5 Unit Test Condition
II(L) IO(L) ICC1
ICC3
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Characteristics (cont'd) Parameter Symbol Limit Values min. Average supply current, ICC4 during fast page mode: version version version (RAS VIL, CAS, address cycling,tPC min.) Standby supply current (RAS Average supply current, during CASbefore-RAS refresh mode: version version version (RAS, cycling, min.) Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., held low, WE=Vcc-0.2V, Address Din=Vcc-0.2V 0.2V)
max.
Unit Test Condition
ICC5 ICC6
ICC7
Capacitance °C,VCC Parameter Input capacitance A10) Input capacitance (RAS, CAS, capacitance (I/O1-I/O8) Symbol Limit Values min. max. Unit
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Characteristics 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
common parameters
Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay time hold time hold time precharge time Transition time (rise fall) Refresh period tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tREF
Read Cycle
Access time from Access time from access time Read command setup time Read command hold time Read command hold time referenced output low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF 8,10
Access time from column address Column address lead time tRAL
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Characteristics (cont'd) 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
Output buffer turn-off delay from Data delay high data delay high data delay
tOEZ tDZO tCDD tODD
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWCS
Write command lead time tRWL Write command lead time tCWL Data setup time Data hold time Data delay tDZC
Read-Modify-Write Cycle
Read-write cycle time delay time delay time command hold time tRWC tRWD tCWD tOEH
Column address delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time precharge time Access time from precharge pulse width precharge Delay tCPA tRAS tRHPC
200k
200k
200k
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Characteristics (cont'd) 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time precharge tPRWC tCPWD
CAS-before-RAS Refresh Cycle
setup time hold time precharge time Write precharge time tCSR tCHR tRPC tWRP
Write hold time referenced tWRH
CAS-before-RAS Counter Test Cycle
precharge time tCPT
Test Mode
hold time Write command setup time Write command hold time tCHRT tWTS tWTH
Self Refresh Cycle
pulse width precharge time hold time tRASS tRPS tCHS 100k 100k 100k
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Notes:
voltages referenced VSS. ICC1, ICC3, ICC4 ICC6 depend cycle rate. ICC1 ICC4 depend output loading. Specified values measured with output open. Address changed once less while VIL. case ICC4 changed once less during fast page mode cycle (tPC). initial pause required after power-up followed cycles which least cycle refresh cycle, before proper device operation achieved. case using internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. measurements assume (min.) (max.) reference levels measuring timing input signals. Transition times also measured between VIL. Measured with load equivalent loads Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only: tRCD greater than specified tRCD (max.) limit, then access time controlled tCAC. 10)Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only: tRAD greater than specified tRAD (max.) limit, then access time controlled tAA. 11)Either tRCH tRRH must satisfied read cycle. 12)tOFF (max.) tOEZ (max.) define time which outputs achieve open-circuit condition referenced output voltage levels. 13)Either tDZC tDZO must satisfied. 14)Either tCDD tODD must satisfied. 15)tWCS, tRWD, tCWD, tAWD tCPWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min.), cycle early write cycle will remain open-circuit (high impedance) through entire cycle; tRWD tRWD (min.), tCWD tCWD (min.), tAWD tAWD (min.) tCPWD tCPWD (min.) cycle read-write cycle pins will contain data read from selected cells. neither above sets conditions satisfied, condition pins access time) indeterminate. 16)These parameters referenced leading edge early write cycles leading edge read-write cycles. 17)When using Self Refresh mode, following refresh operations must performed ensure proper DRAM operation: addresses being refreshed evenly distributed manner over refresh interval using refresh cycles, then only cycle must performed immediately after exit from Self Refresh. addresses being refreshed other manner (ROR Distributed/Burst; CBR-Burst) over refresh interval, then full refreshes must performed immediately before entry immediately after exit from Self Refresh.
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tRCH
tRAH
tRCS
tRRH tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC tDZO
tCDD
tODD tCAC tCLZ tOEZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
(Inputs)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOFF
(Outputs)
Valid Data
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Read Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
AAAAAAA AAAAAAA
tRAH
tWCS
tCWL
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tWCH tRWL
(Inputs)
Valid Data
(Outputs)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
Write Cycle (Early Write)
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
tRAD tASR tASC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL
Address AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
AAAAAAAAA IHAAAAAAAAA AAAAAAAAA
tRAH
tRWL
tOEH
AAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
(Inputs)
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tODD tOEZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
AAAA
Valid Data
tCLZ tOEA
(Outputs)
Hi-Z
Hi-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Write Cycle Controlled Write)
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRWC tRAS
tCSH tRCD tRSH tCAS tCRP
tRAH tASR
tCAH tASC
tASR
Address
AAAA AAAA AAAA
AAAA AAAA AAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
tRAD
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tCWL tAWD
tCWD tRWD
tRWL
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
tRCS
tOEA
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
Valid Data
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
(Inputs)
tCLZ tCAC
tODD tOEZ
AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA AAAAAA
(Outputs)
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRASP
tRCD
tCAS
tCAS
tRHCP tRSH tCAS
tCRP
tCSH tRAH tASR tASC tCAH
Column
tASC
tCAH
tCAH tASC AAAAAAAAA AAAAAAAAA AAAAAAAAA Column AAAAAAAAA AAAAAAAAA AAAAAAAAA tRCS
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAA tRRH AAAAAAA
tASR
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
Address
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tRAD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tRCH
tRCH tRCS
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRCS
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
tCPA tOEA
tOEA
tCPA tOEA tDZC
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tDZC tDZO tODD
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tDZC tDZO tODD tDZO
tCDD tODD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tOFF
(Inputs)
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tCAC tCLZ
tCAC tCLZ
tRAC
(Outputs)
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tCAC tCLZ
tOEZ
tOEZ
tOEZ
AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data AAAAA AAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data AAAAAA AAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
FPM1
Fast Page Mode Read Cycle Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tRCD
tRSH tCAS tCAS tCRP
tCAS
tRAH tASR
AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRAL tCAH tASC tASC
AAAAAAAAAA AAAAAAAAAA
tCAH tASC
AAAAAAAAAA AAAAAAAAAA
tCAH
tASR
AAAAAAAAA AAAAAAAAA
Address
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA
tRAD tWCS
tCWL tWCH
tWCS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
tCWL tWCH
tWCS
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tCWL tRWL
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tWCH AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
(Inputs)
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
Valid Data
Valid Data
Valid Data
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
(Outputs)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
HI-Z
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tCPWD tCWD
tAWD
tOEA
tCPWD tCWD
tOEA
tCAH
tRWD tCWD
tAWD
tOEA
tCAH
tDZC tCLZ tDZO
tCSH
Column
tASC
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Data
tOEH
tOEZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column Address
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
Data
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCAH
tCPA
Column
tCLZ
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
Data
tOEZ
AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRAL
tRWL tCWL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCRP
tASR
tODD
tCAS
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tASC
tCWL
tDZC
tPRWC tCAS
tRAS
tODD
tOEZ
tAWD
tASC
tCPA tDZC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCWL
AAAAAA AAAAAA AAAAAA AAAAAA
tODD
tCAS
(Inputs)
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
(Outputs)
Address
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
tRAD
tRAH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRCD
tRCS
tRAC
Data
AAAAA AAAAA AAAAA
Data
AAAAA AAAAA AAAAA
Data
AAAAA AAAAA AAAAA
tRSH
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tCRP tRPC
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tRAH tASR
tASR
Address
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
(Outputs)
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
HI-Z
RAS-Only Refresh Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tRPC
tCSR tCHR tRPC
tCRP
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWRP tWRH
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tOEZ
tCDD
(Inputs)
tODD
(Outputs)VOL
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tRAS
tRCD
tRSH tCHR tCRP
tRAD tASC tASR tRAH
AAAAA AAAAA AAAAA AAAAA
tWRP tCAH tWRH tASR
Address
AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAA AAAAA Column
tRCS
AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tRRH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC
tCDD
tDZO
tODD tCAC tCLZ
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
(Inputs)
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOFF tOEZ
Valid Data
tRAC
(Outputs)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
HI-Z
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tRAS
tRCD
tRSH
tCHR
tCRP
tRAD tRAH tASR tASC tCAH tASR
Address
AAAAAAA IHAAAAAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAAA AAAAA AAAAA Column AAAAA AAAAA AAAAA tWCS tWRP tWRH tWCH
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
(Input)
AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
Valid Data
(Output)
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRASS
tRPS
tRPC tCSR
tCHS
tCRP
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tWRP tWRH
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tCDD
(Inputs)
tODD tOEZ
(Outputs)
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL13
before Self Refresh Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
Read Cycle:
tCSR
tCHR
tRSH tCAS tRAL
tASC
Address
tCAH tCAC
tASR
Column
tWRP
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRRH
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
IHAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAA tWRH AAAAAAAAAAAAAA
tRCS
tOEA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRCH
tDZC
(Inputs)
tODD tDZO tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCDD
tOFF tOEZ
Data
AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA
(Outputs)
tWRP
Write Cycle:
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
tWCS
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAA
tWCH
tRWL tCWL
tWRH
(Inputs) (Outputs)
Data
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
tRAS
tRPC tCSR tCHR tRPC tCRP
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tASR tRAH
AAAAAAAAAAAAAAAAAAAAAAAAAAA Address IHAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
tWTS
tWTH
AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
(Inputs)
tODD
HI-Z
tCDD tOEZ
(Outputs)
AAAAAAAAAAAAAAAAAAAAAAA OHAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
HI-Z
tOFF
WL15
Test Mode Entry
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Test Mode 5117800BSJ organized internally 16-bits, test mode cycle using compression used improve test time. Note that version test time reduced test pattern. test mode "write" data from each written into blocks simultaneously (all test mode "read" each output used indicating test mode result. internal bits equal, would indicate "1". they were equal, would indicate "0". WCBR cycle (WE, before RAS) puts device into test mode. exit from test mode, "CAS before refresh", "RAS only refresh" "Hidden refresh" used. Refresh during test mode operation performed normal read cycles WCBR refresh cylces. addresses through have kept high perform testmode entry cycle. other addresses don't care.
Semiconductor Group
5117800BSJ-50/-60/-70 8-DRAM
Package Outlines
Plastic Package P-SOJ-28-3 (400 mil) (Small Outline J-lead, SMD)
min. 3.75 -0.5
1.27 0.51
-0.13
0.81max 0.18
0.25 11.18
+0.13
0.18
10.16 +0.13
GPJ05699
18.54 Index Marking
-0.25
Does include plastic metal protrusion 0.15 max. side
Semiconductor Group

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HS2678RECH61H - HS2678RECH61H   HS2678RECH61H Datasheet
HS2678RECH61HE - HS2678RECH61HE   HS2678RECH61HE Datasheet
ENN8257 - ENN8257   ENN8257 Datasheet
CPH6901 - CPH6901   CPH6901 Datasheet
DSS-4832 - DSS-4832   DSS-4832 Datasheet
AN-9043 - AN-9043   AN-9043 Datasheet
ACE9030 - ACE9030   ACE9030 Datasheet

 

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