Table Item Memory H8/300H Series H8/3003 H8/300H Mask (

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Table Item Memory H8/300H Series H8/3003 H8/300H Mask (

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H8/300H series microcontrollers high-performance Hitachi-original 16-bit microcontrollers that build optimum peripheral equipment industrial machinery around high-speed H8/300 CPUs that have architecture upwardly compatible with H8/300 CPUs. microcontroller puts CPU, RAM, direct memory access controller (DMAC), controller, timers, serial communication interface (SCI) single chip, making suitable wide range applications from small large systems. This microcontroller technical covers H8/3001, H8/3002, H8/3003, H8/3042 series, H8/3032 series, H8/3048 series.
Table
Item Memory
H8/300H Series
H8/3003 H8/300H Mask (byte) ZTATTM* (byte) 8/16 bits bits On-chip QFP-112 H8/3002 H8/300H 8/16 bits bits On-chip QFP-100 TQFP-100 H8/3001 H8/300H 8/16 bits bits QFP-80 TQFP-80 H8/3042 H8/300H 8/16 bits bits bits On-chip QFP-100 TQFP-100 H8/3041 H8/300H 8/16 bits bits bits On-chip QFP-100 TQFP-100 H8/3040 H8/300H 8/16 bits bits bits On-chip QFP-100 TQFP-100
Address space (byte) External data width (bit) Timers (integrated timer unit) Watchdog timer controller Memory Memory memory
Programmable timing pattern controller (TPC) (Asynchronous/clocksynchronous) converter Resolution Input channel External trigger input converter Resolution Input channel
Refresh controller Interrupts External interrupts Internal Interrupts port Package Miscellaneous
Note: ZTAT (Zero turn around time) trademark Hitachi Ltd.
Table
Item Memory
H8/300H Series (cont)
H8/3048 H8/300H Mask (byte) ZTATTM* (byte) 8/16 bits bits bits On-chip QFP-100 TQFP-100 H8/3047 H8/300H 8/16 bits bits bits On-chip QFP-100 TQFP-100 H8/3044 H8/300H 8/16 bits bits bits On-chip QFP-100 TQFP-100 H8/3032 H8/300H bits bits QFP-80 TQFP-80 H8/3031 H8/300H bits bits QFP-80 TQFP-80 H8/3030 H8/300H bits bits QFP-80 TQFP-80
Address space (byte) External data width (bit) Timers (integrated timer unit) Watchdog timer controller Memory Memory memory
Programmable timing pattern controller (TPC) (Asynchronous/clocksynchronous) converter Resolution Input channel External trigger input converter Resolution Input channel
Refresh controller Interrupts External interrupts Internal Interrupts port Package Miscellaneous
Built-in smart card interface, improved low-voltage, low-power performance
Users Microcontroller Technical
This Microcontroller Technical compiled from answers technical questions received from Hitachi microcontroller users. hope that will useful addition H8/300H series user manuals. Before starting design products that microcontrollers, read through manual deepen your understanding microcontroller products re-familiarize yourself with those areas difficulty design stage.
Contents
Page
Section
Registers Difference Between CCR's Flag Flag Relationship Between Data Size Flag Changes General Registers Controller State While Operating Modes Setting Controller Area External Installation 8-Bit Areas Changing Number Wait States Inserted Area Receiving BREQ Power-Down Mode Maximum Wait Time After BREQ Input Interrupts Interrupt Sampling Holding External Interrupts Receiving NMIs During Processing Edge Rise Fall Times Interrupt Pins Disable Timing Interrupts Exception Processing After Reset Using Interrupt Controller Receiving External IRQ1 After Returning From Hardware Standby Mode Interrupt Priority Within Groups (10) Interrupts When Released Resets Sampling Timing Receiving After Reset Initializing After Reset State During Power-On Reset RESO Output From Input Connecting RESO Pins Cautions Reset Input Power-Down Mode Executing Instructions When Switching Hardware Standby Mode Mode Pins During Hardware Standby Mode Returning From Hardware Standby Mode Interrupt Sampling Receiving Sleep Mode Execution Time Software Standby Mode Operation When Interrupt Requested During Execution While Fetching SLEEP Instruction QA300H-001A QA300H-002A QA300H-003A
QA300H-004 QA300H-005A QA300H-006A QA300H-007A QA300H-008A QA300H-009A QA300H-010A
QA300H-011A QA300H-012A QA300H-013A QA300H-014A QA300H-015A QA300H-016A QA300H-017A QA300H-018A QA300H-019A QA300H-020A
QA300H-021A QA300H-022A QA300H-023A QA300H-024A QA300H-025A QA300H-026A
QA300H-027A QA300H-028A QA300H-029A QA300H-030A QA300H-031A QA300H-032A
Instructions Support (DAS) Instruction with (DEC) Instruction Instructions Instruction SUBX Instruction Address Values During Instruction Execution Interrupts Transfer Requests While EEPMOV Instruction Executing Difference Between EEPMOV.B EEPMOV.W Miscellaneous Cautions Stack Operation On-Chip Peripheral Access When Released Areas That Used Vector Table State During Oscillation Settling Time QA300H-033A QA300H-034A QA300H-035A QA300H-036A QA300H-037A QA300H-038A QA300H-039A
Page
QA300H-040A QA300H-041A QA300H-042A QA300H-043A
Section On-Chip Peripherals
Controller Receiving DMAC Startup Requests Addresses During Transfers TEND Signal Output Timing TEND Signal Output Timing Relationship Between DMAC's DTIE Bits DMAC Startup DMAC Timer Interrupts Operation After DMAC Interrupt Generated Operation After DMAC Interrupt Generated (10) Transfers Started Serial Transfers (11) Time Until DMAC Startup DREQ (12) Reverse Operation Repeat Mode (13) Dual-Function Pins (14) Ports DREQ QA300H-101 QA300H-102 QA300H-103 QA300H-104 QA300H-105 QA300H-106 QA300H-107 QA300H-108 QA300H-109 QA300H-110 QA300H-111 QA300H-112 QA300H-113 QA300H-114
Mode Interrupts Clearing Counters Pulse Output From Cascade Connections Setting ITU's Output Output Port Output Settings Independent Operation TCNT4 Using Reset-Synchronized Mode
QA300H-115 QA300H-116 QA300H-117 QA300H-118 QA300H-119 QA300H-120 QA300H-121 QA300H-122
Watchdog Timer Halting WDT's System Clock
QA300H-123
Serial Communications Interface (SCI) Using When Being Used Settings Clock Pins Serial State Simultaneous Transmission Reception with RDRF Setting Asynchronous Transmission Data Transferred Timing Setting RDRF Timing Setting TDRE (10) Reception Errors (11) Operating External Clock Mode (12) System Clocks Phases Converter Changing Mode Channel During Conversion Ports Using General-Purpose Ports Processing Ports When QA300H-124 QA300H-125 QA300H-126 QA300H-127 QA300H-128 QA300H-129 QA300H-130 QA300H-131A QA300H-132A QA300H-133 QA300H-134 QA300H-135
Page
QA300H-136
QA300H-137 QA300H-138
Section
Technical Questions Answers
Product Topic Question H8/300H QA300H-001A
Difference Between CCR's Flag Flag Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
Since CCR's flag flag both flag when operation overflows, what difference?
Answer
Related Manuals Manual Title
CCR's flag accessed overflow occurred signed operation. figure 1.1, which byte-sized operation, flag when result smaller than negative minimum (H'80) larger than positive maximum (H'7F).
H'80 flag Overflow Overflow H'00 H'7F
Other Technical Documentation Document Name
Figure Flag Operation
contrast, CCR's flag accessed overflow occurred unsigned operation. figure 1.2, which byte-sized operation, flag when result smaller than minimum (H'00) larger than maximum (H'FF).
H'00 flag Overflow Overflow H'FF
Related Microcomputer Technical Title
Figure Flag Operation
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-002A
Relationship Between Data Size Flag Changes Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
changes CCR's flag vary with data size?
Answer
Related Manuals Manual Title
CCR's flag changes when overflow detected result signed arithmetic operation. This operation same data sizes. However, timing changes flag varies follows: Byte: When value smaller than H'80 larger than H'7F. Word: When value smaller than H'8000 larger than H'7FFF. Longword: When value smaller than H'80000000 larger than H'7FFFFFFF.
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Product Topic Question H8/300H General Registers Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-003A
different general registers used 8-bit, 16-bit, 32-bit registers same time?
Answer
Related Manuals Manual Title
Yes. Registers freely shown figure 1.3.
Other Technical Documentation Document Name
(SP)
section 2.4.2, General Registers, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
Note: used without special notice being given.
Figure General Registers
References
Technical Questions Answers
Product Topic Question H8/300H State While Operating Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-004
What state during internal processing? What state after DREQ received? What state after BREQ received?
Answer
Related Manuals Manual Title
table 1.1.
Table State While Operating
Address Hold address High impedance Data High impedance data High impedance
Operation During internal processing After DREQ received After BREQ received
Other Technical Documentation Document Name
figure 6.18, External Release State, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Modes Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-005A
Section 6.2.1 H8/3003 Hardware Manual says, "When even ABWCR cleared mode becomes bits." Does this mean that areas accessed 16-bit mode?
Answer
Related Manuals Manual Title
When given ADWn (bus width control area ABWCR (bus width control register) cleared only that area whose cleared accessed 16-bit mode. manual description might better read, "When even area 16-bit accessed space, H8/300H goes into 16-bit mode D15-D0 used data bus. This means that ports that also used lower data (D7-D0) cannot used general ports, even 8-bit access space."
Other Technical Documentation Document Name
table 6.4, Address Space Data Used, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Setting Controller Area Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-006A
Since area mixes on-chip internal registers, which areas widths access states controller valid?
Answer
Related Manuals Manual Title
area width number access states controller valid areas other than on-chip internal registers. (The addresses area differ according product. manual details.) On-chip fixed width 16-bits fixed number access states internal registers have widths 8-bits 16-bits, have fixed number access states
Other Technical Documentation Document Name
figure 6.2, Access Area Each Operating Mode, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
References
When RAME (RAM enable) SYSCR (system control register) cleared on-chip valid settings area followed. signal outputs area
Technical Questions Answers
Product Topic Question H8/300H QA300H-007A
External Installation 8-Bit Areas Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When externally installed 8-bit space, which signal should used access LWR?
Answer
Related Manuals Manual Title
signal.
Other Technical Documentation Document Name
table 6.4, Address Space Data Used, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-008A-1
Changing Number Wait States Inserted Area Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
wait mode individual areas? not, should wait mode change number access states inserted individual areas?
Answer
Related Manuals Manual Title
(wait mode select) bits (wait control register), which wait mode, common areas. this reason, wait mode cannot individual areas. following areas, can, however, mixed: Wait disabled areas Areas which wait states only inserted WAIT (pin wait mode Areas which (wait count) bits valid (programmable wait mode, wait mode autowait mode) number access states individual areas changed using these combination. example shown below tables 1.3.
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section 6.3.5 (5), Setting Example, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
References
width enabled/disabled state (wait state controller) operation individual areas.
Technical Questions Answers
Product Topic Answer H8/300H QA300H-008A-2
Changing Number Wait States Inserted Area
Example: following access states following areas: Areas 0-1: states Area states Areas 3-4: states Area states Areas 6-7: states
Table
Area Area Area Area Area Area Area Area Area 3-state access space wait mode Invalid 3-state access space wait mode Enable Enable
Changing Number Wait States Inserted Area
Memory 2-state access space Wait-disabled area 3-state access space wait mode Invalid Valid/1 state Enable Enable Wait States from Invalid Enable/Disable Wait Insertion from WAIT Disable Waits from WAIT Access States
Table
Register
Register Settings
Address H'FC Setting
ASTCR (Access state control register)
WCER (Wait state control enable register)
H'38
H'F9
Technical Questions Answers
Product Topic Question H8/300H Receiving BREQ Power-Down Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-009A
BREQ received sleep mode? BREQ received hardware/software standby mode?
Answer
Related Manuals Manual Title
Since both hardware standby mode software standby mode bring on-chip peripheral modules halt (including clock), BREQ cannot received.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H Maximum Wait Time After BREQ Input Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-010A
does take long between BREQ input BACK output?
Answer
Related Manuals Manual Title
Because BREQ request held following cases: When DMAC (DMA controller) data being transferred burst mode block transfer mode. When waits inserted during accesses external addresses.
Other Technical Documentation Document Name
Example: When instruction with word-size operand executed with 8-bit wait mode cycle states inserted wait states wait states inserted pin)
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H Interrupt Sampling Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-011A
When external interrupts (NMI, IRQn) sampled?
Answer
Related Manuals Manual Title
Sampling occurs every fall system clock
Other Technical Documentation Document Name
figure 18.17, Interrupt Input Timing, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual figure 20.17, Interrupt Input Timing, following manual: H8/3042 Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Holding External Interrupts Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-012A
IRQn interrupt requests held they produced when IRQnE (IRQ enable) (IRQ enable register), which controls external interrupts (IRQn), cleared IRQn interrupt requests held they produced when interrupts masked with bits (condition code register)?
Answer
Related Manuals Manual Title
Yes. When signal specified ISCR (IRQ sense control register) drives IRQn pin, IRQnF (IRQn flag) (IRQ status register) This affected state IRQnE bit. When IRQnE while IRQnF interrupt requested. IRQnF cleared with software. Yes. above case, IRQnF affected state bits. When IRQnE IRQnF bits interrupt mask cleared, interrupt accepted.
Other Technical Documentation Document Name
figure 5.2, Interrupt Block Diagram, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Receiving NMIs During Processing Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-013A
highest priority always accepted, will another accepted generated while interrupt processing routine running?
Answer
Related Manuals Manual Title
another generated while interrupt processing routine running, that interrupt request accepted superimposed over first.
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References
Technical Questions Answers
Product Topic Question H8/300H QA300H-014A
Edge Rise Fall Times Interrupt Pins Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When edge trigger used external interrupt, what longest allowed rise fall times edge?
Answer
Related Manuals Manual Title
Make more than states. More than this will produce following effects: Interrupts will accepted because edge change detected. More than edge will detected internally each change external signal, multiple interrupts will requested.
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Technical Questions Answers
Product Topic Question H8/300H Disable Timing Interrupts Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-015A
interrupts disabled instant that peripheral module's interrupt enable cleared When interrupt enable (IRQ enable register) cleared interrupt instantly disabled?
Answer
Related Manuals Manual Title
Interrupts disabled after instruction that cleared interrupt enable finishes executing. When interrupt request generated while zeroing instruction executing, that interrupt request accepted after instruction completes execution. Interrupts disabled after instruction that cleared interrupt enable finishes executing. When interrupt request generated while zeroing instruction executing, that interrupt request accepted after instruction completes execution since request signal cleared simultaneously with enable bit. However, since IRQn flag held, next time interrupt enable that interrupt accepted.
Other Technical Documentation Document Name
section 5.5.1, Interrupt Generation Disable Contention, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
Also section 1.3.2, Holding External Interrupts (QA300H-012A), this manual.
References
Technical Questions Answers
Product Topic Question H8/300H Exception Processing After Reset Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-016A
interrupts ever generated immediately following resets?
Answer
Related Manuals Manual Title
Immediately after reset, interrupts, including NMIs, disabled. However, when first instruction program executed, NMIs accepted.
Other Technical Documentation Document Name
section 4.2.3, Interrupts After Reset, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Using Interrupt Controller Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-017A-1
should interrupt priority levels used make effective interrupt controller?
Answer
Related Manuals Manual Title
rewriting values IPRA IPRB (interrupt priority registers every interrupt processing routine, interrupt priority changed time. IPRA IPRB 1-word registers, they easy manipulate. sample program shown figure 1.4. procedures after figure more concrete example use.
PUSH MOV.W PUSH MOV.W MOV.W ANDC MOV.W @IPRA, #NEW, @IPRA #H'BF, @IPRA Saves content Saves IPRA value Sets IPRA value Clears Reverts saved IPRA value Reverts saved value
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Figure Sample Program
References
Technical Questions Answers
Product Topic Answer H8/300H Using Interrupt Controller QA300H-017A-2
Procedure setting interrupt priority: (user enable) SYSCR (system control register) (interrupt mask) (condition code register) CCR's (user bit/interrupt mask) this state, only NMIs priority interrupt sources accepted. interrupt priorities each interrupt source user end. Perform following processing during interrupt processing routines. Following interrupt priorities user, interrupts priorities lower than interrupt question masked writing appropriate bits IPRA IPRB.
Figure shows processing procedures when interrupt priorities user shown table 1.4.
Interrupt Priorities
User-Set Priorities Lowest Highest Initial IPRA, IPRB Settings
Table
Timer Timer Timer Timer
Interrupt Source
Main routine SCI1 interrupt (priority (masks interrupts other than NMI) SCI1 interrupt request flag Masks priority interrupts; SCI2 IPRA IPRB interrupts timers (interrupts enabled priority higher) (interrupts enabled priority higher)
Timer interrupt (priority (masks interrupts) Timer interrupt request flag Masks priority interrupts; SCI1, SCI2 IPRA IPRB interrupts timers (interrupts enabled priority higher)
(masks interrupts other than NMI) Enables priority interrupts; SCI2 IPRA IPRB interrupts timers State Processing Processing unique H8/300H
(masks interrupts other than NMI) Masks priority interrupts (enables priority interrupts); SCI2 IPRA IPRB interrupts timers (SCI1 interrupt
Figure Processing Procedures
Technical Questions Answers
Product Topic Question H8/300H QA300H-018A
Receiving External IRQ1 After Returning From Hardware Standby Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
hardware standby mode, IRQ1 then left hardware standby mode. Will interrupts accepted after returning while IRQ1 remains low?
Answer
Related Manuals Manual Title
Interrupts will accepted immediately after returning. reset clears hardware standby mode. This initializes (IRQ enable register) IRQ1 becomes disabled (the IRQ1E (IRQ1 enable) Thereafter, IRQ1E bits enable interrupts, interrupts will accepted.
Other Technical Documentation Document Name
section 4.2.3, Interrupts After Reset, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Interrupt Priority Within Groups Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-019A
When external interrupts occur simultaneously within groups with same priority (for example, IRQ4-IRQ7) which priority? When IRQ4 interrupt occurs during IRQ7 interrupt processing routine, what happens? (Does IRQ4 wait does IRQ4 processing take priority?)
Answer
Related Manuals Manual Title
priority within IRQ4-IRQ7 interrupt group IRQ4 IRQ5 IRQ6 IRQ7. IRQ7 accepted first. After accepted, IRQ4-IRQ7 masked. When (interrupt mask) (interrupt mask) bits (condition code register) enabled during IRQ7 processing routine, IRQ4-IRQ7 accepted. When enabled IRQ7 processing routine, IRQ4 accepted after returning from IRQ7 processing routine.
Other Technical Documentation Document Name
table 5.3, Interrupt Factors, Vector Addresses, Interrupt Priority Ranking following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H Interrupts When Released Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-020A
interrupts that occur when released held?
Answer
Related Manuals Manual Title
They are. After release ends, they accepted after execution instruction. This same regardless whether they sensed edge level.
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Product Topic Question H8/300H QA300H-021A
Sampling Timing Receiving After Reset Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
After reset, when does sampling signal begin?
Answer
Related Manuals Manual Title
Sampling signal begins simultaneously with fall system clock which reset clear sampled. accepted, however, until after execution first instruction after reset cleared (see figure 1.6)
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Reset clear tRESS sampling
Document Name
tRESS
tRESW sampled sampled
Related Microcomputer Technical Title
Figure Sampling Timing Receiving After Reset
References
Technical Questions Answers
Product Topic Question H8/300H Initializing After Reset Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-022A
does (stack pointer) have initialized immediately after reset?
Answer
Related Manuals Manual Title
interrupt accepted before initialized, save address when (program counter) saved interrupt exception processing becomes undefined. could written blank address, registers which makes impossible read them correctly return. This cause run-away operation. avoid this, initialize immediately after reset.
Other Technical Documentation Document Name
section 4.2.3, Interrupts After Reset, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H State During Power-On Reset Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-023A
What states need attention during power-on resets?
Answer
Related Manuals Manual Title
During power-on reset, device operating mode that uses mode pins (MD0-MD2) keep STBY high. Also remember that output data undefined until oscillation settles.
Other Technical Documentation Document Name
section 3.1.1, Types Operating Mode Selection, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
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Product Topic Question H8/300H RESO Output From Input Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-024A
What RESO state reset state (RES low)?
Answer
Related Manuals Manual Title
RESO high impedance reset state (RES low). does reset output (RESO low).
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References
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Product Topic Question H8/300H Connecting RESO Pins Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-025A
there problem with taking RESO output inputting directly pin?
Answer
Related Manuals Manual Title
Yes. When (watchdog timer) overflow causes RESO output input directly pin, reset caused input triggered that moment everything internal LSI, including WDT, initialized. This forcibly disables RESO output well, meaning that input spec tRESW (RES pulse width) minimum tcyc cannot satisfied operation H8/300H after that point cannot guaranteed. buffer thus needs inserted ensure that RESO output does find pin. (See figure 1.7.)
Other Technical Documentation Document Name
Peripheral
RESO
H8/300H
External reset
Related Microcomputer Technical Title
Figure Connecting RESO Pins
References
Technical Questions Answers
Product Topic Question H8/300H Cautions Reset Input Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-026A
there cautions reset input?
Answer
Related Manuals Manual Title
When made low, reset begins, sure that reset performed, must least when power turned least system clock cycles when operating. When goes high thereafter, reset exception processing begins. these conditions satisfied, operation thereafter cannot guaranteed.
Other Technical Documentation Document Name
section 4.2.2, Reset Sequence, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H QA300H-027A
Executing Instructions When Switching Hardware Standby Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
What happens executing instructions when STBY goes hardware standby mode entered?
Answer
Related Manuals Manual Title
executing instruction halts without waiting finish operation cannot guaranteed. preserve contents RAM, clear RAME (RAM enable) SYSCR (system control register)
Other Technical Documentation Document Name
section 17.5.1, Transition Hardware Standby Mode, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual section 19.5.1, Transition Hardware Standby Mode, following manual: H8/3042 Series Hardware Manual
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References
Technical Questions Answers
Product Topic Question H8/300H QA300H-028A
Mode Pins During Hardware Standby Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
What happens when mode pins (MD2-MD0) changed hardware standby mode?
Answer
Related Manuals Manual Title
result abnormal hardware standby mode operation. change mode pins while hardware standby mode. When mode changed PROM mode, example, power consumption goes
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-029A
Returning From Hardware Standby Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
know that kept STBY changed high return from hardware standby mode, long before STBY changed high does have low?
Answer
Related Manuals Manual Title
return from hardware standby mode, before STBY changed high. (See figure 1.8.)
STBY
Other Technical Documentation Document Name
tOSC
Appendix Hardware Standby Mode Transition (Return Timing), following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
Figure Standby Release Timing
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-030A
Interrupt Sampling Receiving Sleep Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When external interrupts sampled during sleep mode? many states after interrupt sampled sleep mode cleared?
Answer
Related Manuals Manual Title
Sampling same during program execution. Sampling occurs every fall system clock. Sleep mode cleared states after interrupt sampled. (See figure 1.9.)
Other Technical Documentation
Sleep mode Address Data (D15-D0) Interrupt request signal states
Document Name
Related Microcomputer Technical Title
SP-2 SP-4 Interrupt vector address Saved saved Interrupt processing routine start address (contents vector address) Note: Example H8/3003 (16-bit mode, 2-state access, stack external memory)
Figure Timing Clearing Sleep Mode Interrupt
Technical Questions Answers
Product Topic Question H8/300H QA300H-031A
Execution Time Software Standby Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
many states needed transition software standby mode using SLEEP instruction?
Answer
Related Manuals Manual Title
time required transition software standby mode time (states) required SLEEP instruction execute. When SLEEP instruction stated on-chip memory, takes states; when SLEEP instruction external 8-bit 3-state-access space, takes states. figure below shows timing execution SLEEP instruction. (See figure 1.10.)
SLEEP instruction execution time Sleep mode Internal address Internal data bits)
Other Technical Documentation Document Name
Related Microcomputer Technical
Title
PC+2 SLEEP instruction Next instruction (not executed)
Figure 1.10 Sleep Instruction Timing
Technical Questions Answers
Product Topic Question H8/300H QA300H-032A-1
Operation When Interrupt Requested During Execution While Fetching SLEEP Instruction Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
does H8/300H operate when interrupt comes during SLEEP instruction fetch while SLEEP instruction executing?
Answer
Related Manuals Manual Title
Operation varies, depending time interrupt request occurs, shown below: During SLEEP instruction fetch: interrupt exception processing starts after previous instruction finishes executing. saved becomes address SLEEP instruction. After returning from interrupt service routine, SLEEP instruction executes. During SLEEP instruction execution (case Interrupt exception processing starts without going through sleep state. saved becomes address instruction after SLEEP instruction. After returning from interrupt service routine, instruction after SLEEP instruction executes. During SLEEP instruction execution (case sleep mode canceled states later interrupt service routine starts. (See figure 1.11.)
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Answer H8/300H QA300H-032A-2
Operation When Interrupt Requested During Execution While Fetching SLEEP Instruction
SLEEP instruction instruction Sleep mode
Internal address Internal data bits)
Interrupt request signal
SLEEP instruction Next instruction Note: During H8/3003 (mode 2-state access)
Figure 1.11 Timing When Interrupt Request Occurs During SLEEP Instruction Fetch Execution
Technical Questions Answers
Product Topic Question H8/300H QA300H-033A
Support (DAS) Instruction with (DEC) Instruction Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
instruction used with instruction (ADD), about executing after instruction executes? instruction used with subtract instruction (SUB), about executing after instruction executes?
Answer
Related Manuals Manual Title
Execution instruction after execution instruction supported, since flags reflect results operation after instruction execution. increment decimal data, execute instruction after adding with instruction (ADD.B Rd). Execution instruction after execution instruction supported, since flags reflect results operation after instruction execution. decrement decimal data, execute instruction after adding with instruction (ADD #-1, inverting flags (XORC #A0, CCR).
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Actual operation determined flag state.
Technical Questions Answers
Product Topic Question H8/300H Instructions Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-034A
What difference between (BT) JMP? Also, what does mean condition "True"? What does mean (BF) condition "False"?
Answer
Related Manuals Manual Title
instruction used just like instruction, differs following points: only branch range +127 bytes -128 bytes +32767 bytes -32768 bytes d:16. relative values objects change, program relocated. Execution states instruction size different. Assembler format different. condition True means that since this instruction always branches, branch condition always True.
Other Technical Documentation Document Name
condition False means that since this instruction never branches, branch condition always False.
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H Instruction Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-035A
What kind instruction (BF)?
Answer
Related Manuals Manual Title
convenient instruction that replaces conditional branch instructions during debugging. operates same instruction, size execution time differ described table 1.5.
Table
Instruction d:16 Note:
Instruction
Instruction Size (Bytes) Instruction Execution Time (States)
Other Technical Documentation Document Name
16-bit bus/2-state access space instruction fetch from onchip ROM.
Related Microcomputer Technical Title
References
Like BRN, (BT) convenient during debugging.
Technical Questions Answers
Product Topic Question H8/300H SUBX Instruction Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-036A
does SUBX instruction (subtraction with carry) preserve flag when result execution
Answer
Related Manuals Manual Title
SUBX instruction used divide subtraction operation into multiple subtractions. After SUBX instruction executed, flag reflects result these operations (See figure 1.12.). does reflect results each individual SUBX instruction.
RmL, Reflected flag SUBX RmH,
Other Technical Documentation Document Name
Figure 1.12 Flag
When SUBX instruction results flag thus holds result previous operation.
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-037A
Address Values During Instruction Execution Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
What address value when instruction executed stored (register indirect) even address?
Answer
Related Manuals Manual Title
Undefined.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-038A
Interrupts Transfer Requests While EEPMOV Instruction Executing Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When interrupt occurs during execution EEPMOV instruction, what happens that interrupt request? What happens when transfer request occurs during execution EEPMOV instruction?
Answer
Related Manuals Manual Title
When interrupt occurs during execution EEPMOV.B instruction, interrupt held accepted when instruction finishes executing. handled same when interrupt occurs during ordinary instruction execution. However, NMIs that occur during EEPMOV.W execution accepted after transfer byte transfer completed. interrupts other than NMIs, operation same EEPMOV.B. transfer executed between read cycle write cycle EEPMOV instruction.
Other Technical Documentation Document Name
section 2.2.28 (items EEPMOV, following manual: H8/300H Series Programming Manual
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-039A
Difference Between EEPMOV.B EEPMOV.W Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
What difference between EEPMOV.B EEPMOV.W?
Answer
Related Manuals Manual Title
transfer data size both EEPMOV.B EEPMOV.W instructions byte, there some differences, described below. Size register that counts transfer bytes: EEPMOV.B: Byte (maximum number transfer bytes 255). EEPMOV.W: Word (maximum number transfer bytes 65535). Enable/disable interrupt acceptance: EEPMOV.B: Accepted after instruction executes (all held). EEPMOV.W: alone accepted after transfer byte transfer completed (all others held).
Other Technical Documentation Document Name
section 2.2.28 (1), EEPMOV H8/300H Series Programming Manual
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H Cautions Stack Operation Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-040A
there particular cautions about stack operation aware
Answer
Related Manuals Manual Title
H8/300H, stack area always accessed word longword. When stack pointer number, malfunctions result. PUSH instructions stack. initial value (stack pointer) undefined. initialized user.
Other Technical Documentation Document Name
section 2.4.4 Inicial Resistor, section 2.5.2 Memory Data Formats, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-041A
On-Chip Peripheral Access When Released Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
external devices (bus master) access internal registers H8/300H when H8/300H released external device?
Answer
Related Manuals Manual Title
Internal registers cannot accessed from external devices.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question H8/300H QA300H-042A
Areas That Used Vector Table Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
empty areas vector table (reserved system reserve) used ROM? empty areas registers used ROM?
Answer
Related Manuals Manual Title
vector numbers reserved system (4-6) vector table cannot used. Reserve addresses, however, used ROM. Unused interrupt vector addresses vector table also used. empty areas registers cannot used.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Items reserved system used development tools. Addresses reserved system reserve addresses listed manual. Branch address areas "memory indirect" addressing addresses other than those reserved system those used vector table.
Technical Questions Answers
Product Topic Question H8/300H QA300H-043A
State During Oscillation Settling Time Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
What states during oscillation settling time after software standby mode cleared?
Answer
Related Manuals Manual Title
same software standby mode.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Section On-Chip Peripherals
Technical Questions Answers
Product Topic Question Common Receiving DMAC Startup Requests Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-101-1
When controller startup request occurs: When request forced wait? request accepted under following conditions? During EEPMOV execution During read-modify-write instruction execution During DMAC cycle steal transfers.
Answer
Related Manuals Manual Title
arbiter priority order external master refresh controller DMAC CPU. This means that requests accepted when external master refresh controller with priority higher than DMAC bus. Since DMAC channels have priorities (for H8/3003) shown table 2.1, request waits when higher priority channel transferring.
DMAC Channel Priority
Full Address Mode Channel Channel Channel Channel Lowest Priority Highest
Other Technical Documentation Document Name
Table
Short Address Mode Channel Channel Channel Channel Channel Channel Channel Channel
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Answer Common Receiving DMAC Startup Requests QA300H-101-2
During EEPMOV execution, requests accepted between read cycle write cycle. During read-modify-write instruction execution, requests accepted between read cycle, instruction fetch, write cycle. During cycle steal transfers, requests accepted channel transfer request higher priority than current channel.
References
BSET, BCLR, BNOT, BIST read-modify-write instructions. When wait longer than those described above, wait states have been inserted cycle that DREQ request. (See figure 2.1.)
cycle
cycle
cycle
DREQ request
Requires states case shown
Figure Wait State Insertion
Technical Questions Answers
Product Topic Question Common Addresses During Transfers Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-102
Doesn't cause problems DMAC operation reads (memory address register) during transfers?
Answer
Related Manuals Manual Title
Reading does have affect operation. However, when longword data read, cycle enter between reading 16-bits data bottom 16-bits data, described manual. result, value read differ from actual value. timing which updated shown figure 2.2.
cycle
Other Technical Documentation Document Name
Transfer source
Transfer destination
Related Microcomputer Technical Title
updated transfer source. Counter updated. updated transfer destination Note: also updated transfer source (during burst transfers block transfer mode).
Figure Update Timing
References
There should mistake value read long bottom 16-bit (MARH, MARL) value read with MOV.W instruction.
Technical Questions Answers
Product Topic Question Common TEND Signal Output Timing Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-103
TEND signal output every byte/word transfer?
Answer
Related Manuals Manual Title
TEND signal output when startup source external request (using DREQ pin). operating modes other than block transfer mode, TEND signal driven during final transfer write cycle. block transfers, during write cycle just before block transfer. output every byte/word. (See figure 2.3.)
Final cycle Address HWR, TEND cycle
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Related Microcomputer Technical Title
Figure TEND Output
References
Technical Questions Answers
Product Topic Question Common TEND Signal Output Timing Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-104
what timing TEND signal output?
Answer
Related Manuals Manual Title
TEND signal output write cycle when ETCR (transfer count register) becomes H'00. Figure illustrates timing.
Final cycle Address HWR, TEND ETCR H'01 H'00 cycle
Other Technical Documentation Document Name
Related Microcomputer Technical Title
Figure TEND Output Timing
References
Technical Questions Answers
Product Topic Question Common QA300H-105
Relationship Between DMAC's DTIE Bits Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous
DTIE interrupt processing Holds values DTIE
When DTIE (data transfer interrupt enable) (data transfer enable) then cleared manual says that interrupt requested CPU. Will transfer interrupts occur continuously, shown figure 2.5? what done keep interrupts from occurring?
controller Watchdog timer converter ports
Figure Continuous Interrupts from DTIE
Answer Related Manuals Manual Title
Yes, interrupts will occur continuously. DTIE (enabling interrupts), interrupts will always produced. prevent this, (the BSET instruction used), clear DTIE (the BCLR instruction used).
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common DMAC Startup Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-106
When DMAC started with compare match interrupt, what happens (interrupt mask) (user bit/interrupt mask) (condition code register) masked?
Answer
Related Manuals Manual Title
Interrupts selected DMAC startup sources affected CPU's interrupt mask bits bits). (See figure 2.6.)
SYSCR Peripheral module Flag compare match like Interrupt enable Priority determination circuit
Other Technical Documentation Document Name
Related Microcomputer Technical
DMAC
Title
Figure DMAC Startup
References
When interrupt disabled with interrupt enable module, interrupts will occur either DMAC startup request CPU.
Technical Questions Answers
Product Topic Question Common DMAC Timer Interrupts Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-107
When DMAC startup source compare-matched ITU, interrupt produced ITU?
Answer
Related Manuals Manual Title
Interrupt requests selected startup sources startup DMAC when (data transfer enable) DMAC's DTCR (data transfer control register) interrupt generated CPU. When startup request generated interrupt goes CPU. interrupt that used startup source cannot simultaneously generate interrupt CPU.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common QA300H-108
Operation After DMAC Interrupt Generated Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When transfer count register becomes H'0000 while DMAC interrupt generated: When next transfer request accepted? transfer requests generated before transfer starts ignored?
Answer
Related Manuals Manual Title
next transfer request accepted when (data transfer enable) software. When transfer count register reaches H'0000 transfer interrupt generated, DTCR (data transfer control register) cleared data transfer disabled. another transfer, transfer count register during interrupt routine then When startup request internal interrupt, interrupt requested when more information, hardware manual. When startup request external request, ignored edge.
Other Technical Documentation Document Name
section 8.6, Cautions Use, following manuals: H8/3002 Hardware Manual H8/3003 Hardware Manual H8/3042 Series Hardware Manual
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common QA300H-109
Operation After DMAC Interrupt Generated Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When transfer count register becomes H'0000 while DMAC transfer ends, when transfer interrupt generated?
Answer
Related Manuals Manual Title
After transfer ends, interrupt request generated released. When captures bus, transfer interrupt performed after executing instruction ends. (See figure 2.7.)
Exception processing started DMAC transfer interrupt
Other Technical Documentation Document Name
cycle Transfer interrupt signal
Final transfer cycle
cycle
Related Microcomputer Technical Title
Figure Timing DMAC Interrupt
References
Technical Questions Answers
Product Topic Question Common QA300H-110
Transfers Started Serial Transfers Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
more than transfers done between memory I/Os when DMAC used together send receive?
Answer
Related Manuals Manual Title
When DMAC started SCI, mode should used. maximum number transfers allowed will then 65,536. transfer more data than this, data must stored memory transfer counter reset with transfer interrupt.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common QA300H-111
Time Until DMAC Startup DREQ Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
states minimum time startup DMAC from DREQ pin?
Answer
Related Manuals Manual Title
delay time from DREQ internal DMAC module states. arbiter internal processing time also states. This means minimum states (the these figures) required.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common QA300H-112
Reverse Operation Repeat Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
What pause transfer that uses repeat mode then start opposite direction?
Answer
Related Manuals Manual Title
flowchart figure illustrates process.
Forward byte transfer (DTID
Disable internal interrupts that cause start-ups
Other Technical Documentation Document Name
true DMAC halted ETCRH
false
(ETCRL ETCRH ETCRL
Related Microcomputer Technical Title
Reversed byte transfer (DTID
Enable internal interrupts that cause start-ups
Number transfer cycles. ETCRL-ETCRH.
Figure Reverse Operation Repeat Mode
Technical Questions Answers
Product Topic Question Common Dual-Function Pins Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-113
When DMAC used under following conditions, TEND/CS dual-function used output? Conditions: Full-address transfer mode, external request (low level input from DREQ pin) startup source.
Answer
Related Manuals Manual Title
cannot used output. When external request selected startup source, TEND/CS dual-function concerned becomes TEND output pin. more information, Port section hardware manual.
Other Technical Documentation Document Name
section Ports, following manual: H8/3003 Hardware Manual
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Ports DREQ Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-114
should (data transfer enable) DTCR (data transfer control register) pins that used both DREQ pins ports ports? should dual-function pins DREQ pins?
Answer
Related Manuals Manual Title
They used ports without regard bit. dual-function pins DREQ pins, clear (data direction register) affected ports When port output detected DREQ input.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Mode Interrupts Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-115
When used mode interrupts enabled, necessary clear IMFB (input capture/compare match flag (timer status register) within interrupt processing routine IMFB automatically cleared when IMIB interrupt generated?
Answer
Related Manuals Manual Title
IMFB flag must cleared within interrupt processing routine. timing when flag cleared program shown figure 2.9.
Other Technical Documentation Document Name
Address
address
Flag cleared
Related Microcomputer Technical Title
Figure IMFB Flag
References
clear IMFB flag, BCLR instruction.
Technical Questions Answers
Product Topic Question Common Clearing Counters Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-116
clear counter using software?
Answer
Related Manuals Manual Title
Clear TCNT (timer counter) writing H'0000 counter value cleared rewriting TSTR (timer start register).
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Pulse Output From Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-117
specific number pulses output (say, then stop pulse output?
Answer
Related Manuals Manual Title
When DMAC channel used: Pulses output ITU's mode. this case, DMAC started compare match. transfers generate transfer interrupt stop ITU. This transfer aimed starting times; data transfer that does affect operation (transfer data, transfer source address, transfer destination address). When other timers used: Output pulses input TCLK (clock input pin) events counted another timer (x). When timer compare register reaches count compare match interrupt generated stops. H8/300H, TIOCA0/TCLKC TIOCB0/TCLKD dualfunction pins. this reason, extra wiring needs added board output pulses from channel TCLKC TCLKD input pins. When using software: Generate compare match interrupts each time count with interrupt processing routine.
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Product Topic Question Common Cascade Connections Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-118
cascade connections used with ITU?
Answer
Related Manuals Manual Title
pins port dual function pins outputs TIOCA0 TIOCB0 ITU's channel clock inputs TCLKC TCLKD. This enables direct cascade connections without external wiring. count timing host shown figure 2.10.
(system clock) TIOCA0/TCLKC TIOCB0/TCLKD Sampling
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Figure 2.10 Count Timing
Related Microcomputer Technical Title
When there wiring from TIOCA0/TCLKC TIOCB0/TCLKD chip load light, TCLKC TCLKD sample compare match output TIOCA0 TIOCB0 rise next
References
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Product Topic Question Common Setting ITU's Output Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-119
When used mode, should TIOR (timer control register) set?
Answer
Related Manuals Manual Title
TIOR setting does affect output. When mode with TMDRs (timer mode registers) located each channels ITU, GRA/GRB used output compare registers output setting, regardless contents TIOR.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Output Port Output Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode
(TCNT value)
QA300H-120-1
When toggle output (output capture/input compare dual-function register compare match output shown figure 2.11, what kind value output when changing from port output output?
Instructions Miscellaneous controller Watchdog timer converter
output Port output output High output output?
TIOCB output, port output
(Time)
ports
toggle output upon compare match TIOR (timer control register)
port output with output upon compare match TIOR (timer control register) disabled
toggle output upon compare match TIOR (timer control register)
Related Manuals Manual Title
Figure 2.11 Output Port Output
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References
Technical Questions Answers
Product Topic Answer Common Output Port Output QA300H-120-2
When port output changed output, value from before change output. When compare match signal generated point when port output changed output, value changes. (See figure 2.12.)
Case TIOCB output, port output Output becomes high toggle output output port output Port output program High output before port output output
toggle output again program level output, since compare match signal generated before setting output
Case Compare match signal TIOCB output, port output Output becomes high toggle output output port output
output
Port output program
toggle output again program
Figure 2.12 Output Port Output
References
When started after reset, TIOCn output until first compare match occurs. When input capture output disabled, output level changes when input capture occurs.
Technical Questions Answers
Product Topic Question Common Settings Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-121-1
Please explain detail pulse width, cycle settings register settings pulse output well relationship internal clock.
Answer
Related Manuals Manual Title
When outputting pulses mode, duty found from following equation. Duty where (set counter value corresponding width (set counter value corresponding cycle Example: When operating frequency MHz, internal clock count duty (with 1)/(9 must exact timing shown figures 2.13 2.16.
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References
Technical Questions Answers
Product Topic Answer Common Settings QA300H-121-2
Internal clock (/4)
tcyc H'0000
tcyc H'0000 H'0001 H'0000
TCNT
TIOCA
Figure 2.13 Settings
Internal clock (/4)
Compare match occurs
tcyc
TCNT TIOCA
Figure 2.14 Settings
Internal clock (/4)
Compare match occurs
tcyc H'0000
TCNT TIOCA
Figure 2.15 Settings
Technical Questions Answers
Product Topic Answer Common Settings QA300H-121-3
TCNT value Figure 2.14
Figure 2.15
Figure 2.13 TIOCA output
Time
Figure 2.16 Settings
Technical Questions Answers
Product Topic Question Common QA300H-122
Independent Operation TCNT4 Using Reset-Synchronized Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
manual states that "TCNT4 runs independently" when resetsynchronized mode used. this mean used other purposes?
Answer
Related Manuals Manual Title
Reset-synchronized mode uses channel together, only counters registers uses TCNT3, GRA3, GRA4, GRB3 GRB4. This allows TCNT4 used independently. might interval timer using counter overflows.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Halting WDT's System Clock Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-123
When system clock halted, does (watchdog timer) detect abnormalities?
Answer
Related Manuals Manual Title
When system clock entire halted, count stops well, cannot detect abnormalities.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common QA300H-124
Using When Being Used Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When being used: (receive data register) used data register? (transmit data register)?
Answer
Related Manuals Manual Title
cannot used data register because read-only register. used data register.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Settings Clock Pins Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-125
When being used, does (data direction register) port (serial clock) specification that pin?
Answer
Related Manuals Manual Title
direction when being used specified (communications mode) (serial mode register) CKE1 CKE0 (clock enable) bits (serial control register). Setting port necessary.
Other Technical Documentation Document Name
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References
Technical Questions Answers
Product Topic Question Common Serial State Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-126
After using dual-function pins that used ports (TXD, SCK) pins, reset them ports with (serial control register) (serial mode register). What happens values (data direction register) pins when this happens?
Answer
Related Manuals Manual Title
operation does affect contents port. This means that case described above holds value before being pin.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common QA300H-127
Simultaneous Transmission Reception with Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When being used, transmission using internal clock occur simultaneous with reception external clock vice versa)?
Answer
Related Manuals Manual Title
Only clock source selected transfer clock. This prevents simultaneous transmission reception using types clocks. Simultaneous transmission/reception using same clock possible.
Other Technical Documentation Document Name
Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common RDRF Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-128
What happens when clearing RDRF (receive data register full) flag (serial status register) during reception, cleared directly without first reading
Answer
Related Manuals Manual Title
will cleared. When BCLR instruction used, first read byte units, then that corresponds RDRF flag cleared write occurs, again byte units. While RDRF flag (RXI interrupt processing routine), BCLR instruction thus cannot clear RDRF flag.
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Related Microcomputer Technical Title
References
Technical Questions Answers
Product Topic Question Common Setting Asynchronous Transmission Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-129-1
Asynchronous transmission uses SCI. transfer software (i.e., using data empty interrupt (TXI) DMAC)?
Answer
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When TDRE data empty interrupt always generated There thus methods. Setting first byte with interrupt processing routine: (transfer counter) (transfer enable) (empty interrupt enable) Setting first byte with initialization: (transfer counter) (transfer enable) First byte TDRE cleared (transfer starts, TDRE after (empty interrupt enable)
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either case, interrupt processing routine shown figure 2.17.
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Product Topic Answer Common Setting Asynchronous Transmission QA300H-129-2
(Empty interrupt generation)
(interrupt disabled)
(Rn)th byte data written TDR; TDRE cleared (TDRE read cleared)
Figure 2.17 Interrupt Processing Routine
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Product Topic Question Common Data Transferred Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous
H8/3003 Data transfer DMAC 16-bit data Transfer data DRAM
QA300H-130-1
there ways, when transferring transfer data located 16-bit space SCI's transmit data register (TDR, length bits) shown figure 2.18, Transfer using software? DMAC?
controller Watchdog timer converter ports
Figure 2.18 Transferring Data
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16-bit spaces accessed byte units. Read transfer data DRAM byte time transfer SCI's TDR. transfer data stored transfer buffer, shown figure 2.19.
10000
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10010 Note: Start address transfer buffer 10000 stored ER0.
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Figure 2.19 Transfer Buffer
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Product Topic Answer Common Data Transferred QA300H-130-2
LOOP:
MOV.B #12,R2L Waiting interrupt DEC.B
number transfer words placed sleep mode Copy transfer data byte) increment transfer buffer pointer (ER0)
Continue until transfer counter hits Interrupt: MOV.B @ER0+,R3L Transfer transfer data SCI's MOV.B R3L,@TDR Decrement transfer counter BCLR #7,@SSR Clear TDRE LOOP Return main routine LOOP Using DMAC: Start DMAC with SCI's interrupt transfer transfer data DRAM byte time SCI's TDR. Byte needs specified size DMAC. (Word size transfers impossible, since they start DMAC every transmission byte.)
References
controller function used enable word-sized transfers shown figure 2.20. each read cycle (16-bit data), consecutive write cycles 8-bit data necessary.
H8/300H transfer
16-bit address space
8-bit space
Figure 2.20 Using Controller Function Enable Word-Sized Transfers
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Product Topic Question Common Timing Setting RDRF Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-131A-1
When data reception ends, RDRF (receive data register full) flag (serial status register) what point asynchronous mode RDRF set? When clock-synchronous mode?
Answer
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RDRF flag after data received data sampling clock falls. (See figure 2.21.)
101112 13141516 10111213141516
Basic clock
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Stop
Receive data Data sampling
RDRF
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Note: When clock source internal clock, basic clocks states. When clock source external clock, states.
Figure 2.21 8-Bit Data, Stop
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Product Topic Answer Common Timing Setting RDRF QA300H-131A-2
RDRF flag after data received synchronization clock rises. (See figure 2.22.)
Synchronization clock
Receive data
RDRF
Note: When clock source internal clock, state. When clock source external clock, states.
Figure 2.22 8-Bit Data
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Product Topic Question Common Timing Setting TDRE Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-132A-1
When 8-bit data transmission ends, TDRE (transmit data register empty) flag (serial status register) what point asynchronous mode TDRE set? When clock-synchronous mode?
Answer
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TDRE flag different times when there transmission data (transmit shift register) when there not. Asynchronous mode. (See figure 2.23.)
101112 13141516 10111213141516
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Basic clock
Transmit data
Stop
Start
TDRE
When clock source internal clock, state. When clock source external clock, state.
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Figure 2.23 Transmit data (Asynchronous mode)
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Product Topic Answer Common Timing Setting TDRE QA300H-132A-2
start transmission according setting (transmit enable) also follows this timing. (See figure 2.24.)
Internal write signal
10111213141516 10111213141516 11121314
Basic clock
TDRE states
Figure 2.24 transmit data (Asynchronous mode)
Clock-synchronous mode (See figures 2.25 2.26.)
Synchronization clock Transmit data
TDRE
When clock source internal clock, state. When clock source external clock, 1.5-2.5 state.
Figure 2.25 Transmit data (Clock-synchronous mode)
Internal write signal
TDRE
TDRE timing
states
Figure 2.26 transmit data (Clock-synchronous mode)
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Product Topic Question Common Reception Errors Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-133
returning main routine during receive error interrupt routine without clearing reception error flags (serial status register), receive error interrupt generated again?
Answer
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receive error flag automatically cleared. After returning main routine (after executing instruction), receive error interrupt will generated again.
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Product Topic Question Common QA300H-134
Operating External Clock Mode Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
When operated clock-synchronous external clock mode: Does start next transmit operation after completion byte data transmission, external clock applied before H8/300H writes (transmit data register)? What happens after reception?
Answer
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results follows: Transmission does start. next transmission will start until TDRE (transmit data register empty) (serial status register) cleared Reception starts, however, overrun error will occur unless RDRF (receive data register full) cleared before next data completely received.
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Product Topic Question Common System Clocks Phases Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-135
(serial transfer clock) output synchronous system clock rise fall?
Answer
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signal output synchronous system clock fall.
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Product Topic Question Common QA300H-136
Changing Mode Channel During Conversion Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports
switch conversion mode during conversion? change selected channel during conversion?
Answer
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Switching conversion mode during conversion will decrease conversion accuracy. advise against Changing selected channel during conversion causes same problem switching conversion mode. Again, advise against
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References
Before switching conversion mode changing selected channel, check (A/D flag) ADCSR (A/D control/status register).
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Product Topic Question Common Using General-Purpose Ports Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-137
instructions that manipulate bits used ports when port designated output port?
Answer
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Yes. When port output port read CPU, contents port data register (DR) read, regardless state. When input port read, state read. This means there problems using instructions that manipulate bits. When there pins port that have been designated input ports, however, values input ports will become undefined (pin state). (See figure 2.27.)
Output Input settings settings contents status contents Read Read Read values values contents after instruction BCLR executed Changes with status
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Figure 2.27 Using General-Purpose Ports
References
BSET, BCLR, BNOT, BIST instructions manipulate bits.
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Product Topic Question Common Processing Ports When Classification-H8/300H Software Registers controller Interrupts Resets Power-down mode Instructions Miscellaneous controller Watchdog timer converter ports QA300H-138
should process ports that use?
Answer
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Clear (data direction register) ports them input state pull each down with resistance about Handle input-only ports same way.
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References

Table Item Memory H8/300H Series H8/3003 H8/300H Mask (

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