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Hitachi Single-Chip Microcomputer
H8/3577 Series, H8/3567 Series
H8/3577 H8/3574 H8/3567 H8/3564 H8/3567U H8/3564U HD6433577, HD6473577 HD6433574 HD6433567, HD6473567 HD6433564-20, HD6433564-10 HD6433567U, HD6473567U HD6433564U Hardware Manual
ADE-602-200A Rev. 11/30/00 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8/3577 Series H8/3567 Series comprise single-chip microcomputers built around H8/300 equipped with on-chip supporting functions required system configuration. Versions available with PROM (ZTATTM) mask on-chip ROM. On-chip supporting functions include a16-bit free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), timers (PWM PWMX), serial communication interface (SCI), interface (IIC), converter (ADC), ports. H8/3577 Series comprises 64-pin models with above supporting functions on-chip. H8/3567 Series comprises 42-pin H8/3567 H8/3564 with fewer PWM, ADC, port channels, 64-pin H8/3567U H8/3564U with on-chip universal serial (USB) hubs function. H8S/3577 Series H8S/3567 Series enables compact, high-performance systems implemented easily. comprehensive timer functions their interconnectability (timer connection facility) make these series ideal applications such monitor systems. This manual describes hardware H8/3577 Series H8/3567 Series. Refer H8/300 Series Programming Manual detailed description instruction set. Note: ZTAT (Zero Turn-Around Time) trademark Hitachi, Ltd.
On-Chip Supporting Modules
Series Product names Universal serial (USB) 8-bit timer (PWM) 14-bit timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Timer connection Watchdog timer (WDT) Serial communication interface (SCI) interface (IIC) converter
H8/3577 Series H8/3577, H8/3574 Available
H8/3567 Series H8/3567, H8/3564, H8/3567U, H8/3564U -/Available (H8/3567U, H8/3564U) Available
Contents
Section
Overview Overview. Internal Block Diagrams. Arrangement Functions 1.3.1 Arrangement 1.3.2 List Functions 1.3.3 Functions.
Section
Overview. 2.1.1 Features 2.1.2 Address Space 2.1.3 Register Configuration Register Descriptions. 2.2.1 General Registers. 2.2.2 Control Registers. 2.2.3 Initial Register Values Data Formats. 2.3.1 Data Formats General Registers. 2.3.2 Memory Data Formats. Addressing Modes 2.4.1 Addressing Modes. 2.4.2 Effective Address Calculation. Instruction Set. 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations. 2.5.5 Manipulations 2.5.6 Branching Instructions. 2.5.7 System Control Instructions 2.5.8 Block Data Transfer Instruction Basic Operational Timing. 2.6.1 Access On-Chip Memory (RAM, ROM) 2.6.2 Access On-Chip Peripheral Modules States 2.7.1 Overview 2.7.2 Reset State 2.7.3 Program Execution State
2.7.4 Program Halt State 2.7.5 Exception-Handling State Application Notes. 2.8.1 Notes Manipulation 2.8.2 Notes EEPMOV Instruction (Cannot used H8/3577 Series H8/3567 Series)
Section
Operating Modes Overview. 3.1.1 Operating Mode Selection. 3.1.2 Register Configuration Register Descriptions. 3.2.1 Mode Control Register (MDCR). 3.2.2 System Control Register (SYSCR) 3.2.3 Serial Timer Control Register (STCR). Address Map. Exception Handling. Overview. 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Sources Vector Table Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Interrupts after Reset Interrupts. Stack Status after Exception Handling Note Stack Handling.
Section
Section
Interrupt Controller
Overview. 5.1.1 Features 5.1.2 Block Diagram. 5.1.3 Configuration 5.1.4 Register Configuration Register Descriptions. 5.2.1 System Control Register (SYSCR) 5.2.2 Enable Register (IER) 5.2.3 Sense Control Registers (ISCRH, ISCRL). 5.2.4 Status Register (ISR) Interrupt Sources. 5.3.1 External Interrupts.
5.3.2 Internal Interrupts 5.3.3 Interrupt Exception Vector Table. Interrupt Operation 5.4.1 Interrupt Operation 5.4.2 Interrupt Control Mode 5.4.3 Interrupt Exception Handling Sequence 5.4.4 Interrupt Response Times. Usage Notes 5.5.1 Contention between Interrupt Generation Disabling. 5.5.2 Instructions that Disable Interrupts 5.5.3 Interrupts during Execution EEPMOV Instruction.
Section
Controller. Overview. Register Descriptions. 6.2.1 Control Register (BCR) 6.2.2 Wait State Control Register (WSCR). Universal Serial Interface (USB)
Section
Overview. 7.1.1 Features 7.1.2 Block Diagram. 7.1.3 Configuration 7.1.4 Register Configuration Register Descriptions. 7.2.1 Data FIFO. 7.2.2 Endpoint Size Register (EPSZR1) 7.2.3 Endpoint Data Registers (EPDR0I, EPDR0O, EPDR1, EPDR2) 7.2.4 FIFO Valid Size Registers (FVSR0I, FVSR0O, FVSR1, FVSR2) 7.2.5 Endpoint Direction Register (EPDIR). 7.2.6 Packet Transmit Enable Register (PTTER). 7.2.7 Interrupt Enable Register (USBIER) 7.2.8 Interrupt Flag Register (USBIFR) 7.2.9 Transfer Success Flag Register (TSFR) 7.2.10 Transfer Fail Flag Register (TFFR). 7.2.11 Control/Status Register (USBCSR0). 7.2.12 Endpoint Stall Register (EPSTLR) 7.2.13 Endpoint Reset Register (EPRSTR). 7.2.14 Device Resume Register (DEVRSMR). 7.2.15 Interrupt Source Select Register (INTSELR0). 7.2.16 Interrupt Source Select Register (INTSELR1). 7.2.17 Overcurrent Control Register (HOCCR). 7.2.18 Control Register (USBCR).
7.2.19 Control Register (UPLLCR). 7.2.20 Port Control Register (UPRTCR). 7.2.21 Test Registers (UTESTR2, UTESTR1, UTESTR0) 7.2.22 Module Stop Control Register (MSTPCR) 7.2.23 Serial Timer Control Register (STCR). Operation 7.3.1 Compound Device Configuration. 7.3.2 Functions Block. 7.3.3 Functions Function. 7.3.4 Operation when SETUP Token Received (Endpoint 7.3.5 Operation when Token Received (Endpoints 7.3.6 Operation when Token Received (Endpoints 7.3.7 Suspend/Resume Operations. 7.3.8 Module Reset Operation-Halted States 7.3.9 Module Startup Sequence. 7.3.10 Module Slave Interrupts.
Section
Ports Overview. Port 8.2.1 Overview 8.2.2 Register Configuration 8.2.3 Functions. 8.2.4 Input Pull-Up Function Port [H8/3577 Series Only] 8.3.1 Overview 8.3.2 Register Configuration 8.3.3 Functions. 8.3.4 Input Pull-Up Function Port [H8/3577 Series Only] 8.4.1 Overview 8.4.2 Register Configuration 8.4.3 Functions. 8.4.4 Input Pull-Up Function Port 8.5.1 Overview 8.5.2 Register Configuration 8.5.3 Functions. Port 8.6.1 Overview 8.6.2 Register Configuration 8.6.3 Functions. Port
8.7.1 Overview 8.7.2 Register Configuration 8.7.3 Functions. Port 8.8.1 Overview 8.8.2 Register Configuration 8.8.3 Functions. Port [H8/3567 Series Version with On-Chip Only]. 8.9.1 Overview 8.9.2 Register Configuration 8.9.3 Functions. 8.10 Port [H8/3567 Series Version with On-Chip Only]. 8.10.1 Overview 8.10.2 Register Configuration 8.10.3 Functions.
Section
8-Bit Timers Overview. 9.1.1 Features 9.1.2 Block Diagram. 9.1.3 Configuration 9.1.4 Register Configuration Register Descriptions. 9.2.1 Register Select (PWSL) 9.2.2 Data Registers (PWDR0 PWDR15) 9.2.3 Data Polarity Registers (PWDPRA PWDPRB). 9.2.4 Output Enable Registers (PWOERA PWOERB) 9.2.5 Peripheral Clock Select Register (PCSR) 9.2.6 Port Data Direction Register (P1DDR) 9.2.7 Port Data Direction Register (P2DDR) 9.2.8 Port Data Register (P1DR) 9.2.9 Port Data Register (P2DR) 9.2.10 Module Stop Control Register (MSTPCR) Operation 9.3.1 Correspondence between Data Register Contents Output Waveform.
Section 14-Bit Timer
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Configuration 10.1.4 Register Configuration
10.2 Register Descriptions. 10.2.1 Counter (DACNT) 10.2.2 Data Registers (DADRA DADRB). 10.2.3 Control Register (DACR) 10.2.4 Module Stop Control Register (MSTPCR) 10.3 Master Interface. 10.4 Operation
Section 16-Bit Free-Running Timer
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Input Output Pins. 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Free-Running Counter (FRC). 11.2.2 Output Compare Registers (OCRA, OCRB) 11.2.3 Input Capture Registers (ICRA ICRD) 11.2.4 Output Compare Registers (OCRAR, OCRAF) 11.2.5 Output Compare Register (OCRDM) 11.2.6 Timer Interrupt Enable Register (TIER) 11.2.7 Timer Control/Status Register (TCSR) 11.2.8 Timer Control Register (TCR) 11.2.9 Timer Output Compare Control Register (TOCR) 11.2.10 Module Stop Control Register (MSTPCR) 11.3 Operation 11.3.1 Increment Timing 11.3.2 Output Compare Output Timing 11.3.3 Clear Timing. 11.3.4 Input Capture Input Timing. 11.3.5 Timing Input Capture Flag (ICFA ICFD) Setting 11.3.6 Setting Output Compare Flags (OCFA, OCFB). 11.3.7 Setting Overflow Flag (OVF). 11.3.8 Automatic Addition OCRA OCRAR/OCRAF. 11.3.9 ICRD OCRDM Mask Signal Generation 11.4 Interrupts. 11.5 Sample Application 11.6 Usage Notes
Section 8-Bit Timers
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram.
12.2
12.3
12.4 12.5 12.6
12.1.3 Configuration 12.1.4 Register Configuration Register Descriptions. 12.2.1 Timer Counter (TCNT) 12.2.2 Time Constant Register (TCORA) 12.2.3 Time Constant Register (TCORB) 12.2.4 Timer Control Register (TCR) 12.2.5 Timer Control/Status Register (TCSR) 12.2.6 Serial/Timer Control Register (STCR) 12.2.7 System Control Register (SYSCR) 12.2.8 Timer Connection Register (TCONRS). 12.2.9 Input Capture Register (TICR) [TMRX Additional Function] 12.2.10 Time Constant Register (TCORC) [TMRX Additional Function]. 12.2.11 Input Capture Registers (TICRR, TICRF) [TMRX Additional Functions] 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]. 12.2.13 Module Stop Control Register (MSTPCR) Operation 12.3.1 TCNT Incrementation Timing. 12.3.2 Compare-Match Timing 12.3.3 TCNT External Reset Timing 12.3.4 Timing Overflow Flag (OVF) Setting. 12.3.5 Operation with Cascaded Connection Interrupt Sources. 8-Bit Timer Application Example Usage Notes 12.6.1 Contention between TCNT Write Clear. 12.6.2 Contention between TCNT Write Increment 12.6.3 Contention between TCOR Write Compare-Match 12.6.4 Contention between Compare-Matches 12.6.5 Switching Internal Clocks TCNT Operation.
Section Timer Connection
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Input Output Pins. 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Timer Connection Register (TCONRI). 13.2.2 Timer Connection Register (TCONRO) 13.2.3 Timer Connection Register (TCONRS). 13.2.4 Edge Sense Register (SEDGR)
13.2.5 Module Stop Control Register (MSTPCR) 13.3 Operation 13.3.1 Decoding (PDC Signal Generation) 13.3.2 Clamp Waveform Generation (CL1/CL2/CL Signal Generation). 13.3.3 Measurement 8-Bit Timer Divided Waveform Period 13.3.4 Signal Modification 13.3.5 Signal Fall Modification Synchronization. 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 13.3.7 HSYNCO Output. 13.3.8 VSYNCO Output. 13.3.9 CBLANK Output.
Section Watchdog Timer (WDT)
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Register Configuration 14.2 Register Descriptions. 14.2.1 Timer Counter (TCNT) 14.2.2 Timer Control/Status Register (TCSR0) 14.2.3 System Control Register (SYSCR) 14.2.4 Notes Register Access 14.3 Operation 14.3.1 Watchdog Timer Operation. 14.3.2 Interval Timer Operation. 14.3.3 Timing Setting Overflow Flag (OVF) 14.4 Interrupts. 14.5 Usage Notes 14.5.1 Contention between Timer Counter (TCNT) Write Increment 14.5.2 Changing Value CKS2 CKS0. 14.5.3 Switching between Watchdog Timer Mode Interval Timer Mode.
Section Serial Communication Interface (SCI)
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Receive Shift Register (RSR). 15.2.2 Receive Data Register (RDR) 15.2.3 Transmit Shift Register (TSR). 15.2.4 Transmit Data Register (TDR)
viii
15.2.5 Serial Mode Register (SMR). 15.2.6 Serial Control Register (SCR). 15.2.7 Serial Status Register (SSR). 15.2.8 Rate Register (BRR). 15.2.9 Serial Interface Mode Register (SCMR) 15.2.10 Module Stop Control Register (MSTPCR) 15.3 Operation 15.3.1 Overview 15.3.2 Operation Asynchronous Mode. 15.3.3 Multiprocessor Communication Function. 15.3.4 Operation Synchronous Mode. 15.4 Interrupts 15.5 Usage Notes
Section Interface (IIC)
16.1 Overview. 16.1.1 Features 16.1.2 Block Diagram. 16.1.3 Input/Output Pins. 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Data Register (ICDR). 16.2.2 Slave Address Register (SAR) 16.2.3 Second Slave Address Register (SARX). 16.2.4 Mode Register (ICMR) 16.2.5 Control Register (ICCR) 16.2.6 Status Register (ICSR). 16.2.7 Serial/Timer Control Register (STCR) 16.2.8 Switch Register (DDCSWR) 16.2.9 Module Stop Control Register (MSTPCR) 16.3 Operation 16.3.1 Data Format. 16.3.2 Master Transmit Operation 16.3.3 Master Receive Operation 16.3.4 Slave Receive Operation 16.3.5 Slave Transmit Operation. 16.3.6 IRIC Setting Timing Control 16.3.7 Automatic Switching from Formatless Mode Format. 16.3.8 Noise Canceler. 16.3.9 Sample Flowcharts 16.3.10 Initialization Internal State. 16.4 Usage Notes
Section Converter
17.1 Overview. 17.1.1 Features 17.1.2 Block Diagram. 17.1.3 Configuration 17.1.4 Register Configuration 17.2 Register Descriptions. 17.2.1 Data Registers (ADDRA ADDRD). 17.2.2 Control/Status Register (ADCSR). 17.2.3 Control Register (ADCR). 17.2.4 Module Stop Control Register (MSTPCR) 17.3 Interface Master. 17.4 Operation 17.4.1 Single Mode (SCAN 17.4.2 Scan Mode (SCAN 17.4.3 Input Sampling Conversion Time. 17.4.4 External Trigger Input Timing 17.5 Interrupts. 17.6 Usage Notes
Section
18.1 Overview. 18.1.1 Block Diagram. 18.1.2 Register Configuration 18.2 System Control Register (SYSCR). 18.3 Operation
Section
19.1 Overview. 19.2 Operation 19.3 Writer Mode (H8/3577, H8/3567, H8/3567U). 19.3.1 Writer Mode Setup 19.3.2 Socket Adapter Assignments Memory 19.4 PROM Programming 19.4.1 Programming Verification 19.4.2 Notes Programming. 19.4.3 Reliability Programmed Data
Section Clock Pulse Generator
20.1 Overview. 20.1.1 Block Diagram. 20.1.2 Register Configuration 20.2 Register Descriptions.
20.2.1 Standby Control Register (SBYCR) 20.3 Oscillator. 20.3.1 Connecting Crystal Resonator 20.3.2 External Clock Input 20.4 Duty Adjustment Circuit. 20.5 Medium-Speed Clock Divider. 20.6 Master Clock Selection Circuit 20.7 Universal Clock Pulse Generator [H8/3567 Series Version with On-Chip USB]. 20.7.1 Block Diagram. 20.7.2 Registers
Section Power-Down State.
21.1 Overview. 21.1.1 Register Configuration 21.2 Register Descriptions. 21.2.1 Standby Control Register (SBYCR) 21.2.2 Module Stop Control Register (MSTPCR) 21.3 Medium-Speed Mode 21.4 Sleep Mode. 21.4.1 Sleep Mode. 21.4.2 Clearing Sleep Mode 21.5 Module Stop Mode 21.5.1 Module Stop Mode 21.5.2 Usage Note 21.6 Software Standby Mode 21.6.1 Software Standby Mode 21.6.2 Clearing Software Standby Mode 21.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode 21.6.4 Software Standby Mode Application Example 21.6.5 Usage Note 21.7 Hardware Standby Mode 21.7.1 Hardware Standby Mode. 21.7.2 Hardware Standby Mode Timing
Section Electrical Characteristics
22.1 Absolute Maximum Ratings. 22.2 Characteristics 22.3 Characteristics 22.3.1 Clock Timing. 22.3.2 Control Signal Timing. 22.3.3 Timing On-Chip Supporting Modules 22.4 Conversion Characteristics 22.5 Function Characteristics
22.6 Usage Notes
Appendix Instruction
Instruction List Operation Code Map. Number States Required Execution.
Appendix Internal Registers.
Addresses. Register Selection Conditions. Functions.
Appendix Port Block Diagrams
Port Block Diagrams Port Block Diagrams Port Block Diagram. Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagram. Port Block Diagrams Port Block Diagram
Appendix States.
Port States Each Mode
Appendix Timing Transition Recovery from Hardware Standby Mode
Timing Transition Hardware Standby Mode Timing Recovery from Hardware Standby Mode.
Appendix Product Code Lineup Appendix Package Dimensions
Section Overview
Overview
H8/3577 Series H8/3567 Series comprise single-chip microcomputers (MCUs) built around H8/300 equipped with on-chip supporting functions required system configuration. On-chip supporting functions required system configuration include memory, a16-bit free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), timers (PWM PWMX), serial communication interface (SCI), interface (IIC), converter (ADC), ports. H8/3577 Series comprises 64-pin MCUs, H8/3567 Series 42pin MCUs, H8/3567 Series also includes 64-pin variation with on-chip universal serial (USB) hubs function. on-chip either PROM (ZTAT) mask ROM, with capacity kbytes. There only operating mode: single-chip mode. features H8/3577 Series H8/3567 Series shown table 1.1.
Table
Item
Features
Specifications General-register architecture Sixteen 8-bit general registers (also usable eight 16-bit registers) High-speed operation suitable realtime control Maximum operating frequency: MHz/5 (HD6433564-10: MHz/5 High-speed arithmetic operations 8/16-bit register-register add/subtract: operation) 8-bit register-register multiply: operation) 8-bit register-register divide: operation) Instruction suitable high-speed operation 2-byte 4-byte instruction length Register-register basic operations Memory-register data transfer instruction Instructions with special features Multiply instructions bits bits) Divide instructions bits bits) Bit-accumulator instructions position specifiable means register indirect specification
16-bit free-running timer (FRT), channel 8-bit timer (TMR), channels (TMR0, TMR1)
16-bit free-running counter (usable external event counting) output compare outputs Four input capture inputs (with buffer operation capability)
Each channel has: 8-bit up-counter (usable external event counting) timer constant registers channels connected
Timer connection 8-bit timer (TMR), channels (TMRX, TMRY)
Input/output FRT, TMR1, TMRX, TMRY interconnected Measurement input signal frequency-divided waveform pulse width cycle (FRT, TMR1) Output waveform obtained modification input signal edge (FRT, TMR1) Determination input signal duty cycle (TMRX) Output waveform synchronized with input signal (FRT, TMRX, TMRY) Automatic generation cyclical waveform (FRT, TMRY)
Item Watchdog timer (WDT), channels 8-bit timer (PWM)
Specifications Watchdog timer interval timer function selectable Maximum (H8/3577 Series) (H8/3567 Series) outputs Pulse duty cycle settable from 100% Resolution: 1/256 1.25 maximum carrier frequency operation) Maximum outputs Resolution: 1/16384 312.5 maximum carrier frequency operation) Asynchronous mode synchronous mode selectable Multiprocessor communication function
14-bit timer (PWMX)
Serial communication interface (SCI), channel (SCI0) converter
Resolution: bits Input: channels (H8/3577 Series) channels (H8/3567 Series) High-speed conversion minimum conversion time operation) Single scan mode selectable Sample-and-hold function conversion activated external trigger timer trigger Input/output pins: (H8/3577 Series, H8/3567 Series models with onchip USB) (H8/3567 Series) Input-only pins: (H8/3577 Series) (H8/3567 Series) PROM mask High-speed static Product Code kbytes kbytes kbytes kbytes
ports
Memory
H8/3577, H8/3567, H8/3567U H8/3574, H8/3564, H8/3564U Interrupt controller
Four external interrupt pins (NMI, IRQ0 IRQ2) internal interrupt sources (H8/3567U Series: sources)
Item Power-down state
Specifications Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Built-in duty correction circuit 64-pin plastic (DP-64S) 64-pin plastic (FP-64A) 42-pin plastic (DP-42S) 44-pin plastic (FP-44A) Conforms Philips interface standard Single master mode/slave mode Arbitration lost condition identified Supports slave addresses Comprises five downstream hubs function (four sets downstream pins) Three-endpoint monitor device class function EP0: control EP1, EP2: monitor control Supports Mbps high-speed transfer mode Built-in clock pulse generator multiplication circuit Built-in driver/receiver (requires analog power supply)
Clock pulse generator Packages
interface (IIC), channels
Universal serial interface (USB) [H8/3567U, H8/3564U]
Item Product lineup
Specifications
Product Code Series H8/3577 Mask Version HD6433577 HD6433574 H8/3567 HD6433567 HD6433564-20 HD6433564-10 HD6433567U HD6433564U ZTAT Version HD6473577 HD6473567 HD6473567U ROM/RAM (Bytes) DP-42S DP-64S, FP-64A DP-42S, FP-44A Packages DP-64S, FP-64A
Port
Internal data
VCL,
EXTAL XTAL STBY Clock pulse generator
Internal address
H8/300 controller Port
Internal Block Diagrams
Interrupt controller Port WDT0 8-bit Port 16-bit 8-bit timer channels Timer connection (TMR0, TMR1, TMRX, TMRY) Port 14-bit channel channels
SDA0/P47 IRQ0/P42 IRQ1/P41 ADTRG/ IRQ2/P40
P27/ PW15/ CBLANK P26/ PW14 P25/ PW13 P24/ PW12/ SCL1 P23/ PW11/ SDA1 P22/ PW10 P21/ P20/
Peripheral address Peripheral data
Port
HSYNCO/TMO1/ TMOX/P67 CSYNCI/TMRI1/ FTOB/P66 HSYNCI/TMCI1/ FTID/P65 CLAMPO/TMO0/ FTIC/P64 VFBACKI/TMRI0/ FTIB/P63 VSYNCI/ TMIY/FTIA/ VSYNCO/FTOA/P61 HFBACKI/TMCI0/TMIX/ FTCI/P60
P17/ P16/ P15/ P14/ P13/ P12/ P11/ PW1/ PWX1 P10/ PW0/ PWX0
Port
Figures show internal block diagrams H8/3577 Series H8/3567 Series.
Figure Internal Block Diagram H8/3577 Series
10-bit converter
P52/ SCK0/ SCL0 P51/ RXD0 P50/ TXD0
AN7/P77 AN6/P76 AN5/P75 AN4/P74 AN3/P73 AN2/P72 AN1/P71 AN0/P70
AVCC AVSS
When on-chip provided When on-chip provided VCL, Port
DrVCC DrVSS EXTAL12 XTAL12
Internal data
Clock pulse generator H8/300
TEST EXTAL XTAL STBY
Internal address
USD- USD+ PD7/DS5D- PD6/DS5D+ PD5/DS4D- PD4/DS4D+ PD3/DS3D- PD2/DS3D+ PD1/DS2D- PD0/DS2D+
Port
Interrupt controller controller Port Port 16-bit 8-bit timer channels Timer connection (TMR0, TMR1, TMRX, TMRY)
PC7/OCP5 PC6/OCP4 PC5/OCP3 PC4/OCP2 PC3/ENP5 PC2/ENP4 PC1/ENP3 PC0/ENP2
Peripheral data Peripheral address
SDA0/P47 IRQ0/P42 IRQ1/P41 ADTRG/ IRQ2/P40 WDT0 8-bit
Port
HSYNCO/TMO1/ TMOX/P67 CSYNCI/TMRI1/ FTOB/P66 HSYNCI/TMCI1/ FTID/P65 CLAMPO/TMO0/ FTIC/P64 VFBACKI/TMRI0/ FTIB/P63 VSYNCI/ TMIY/FTIA/ VSYNCO/FTOA/P61 HFBACKI/TMCI0/TMIX/ FTCI/P60
14-bit
P17/ PW7/ SCL1 P16/ PW6/ SDA1 P15/ PW5/ CBLANK P14/ P13/ P12/ P11/ PW1/ PWX1 P10/ PW0/ PWX0
channel Port
Figure Internal Block Diagram H8/3567 Series
AN3/P73 AN2/P72 AN1/P71 AN0/P70 Port channels 10-bit converter
P52/ SCK0/ SCL0 P51/ RXD0 P50/ TXD0
AVCC AVSS
1.3.1
Arrangement Functions
Arrangement
arrangements H8/3577 Series shown figures 1.4, those H8/3567 Series figures 1.8.
ADTRG/IRQ2/P40 IRQ1/P41 IRQ0/P42 SDA0/P47 TxD0/P50 RxD0/P51 SCL0/SCK0/P52 VCC/VCL STBY XTAL EXTAL AVSS AN0/P70 AN1/P71 AN2/P72 AN3/P73 AN4/P74 AN5/P75 AN6/P76 AN7/P77 AVCC HFBACKI/TMIX/TMCI0/FTCI/P60 VSYNCO/FTOA/P61
P10/PW0/PWX0 P11/PW1/PWX1 P12/PW2 P13/PW3 P14/PW4 P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 P23/PW11/SDA1 P24/PW12/SCL1 P25/PW13 P26/PW14 P27/PW15/CBLANK P67/TMOX/TMO1/HSYNCO P66/FTOB/TMRI1/CSYNCI P65/FTID/TMCI1/HSYNCI P64/FTIC/TMO0/CLAMPO P63/FTIB/TMRI0/VFBACKI P62/FTIA/TMIY/VSYNCI
Figure H8/3577 Series Arrangement (DP-64S: View)
ADTRG/IRQ2/P40 IRQ1/P41 IRQ0/P42 SDA0/P47
P10/PW0/PWX0 P11/PW1/PWX1 P12/PW2 P13/PW3 P14/PW4 P15/PW5 P16/PW6 P17/PW7 P20/PW8 P21/PW9 P22/PW10 P23/PW11/SDA1 P24/PW12/SCL1 P25/PW13 P26/PW14
P27/PW15/CBLANK P67/TMOX/TMO1/HSYNCO P66/FTOB/TMRI1/CSYNCI P65/FTID/TMCI1/HSYNCI P64/FTIC/TMO0/CLAMPO P63/FTIB/TMRI0/VFBACKI P62/FTIA/TMIY/VSYNCI P61/FTOA/VSYNCO P60/FTCI/TMCI0/TMIX/HFBACKI AVCC P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3
Figure H8/3577 Series Arrangement (FP-64A: View)
TxD0/P50 RxD0/P51 SCL0/SCK0/P52 VCC/VCL STBY XTAL EXTAL AVSS AN0/P70 AN1/P71 AN2/P72
ADTRG/IRQ2/P40 IRQ1/P41 IRQ0/P42 SDA0/P47 SCL0/SCK0/P52 VCC/VCL STBY XTAL EXTAL TEST VSS/AVSS AN0/P70 AN1/P71 AN2/P72 AN3/P73 AVCC HFBACKI/TMIX/TMCI0/FTCI/P60
P51/RxD0 P50/TxD0 P10/PW0/PWX0 P11/PW1/PWX1 P12/PW2 P13/PW3 P14/PW4 P15/PW5/CBLANK P16/PW6/SDA1 P17/PW7/SCL1 P61/FTOA/VSYNCO P62/FTIA/TMIY/VSYNCI P63/FTIB/TMRI0/VFBACKI P67/TMOX/TMO1/HSYNCO P66/FTOB/TMRI1/CSYNCI P65/FTID/TMCI1/HSYNCI P64/FTIC/TMO0/CLAMPO
Figure H8/3567 Series Arrangement USB; DP-42S: View)
P10/PW0/PWX0 P11/PW1/PWX1 P12/PW2 P13/PW3 P14/PW4 P15/PW5/CBLANK P16/PW6/SDA1 P17/PW7/SCL1 P61/FTOA/VSYNCO P62/FTIA/TMIY/VSYNCI
TxD0/P50 RxD0/P51 ADTRG/IRQ2/P40 IRQ1/P41 IRQ0/P42 SDA0/P47
P63/FTIB/TMRI0/VFBACKI P67/TMOX/TMO1/HSYNCO P66/FTOB/TMRI1/CSYNCI P65/FTID/TMCI1/HSYNCI P64/FTIC/TMO0/CLAMPO P60/FTCI/TMCI0/TMIX/HFBACKI AVCC P73/AN3 P72/AN2 P71/AN1
Figure H8/3567 Series Arrangement USB; FP-44A: View)
SCL0/SCK0/P52 VCC/VCL STBY XTAL EXTAL TEST VSS/AVSS AN0/P70
ADTRG/IRQ2/P40 IRQ1/P41 IRQ0/P42 SDA0/P47 SCL0/SCK0/P52 VCL/VCC STBY XTAL EXTAL TEST VSS/AVSS AN0/P70 AN1/P71 AN2/P72 AN3/P73 AVCC DrVCC USD+ USDPD0/DS2D+ PD1/DS2DPD2/DS3D+ PD3/DS3DPD4/DS4D+ PD5/DS4DPD6/DS5D+ PD7/DS5DDrVSS
P51/RxD0 P50/TxD0 P10/PW0/PWX0 P11/PW1/PWX1 P12/PW2 P13/PW3 P14/PW4 P15/PW5/CBLANK P16/PW6/SDA1 P17/PW7/SCL1 P61/FTOA/VSYNCO P62/FTIA/TMIY/VSYNCI P63/FTIB/TMRI0/VFBACKI P67/TMOX/TMO1/HSYNCO P66/FTOB/TMRI1/CSYNCI P65/FTID/TMCI1/HSYNCI P64/FTIC/TMO0/CLAMPO P60/FTCI/TMCI0/TMIX/HFBACKI EXTAL12 XTAL12 PC7/OCP5 PC6/OCP4 PC5/OCP3 PC4/OCP2 PC3/ENP5 PC2/ENP4 PC1/ENP3 PC0/ENP2
Figure H8/3567 Series Arrangement (USB On-Chip; DP-64S: View)
PW2/P12 PWX1/PW1/P11 PWX0/PW0/P10 TxD0/P50 RxD0/P51 ADTRG/IRQ2/P40 IRQ1/P41 IRQ0/P42 SDA0/P47 SCL0/SCK0/P52
P13/PW3 P14/PW4 P15/PW5/CBLANK P16/PW6/SDA1 P17/PW7/SCL1 P61/FTOA/VSYNCO P62/FTIA/TMIY/VSYNCI P63/FTIB/TMRI0/VFBACKI P67/TMOX/TMO1/HSYNCO P66/FTOB/TMRI1/CSYNCI P65/FTID/TMCI1/HSYNCI P64/FTIC/TMO0/CLAMPO P60/FTCI/TMCI0/TMIX/HFBACKI EXTAL12 XTAL12
PC7/OCP5 PC6/OCP4 PC5/OCP3 PC4/OCP2 PC3/ENP5 PC2/ENP4 PC1/ENP3 PC0/ENP2 DrVSS DS5D-/PD7 DS5D+/PD6 DS4D-/PD5 DS4D+/PD4 DS3D-/PD3 DS3D+/PD2 DS2D-/PD1
Figure H8/3567 Series Arrangement (USB On-Chip; FP-64A: View)
VCL/VCC STBY XTAL EXTAL TEST VSS/AVSS AN0/P70 AN1/P71 AN2/P72 AN3/P73 AVCC DrVCC USD+ USD- PD0/DS2D+
1.3.2
List Functions
H8/3577 Series functions listed table 1.2, H8/3567 Series functions tables 1.4. Table List H8/3577 Series Functions
Name Single-Chip Mode P40/IRQ2/ADTRG P41/IRQ1 P42/IRQ0 P47/SDA0 P50/TxD0 P51/RxD0 P52/SCK0/SCL0 VCL, (ZTAT) STBY XTAL EXTAL AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 PROM Writer Mode EA16 EA15
DP-64S FP-64A
DP-64S FP-64A Single-Chip Mode P75/AN5 P76/AN6 P77/AN7 AVCC
Name PROM Writer Mode EA14 EA13 EA12 EA11 EA10
P60/FTCI/TMCI0/HFBACKI/TMIX P61/FTOA/VSYNCO P62/FTIA/VSYNCI/TMIY P63/FTIB/TMRI0/VFBACKI P64/FTIC/TMO0/CLAMPO P65/FTID/TMCI1/HSYNCI P66/FTOB/TMRI1/CSYNCI P67/TMO1/TMOX/HSYNCO P27/PW15 /CBLANK P26/PW14 P25/PW13 P24/PW12 /SCL1 P23/PW11 /SDA1 P22/PW10 P21/PW9 P20/PW8 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1/PWX1 P10/PW0/PWX0
DP-64S FP-64A Single-Chip Mode
Name PROM Writer Mode
Table
List H8/3567 Series Functions USB)
Name Single-Chip Mode P40/IRQ2/ADTRG P41/IRQ1 P42/IRQ0 P47/SDA0 P52/SCK0/SCL0 VCL, (ZTAT) STBY XTAL EXTAL TEST AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 AVCC P60/FTCI/TMCI0/HFBACKI/TMIX P64/FTIC/TMO0/CLAMPO P65/FTID/TMCI1/HSYNCI P66/FTOB/TMRI1/CSYNCI P67/TMO1/TMOX/HSYNCO P63/FTIB/TMRI0/VFBACKI P62/FTIA/VSYNCI/TMIY P61/FTOA/VSYNCO P17/PW7/SCL1 PROM Writer Mode EA16 EA11 EA12 EA13 EA14 EA15
DP-42S FP-44A
DP-42S FP-44A Single-Chip Mode P16/PW6/SDA1 P15/PW5/CBLANK P14/PW4 P13/PW3 P12/PW2 P11/PW1/PWX1 P10/PW0/PWX0 P50/TxD0 P51/RxD0
Name PROM Writer Mode EA10
Table
List H8/3567 Series Functions (USB On-Chip)
Name Single-Chip Mode P40/IRQ2/ADTRG P41/IRQ1 P42/IRQ0 P47/SDA0 P52/SCK0/SCL0 VCL, (ZTAT) STBY XTAL EXTAL TEST AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 AVCC DrVCC USD+ USD- 0/DS2D+ 1/DS2D- 2/DS3D+ 3/DS3D- 4/DS4D+ 5/DS4D- 6/DS5D+ PROM Writer Mode EA16 EA11 EA12 EA13 EA14 EA15
DP-64S FP-64A
DP-64S FP-64A Single-Chip Mode 7/DS5D- DrVSS 0/ENP 1/ENP 2/ENP 3/ENP 4/OCP 5/OCP 6/OCP 7/OCP XTAL12 EXTAL12
Name PROM Writer Mode
P60/FTCI/TMCI0/HFBACKI/TMIX P64/FTIC/TMO0/CLAMPO P65/FTID/TMCI1/HSYNCI P66/FTOB/TMRI1/CSYNCI P67/TMO1/TMOX/HSYNCO P63/FTIB/TMRI0/VFBACKI P62/FTIA/VSYNCI/TMIY P61/FTOA/VSYNCO P17/PW7/SCL1 P16/PW6/SDA1 P15/PW5/CBLANK P14/PW4 P13/PW3 P12/PW2 P11/PW1/PWX1 P10/PW0/PWX0 P50/TxD0
DP-64S FP-64A Single-Chip Mode P51/RxD0
Name PROM Writer Mode EA10
1.3.3
Functions
Table summarizes functions H8/3577 Series H8/3567 Series pins. Table Functions
H8/3577 Series Type Power Symbol VCL/VCC DP64S FP64A H8/3567 Series USB) DP42S FP44A H8/3567 Series (USB On-Chip) DP64S FP64A Input Input Name Function Power: connection power supply Internal step-up power: connection external capacitor. ZTAT
version, connect this power supply
Input Ground: connection power supply Connect pins system power supply connection crystal resonator external clock input. connection examples, section Clock Pulse Generator. System clock: Supplies system clock external devices. Mode pins: These pins operating mode. Connect three pins- MD1, MD0, TEST-to power supply
Clock
XTAL
Input
EXTAL
Input
Output
Operating mode control
Input
TEST System control
Input Reset input: When this driven low, chip goes reset state. Standby: When this driven low, transition made hardware standby mode.
STBY
Input
H8/3577 Series Type Interrupts Symbol DP64S FP64A H8/3567 Series USB) DP42S FP44A H8/3567 Series (USB On-Chip) DP64S FP64A Input Name Function Nonmaskable interrupt: Requests nonmaskable interrupt. Interrupt request These pins request maskable interrupt. counter clock input: that inputs external clock signal free-running counter (FRC). output compare output: output compare output pin. output compare output: output compare output pin. input capture input: input capture input pin. input capture input: input capture input pin. input capture input: input capture input pin. input capture input: input capture input pin. Compare-match output: Compare-match output pins TMR0, TMR1, TMRX. Counter external clock input: Pins that input external clock TMR0 TMR1 counters. Counter external reset input: TMR0 TMR1 counter reset input pins.
IRQ0 IRQ2 16-bit freeFTCI running timer (FRT) FTOA
Input Input
Output
FTOB
Output
FTIA FTIB FTIC FTID 8-bit timer TMO0 (TMR0, TMR1, TMRX, TMOX TMRY) TMCI TMCI
Input Input Input Input Output
Input
TMRI TMRI
Input
H8/3577 Series Type 8-bit timer (TMR0, TMR1, TMRX, TMRY) Serial communication interface (SCI0) Symbol TMIX TMIY DP64S FP64A H8/3567 Series USB) DP42S FP44A H8/3567 Series (USB On-Chip) DP64S FP64A Input Name Function Counter external clock input/reset input: Pins with dual function TMRX TMRY counter clock input reset input. Transmit data: Data output pins. Receive data: Data input pins. Serial clock: Clock input/output pins. output type NMOS push-pull. converter ADTRG Input Analog Analog input pins.
SCK0
Output Input Input/ output
Input Input conversion external trigger input: input external trigger start conversion. Analog power: converter reference power supply pin. When converter used, connect this system power supply
Input
Input
Analog ground: converter ground pin. Connect this system power supply timer output: timer pulse output pins.
timer (PWM)
PW15
Output
H8/3577 Series Type 14-bit timer (PWMX) Timer connection Symbol PWX0 PWX1 VSYNCI HSYNCI CSYNCI VFBACKI HFBACKI VSYNCO HSYNCO CLAMPO CBLANK interface (IIC)
H8/3567 Series USB) DP42S FP44A
H8/3567 Series (USB On-Chip) DP64S FP64A Input/ Output clock input/output (channels clock input/output pins. These pins have drive function. output type NMOS open-drain. Output Timer connection output: Timer connection synchronization signal output pins. Input Output Name Function PWMX timer output: pulse output pins. Timer connection input: Timer connection synchronization signal input pins.
DP64S
FP64A
SDA0 SDA1
Input/ Output
data input/output (channels data input/output pins. These pins have drive function. output type NMOS open-drain.
Universal serial (USB)
USD+ USD- DS2D+ DS2D- DS3D+ DS3D- DS4D+ DS4D- DS5D+ DS5D-
Input/ Output Input/ Output
Upstream data input/output: upstream data input/ output pins. Upstream data input/output downstream data input/output pins.
H8/3577 Series Type Universal serial (USB) Symbol ENP2 ENP5 DP64S FP64A H8/3567 Series USB) DP42S FP44A H8/3567 Series (USB On-Chip) DP64S FP64A Name Function Power supply control power output enable signal output: Output pins port power supply control enable input Overcurrent detection signal input: Input pins overcurrent detection signal from port power supply control clock input: connection crystal resonator external clock input. Quadrupled inside chip. driver power: connection driver/receiver power supply (3.3 driver ground: connection driver/receiver power supply Port Eight input/output pins. direction each selected port data direction register (P1DDR). Port Eight input/output pins. direction each selected port data direction register (P2DDR). Port Eight input/output pins. direction each selected port data direction register (P3DDR). Port Eight input/output pins. direction each (except P46) selected port data direction register (P4DDR). NMOS push-pull output.
Output
OCP2 OCP5
Input
XTAL12
Input
EXTAL12 DrVCC
Input Input
DrVSS
Input
ports
Input/ Output Input/ Output
Input/ Output
Input/ Output
H8/3577 Series Type ports Symbol DP64S FP64A H8/3567 Series USB) DP42S FP44A H8/3567 Series (USB On-Chip) DP64S FP64A Input/ Output Name Function Port Three input/output pins. direction each selected port data direction register (P5DDR). NMOS push-pull output. Port Eight input/output pins. direction each selected port data direction register (P6DDR).
Input/ Output Input
Port Eight (H8/3577 Series) four (H8/3567 Series) input pins.
Input/ Output Port Eight input/output pins. direction each selected port data direction register (PCDDR). Port Eight input/output pins. direction each selected port data direction register (PDDDR). These pins driven (3.3
Input/ Output
Section
Overview
H8/300L sixteen 8-bit general registers, which also paired eight 16-bit registers. concise instruction designed high-speed operation. 2.1.1 Features
Features H8/300L listed below. General-register architecture Sixteen 8-bit general registers, also usable eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment pre-decrement (@Rn+/@-Rn) Absolute address (@aa:8/@aa:16) Immediate (#xx:8/#xx:16) Program-counter relative (@(d:8, PC)) Memory indirect (@@aa:8) 64-kbyte address space High-speed operation frequently used instructions executed four states High-speed arithmetic logic operations 16-bit register-register subtract: (operating MHz) 8-bit multiply: (operating MHz) 8-bit divide: (operating MHz) Low-power operation modes SLEEP instruction transfer low-power operation
2.1.2
Address Space
H8/300L supports address space kbytes storing program code data. section 3.3, Address Map, details memory map. 2.1.3 Register Configuration
Figure shows register structure H8/300L CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack pointer
Control registers (CR) UHUNZ Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used data registers, they accessed 16-bit registers R7), high bytes (R0H R7H) bytes (R0L R7L) accessed separately 8-bit registers. When used address registers, general registers accessed 16-bit registers R7). also functions stack pointer (SP), used implicitly hardware exception processing subroutine calls. When functions stack pointer, indicated figure 2.2, (R7) points stack.
Lower address side [H'0000] Unused area (R7) Stack area
Upper address side [H'FFFF]
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. instructions fetched bits word) time, least significant ignored (always regarded
Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. These bits read written software (using LDC, STC, ANDC, ORC, XORC instructions). flags used branching conditions conditional branching (Bcc) instructions. 7-Interrupt Mask (I): When this interrupts masked. This automatically start exception handling. interrupt mask read written software. further details, section Interrupt Controller. 6-User (U): used freely user. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. flag used implicitly instructions. When ADD.W, SUB.W, CMP.W instruction executed, flag there carry borrow cleared otherwise. 4-User (U): used freely user. 3-Negative Flag (N): Indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): indicate zero result, cleared indicate non-zero result. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift/rotate carry carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. Refer H8/300L Series Programming Manual action each instruction flag bits.
2.2.3
Initial Register Values
reset exception handling, program counter (PC) initialized vector address (H'0000) load, other bits general registers initialized. particular, stack pointer (R7) initialized. stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300L process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. 1-bit data handled manipulation instructions, accessed being specified operand data (byte). Byte data handled arithmetic logic instructions except ADDS SUBS. Word data handled MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions. With decimal adjustment instructions, byte data handled 4-bit data units.
2.3.1
Data Formats General Registers
Data sizes above stored general registers shown figure 2.3.
Data Type Register
Data Format
1-bit data
don't care
1-bit data
don't care
Byte data
don't care
Byte data
don't care
Word data
Upper digit
Lower digit
4-bit data
don't care
Upper digit
Lower digit
4-bit data
don't care
Legend: RnH: Upper byte general register RnL: Lower byte general register MSB: Most significant LSB: Least significant
Figure General Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. access H8/300L CPU, word data stored memory must always begin even address. When word data beginning address accessed, least significant regarded word data beginning preceding address accessed. same applies instruction codes.
Data Type Address Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
CCR: Condition code register Note: Ignored return
Figure Memory Data Formats When stack accessed using address register, word access should always performed. stored word data with same value upper bits lower bits. return, lower bits ignored.
2.4.1
Addressing Modes
Addressing Modes
H8/300L supports eight addressing modes listed table 2.1. Each instruction uses subset these addressing modes. Table
Addressing Modes
Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register Indirect-@Rn: register field instruction specifies 16-bit general register containing address operand memory. Register Indirect with Displacement-@(d:16, Rn): instruction second word (bytes containing displacement which added contents specified general register obtain operand address memory. This mode used only instructions. MOV.W instruction, resulting address must even.
Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with post-increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. register field instruction specifies 16-bit general register containing address operand. After operand accessed, register incremented MOV.B MOV.W, result addition stored register. MOV.W, original contents 16-bit general register must even. Register indirect with pre-decrement-@-Rn @-Rn mode used with instructions that store register contents memory. register field instruction specifies 16-bit general register which decremented obtain address operand memory. register retains decremented value. size decrement MOV.B MOV.W. MOV.W, original contents register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. absolute address bits long (@aa:8) bits long (@aa:16). MOV.B manipulation instructions 8-bit absolute addresses. MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. 8-bit absolute address, upper bits assumed (H'FF). address range H'FF00 H'FFFF (65280 65535). Immediate-#xx:8 #xx:16: second byte (#xx:8) third fourth bytes (#xx:16) instruction code used directly operand. Only MOV.W instructions used with #xx:16. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data second fourth byte instruction, specifying number. Program-Counter Relative-@(d:8, PC): This mode used instructions. 8-bit displacement byte instruction code sign-extended bits added program counter contents generate branch destination address, contents added start address next instruction, that possible branching range -126 +128 bytes (-63 words) from branch instruction. displacement should even number.
Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address. This specifies operand memory, branch performed with contents this operand branch address. upper bits absolute address assumed (H'00), address range from H'0000 H'00FF 255). Note that with H8/300L Series, lower address area also used vector area. section Exception Handling, details vector area. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. 2.3.2, Memory Data Formats, further information. 2.4.2 Effective Address Calculation
Table shows effective addresses calculated each addressing modes. Arithmetic logic instructions register direct addressing (1). ADD.B, ADDX, SUBX, CMP.B, AND, instructions also immediate addressing (6). Data transfer instructions addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), 8-bit absolute addressing specify byte operand, 3-bit immediate addressing specify position that byte. BSET, BCLR, BNOT, BTST instructions also register direct addressing specify position.
Table
Effective Address Calculation
Effective Address Calculation Method Effective Address (EA)
Addressing Mode Instruction Format Register direct,
Operand contents registers indicated rm/rn
Contents bits) register indicated
Register indirect,
Register indirect with displacement, @(d:16,
Contents bits) register indicated
disp
disp
Register indirect with post-increment, @Rn+
Contents bits) register indicated
Register indirect with pre-decrement, @-Rn
Contents bits) register indicated
Incremented decremented operand byte size, word size
Addressing Mode Instruction Format Absolute address @aa:8
Effective Address Calculation Method
Effective Address (EA)
H'FF
@aa:16
Immediate #xx:8
Operand 2-byte immediate data
#xx:16
Program-counter relative @(d:8,
contents
Sign extension
disp
disp
Addressing Mode Instruction Format Memory indirect, @@aa:8
Effective Address Calculation Method
Effective Address (EA)
H'00
Memory contents bits) Legend: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300L Series total instructions, which grouped function table 2.3. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer (Cannot used H8/3577 Series H8/3567 Series)
Instruction
Instructions MOV, PUSH* POP*
Number
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Total: Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, same applies machine language. conditional branch instruction.
Tables 2.11 show function each instruction. notation used defined next. Notation
(EAd), <Ead> (EAs), <Eas> #IMM disp General register (destination) General register (source) General register Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move Logical negation (logical complement) 3-bit length 8-bit length 16-bit length Contents operand indicated effective address
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, @Rn+ addressing modes available word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word-size specification. @SP+ Pops general register from stack. Equivalent MOV.W @SP+,
PUSH
@-SP Pushes general register onto stack. Equivalent MOV.W @-SP.
Notes: Size: Operand size Byte Word
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, @-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
Legend: Operation field Register field disp: Displacement abs: Absolute address IMM: Immediate data
PUSH, @SP+ @-SP
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. Table
Instruction
Arithmetic Instructions
Size* Function #IMM Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #IMM Performs addition subtraction with carry data general registers, addition subtraction with carry immediate data data general register. Increments decrements general register Adds subtracts from general register decimal adjust Decimal-adjusts (adjusts packed BCD) addition subtraction result general register referring Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder
#IMM Compares data general register with data another general register with immediate data, indicates result CCR. Word data compared only between general registers.
Obtains two's complement (arithmetic complement) data general register
Notes: Size: Operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. Table
Instruction
Logic Operation Instructions
Size* Function #IMM Performs logical operation general register another general register immediate data
#IMM Performs logical operation general register another general register immediate data
#IMM Performs logical exclusive operation general register another general register immediate data
Obtains one's complement (logical complement) general register contents
Notes: Size: Operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Notes: Size: Operand size Byte
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents shift Performs logical shift operation general register contents rotate Rotates general register contents rotate Rotates general register contents through (carry)
Figure shows instruction code format arithmetic, logic, shift instructions.
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#XX:8)
AND, (Rm)
AND, (#xx:8)
Legend: Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory number specified 3-bit immediate data lower three bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory number specified 3-bit immediate data lower three bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory. number specified 3-bit immediate data lower three bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
BAND
(<bit-No.> <EAd>) ANDs flag with specified general register memory, stores result flag.
BIAND
(<bit-No.> <EAd>)] ANDs flag with inverse specified general register memory, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) flag with specified general register memory, stores result flag.
BIOR
(<bit-No.> <EAd>)] flag with inverse specified general register memory, stores result flag. number specified 3-bit immediate data.
Notes: Size: Operand size Byte
Instruction BXOR
Size*
Function (<bit-No.> <EAd>) XORs flag with specified general register memory, stores result flag.
BIXOR
[~(<bit-No.> <EAd>)] XORs flag with inverse specified general register memory, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies specified general register memory flag. (<bit-No.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies flag specified general register memory. (<bit-No.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BILD
BIST
Notes: Size: Operand size Byte
Certain precautions required manipulation. 2.8.2, Notes Manipulation, details.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: register indirect (@Rn) No.:
register direct (Rm)
Operand: absolute (@aa:8) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Legend: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Legend: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches designated address condition true. branching conditions given below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table 2.10 describes system control instructions. Figure shows their object code formats. Table 2.10 System Control Instructions
Instruction SLEEP Size* Function Returns from exception-handling routine Causes transition from active mode power-down mode. section Power-Down State, details. CCR, #IMM Moves immediate data general register contents condition code register Copies condition code register specified general register ANDC #IMM Logically ANDs condition code register with immediate data #IMM Logically condition code register with immediate data XORC #IMM Logically exclusive-ORs condition code register with immediate data Only increments program counter Notes: Size: Operand size Byte
RTE, SLEEP,
LDC, (Rn)
ANDC, ORC, XORC, (#xx:8)
Legend: Operation field Register field IMM: Immediate data
Figure System Control Instruction Codes 2.5.8 Block Data Transfer Instruction
Table 2.11 describes block data transfer instruction. Figure 2.10 shows object code format. Table 2.11 Block Data Transfer Instruction
Instruction EEPMOV (Cannot used H8/3577 Series H8/3567 Series) Size Function then repeat @R5+ @R6+ until else next; Block transfer instruction. Transfers number data bytes specified from locations starting address indicated locations starting address indicated After transfer, next instruction executed.
Certain precautions required using EEPMOV instruction. 2.8.2, Notes EEPMOV Instruction, details.
Legend: Operation field
Figure 2.10 Block Data Transfer Instruction Code
Basic Operational Timing
operation synchronized system clock period from rising edge next rising edge called state. cycle consists states three states. cycle differs depending whether access on-chip memory on-chip peripheral modules. 2.6.1 Access On-Chip Memory (RAM, ROM)
Access on-chip memory takes place states. data width bits, allowing access byte word size. Figure 2.11 shows on-chip memory access cycle.
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
2.6.2
Access On-Chip Peripheral Modules
On-chip peripheral modules accessed three states. data width either bits, access both byte word size supported. There categories on-chip peripheral modules: 8-bit 16-bit. access word data from 8-bit module, instructions must used. upper byte accessed first, followed lower byte. Accessing word data from 16-bit module requires only instruction. There types registers: byte word. word register refers registers were, with 16-bit counter, attempting access bytes separately will cause problems. word registers containing 8-bit modules, circuit with temporary register available allow normal access upper byte first, followed lower byte. Note that word registers containing only 16-bit modules have such circuit. Therefore, only word access used with such registers. Figure 2.12 shows access timing on-chip peripheral modules.
cycle state state state
Internal address
Address
Internal read signal
Internal data (read access)
Read data
Internal write signal
Internal data (write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle
2.7.1
States
Overview
There four states: reset state, program execution state, program halt state, exception-handling state. program execution state includes active (high-speed mediumspeed) mode. program halt state there sleep (high-speed medium-speed) mode standby mode. These states shown figure 2.13. Figure 2.14 shows state transitions.
state
Reset state initialized Program execution state
Active (high speed) mode executes successive program instructions high speed, synchronized system clock Active (medium speed) mode executes successive program instructions reduced speed, synchronized system clock Low-power modes
Program halt state state which some chip functions stopped conserve power
Sleep (high-speed) mode Sleep (medium-speed) mode
Standby mode Exceptionhandling state transient state which changes processing flow reset interrupt Note: section Power-Down Modes, details modes their transitions.
Figure 2.13 Operation States
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Exception- Exceptionhandling handling request complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.14 State Transitions 2.7.2 Reset State
initialized reset state. 2.7.3 Program Execution State
program execution state executes program instructions sequence. There active modes (high-speed medium-speed) when program execution state. 2.7.4 Program Halt State
program halt state there three modes: sleep modes (high speed medium speed) standby mode. section Power-Down Modes details these modes. 2.7.5 Exception-Handling State
exception-handling state transient state occurring when exception handling started reset interrupt changes normal processing flow. exception handling caused interrupt, (R7) referenced values saved stack. details interrupt handling, section Exception Handling.
2.8.1
Application Notes
Notes Manipulation
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify data, then write data byte again. Special care required when using these instructions cases where registers assigned same address, case registers that include writeonly bits, when instruction accesses port.
Order Operation Read Modify Write Operation Read byte data designated address Modify designated read data Write altered byte data designated address
examples above, input pins, with low-level signal input high-level signal P16. remaining pins, P10, output pins that output low-level signals. this example, BCLR instruction used change input port. Prior executing BCLR]
Input/output state Input level Input High level Output level Output level Output level Output level Output level Output level
BCLR instruction executed] BCLR P1DDR BCLR instruction executed designating DDR.
After executing BCLR]
Input/output state Output level Output High level Output level Output level Output level Output level Output level Input level
Explanation BCLR operates] When BCLR instruction executed, first reads P1DDR. Since P1DDR writeonly register, reads undefined value. this example, value H'FF, data read undefined; taken H'FF. Next, clears read data changing data H'FE. Finally, this value (H'FE) written BCLR instruction execution ends. result this operation, becomes making input port. However, bits change that change from input pins output pins. 2.8.2 Notes EEPMOV Instruction (Cannot used H8/3577 Series H8/3567 Series)
EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8/3577 Series H8/3567 Series operate single-chip mode. operating mode specified setting mode pins (MD1 TEST). Table lists operating modes. Table Operating Mode Selection
H8/3577 Series
Description Single-chip mode
Operating Mode Mode Mode Mode Mode
H8/3567 Series
TEST Description Single-chip mode
Operating Mode Mode Mode
H8/3577 Series H8/3567 Series support mode only. Therefore, mode pins must mode indicated above. 3.1.2 Register Configuration
H8/3577 Series H8/3567 Series have mode control register (MDCR) that indicates inputs mode pins (MD1 TEST), system control register (SYSCR) that controls operation MCU, serial/timer control register (STCR) that controls operation supporting modules. Table summarizes these registers.
Table
Name
Registers
Abbreviation MDCR SYSCR STCR Initial Value H'03 H'09 H'00 Address* H'FFC5 H'FFC4 H'FFC3
Mode control register System control register Serial/timer control register
Note: Lower bits address.
3.2.1
Register Descriptions
Mode Control Register (MDCR)
EXPE MDS1 MDS0
Initial value Read/Write
Note: Determined pins TEST pin.
MDCR 8-bit read-only register that indicates operating mode setting current operating mode MCU. 7-Expanded Mode Enable (EXPE): This should Bits 2-Reserved: These bits cannot modified always read Bits 0-Mode Select (MDS1, MDS0): These bits indicate input levels pins MD1, MD0, TEST (the current operating mode). Bits MDS1 MDS0 correspond (H8/3577 Series). Alternately, bits MDS1 MDS0 both correspond TEST (H8/3567 Series). MDS1 MDS0 read-only bits-they cannot written mode (MD1, MD0, TEST) input levels latched into these bits when MDCR read. 3.2.2
System Control Register (SYSCR)
CS2E IOSE INTM1 INTM0 XRST NMIEG RAME
Initial value Read/Write
SYSCR readable/writable register that performs selection system functions, reset source monitoring, interrupt control mode selection, detected edge selection, supporting module register access control, address space control. Only bits described here. detailed description these bits, refer also description relevant modules (watchdog timer, RAM, etc.). information bits section 5.2.1, System Control Register (SYSCR). SYSCR initialized H'09 reset hardware standby mode. initialized software standby mode. 7-Chip Select Enable (CS2E): This should 6-IOS Enable (IOSE): This should 3-External Reset (XRST): Indicates reset source. When watchdog timer used, reset generated watchdog timer overflow well external reset input. XRST read-only bit. external reset cleared watchdog timer overflow.
XRST Description reset generated watchdog timer overflow reset generated external reset (Initial value)
1-Host Interface Enable (HIE): Enables disables access on-chip supporting function registers. This controls access 8-bit timer (channel data registers control registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, TCORBX), timer connection control registers (TCONRI, TCONRO, TCONRS, SEDGR).
Description areas H'FFF0 H'FFF7 H'FFFC H'FFFF, access 8-bit (Initial value) timer (channel data registers control registers, timer connection control registers, permitted areas H'FFF0 H'FFF7 H'FFFC H'FFFF, access 8-bit timer (channel data registers control registers, timer connection control registers, permitted
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset state released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
3.2.3
Serial Timer Control Register (STCR)
IICX1 IICX0 IICE USBE ICKS1 ICKS0
Initial value Read/Write
STCR 8-bit readable/writable register that controls register access, operating mode, selects TCNT input clock controls USB. details functions other than register access control, descriptions relevant modules. module controlled STCR used, write corresponding bit. STCR initialized H'00 reset hardware standby mode. 7-Reserved: write this bit. Bits 5-I2C Control (IICX1, IICX0): These bits control operation interface. details, section Interface. 4-I2C Master Enable (IICE): Controls access interface data registers control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX data registers control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), control registers (SMR, BRR, SCMR).
IICE Description Addresses H'FFD8 H'FFD9, H'FFDE H'FFDF, used SCI0 control register access (Initial value) Addresses H'FF88 H'FF89, H'FF8E H'FF8F, used IIC1 data register control register access Addresses H'FFA0 H'FFA1, H'FFA6 H'FFA7, used PWMX data register control register access Addresses H'FFD8 H'FFD9, H'FFDE H'FFDF, used IIC0 data register control register access
3-Reserved: write this bit. 2-USB enable (USBE): This controls access data register control register.
USBE Description Prohibition above register access Permission above register access (Initial value)
Bits 0-Internal Clock Source Select (ICKS1, ICKS0): These bits, together with bits CKS2 CKS0 TCR, select clock input TCNT. details, section 8-Bit Timers.
Address
Address maps shown figure figure 3.2. on-chip capacity kbytes (H8/3577, H8/3567, H8/3567U) kbytes (H8/3574, H8/3564, H8/3564U). access reserved areas addresses where memory register exists.
H'0000
On-chip
H'DFFF
H'E080 Reserved area H'E880 On-chip H'EFFF H'F000 Reserved area H'F7FF H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal register (H8/3567U only) Internal register On-chip (128 bytes) Internal register
Figure H8/3577, H8/3567, H8/3567U Address
H'0000
On-chip
H'7FFF
Reserved area
H'DFFF
H'E080 Reserved area H'E880 H'EFFF H'F000 H'F7FF H'F800 Internal register (H8/3564U only) H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80 H'FFFF Internal register On-chip (128 bytes) Internal register On-chip Reserved area
Figure H8/3574, H8/3564, H8/3564U Address
Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, interrupt. Exception handling prioritized shown table 4.1. more exceptions occur simultaneously, they accepted processed order priority. Table
Priority High
Exception Types Priority
Exception Type Reset Interrupt Start Exception Handling Starts immediately after low-to-high transition pin, when watchdog timer overflows. Starts when execution current instruction exception handling ends, interrupt request been issued.*
Note: Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling.
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows: program counter (PC) condition-code register (CCR) pushed onto stack. interrupt mask bits updated. vector address corresponding exception source generated, program execution starts from that address. reset exception, steps above carried out.
4.1.3
Exception Sources Vector Table
exception sources classified shown figure 4.1. Different vector addresses assigned different exception sources. Table lists exception sources their vector addresses.
Reset Exception sources External interrupts: NMI, IRQ2 IRQ0 Interrupts Internal interrupts: interrupt sources on-chip supporting modules
Figure Exception Sources Table Exception Vector Table
Vector Number External interrupt IRQ0 IRQ1 IRQ2 Reserved Internal interrupt* Vector Address* H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'006A H'006B
Exception Source Reset Reserved system
Note: details internal interrupt vectors, section 5.3.3, Interrupt Exception Vector Table.
4.2.1
Reset
Overview
reset highest exception priority. When goes low, processing halts enters reset state. reset initializes internal state registers on-chip supporting modules. Reset exception handling begins when changes from high. MCUs also reset overflow watchdog timer. details, section Watchdog Timer. 4.2.2 Reset Sequence
enters reset state when goes low. ensure that chip reset, hold least when powering reset chip during operation, hold least states. states reset, Appendix D.1, Port States Each Processing State. When goes high after being held necessary time, chip starts reset exception handling follows: internal state registers on-chip supporting modules initialized, CCR. reset exception vector address read transferred program execution starts from address indicated Figure shows example reset sequence.
Vector Internal Fetch first program fetch processing instruction
Internal address Internal read signal Internal write signal Internal data High
Reset exception vector address ((1) H'0000) Start address (contents reset exception vector address) Start address ((3) (2)) First program instruction
Figure Reset Sequence 4.2.3 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. Since first instruction program always executed immediately after reset state ends, make sure that this instruction initializes stack pointer (example: MOV.W #xx:16, SP).
Interrupts
Interrupt exception handling requested four external sources (NMI IRQ2 IRQ0), internal sources on-chip supporting modules. Figure shows interrupt sources number interrupts each type. on-chip supporting modules that request interrupts include watchdog timer (WDT), 16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), converter (ADC), interface (IIC). Each interrupt source separate vector address. highest-priority interrupt. Interrupts controlled interrupt controller. details interrupts, section Interrupt Controller.
External interrupts Interrupts
IRQ2 IRQ0
Internal interrupts
WDT* (10)
Notes: Numbers parentheses numbers interrupt sources. When watchdog timer used interval timer, generates interrupt request each counter overflow.
Figure Interrupt Sources Number Interrupts
Stack Status after Exception Handling
Figure shows stack after completion interrupt exception handling.
CCR* bits)
Interrupt control mode Note: Ignored return.
Figure Stack Status after Exception Handling
Note Stack Handling
word access, least significant address always assumed stack always accessed word access. Care should taken keep even value stack pointer (general register R7). PUSH MOV.W @-SP MOV.W @SP+, instructions push registers stack. Setting stack pointer value cause programs crash. Figure shows example damage caused when stack pointer contains address.
H'FECC H'FECD
H'FECF
instruction
MOV.B R1L, @-R7
H'FECF
improperly stored beyond stack
lost
PCH: PCL: R1L:
Upper byte program counter Lower byte program counter General register Stack pointer
Figure Example Damage Caused Setting Address
Section Interrupt Controller
5.1.1
Overview
Features
MCUs control interrupts means interrupt controller. interrupt controller following features: Independent vector addresses interrupt sources assigned independent vector addresses, making unnecessary source identified interrupt handling routine. Four external interrupt pins highest-priority interrupt, accepted times. rising falling edge selected interrupt. Falling edge, rising edge, both edge detection, level sensing, pins IRQ2 IRQ0 selected interrupts IRQ2 IRQ0.
5.1.2
Block Diagram
block diagram interrupt controller shown figure 5.1.
SYSCR NMIEG input unit input unit ISCR Priority determination
input input
Interrupt request Vector number
Internal interrupt requests WOVI IICI1 USB-related interrupts Interrupt controller
Legend: ISCR: IER: ISR: SYSCR:
sense control register enable register status register System control register
Figure Block Diagram Interrupt Controller 5.1.3 Configuration
Table summarizes pins interrupt controller. Table
Name Nonmaskable interrupt External interrupt requests
Interrupt Controller Pins
Symbol IRQ2 IRQ0 Input Input Function Nonmaskable external interrupt; rising falling edge selected Maskable external interrupts; rising, falling, both edges, level sensing, selected
5.1.4
Register Configuration
Table summarizes registers interrupt controller. Table
Name System control register sense control register sense control register enable register status register
Interrupt Controller Registers
Abbreviation SYSCR ISCRH ISCRL R/(W)* Initial Value H'09 H'00 H'00 H'F8 H'00 Address H'FFC4 H'FEEC H'FEED H'FFC2 H'FEEB
Note: Only written, flag clearing.
5.2.1
Register Descriptions
System Control Register (SYSCR)
CS2E IOSE INTM1 INTM0 XRST NMIEG RAME
Initial value Read/Write
SYSCR 8-bit readable/writable register, which selects detected edge NMI. Only bits described here; details other bits, section 3.2.2, System Control Register (SYSCR). SYSCR initialized H'09 reset hardware standby mode. initialized software standby mode.
Bits 4-Interrupt Control Mode (INTM1, INTM0): INTM1 bits must
INTM1 INTM0 Interrupt Control Mode
Description Interrupts controlled (Initial value)
Cannot used H8/3577 Series H8/3567 Series Cannot used H8/3577 Series H8/3567 Series Cannot used H8/3577 Series H8/3567 Series
2-NMI Edge Select (NMIEG): Selects input edge pin.
NMIEG Description Interrupt request generated falling edge input Interrupt request generated rising edge input (Initial value)
5.2.2
Enable Register (IER)
IRQ2E IRQ1E IRQ0E
Initial value Read/Write
register that controls enabling disabling interrupt requests IRQ2 IRQ0. initialized H'F8 reset hardware standby mode. Bits 3-Reserved: These bits cannot modified always read Bits 0-IRQ2 IRQ0 Enable (IRQ2E IRQ0E): These bits select whether IRQ2 IRQ0 enabled disabled.
IRQnE Description IRQn interrupt disabled IRQn interrupt enabled (Initial value)
5.2.3
Sense Control Registers (ISCRH, ISCRL)
ISCRH
Initial value Read/Write
ISCRL
Initial value Read/Write
IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
ISCRH ISCRL 8-bit readable/writable registers that select rising edge, falling edge, both edge detection, level sensing, input pins IRQ2 IRQ0. Each ISCR registers initialized H'00 reset hardware standby mode. ISCRH Bits ISCRL Bits 6-Reserved: write this bit. ISCRL Bits 0-IRQ2 Sense Control (IRQ2SCA, IRQ2SCB) IRQ0 Sense Control (IRQ0SCA, IRQ0SCB)
ISCRL Bits IRQ2SCB IRQ0SCB IRQ2SCA IRQ0SCA Description Interrupt request generated IRQ2 IRQ0 input level (Initial value) Interrupt request generated falling edge IRQ2 IRQ0 input Interrupt request generated rising edge IRQ2 IRQ0 input Interrupt request generated both falling rising edges IRQ2 IRQ0 input
5.2.4
Status Register (ISR)
IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)*
Initial value Read/Write
Note: Only written, clear flag.
8-bit readable/writable register that indicates status IRQ2 IRQ0 interrupt requests. initialized H'00 reset hardware standby mode. Bits 3-Reserved Bits 0-IRQ2 IRQ0 Flags (IRQ2F IRQ0F): These bits indicate status IRQ2 IRQ0 interrupt requests.
IRQnF Description [Clearing conditions] (Initial value) Cleared reading IRQnF when then writing IRQnF When interrupt exception handling executed when low-level detection (IRQnSCB IRQnSCA IRQn input high When IRQn interrupt exception handling executed when falling, rising, both-edge detection (IRQnSCB IRQnSCA
[Setting conditions] When IRQn input goes when low-level detection (IRQnSCB IRQnSCA When falling edge occurs IRQn input when falling edge detection (IRQnSCB IRQnSCA When rising edge occurs IRQn input when rising edge detection (IRQnSCB IRQnSCA When falling rising edge occurs IRQn input when both-edge detection (IRQnSCB IRQnSCA
Interrupt Sources
Interrupt sources comprise external interrupts (NMI IRQ2 IRQ0) internal interrupts. 5.3.1 External Interrupts
There four external interrupt sources: NMI, IRQ2 IRQ0. NMI, IRQ2 IRQ0 used restore H8/3577 Series H8/3567 Series chip from software standby mode. Interrupt: highest-priority interrupt, always accepted regardless interrupt control mode status interrupt mask bits. NMIEG SYSCR used select whether interrupt requested rising edge falling edge pin. vector number interrupt exception handling IRQ2 IRQ0 Interrupts: Interrupts IRQ2 IRQ0 requested input signal pins IRQ2 IRQ0. Interrupts IRQ2 IRQ0 have following features: Using ISCR, possible select whether interrupt generated level, falling edge, rising edge, both edges, pins IRQ2 IRQ0. Enabling disabling interrupt requests IRQ2 IRQ0 selected with IER. status interrupt requests IRQ2 IRQ0 indicated ISR. flags cleared software. block diagram interrupts IRQ2 IRQ0 shown figure 5.2.
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: IRQn interrupt request
Figure Block Diagram Interrupts IRQ2 IRQ0
Figure shows timing IRQnF setting.
IRQn input
IRQnF
Figure Timing IRQnF Setting vector numbers IRQ2 IRQ0 interrupt exception handling Detection IRQ2 IRQ0 interrupts does depend whether relevant been input output. Therefore, when used external interrupt input pin, clear corresponding another function. interrupt request flags IRQ2F IRQ0F when setting condition met, regardless setting, only necessary flags should referenced. 5.3.2 Internal Interrupts
There sources sources version with on-chip USB) internal interrupts from on-chip supporting modules. each on-chip supporting module there flags that indicate interrupt request status, enable bits that select enabling disabling these interrupts. these interrupt request issued interrupt controller. 5.3.3 Interrupt Exception Vector Table
Table shows interrupt exception handling sources, vector addresses, interrupt priorities. default priorities, lower vector number, higher priority. Priorities within module fixed shown table 5.3.
Table
Interrupt Exception Handling Sources, Vector Addresses, Interrupt Priorities
Origin Interrupt Source External Vector Number 8-bit timer channel 8-bit timer channel Vector Address H'0008 H'000A H'000C H'000E H'0010 H'0018 H'001A H'001C H'001E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 Priority High
Interrupt Source IRQ0 IRQ1 IRQ2 Reserved
WOVI0 (interval timer) (A/D conversion end) ICIA (input capture ICIB (input capture ICIC (input capture ICID (input capture OCIA (output compare OCIB (output compare FOVI (overflow) CMIA0 (compare-match CMIB0 (compare-match OVI0 (overflow) CMIA1 (compare-match CMIB1 (compare-match OVI1 (overflow)
Watchdog timer Free-running timer
Interrupt Source CMIAY (compare-match CMIBY (compare-match OVIY (overflow) ICIX (input capture Reserved
Origin Interrupt Source 8-bit timer channels
Vector Number
Vector Address H'0038 H'003A H'003C H'003E H'0040 H'0046 H'0048 H'004A H'004C H'004E H'0050 H'0056 H'0058 H'005A H'005C H'005E H'0062 H'0064 H'0066 H'0068 H'006A
Priority High
ERI0 (receive error RXI0 (reception completed TXI0 (transmit data empty TEI0 (transmission Reserved
channel
IICI0 (1-byte transmission/ reception completed) DDCSWI (format switch) IICI1 (1-byte transmission/ reception completed) Reserved
channel
channel
USBIA USBIB USBIC USBID
5.4.1
Interrupt Operation
Interrupt Operation
interrupts accepted times except reset state hardware standby state. case interrupts on-chip supporting module interrupts, enable provided each interrupt. Clearing enable disables corresponding interrupt request. Interrupt sources which enable bits controlled interrupt controller. Table shows interrupt control modes. Table Interrupt Control Modes
SYSCR Interrupt Control Mode INTM1 INTM0 Interrupt Mask Bits Description Interrupt mask control performed
Figure shows block diagram priority decision circuit.
Interrupt source
Interrupt acceptance control
Default priority determination
Vector number
Figure Block Diagram Interrupt Control Operation
Interrupt Acceptance Control: interrupt control mode interrupt acceptance control performed means CCR. Table shows interrupts selected each interrupt control mode. Table Interrupts Selected Each Interrupt Control Mode
Interrupt Mask Bits Interrupt Control Mode Selected Interrupts interrupts interrupts
Default Priority Determination: priority determined selected interrupt, vector number generated. Interrupt sources with lower priority than accepted interrupt source held pending. Table shows operations control signal functions each interrupt control mode. Table Operations Control Signal Functions Each Interrupt Control Mode
Setting INTM1 INTM0 Interrupt Acceptance Control Determination
Interrupt Control Mode
Legend: Interrupt operation control performed Used interrupt mask
5.4.2
Interrupt Control Mode
Enabling disabling interrupts on-chip supporting module interrupts means CPU's CCR. Interrupts enabled when cleared disabled when Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. number interrupt requests generated same time, interrupt request with highest priority according priority system shown table selected. then referenced. cleared interrupt request accepted. only interrupt accepted, other interrupt requests held pending. When interrupt request accepted, interrupt exception handling starts after execution current instruction been completed. saved stack area interrupt exception handling. saved stack shows address first instruction executed after returning from interrupt handling routine. Next, This disables interrupts except NMI. vector address generated accepted interrupt, execution interrupt handling routine starts address indicated contents that vector address.
Program execution state
Interrupt generated?
NMI?
Hold pending
IRQ0?
IRQ1?
IICI1*?
Save Read vector address
Branch interrupt handling routine
Note: built-in version USBID.
Figure Flowchart Procedure Interrupt Acceptance
5.4.3
Interrupt acceptance Instruction prefetch Internal operation Stack Vector fetch Internal operation Interrupt handling routine instruction prefetch
Interrupt level determination Wait instruction
Interrupt request signal
Internal address
Interrupt Exception Handling Sequence
Internal read signal
Figure shows interrupt exception handling sequence.
Internal write signal (10)
Figure Interrupt Exception Handling
Internal data
(10)
Instruction prefetch address (Not executed. This contents saved return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4 Saved Vector address Interrupt handling routine start address (vector address contents) First instruction interrupt handling routine
5.4.4
Interrupt Response Times
Table shows interrupt response times-the interval between generation interrupt request execution first instruction interrupt handling routine. Table Interrupt Response Times
Number States Total Notes: Item Interrupt priority determination*
Normal Mode
Number wait states until executing instruction ends* stack save Vector fetch Instruction fetch*
Internal processing*
states case internal interrupt. Refers MULXS DIVXS instructions. Except EEPMOV instruction. Prefetch after interrupt acceptance interrupt handling routine prefetch. Internal processing after interrupt acceptance internal processing after vector fetch.
5.5.1
Usage Notes
Contention between Interrupt Generation Disabling
When interrupt enable cleared disable interrupts, disabling becomes effective after execution instruction. other words, when interrupt enable cleared instruction such BCLR MOV, interrupt generated during execution instruction, interrupt concerned will still enabled completion instruction, interrupt exception handling that interrupt will executed completion instruction. However, there interrupt request higher priority than that interrupt, interrupt exception handling will executed higher-priority interrupt, lower-priority interrupt will ignored. same also applies when interrupt source flag cleared Figure shows example which CMIEA 8-bit timer register cleared
write cycle
CMIA exception handling
Internal address Internal write signal
address
CMIEA
CMFA
CMIA interrupt signal
Figure Contention between Interrupt Generation Disabling above contention will occur enable interrupt source flag cleared while interrupt masked. 5.5.2 Instructions that Disable Interrupts
Instructions that disable interrupts LDC, ANDC, ORC, XORC. After these instructions executed, interrupts, including NMI, disabled next instruction always executed. When these instructions, value becomes valid states after execution instruction ends. 5.5.3 Interrupts during Execution EEPMOV Instruction
With EEPMOV instruction, interrupt request (including NMI) issued during transfer accepted until move completed. EEPMOV instruction cannot used H8/3577 Series H8/3567 Series.
Section Controller
Overview
H8/3577 Series H8/3567 Series have external expansion functions, they incorporate controller function. However, from viewpoint maintaining software compatibility with similar products, care must taken inappropriate values controller related control registers.
6.2.1
Register Descriptions
Control Register (BCR)
ICIS1 ICIS0 IOS1 IOS0
BRSTRM BRSTS1 BRSTS0
Initial value Read/Write
Bits 6-Idle Cycle Insert (ICIS1, ICIS0): write these bits. 5-Burst Enable (BRSTRM): write this bit. 4-Burst Cycle Select (BRSTS1): write this bit. 3-Burst Cycle Select (BRSTS0): write this bit. 2-Reserved: write this bit. Bits 0-IOS Select (IOS1, IOS0): write these bits.
6.2.2
Wait State Control Register (WSCR)
RAMS RAM0 WMS1 WMS0
Initial value Read/Write
7-RAM Select (RAMS)/Bit 6-RAM Area Setting (RAM0): Reserved bits. 5-Bus Width Control (ABW): write this bit. 4-Access State Control (AST): write this bit. Bits 2-Wait Mode Select (WMS1, WMS0): write these bits. Bits 0-Wait Count (WC1, WC0): write these bits.
Section Universal Serial Interface (USB)
built H8/3567U H8/3564U Series H8/3577, H8/3574, H8/3567 H8/3564 Series.
Overview
H8/3567U H8/3564U have on-chip universal serial (USB) comprising hubs function. universal serial interface personal computer peripherals whose standardization being promoted core group companies, including Intel Corporation. provided with number device classes handle great variety personal computer peripheral devices. H8/3567U H8/3564U targeted device class (Human Interface Device) class (mainly monitor device class). 7.1.1 Features
Compound device conforming standard* Apart from initial settings power-down mode settings, hubs decode execute class commands automatically, independently operations function decodes executes standard commands Device class commands decoded executed (firmware creation required) Five downstream hubs function down stream connected internally function Internal downstream disconnection function (Only power-down mode hubs operable) Four sets downstream external pins Automatic control downstream port external power supply control (individual port control) Three-endpoint monitor device class function EP0: control endpoint (dedicated control transfer) EP1, EP2: Monitor control endpoints (dedicated interrupt transfer) EP0I, EP0O, maximum 16-byte FIFO (maximum packet size bytes), maximum 32-byte FIFO (maximum packet size bytes) Supports Mbps high-speed transfer mode Built-in clock pulse generator frequency division/multiplication circuit Built-in driver/receiver Driven /DrV (3.3 Note: function conforms Standard Standard 1.0.
7.1.2
Block Diagram
Figure shows block diagram USB.
FIFO control EPDR2 FVSR2 EPSZR1 EPDR1 FVSR1 EPDR0I FVSR0I EPDR0O FVSR0O Data Address Registers PTTER EPSTLR USBIER EPDIR USBIFR EPRSTR TSFR DEVRSMR TFFR INTSELR0 USBCSR0 INTSELR1 HOCCR USBCR UPLLCR UPRTCR UTESTR0 UTESTR1 UTESTR2 Internal interrupts Interrupt operating clock driver/ receiver FIFO bytes Clock selection (XTAL12, EXTAL12) USD+ USD- Connection selection DrVCC DrVSS core Connection selection function core driver/ receiver Power supply control Control DS2D+ DS2D- DS3D+ DS4D+ DS5D+ DS3D- DS4D- DS5D- ENP2, ENP3 ENP4, ENP5 OCP2, OCP3 OCP4, OCP5 Legend EPDR2: EPDR1: EPDR0I: EPDR0O: FVSR2: FVSR1: FVSR0I: FVSR0O: EPSZR1: PTTER: USBIER: USBIFR: TSFR: TFFR: USBCSR0: EPSTLR: EPDIR: EPRSTR: DEVRSMR: INTSELR0: INTSELR1: HOCCR: USBCR: UPLLCR: UPRTCR: Endpoint data register Endpoint data register Endpoint data register Endpoint data register FIFO valid size register FIFO valid size register FIFO valid size register FIFO valid size register Endpoint size register Packet transmit enable register interrupt enable register interrupt flag register Transfer success flag register Transfer fail flag register control/status register Endpoint stall register Endpoint direction register Endpoint reset register Device resume register Interrupt source select register Interrupt source select register overcurrent control register control register control register port control register UTESTR0: UTESTR1: UTESTR2: USD+: USD-: DS2D+: DS2D-: DS3D+: DS3D-: DS4D+: DS4D-: DS5D+: DS5D-: XTAL12: EXTAL12: DrVCC: DrVSS: OCP2: OCP3: OCP4: OCP5: ENP2: ENP3: ENP4: ENP5: test register test register test register Upstream data Upstream data Downstream data Downstream data Downstream data Downstream data Downstream data Downstream data Downstream data Downstream data clock oscillator clock oscillator driver power supply driver ground Overcurrent detection Overcurrent detection Overcurrent detection Overcurrent detection Power supply output enable Power supply output enable Power supply output enable Power supply output enable
Module data
Internal data
Figure Block Diagram
7.1.3
Configuration
Table shows pins used USB. Table
Name Upstream data Upstream data Downstream data Downstream data Downstream data Downstream data Downstream data Downstream data Downstream data Downstream data Overcurrent detection pins
Pins
Abbreviation USD+ USD- DS2D+ DS2D- DS3D+ DS3D- DS4D+ DS4D- DS5D+ DS5D- Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Output Input Power supply control overcurrent detection signal input Power supply control power output enable signal output crystal oscillation repeater input/output (port repeater input/output (port repeater input/output (port repeater input/output (port Function hub/function data input/output
Power supply output enable control pins clock oscillator clock oscillator XTAL12
EXTAL12 Input Input Input driver/receiver, port power supply driver/receiver, port ground
Driver power supply DrVCC Driver ground DrVSS
7.1.4
Register Configuration
register configuration shown table 7.2. Registers relating initialization status display USBCR, USBCSR0, HOCCR, UPLLCR, well some bits test registers; other registers relate function. When USBCR, USBCSR0, HOCCR, UPLLCR initial state, module completely disabled, ports function ports. When accessing register, USBE STCR must
Table
Name
Registers
Abbreviation EPDR2 FVSR2 EPSZR1 EPDR1 FVSR1 EPDR0O FVSR0O EPDR0I FVSR0I PTTER USBIER USBIFR TSFR TFFR USBCSR0 EPSTLR EPDIR EPRSTR DEVRSMR INTSELR0 INTSELR1 HOCCR USBCR UPLLCR UPRTCR UTESTR0 UTESTR1 UTESTR2 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Initial Value H'00 H'0010 H'44 H'00 H'0010 H'00 H'0000 H'00 H'0010 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FC H'00 H'00 H'00 H'00 H'00 H'7F H'01 H'00 H'00 H'00 H'FF
Address H'FDE1 H'FDE2 H'FDE4 H'FDE5 H'FDE6 H'FDE9 H'FDEA H'FDED H'FDEE H'FDF0 H'FDF1 H'FDF2 H'FDF3 H'FDF4 H'FDF5 H'FDF6 H'FDF7 H'FDF8 H'FDF9 H'FDFA H'FDFB H'FDFC H'FDFD H'FDFE H'FDC0 H'FDC1 H'FDC2 H'FDFF H'FDC3 H'FDE0
Endpoint data register FIFO valid size register Endpoint size register Endpoint data register FIFO valid size register Endpoint data register FIFO valid size register Endpoint data register FIFO valid size register Packet transmit enable register interrupt enable register interrupt flag register Transfer success flag register Transfer fail flag register control/status register Endpoint stall register Endpoint direction register Endpoint reset register Device resume register Interrupt source select register Interrupt source select register overcurrent control register control register control register port control register test register test register test register Other test registers
Name Serial timer control register Module stop control register
Abbreviation STCR MSTPCRH MSTPCRL
Initial Value H'00 H'3F H'FF
Address H'FFC3 H'FF86 H'FF87
Notes: Write-only read-only depending transfer direction endpoint direction register. Only written. Only written after reading clear flags.
Register Descriptions
protocol, host transmits token initiate single data transfer transaction). transaction consists token packet, data packet, handshake packet. token packet contains address endpoint transfer target device transfer type, data packet contains data, handshake packet contains information relating transfer setup/non-setup. data transfer from host slave, host transmits token SETUP token, followed data SETUP transaction). data transfer from slave host, host transmits token waits data from slave transaction). following descriptions, these host-based operations referred "input" "output." Also, items relating host input transfer designated "IN" transaction, IN-FIFO, EP0in, etc.), while items relating host output transfer designated "OUT" (OUT transaction, OUT-FIFO, EP0out, etc.). Where explicit expression such "transmitted host" "received host" used, terms "transmission" "reception" refer transmission reception from standpoint module slave CPU. 7.2.1 Data FIFO
FIFO, together with EPDR, functions intermediary role data transfer between (slave) function. function uses FIFO execute data transfer from host (host). H8/3567U H8/3564U have on-chip 64-byte FIFO. This FIFO divided into four 16byte FIFOs, used endpoint host input transfer host output transfer (control transfer), endpoint host input transfer (interrupt transfer), endpoint host input transfer host output transfer. endpoint used, 32-byte length selected endpoint FIFO. maximum data packet size half number FIFO bytes.
host input transfer, data transmitted from slave written FIFO before slave transmission started. host output transfer, slave reads data from FIFO after host output transfer completed. 7.2.2
Endpoint Size Register (EPSZR1)
EP1SZ3 EP2SZ0
EP1SZ2 EP1SZ1
EP1SZ0 EP2SZ3
EP2SZ2 EP2SZ1
Initial value Read/Write
EPSZR1 specifies number FIFO bytes used each function endpoint host input transfer/host output transfer. number bytes endpoint FIFO fixed Both host input (EP0in) host output (EP0out) selected endpoint host input endpoint host input host output endpoint With H8/3567U H8/3564U, when endpoints both used, 16-byte size respective FIFOs. When only endpoint used, 32-byte size. 32-byte size selected, endpoint FIFO size. EPSZR1 initialized H'44 system reset function soft reset.
EPSZR1 EPSZR1 Bits Bits FIFO size FIFO size
Operating Mode FIFO size bytes (settable only) Setting prohibited Setting prohibited Setting prohibited FIFO size bytes (Initial value)
FIFO size bytes (settable only) Setting prohibited Setting prohibited Setting prohibited
7.2.3
Endpoint Data Registers (EPDR0I, EPDR0O, EPDR1, EPDR2)
Initial value EPDR0I Read/ Write EPDR0O EPDR1 EPDR2
Note: Write-only read-only depending transfer direction endpoint direction register.
EPDR registers play intermediary role data transfer between FIFO each host input transfer/host output transfer involving respective function endpoints. EPDR0I EPDR1 used host input transfer, write-only registers; read, contents read data guaranteed. EPDR0O used host output transfer, read-only register; cannot written EPDR2, endpoint transfer direction determined endpoint direction register. EPDR2 write-only register when designated host input transfer, read-only register when designated host output transfer. EPDR2 read when functioning write-only register, contents read data guaranteed. When EPDR2 functioning readonly register, cannot written Data written EPDR0I, EPDR1, EPDR2 (when write-only register) stored FIFO, made valid setting EPTE packet transmit enable register (PTTER). Valid data transferred function, transferred host, accordance with function request. Data transferred from host stored FIFO function, becomes valid when data packet bytes have been received handshake transmitted. When EPDR0O EPDR2 (when read-only register) read, contents stored FIFO, when data valid read order which transferred. EPDR registers initialized H'00 system reset function soft reset.
7.2.4
FIFO Valid Size Registers (FVSR0I, FVSR0O, FVSR1, FVSR2)
FVSR0IH, FVSR0OH, FVSR1H, FVSR2H FVSR0IL, FVSR0OL, FVSR1L, FVSR2L
0/1*
Initial value Read/Write
Note: initial value FVSR0O, other FVSR registers.
FVSR registers indicate number valid data bytes FIFO each host input/host output involving respective function endpoints. host input transfer, FVSR register indicates number bytes that slave write FIFO (the FIFO size minus number bytes written FIFO slave read (transmitted) function). host output transfer, FVSR register indicates number bytes received written FIFO function read slave CPU. host input transfer, FVSR value decremented number bytes written when slave writes EPDR sets EPTE PTTER, incremented number bytes read when function reads FIFO receives handshake from host. host output transfer, FVSR value incremented number bytes written when function writes FIFO transmits handshake, decremented each time slave reads EPDR. transfer error occurs, data retransfer necessary. this case, FVSR value changed FIFO relevant channel rewound. protocol, each endpoint DATA0 DATA1 packets transmitted received alternately when data transfer performed. This toggling between DATA0 DATA1 also serves indicator whether data transfer been performed normally. DATA0/DATA1 toggling performed normally host output transfer, function will abort processing that transaction FVSR value will change. Since FVSR registers 2-byte registers H8's FIFOs bytes length, FIFO status indicated lower byte alone. Only lower byte FVSR registers should read. upper byte FVSR registers cannot accessed directly. When lower byte read, upper byte transferred temporary register, when upper byte read, contents this temporary register read. When word read used FVSR register, operation automatically divided into byte accesses, with upper byte read first, followed lower
byte. Caution required this case, since upper byte value that read value point when lower byte read previously. FVSR0I FVSR1 automatically initialized H'0010 H'0000, respectively, when SETUP token received. FVSR registers initialized system reset function soft reset. initial value depends transfer direction FIFO size determined EPDIR EPSZR. 7.2.5
Endpoint Direction Register (EPDIR)
EP2DIR EP1DIR
Initial value Read/Write
EPDIR controls data transfer direction function endpoints other than endpoint With H8/3567U H8/3564U, should designated host input transfer host input transfer host output transfer. EPDIR initialized H'FC system reset function soft reset. 3-Endpoint Data Transfer Direction Control Flag (EP2DIR): Switches endpoint data transfer direction.
EP2DIR Description Endpoint designated host output transfer Endpoint designated host input transfer (Initial value)
2-Endpoint Data Transfer Direction Control Flag (EP1DIR): Switches endpoint data transfer direction. This must cleared
EP1DIR Description Setting prohibited Endpoint designated host input transfer (Initial value)
7.2.6
Packet Transmit Enable Register (PTTER)
EP2TE R/(W)* EP1TE R/(W)* EP0ITE R/(W)*
Initial value Read/Write
Note: Only written.
PTTER contains control bits (EPTE) that control FIFO valid size registers function host input transfer. protocol, communication carried using packets. minimum unit data transfer transaction, transaction made token packet, data packet, handshake packet. host input transfer, function receives token (packet). operation stalled, response this token function must transmit data packet there data, handshake. When EPTE after data transmitted function been written FIFO slave CPU, FVSR contents updated. This enables transmission data written FIFO. This EPTE-bit data transmission control prevents data transmission from being done while slave writing data FIFO. EPTE only written with always read 3-Endpoint Packet Transmit Enable (EP2TE): Updates endpoint FVSR2 when EP2DIR
EP2TE Description Normal read value write] Endpoint IN-FIFO FVSR2 updated (Initial value)
2-Endpoint Packet Transmit Enable (EP1TE): Updates endpoint FVSR1.
EP1TE Description Normal read value write] Endpoint IN-FIFO FVSR1 updated (Initial value)
1-Endpoint Packet Transmit Enable (EP0ITE): Updates endpoint FVSR0I.
EP0ITE Description Normal read value write] Endpoint IN-FIFO FVSR0I updated (Initial value)
7.2.7
Interrupt Enable Register (USBIER)
BRSTE SOFE SPNDE SETUPE
Initial value R
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