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Hitachi Single-Chip Microcomputer
H8/3052 F-ZTATHD64F3052TE, HD64F3052F, HD64F3052BTE, HD64F3052BF, HD64F3052BVTE, HD64F3052BVF
Hardware Manual
revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
ADE-602-180A Rev. 3/23/2001 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8/3052F series high-performance microcontrollers that integrate system supporting functions together with H8/300H core. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. on-chip supporting functions include ROM, RAM, 16-bit integrated timer unit (ITU), programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports, direct memory access controller (DMAC), refresh controller, other facilities. channels, been expanded support ISO/IEC7816-3 smart card interface. Functions have also been added reduce power consumption battery-powered applications: individual modules placed standby, frequency system clock supplied chip divided down under software control. address space divided into eight areas. data width access cycle length selected independently each area, simplifying connection different types memory. Seven operating modes (modes provided, offering choice data width address space size. With these features, H8/3052F used implement compact, high-performance systems easily. H8/3052F F-ZTATTM* version with on-chip flash memory that programmed on-board. These versions enable users respond quickly flexibly changing application specifications. This manual describes H8/3052F hardware. details instruction set, refer H8/300H Series Programming Manual. Note: F-ZTAT(Flexible-Zero Turn Around Time) trademark Hitachi, Ltd.
Rev. 2.0, 03/01, page
Rev. 2.0, 03/01, page
List Items Revised Added This Version
Section Page Item Description Amendments introduction H8/3052F-ZTAT mask version. Table Feature Figure1.1 Block Diagram Table Assignments Each Mode(FP-100B TFP-100B) Table1.3 Functions Table 18.12 H8/3052F Socket Adapter Product Codes 19.2.1 Connecting Crystal Resonator "Circuit Configuration" Figure 19.2 Connecting Crystal Resonator (Example) Table 19.1(1) Damping Resistance Value Table 19.1(2) External Capacitance Values 19.2.2 External Clock Input 21.1 Absolute Maximum Ratings 639, 21.2.2 Characteristics 643, Table 19.2 Crystal Resonator Parameters Table 19.3 Clock Timing Table 21.1 Absolute Maximum Ratings Table 21.2 (1)DC Characteristics Table 21.2(2) Characteristics Table 21.3 Permissible Output Currents Table 21.4 Timing Table 21.5 Refresh Controller Timing Table 21.6 Control Signal Timing Amended added Added added Amended Amended Current dissipation amended Added Conditions amended Amended Amended Amended Product lineup amended amended VCL/VCC note amended Note added Product codes added
Overview Block Diagram 1.3.2 Assignments Each Mode 1.3.3 Functions 18.10.1 Socket Adapters Memory 19.2 Oscillator Circuit
8,12
Description added
Rev. 2.0, 03/01, page
Section 21.2.2 Characteristics 21.2.3 Conversion Characteristics 21.2.4 Conversion Characteristics 21.2.5 Flash Memory Characteristics Appendix Product Code Lineup Appendix Differences from H8/3048F-ZTAT
Page
Item Table 21.7 Timing On-Chip Supporting Modules Table 21.8 Converter Characteristics Table 21.9 Converter Characteristics Table 21.10 Flash Memory Characteristics Table H8/3052F Product Code Lineup Table Differences between H8/3052F-ZTAT H8/3048F-ZTAT
Description Amended Amended
Amended
Conditions amended
Product types added H8/3052F-ZTAT specifications amended
Rev. 2.0, 03/01, page
Contents
Section
Overview Overview Block Diagram Description 1.3.1 Arrangement 1.3.2 Assignments Each Mode. 1.3.3 Functions.
Section
Overview 2.1.1 Features 2.1.2 Differences from H8/300 CPU. Operating Modes Address Space Register Configuration 2.4.1 Overview 2.4.2 General Registers 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction 2.6.1 Instruction Overview. 2.6.2 Instructions Addressing Modes 2.6.3 Tables Instructions Classified Function 2.6.4 Basic Instruction Formats. 2.6.5 Notes Manipulation Instructions Addressing Modes Effective Address Calculation 2.7.1 Addressing Modes. 2.7.2 Effective Address Calculation. Processing States 2.8.1 Overview 2.8.2 Program Execution State 2.8.3 Exception-Handling State. 2.8.4 Exception-Handling Sequences. 2.8.5 Bus-Released State 2.8.6 Reset State 2.8.7 Power-Down State.
Rev. 2.0, 03/01, page
Basic Operational Timing. 2.9.1 Overview 2.9.2 On-Chip Memory Access Timing 2.9.3 On-Chip Supporting Module Access Timing. 2.9.4 Access External Address Space
Section
Operating Modes
Overview 3.1.1 Operating Mode Selection. 3.1.2 Register Configuration Mode Control Register (MDCR). System Control Register (SYSCR). Operating Mode Descriptions. 3.4.1 Mode 3.4.2 Mode 3.4.3 Mode 3.4.4 Mode 3.4.5 Mode 3.4.6 Mode 3.4.7 Mode Functions Each Operating Mode. Memory Each Operating Mode.
Section
Exception Handling Overview 4.1.1 Exception Handling Types Priority 4.1.2 Exception Handling Operation 4.1.3 Exception Sources Vector Table Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Interrupts after Reset Interrupts Trap Instruction Stack Status after Exception Handling Notes Stack
Section
Interrupt Controller
Overview 5.1.1 Features 5.1.2 Block Diagram 5.1.3 Configuration 5.1.4 Register Configuration
Rev. 2.0, 03/01, page viii
Register Descriptions. 5.2.1 System Control Register (SYSCR) 5.2.2 Interrupt Priority Registers (IPRA, IPRB) 5.2.3 Status Register (ISR) 5.2.4 Enable Register (IER). 5.2.5 Sense Control Register (ISCR). Interrupt Sources 5.3.1 External Interrupts. 5.3.2 Internal Interrupts. 5.3.3 Interrupt Exception Vector Table. Interrupt Operation 5.4.1 Interrupt Handling Process. 5.4.2 Interrupt Exception Handling Sequence. 5.4.3 Interrupt Response Time Usage Notes. 5.5.1 Contention between Interrupt Generation Disabling 5.5.2 Instructions that Inhibit Interrupts 5.5.3 Interrupts during EEPMOV Instruction Execution 5.5.4 Notes External Interrupts
Section
Controller Overview 6.1.1 Features 6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration Register Descriptions. 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR). 6.2.3 Wait Control Register (WCR) 6.2.4 Wait State Controller Enable Register (WCER) 6.2.5 Release Control Register (BRCR). 6.2.6 Chip Select Control Register (CSCR) Operation. 6.3.1 Area Division 6.3.2 Chip Select Signals. 6.3.3 Data 6.3.4 Control Signal Timing. 6.3.5 Wait Modes 6.3.6 Interconnections with Memory (Example). 6.3.7 Arbiter Operation Usage Notes. 6.4.1 Connection Dynamic Pseudo-Static
Rev. 2.0, 03/01, page
6.4.2 6.4.3 6.4.4
Register Write Timing. BREQ Input Timing Transition Software Standby Mode
Section
Refresh Controller Overview 7.1.1 Features 7.1.2 Block Diagram 7.1.3 Configuration 7.1.4 Register Configuration Register Descriptions. 7.2.1 Refresh Control Register (RFSHCR) 7.2.2 Refresh Timer Control/Status Register (RTMCSR). 7.2.3 Refresh Timer Counter (RTCNT) 7.2.4 Refresh Time Constant Register (RTCOR). Operation. 7.3.1 Overview 7.3.2 DRAM Refresh Control 7.3.3 Pseudo-Static Refresh Control 7.3.4 Interval Timing. Interrupt Source. Usage Notes. Controller Overview 8.1.1 Features 8.1.2 Block Diagram 8.1.3 Functional Overview 8.1.4 Configuration 8.1.5 Register Configuration Register Descriptions (Short Address Mode) 8.2.1 Memory Address Registers (MAR). 8.2.2 Address Registers (IOAR) 8.2.3 Execute Transfer Count Registers (ETCR) 8.2.4 Data Transfer Control Registers (DTCR). Register Descriptions (Full Address Mode) 8.3.1 Memory Address Registers (MAR). 8.3.2 Address Registers (IOAR) 8.3.3 Execute Transfer Count Registers (ETCR) 8.3.4 Data Transfer Control Registers (DTCR). Operation. 8.4.1 Overview 8.4.2 Mode
Section
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8.4.3 Idle Mode 8.4.4 Repeat Mode 8.4.5 Normal Mode 8.4.6 Block Transfer Mode 8.4.7 DMAC Activation 8.4.8 DMAC Cycle 8.4.9 DMAC Multiple-Channel Operation. 8.4.10 External Requests, Refresh Controller, DMAC 8.4.11 Interrupts DMAC. 8.4.12 Aborting Transfer. 8.4.13 Exiting Full Address Mode 8.4.14 DMAC States Reset State, Standby Modes, Sleep Mode. Interrupts Usage Notes. 8.6.1 Note Word Data Transfer 8.6.2 DMAC Self-Access. 8.6.3 Longword Access Memory Address Registers 8.6.4 Note Full Address Mode Setup 8.6.5 Note Activating DMAC Internal Interrupts. 8.6.6 Interrupts Block Transfer Mode. 8.6.7 Memory Address Register Values. 8.6.8 Cycle when Transfer Aborted.
Section
Ports Overview Port 9.2.1 Overview 9.2.2 Register Configuration Port 9.3.1 Overview 9.3.2 Register Configuration Port 9.4.1 Overview 9.4.2 Register Configuration Port 9.5.1 Overview 9.5.2 Register Configuration Port 9.6.1 Overview 9.6.2 Register Configuration Port 9.7.1 Overview 9.7.2 Register Configuration
Rev. 2.0, 03/01, page
Port 9.8.1 Overview 9.8.2 Register Configuration Port 9.9.1 Overview 9.9.2 Register Configuration 9.10 Port 9.10.1 Overview 9.10.2 Register Configuration 9.11 Port 9.11.1 Overview 9.11.2 Register Configuration 9.11.3 Functions. 9.12 Port 9.12.1 Overview 9.12.2 Register Configuration 9.12.3 Functions.
Section 16-Bit Integrated Timer Unit (ITU)
10.1 Overview 10.1.1 Features 10.1.2 Block Diagrams. 10.1.3 Configuration 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Timer Start Register (TSTR) 10.2.2 Timer Synchro Register (TSNC). 10.2.3 Timer Mode Register (TMDR) 10.2.4 Timer Function Control Register (TFCR) 10.2.5 Timer Output Master Enable Register (TOER). 10.2.6 Timer Output Control Register (TOCR) 10.2.7 Timer Counters (TCNT). 10.2.8 General Registers (GRA, GRB) 10.2.9 Buffer Registers (BRA, BRB). 10.2.10 Timer Control Registers (TCR). 10.2.11 Timer Control Register (TIOR) 10.2.12 Timer Status Register (TSR) 10.2.13 Timer Interrupt Enable Register (TIER) 10.3 Interface 10.3.1 16-Bit Accessible Registers. 10.3.2 8-Bit Accessible Registers. 10.4 Operation. 10.4.1 Overview
Rev. 2.0, 03/01, page
10.4.2 Basic Functions 10.4.3 Synchronization. 10.4.4 Mode 10.4.5 Reset-Synchronized Mode 10.4.6 Complementary Mode 10.4.7 Phase Counting Mode 10.4.8 Buffering 10.4.9 Output Timing 10.5 Interrupts 10.5.1 Setting Status Flags. 10.5.2 Clearing Status Flags 10.5.3 Interrupt Sources Controller Activation 10.6 Usage Notes.
Section Programmable Timing Pattern Controller
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Port Data Direction Register (PADDR) 11.2.2 Port Data Register (PADR) 11.2.3 Port Data Direction Register (PBDDR) 11.2.4 Port Data Register (PBDR). 11.2.5 Next Data Register (NDRA). 11.2.6 Next Data Register (NDRB) 11.2.7 Next Data Enable Register (NDERA) 11.2.8 Next Data Enable Register (NDERB). 11.2.9 Output Control Register (TPCR). 11.2.10 Output Mode Register (TPMR) 11.3 Operation. 11.3.1 Overview 11.3.2 Output Timing 11.3.3 Normal Output 11.3.4 Non-Overlapping Output 11.3.5 Output Triggering Input Capture 11.4 Usage Notes. 11.4.1 Operation Output Pins 11.4.2 Note Non-Overlapping Output
Rev. 2.0, 03/01, page xiii
Section Watchdog Timer
12.1 Overview 12.1.1 Features 12.1.2 Block Diagram 12.1.3 Register Configuration 12.2 Register Descriptions. 12.2.1 Timer Counter (TCNT) 12.2.2 Timer Control/Status Register (TCSR) 12.2.3 Reset Control/Status Register (RSTCSR) 12.2.4 Notes Register Access 12.3 Operation. 12.3.1 Watchdog Timer Operation. 12.3.2 Interval Timer Operation. 12.3.3 Timing Setting Overflow Flag (OVF) 12.3.4 Timing Setting Watchdog Timer Reset (WRST). 12.4 Interrupts 12.5 Usage Notes.
Section Serial Communication Interface.
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Receive Shift Register (RSR). 13.2.2 Receive Data Register (RDR) 13.2.3 Transmit Shift Register (TSR). 13.2.4 Transmit Data Register (TDR) 13.2.5 Serial Mode Register (SMR) 13.2.6 Serial Control Register (SCR) 13.2.7 Serial Status Register (SSR). 13.2.8 Rate Register (BRR). 13.3 Operation. 13.3.1 Overview 13.3.2 Operation Asynchronous Mode. 13.3.3 Multiprocessor Communication 13.3.4 Synchronous Operation 13.4 Interrupts 13.5 Usage Notes.
Rev. 2.0, 03/01, page
Section Smart Card Interface
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Smart Card Mode Register (SCMR) 14.2.2 Serial Status Register (SSR). 14.2.3 Serial Mode Register (SMR) 14.2.4 Serial Control Register (SCR) 14.3 Operation. 14.3.1 Overview 14.3.2 Connections. 14.3.3 Data Format. 14.3.4 Register Settings. 14.3.5 Clock 14.3.6 Transmitting Receiving Data. 14.4 Usage Notes.
Section Converter 15.1 Overview 15.1.1 Features 15.1.2 Block Diagram 15.1.3 Configuration 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Data Registers (ADDRA ADDRD) 15.2.2 Control/Status Register (ADCSR). 15.2.3 Control Register (ADCR). 15.3 Interface 15.4 Operation. 15.4.1 Single Mode (SCAN 15.4.2 Scan Mode (SCAN 15.4.3 Input Sampling Conversion Time. 15.4.4 External Trigger Input Timing 15.5 Interrupts 15.6 Usage Notes. Section Converter 16.1 Overview 16.1.1 Features 16.1.2 Block Diagram
Rev. 2.0, 03/01, page
16.1.3 Configuration 16.1.4 Register Configuration 16.2 Register Descriptions. 16.2.1 Data Registers (DADR0/1) 16.2.2 Control Register (DACR). 16.2.3 Standby Control Register (DASTCR) 16.3 Operation. 16.4 Output Control.
Section 17.1 Overview 17.1.1 Block Diagram 17.1.2 Register Configuration 17.2 System Control Register (SYSCR). 17.3 Operation. Section 18.1 Features 18.2 Overview 18.2.1 Block Diagram 18.2.2 Mode Transitions. 18.2.3 On-Board Programming Modes 18.2.4 Flash Memory Emulation RAM. 18.2.5 Differences between Boot Mode User Program Mode. 18.2.6 Block Configuration. 18.3 Configuration 18.4 Register Configuration 18.5 Register Descriptions. 18.5.1 Flash Memory Control Register (FLMCR1) 18.5.2 Flash Memory Control Register (FLMCR2) 18.5.3 Erase Block Register (EBR1). 18.5.4 Erase Block Register (EBR2). 18.5.5 Control Register (RAMCR) 18.6 On-Board Programming Modes 18.6.1 Boot Mode. 18.6.2 User Program Mode 18.7 Programming/Erasing Flash Memory 18.7.1 Program Mode. 18.7.2 Program-Verify Mode 18.7.3 Notes Program/Program-Verify Procedure 18.7.4 Erase Mode. 18.7.5 Erase-Verify Mode. 18.8 Protection
Rev. 2.0, 03/01, page
18.8.1 Hardware Protection. 18.8.2 Software Protection 18.8.3 Error Protection 18.8.4 Input Disable Conditions 18.9 Flash Memory Emulation RAM. 18.10 Flash Memory PROM Mode 18.10.1 Socket Adapters Memory Map. 18.10.2 Notes PROM Mode 18.11 Notes Flash Memory Programming/Erasing
Section Clock Pulse Generator.
19.1 Overview 19.1.1 Block Diagram 19.2 Oscillator Circuit 19.2.1 Connecting Crystal Resonator 19.2.2 External Clock Input 19.3 Duty Adjustment Circuit 19.4 Prescalers. 19.5 Frequency Divider. 19.5.1 Register Configuration 19.5.2 Division Control Register (DIVCR). 19.5.3 Usage Notes.
Section Power-Down State. 20.1 Overview 20.2 Register Configuration 20.2.1 System Control Register (SYSCR) 20.2.2 Module Standby Control Register (MSTCR) 20.3 Sleep Mode. 20.3.1 Transition Sleep Mode 20.3.2 Exit from Sleep Mode 20.4 Software Standby Mode 20.4.1 Transition Software Standby Mode. 20.4.2 Exit from Software Standby Mode. 20.4.3 Selection Waiting Time Exit from Software Standby Mode. 20.4.4 Sample Application Software Standby Mode 20.4.5 Note 20.5 Hardware Standby Mode. 20.5.1 Transition Hardware Standby Mode 20.5.2 Exit from Hardware Standby Mode 20.5.3 Timing Hardware Standby Mode 20.6 Module Standby Function 20.6.1 Module Standby Timing.
Rev. 2.0, 03/01, page xvii
20.6.2 Read/Write Module Standby 20.6.3 Usage Notes. 20.7 System Clock Output Disabling Function
Section Electrical Characteristics (Preliminary)
21.1 Absolute Maximum Ratings. 21.2 Electrical Characteristics 21.2.1 Characteristics. 21.2.2 Characteristics. 21.2.3 Conversion Characteristics 21.2.4 Conversion Characteristics 21.2.5 Flash Memory Characteristics. 21.3 Operational Timing 21.3.1 Timing. 21.3.2 Refresh Controller Timing 21.3.3 Control Signal Timing. 21.3.4 Clock Timing 21.3.5 Port Timing 21.3.6 Timing 21.3.7 Input/Output Timing 21.3.8 DMAC Timing
Appendix
Instruction
Instruction List Operation Code Number States Required Execution.
Appendix
Internal Register. Addresses Function.
Appendix
C.10 C.11
Port Block Diagrams Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams.
Rev. 2.0, 03/01, page xviii
Appendix
States Port States Each Mode States Reset Timing Transition Recovery from Hardware Standby Mode
Appendix
Timing Transition Hardware Standby Mode Timing Recovery from Hardware Standby Mode
Appendix Appendix Appendix
Product Code Lineup Package Dimensions Differences from H8/3048F-ZTAT
Rev. 2.0, 03/01, page
Rev. 2.0, 03/01, page
Section Overview
Overview
H8/3052F series microcontrollers (MCUs) that integrate system supporting functions together with H8/300H core having original Hitachi architecture. H8/300H 32-bit internal architecture with sixteen 16-bit general registers, concise, optimized instruction designed speed. address 16-Mbyte linear address space. instruction upward-compatible object-code level with H8/300 CPU, enabling easy porting software from H8/300 Series. on-chip system supporting functions include ROM, RAM, 16-bit integrated timer unit (ITU), programmable timing pattern controller (TPC), watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports, direct memory access controller (DMAC), refresh controller, other facilities. H8/3052F kbytes kbytes RAM. Seven operating modes offer choice data width address space size. modes (modes include single-chip mode expanded modes. H8/3052F F-ZTATTM* version with on-chip flash memory that programmed on-board. Table summarizes features H8/3052F. Note: F-ZTAT (Flexible-Zero Turn Around Time) trademark Hitachi, Ltd.
Rev. 2.0, 03/01 page
Table
Feature
Features
Description Upward-compatible with H8/300 object-code level General-register machine Sixteen 16-bit general registers (also usable eight 16-bit registers eight 32-bit registers) High-speed operation Maximum clock rate: Add/subtract: Multiply/divide: 16-Mbyte address space Instruction features 8/16/32-bit data transfer, arithmetic, logic instructions Signed unsigned multiply instructions bits bits, bits bits) Signed unsigned divide instructions bits bits, bits bits) accumulator function manipulation instructions with register-indirect specification positions
Memory
Flash memory: kbytes RAM: kbytes Seven external interrupt pins: NMI, IRQ0 IRQ5 internal interrupts Three selectable interrupt priority levels
Interrupt controller
Rev. 2.0, 03/01, page
Feature controller
Description Address space partitioned into eight areas, with independent specifications each area Chip select output available areas 8-bit access 16-bit access selectable each area Two-state three-state access selectable each area Selection four wait modes arbitration function DRAM refresh Directly connectable 16-bit-wide DRAM CAS-before-RAS refresh Self-refresh mode selectable Pseudo-static refresh Self-refresh mode selectable Usable interval timer Short address mode Maximum four channels available Selection mode, idle mode, repeat mode activated compare match/input capture interrupts from channels transmit-data-empty receive-data-full interrupts from channel external requests Full address mode Maximum channels available Selection normal mode block transfer mode activated compare match/input capture interrupts from channels external requests, auto-request
Refresh controller
controller (DMAC)
Rev. 2.0, 03/01 page
Feature 16-bit integrated timer unit (ITU)
Description Five 16-bit timer channels, capable processing pulse outputs pulse inputs 16-bit timer counter (channels multiplexed output compare/input capture pins (channels Operation synchronized (channels mode available (channels Phase counting mode available (channel Buffering available (channels Reset-synchronized mode available (channels Complementary mode available (channels DMAC activated compare match/input capture interrupts (channels Maximum 16-bit pulse output, using time base four 4-bit pulse output groups 16-bit group, 8-bit groups) Non-overlap mode available Output data transferred DMAC Reset signal generated overflow Usable interval timer Selection asynchronous synchronous mode Full duplex: transmit receive simultaneously On-chip baud-rate generator Smart card interface functions added (SCI0 only) Resolution: bits Eight channels, with selection single scan mode Variable analog conversion voltage range Sample-and-hold function conversion externally triggered
Programmable timing pattern controller (TPC)
Watchdog timer (WDT), channel Serial communication interface (SCI), channels
converter
Rev. 2.0, 03/01, page
Feature converter
Description Resolution: bits channels outputs sustained software standby mode input/output pins input-only pins Seven operating modes
Address Space Mbyte Mbyte Mbytes Mbytes Mbyte Mbytes Mbyte Address Pins Initial Width bits bits bits bits bits bits Max. Width bits bits bits bits bits bits
ports
Operating modes
Mode Mode Mode Mode Mode Mode Mode Mode
On-chip disabled modes Sleep mode Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division On-chip clock pulse generator
Product Code version HD64F3052F HD64F3052TE Package(Hitachi Package Code) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B)
Power-down state
Other features Product lineup
Product Type H8/3052F-ZTAT
H8/3052F-ZTAT mask version
version HD64F3052BF HD64F3052BTE version HD64F3052BVF
HD64F3052BVTE 100-pin TQFP (TFP-100B)
Rev. 2.0, 03/01 page
Block Diagram
Figure shows internal block diagram.
VCL/VCC
P37/D15
P36/D14
P35/D13
P34/D12
P33/D11
P32/D10
P31/D9
P30/D8
P47/D7
P46/D6
P45/D5
P44/D4
P43/D3
P42/D2
P41/D1
Port Address
Port P53/A19
Port Port Port Port
Port
EXTAL XTAL STBY P66/LWR P65/HWR P64/RD P63/AS P62/BACK P61/BREQ P60/WAIT P84/CS0 P82/CS2/IRQ2 P81/CS3/IRQ1 P80/RFSH/IRQ0 Interrupt controller
Data (upper) Data (lower)
P40/D0
P52/A18 P51/A17 P50/A16
Clock pulse generator
P27/A15 H8/300H P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 P17/A7 P16/A6 P15/A5 Refresh controller P14/A4 P13/A3 P12/A2 P11/A1 Watchdog timer (WDT) P10/A0
controller (DMAC)
Port
(flash memory)
Port
P83/CS1/IRQ3
16-bit integrated timer unit (ITU)
Serial communication interface (SCI) channels P95/SCK1/IRQ5 P94/SCK0/IRQ4 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0
Programmable timing pattern controller (TPC)
converter converter
Port
Port
PA6/TP6/TIOCA2/A21/CS4
PA5/TP5/TIOCB1/A22/CS5
PB7/TP15/DREQ1/ADTRG
PA4/TP4/TIOCA1/A23/CS6
PB6/TP14/DREQ0/CS7
PA7/TP7/TIOCB2/A20
PA3/TP3/TIOCB0/TCLKD
PA2/TP2/TIOCA0/TCLKC
PA1/TP1/TEND1/TCLKB
PA0/TP0/TEND0/TCLKA
PB5/TP13/TOCXB4
PB4/TP12/TOCXA4
PB3/TP11/TIOCB4
PB2/TP10/TIOCA4
PB1/TP9/TIOCB3
PB0/TP8/TIOCA3
P77/AN7/DA1
P76/AN6/DA0
controller P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
Figure Block Diagram
Rev. 2.0, 03/01, page
P70/AN0
VREF
AVCC
AVSS
1.3.1
Description
Arrangement
Figure shows arrangement H8/3052F.
/BREQ /BACK /WAIT /HWR
/LWR
AVCC VREF /AN6 /AN7 AVSS /RFSH/IRQ /IRQ /IRQ /IRQ /TP0 /TEND /TCLKA /TP1 /TEND1 /TCLKB /TP2 /TIOCA 0/TCLKC /TP3 /TIOCB0 /TCLKD /TP4 /TIOCA1 /A23 /CS6 /TP5 /TIOCB1 /A22 /CS5 6/TP /TIOCA 21/CS4 /TP7 /TIOCB
EXTAL
STBY
XTAL
view (FP-100B, TFP-100B)
A13/P2 A12/P2 A11/P2 A10/P2 /P17 /P16 /P15 /P14 /P13 /P12 /P11 /P10 D15/P3 D14/P3 D13/P3 D12/P3 D11/P3 D10/P3 /P31 /P30 /P47
VCL/VCC* TIOCA3
TIOCB3
TIOCA4 /TP10
TIOCB4 /TP11
TOCXA4 /TP12
TOCXB4 /TP13
CS7/DREQ /TP14
ADTRG/DREQ /TP15
TxD0
TxD1
RxD0
RxD1
4/SCK0
5/SCK1
(Preliminary)
Note: This functions during operation during operation. external capacitor must connected pin.
Figure Arrangement (FP-100B TFP-100B, View)
Rev. 2.0, 03/01 page
1.3.2
Assignments Each Mode
Table lists assignments each mode. Table Assignments Each Mode (FP-100B TFP-100B)
Name Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0/ PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Mode VCL(VCC)* PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 PB6/TP14/ DREQ0 PB7/TP15/ DREQ1/ ADTRG P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/ IRQ4 P95/SCK1/ IRQ5
Rev. 2.0, 03/01, page
Name Mode P40/D0* P41/D1* P42/D2* P43/D3*
P44/D4* P45/D5* P46/D6*
Mode P40/D0* P41/D1* P42/D2* P43/D3*
P44/D4* P45/D5* P46/D6*
Mode P40/D0* P41/D1* P42/D2* P43/D3*
P44/D4* P45/D5* P46/D6*
Mode P40/D0* P41/D1* P42/D2* P43/D3*
P44/D4* P45/D5* P46/D6*
Mode P40/D0* P41/D1* P42/D2* P43/D3*
P44/D4* P45/D5* P46/D6*
Mode P40/D0* P41/D1* P42/D2* P43/D3*
P44/D4* P45/D5* P46/D6*
Mode
P47/D7*
P47/D7*
P47/D7*
P47/D7*
P47/D7* P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9
P47/D7* P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9
Rev. 2.0, 03/01 page
Name Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 P60/WAIT P61/BREQ P62/BACK STBY EXTAL XTAL Mode STBY EXTAL XTAL
Rev. 2.0, 03/01, page
Name Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS P80/RFSH/ IRQ0 P81/CS3/ IRQ1 P82/CS2/ IRQ2 P83/CS1/ IRQ3 P84/CS0 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS Mode AVCC VREF P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/ P77/AN7/ AVSS
P80/RFSH/ P80/RFSH/ P80/RFSH/ IRQ0 IRQ0 IRQ0 P81/CS3/ IRQ1 P82/CS2/ IRQ2 P83/CS1/ IRQ3 P84/CS0 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC P81/CS3/ IRQ1 P82/CS2/ IRQ2 P83/CS1/ IRQ3 P84/CS0 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC P81/CS3/ IRQ1 P82/CS2/ IRQ2 P83/CS1/ IRQ3 P84/CS0 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC
P80/RFSH/ P80/RFSH/ P80/IRQ0 IRQ0 IRQ0 P81/CS3/ IRQ1 P82/CS2/ IRQ2 P83/CS1/ IRQ3 P84/CS0 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC P81/CS3/ IRQ1 P82/CS2/ IRQ2 P83/CS1/ IRQ3 P84/CS0 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC P81/IRQ1 P82/IRQ2 P83/IRQ3 PA0/TP0/ TEND0/ TCLKA PA1/TP1/ TEND1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC
Rev. 2.0, 03/01 page
Name Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ PA5/TP5/ TIOCB1/ PA6/TP6/ TIOCA2/ PA7/TP7/ TIOCB2 Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ PA5/TP5/ TIOCB1/ PA6/TP6/ TIOCA2/ PA7/TP7/ TIOCB2 Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ PA5/TP5/ TIOCB1/ PA6/TP6/ TIOCA2/ Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ PA5/TP5/ TIOCB1/ PA6/TP6/ TIOCA2/ Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ PA5/TP5/ TIOCB1/ PA6/TP6/ TIOCA2/ PA7/TP7/ TIOCB2 Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/ A23/CS6 PA5/TP5/ TIOCB1/ A22/CS5 PA6/TP6/ TIOCA2/ A21/CS4 Mode PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2
Notes: This functions during operation during operation. external capacitor must connected when this functions pin. modes functions pins P40/D0 P47/D7 selected after reset, they changed software. modes functions pins P40/D0 P47/D7 selected after reset, they changed software.
Rev. 2.0, 03/01, page
1.3.3
Functions
Table summarizes functions. Table
Type Power
Functions
Symbol Input Name Function Power: connection power supply. Connect pins system power supply. Ground: connection ground Connect pins system power supply. Connect external capacitor between this
Input
Input
Clock
XTAL
Input
connection crystal resonator. examples crystal resonator external clock input, section Clock Pulse Generator. connection crystal resonator input external clock signal. examples crystal resonator external clock input, section Clock Pulse Generator. System clock: Supplies system clock external devices. Mode mode setting operating mode, follows. Inputs these pins must changed during operation. Operating Mode Mode Mode Mode Mode Mode Mode Mode
EXTAL
Input
Operating mode control
Output Input
Rev. 2.0, 03/01 page
Type System control
Symbol STBY BREQ BACK
Input Input Input Input Output
Name Function Reset input: When driven low, this resets chip Flash write enable: Allows program mode setting. Standby: When driven low, this forces transition hardware standby mode request: Used external master request right request acknowledge: Indicates that been granted external master Nonmaskable interrupt: Requests nonmaskable interrupt Interrupt request Maskable interrupt request pins Address bus: Outputs address signals
Interrupts
IRQ5 IRQ0
100,
Input Input Output
Address
Data control
Input/ output Output Output Output Output
Data bus: Bidirectional data Chip select: Select signals areas Address strobe: Goes indicate valid address output address Read: Goes indicate reading from external address space High write: Goes indicate writing external address space; indicates valid data upper data (D15 D8). write: Goes indicate writing external address space; indicates valid data lower data D0). Wait: Requests insertion wait states cycles during access external address space
Output
WAIT
Input
Rev. 2.0, 03/01, page
Type Refresh controller
Symbol RFSH
Output Output Output
Name Function Refresh: Indicates refresh cycle address strobe address RAS: strobe signal DRAM connected area Column address strobe Column CAS: address strobe signal DRAM connected area used with DRAM. Write enable Write enable signal DRAM connected area used with 2CAS DRAM.
Output
Upper write Write enable signal DRAM connected area used with DRAM. Upper column address strobe UCAS UCAS: Column address strobe signal DRAM connected area used with 2CAS DRAM.
Output
Lower write Write enable signal DRAM connected area used with DRAM. Lower column address strobe LCAS: LCAS Column address strobe signal DRAM connected area used with 2CAS DRAM.
controller (DMAC)
DREQ1, DREQ0 TEND1, TEND0
Input Output
request DMAC activation requests Transfer These signals indicate that DMAC ended data transfer Clock input External clock inputs Input capture/output compare GRA4 GRA0 output compare input capture, output Input capture/output compare GRB4 GRB0 output compare input capture, output Output compare XA4: output Output compare XB4: output
16-bit integrated TCLKD timer unit (ITU) TCLKA TIOCA4 TIOCA0 TIOCB4 TIOCB0 TOCXA4 TOCXB4
100,
Input Input/ output Input/ output Output Output
Rev. 2.0, 03/01 page
Type
Symbol
Output
Name Function output Pulse output
Programmable TP15 timing pattern controller (TPC) Serial communication interface (SCI) TxD1, TxD0 RxD1, RxD0
Output Input Input/ output Input Input Output Input
Transmit data (channels data output Receive data (channels data input Serial clock (channels clock input/output Analog Analog input pins trigger: External trigger input starting conversion Analog output: Analog output from converter Power supply converters. Connect system power supply when using converters. Ground converters. Connect system ground Reference voltage input converters. Connect system power supply when using converters. Port Eight input/output pins. direction each selected port data direction register (P1DDR). Port Eight input/output pins. direction each selected port data direction register (P2DDR). Port Eight input/output pins. direction each selected port data direction register (P3DDR). Port Eight input/output pins. direction each selected port data direction register (P4DDR).
SCK1, SCK0 converter ADTRG converter converters DA1, AVCC
AVSS VREF
Input Input
ports
Input/ output Input/ output Input/ output Input/ output
Rev. 2.0, 03/01, page
Type ports
Symbol
Input/ output Input/ output Input Input/ output Input/ output Input/ output Input/ output
Name Function Port Four input/output pins. direction each selected port data direction register (P5DDR). Port Seven input/output pins. direction each selected port data direction register (P6DDR). Port Eight input pins Port Five input/output pins. direction each selected port data direction register (P8DDR). Port input/output pins. direction each selected port data direction register (P9DDR). Port Eight input/output pins. direction each selected port data direction register (PADDR). Port Eight input/output pins. direction each selected port data direction register (PBDDR).
Notes:
This functions during operation (should connected system power supply) during operation.
Rev. 2.0, 03/01 page
Rev. 2.0, 03/01, page
Section
Overview
H8/300H high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 CPU. H8/300H sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. 2.1.1 Features
H8/300H following features. Upward compatibility with H8/300 execute H8/300 Series object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-two basic instructions 8/16/32-bit data transfer arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) @(d:24, ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8, @(d:16, PC)] Memory indirect [@@aa:8] 16-Mbyte linear address space High-speed operation frequently-used instructions execute four states Maximum clock frequency: 8-bit register-register multiply: 8-bit register-register divide: 16-bit register-register multiply: 16-bit register-register divide: 0.88 0.88
Rev. 2.0, 03/01, page
8/16/32-bit register-register add/subtract:
operating modes Normal mode (not available H8/3052F) Advanced mode Low-power mode Transition power-down state SLEEP instruction 2.1.2 Differences from H8/300
comparison H8/300 CPU, H8/300H following enhancements. More general registers Eight 16-bit registers have been added. Expanded address space Advanced mode supports maximum 16-Mbyte address space. Normal mode supports same 64-kbyte address space H8/300 CPU. (Normal mode available H8/3052F.) Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Data transfer, arithmetic, logic instructions operate 32-bit data. Signed multiply/divide instructions other instructions have been added.
Rev. 2.0, 03/01, page
Operating Modes
H8/300H operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports Mbytes. H8/3052F used only advanced mode. (Information from this point will apply advanced mode unless otherwise stated.)
Normal mode
Maximum kbytes, program data areas combined
operating modes Maximum Mbytes, program data areas combined
Advanced mode
Figure Operating Modes
Rev. 2.0, 03/01, page
Address Space
maximum address space H8/300H Mbytes. H8/3052F various operating modes (MCU modes), some providing 1-Mbyte address space, others supporting full Mbytes. Figure shows address ranges H8/3052F. further details section 3.6, Memory Each Operating Mode. 1-Mbyte operating modes 20-bit addressing. upper bits effective addresses ignored.
H'00000
H'000000
H'FFFFF
H'FFFFFF 1-Mbyte modes 16-Mbyte modes
Figure Memory
Rev. 2.0, 03/01, page
2.4.1
Register Configuration
Overview
H8/300H internal registers shown figure 2.3. There types registers: general registers control registers.
General Registers (ERn) Control Registers (CR) Legend Stack pointer Program counter CCR: Condition code register Interrupt mask User interrupt mask Half-carry flag User Negative flag Zero flag Overflow flag Carry flag (SP)
Figure Internal Registers
Rev. 2.0, 03/01, page
2.4.2
General Registers
H8/300H eight 32-bit general registers. These general registers functionally alike used without distinction between data registers address registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers registers
registers
registers
Figure Usage General Registers
Rev. 2.0, 03/01, page
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area (ER7) Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word) multiple bytes, least significant ignored. When instruction fetched, least significant regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask Masks interrupts other than when accepted regardless setting. start exception-handling sequence. 6-User Interrupt Mask (UI) written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details section Interrupt Controller. 5-Half-Carry Flag When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L,
Rev. 2.0, 03/01, page
NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag Indicates most significant (sign bit) data. 2-Zero Flag indicate zero data, cleared indicate non-zero data. 1-Overflow Flag when arithmetic overflow occurs, cleared other times. 0-Carry Flag when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions. Some instructions leave flag bits unchanged. Operations performed LDC, STC, ANDC, ORC, XORC instructions. flags used conditional branch (Bcc) instructions. action each instruction flag bits, appendix A.1, Instruction List. bits, section Interrupt Controller. 2.4.4 Initial Register Values
reset exception handling, initialized value loaded from vector table, other bits general registers initialized. initial value stack pointer (ER7) undefined. stack pointer must therefore initialized MOV.L instruction executed immediately after reset.
Rev. 2.0, 03/01, page
Data Formats
H8/300H process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure shows data formats general registers.
Data Type
General Register
Data Format Don't care
1-bit data
1-bit data
Don't care
4-bit data
Upper digit Lower digit
Don't care
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care
Byte data
Don't care
Figure General Register Data Formats
Rev. 2.0, 03/01, page
Data Type
General Register
Data Format
Word data
Word data
Longword data Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure General Register Data Formats
Rev. 2.0, 03/01, page
2.5.2
Memory Data Formats
Figure shows data formats memory. H8/300H access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type
Address
Data Format
1-bit data Byte data Word data Address Address Address Address Address Longword data Address Address Address
Figure Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
Rev. 2.0, 03/01, page
2.6.1
Instruction
Instruction Overview
H8/300H types instructions, which classified table 2.1. Table
Function Data transfer Arithmetic operations
Instruction Classification
Instruction MOV, PUSH* POP* MOVTPE* MOVFPE*
Types
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Logic operations Shift operations manipulation Branch System control Block data transfer
Total types
Notes: POP.W identical MOV.W @SP+, PUSH.W identical MOV.W @-SP. POP.L identical MOV.L @SP+, PUSH.L identical MOV.L @-SP. available H8/3052F. generic branching instruction.
Rev. 2.0, 03/01, page
2.6.2
Instructions Addressing Modes
Table indicates instructions available H8/300H CPU. Table Instructions Addressing Modes
Addressing Modes
@(d:16,ERn) @ERn+/@-ERn @(d:24,ERn)
@(d:8,PC)
Function
Instruction
@ERn
@(d:16,PC)
@@aa:8
@aa:16
@aa:24
@aa:8
Data transfer
POP, PUSH MOVFPE,* MOVTPE*
Arithmetic operations
ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, MULXS, DIVXU, DIVXS EXTU, EXTS
Logic operations
AND,
Shift instructions manipulation Branch Bcc, JMP, System control TRAPA SLEEP ANDC, ORC, XORC Block data transfer
Legend Byte Word Longword Note: available H8/3052F.
Rev. 2.0, 03/01, page
2.6.3
Tables Instructions Classified Function
Tables 2.10 summarize instructions each functional category. operation notation used these tables defined next. Operation Notation
(EAd) (EAs) #IMM disp :3/:8/:16/:24 General register (destination)* General register (source)* General register* General register (32-bit register address register) Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move (logical complement) 16-, 24-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit data address registers (ER0 ER7).
Rev. 2.0, 03/01, page
Table
Instruction
Data Transfer Instructions
Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register.
MOVFPE MOVTPE
(EAs) Cannot used H8/3052F. (EAs) Cannot used H8/3052F. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, Similarly, POP.L identical MOV.L @SP+, ERn.
PUSH
@-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. Similarly, PUSH.L identical MOV.L ERn, @-SP.
Note: Size refers operand size. Byte Word Longword
Rev. 2.0, 03/01, page
Table
Instruction ADD,
Arithmetic Operation Instructions
Size* B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from data general register. SUBX instruction.)
ADDX, SUBX
#IMM Performs addition subtraction with carry borrow data general registers, immediate data data general register.
INC,
B/W/L
Increments decrements general register (Byte operands incremented decremented only.)
ADDS, SUBS
Adds subtracts value from data 32-bit register.
DAA,
decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data.
MULXU
Performs unsigned multiplication data general registers: either bits bits bits bits bits bits.
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits.
Rev. 2.0, 03/01, page
Instruction DIVXU
Size*
Function Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
DIVXS
Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder, bits bits 16-bit quotient 16-bit remainder.
B/W/L
#IMM Compares data general register with data another general register with immediate data, sets according result.
B/W/L
Takes two's complement (arithmetic complement) data general register.
EXTS
(sign extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, extending sign bit.
EXTU
(zero extension) Extends byte data lower bits 16-bit register word data, extends word data lower bits 32-bit register longword data, padding with zeros.
Note: Size refers operand size. Byte Word Longword
Rev. 2.0, 03/01, page
Table
Instruction
Logic Operation Instructions
Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data.
B/W/L
Takes one's complement general register contents.
Note: Size refers operand size. Byte Word Longword
Table
Instruction SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR
Shift Instructions
Size* B/W/L B/W/L B/W/L B/W/L Function (shift) Performs arithmetic shift general register contents. (shift) Performs logical shift general register contents. (rotate) Rotates general register contents. (rotate) Rotates general register contents through carry bit.
Note: Size refers operand size. Byte Word Longword
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Table
Instruction BSET
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower bits general register.
BAND
(<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag.
BIAND
(<bit-No.> <EAd>)] ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
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Instruction
Size*
Function (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag.
BIOR
(<bit-No.> <EAd>)] carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BXOR
(<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag.
BIXOR
(<bit-No.> <EAd>)] Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers specified general register memory operand carry flag.
BILD
(<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand.
BIST
(<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
Note: Size refers operand size. Byte
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Table
Instruction
Branching Instructions
Size Function Branches specified address specified condition true. branching conditions listed below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
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Table
Instruction TRAPA SLEEP
System Control Instructions
Size* Function Starts trap-instruction exception handling Returns from exception-handling routine Causes transition power-down state (EAs) Moves source operand contents condition code register. condition code register size byte, transfer from memory, data read word access.
(EAd) Transfers contents destination location. condition code register size byte, transfer memory, data written word access.
ANDC XORC
#IMM Logically ANDs condition code register with immediate data. #IMM Logically condition code register with immediate data. #IMM Logically exclusive-ORs condition code register with immediate data.
Only increments program counter.
Note: Size refers operand size. Byte Word
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Table 2.10 Block Transfer Instruction
Instruction EEPMOV.B Size Function then repeat until else next; EEPMOV.W then repeat until else next; Transfers data block according parameters general registers ER5, ER6. Size block (bytes) ER5: Starting source address ER6: Starting destination address Execution next instruction begins soon transfer completed. @ER5+ @ER6+, @ER5+ @ER6+,
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2.6.4
Basic Instruction Formats
H8/300H instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. 24-bit address displacement treated 32-bit data which first bits (H'00). Condition Field: Specifies branching condition instructions. Figure shows examples instruction formats.
Operation field only Operation field register fields ADD.B etc. NOP, RTS, etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) MOV.B @(d:16, Rn),
Figure Instruction Formats
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2.6.5
Notes Manipulation Instructions
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify byte, then write byte back. Care required when these instructions used access registers with write-only bits, access ports. BCLR instruction used clear flags on-chip registers. interrupt-handling routine, example, known that flag necessary read flag ahead time.
Step Read manipulation Write Description Read data (byte unit) specified address Modify specified read data Write modified data (byte unit) specified address
following example, BCLR instruction executed data direction register (DDR) port input pins, inputting low-level high-level signals, respectively. output pins, low-level output state. this example, BCLR instruction used make input port. Before Execution BCLR Instruction
Input/output Input Input Output Output Output Output Output Output
Execution BCLR Instruction
BCLR @P4DDR
Execute BCLR instruction
After Execution BCLR Instruction
Input/output Output Output Output Output Output Output Output Input
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Explanation BCLR Instruction execute BCLR instruction, begins reading P4DDR. Since P4DDR writeonly register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back complete BCLR instruction. result, P40DDR cleared making input pin. addition, P47DDR P46DDR making output pins. BCLR instruction used clear flags internal registers interrupthandling routine, example, known that flag necessary read flag ahead time.
2.7.1
Addressing Modes Effective Address Calculation
Addressing Modes
H8/300H supports eight addressing modes listed table 2.11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. manipulation instructions register direct, register indirect, absolute (@aa:8) addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2.11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16, ERn)/@(d:24, ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, @@aa:8
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Register Direct-Rn: register field instruction code specifies 16-, 32-bit register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn), lower bits which contain address operand. Register Indirect with Displacement-@(d:16, ERn) @(d:24, ERn): 16-bit 24-bit displacement contained instruction code added contents address register (ERn) specified register field instruction, lower bits specify address memory operand. 16-bit displacement sign-extended when added. Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) lower bits which contain address memory operand. After operand accessed, added address register contents bits) stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, lower bits result become address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, resulting register value should even. Absolute Address-@aa:8, @aa:16, @aa:24: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24). 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 24-bit absolute address access entire address space. Table 2.12 indicates accessible address ranges.
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Table 2.12 Absolute Address Access Ranges
Absolute Address bits (@aa:8) bits (@aa:16) 1-Mbyte Modes H'FFF00 H'FFFFF (1048320 1048575) H'00000 H'07FFF, H'F8000 H'FFFFF 32767, 1015808 1048575) H'00000 H'FFFFF 1048575) 16-Mbyte Modes H'FFFF00 H'FFFFFF (16776960 16777215) H'000000 H'007FFF, H'FF8000 H'FFFFFF 32767, 16744448 16777215) H'000000 H'FFFFFF 16777215)
bits (@aa:24)
Immediate-#xx:8, #xx:16, #xx:32: instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. instruction codes ADDS, SUBS, INC, instructions contain immediate data implicitly. instruction codes some manipulation instructions contain 3-bit immediate data specifying number. TRAPA instruction code contains 2-bit immediate data specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction code signextended bits added 24-bit contents generate 24-bit branch address. value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. memory operand accessed longword access. first byte memory operand ignored, generating 24-bit branch address. figure 2.9. upper bits 8-bit absolute address assumed (H'0000), address range (H'000000 H'0000FF). Note that first part this range also exception vector area. further details section Interrupt Controller.
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Specified @aa:8
Reserved
Branch address
Figure Memory-Indirect Branch Address Specification When word-size longword-size memory operand specified, when branch address specified, specified memory address odd, least significant regarded accessed data instruction code therefore begins preceding address. section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation
Table 2.13 explains effective address calculated each addressing mode. 1-Mbyte operating modes upper bits calculated address ignored order generate 20-bit effective address.
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Table 2.13 Effective Address Calculation
Addressing Mode Instruction Format Register direct (Rn)
Effective Address Calculation
Effective Address Operand general register contents
Register indirect (@ERn)
General register contents
Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
General register contents disp
Sign extension
disp
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
General register contents
Register indirect with pre-decrement @-ERn
General register contents byte operand, word operand, longword operand
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Addressing Mode Instruction Format Absolute address @aa:8
Effective Address Calculation
Effective Address
H'FFFF
@aa:16
Sign extension
@aa:24
Immediate #xx:8, #xx:16, #xx:32
Operand immediate data
Program-counter relative @(d:8, @(d:16,
contents
Sign extension disp
disp
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Addressing Mode Instruction Format Memory indirect @@aa:8
Normal mode
Effective Address Calculation
Effective Address
H'0000
Memory contents
H'00
Advanced mode
H'0000
Memory contents
Legend: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address
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2.8.1
Processing States
Overview
H8/300H five processing states: program execution state, exception-handling state, power-down state, reset state, bus-released state. power-down state includes sleep mode, software standby mode, hardware standby mode. Figure 2.10 classifies processing states. Figure 2.12 indicates state transitions.
Processing states
Program execution state executes program instructions sequence Exception-handling state transient state which executes hardware sequence (saving CCR, fetching vector, etc.) response reset, interrupt, other exception
Bus-released state external been released response request signal from master other than Reset state on-chip supporting modules initialized halted
Power-down state halted conserve power
Sleep mode
Software standby mode
Hardware standby mode
Figure 2.10 Processing States
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2.8.2
Program Execution State
this state executes program instructions normal sequence. 2.8.3 Exception-Handling State
exception-handling state transient state that occurs when alters normal program flow reset, interrupt, trap instruction. fetches starting address from exception vector table branches that address. interrupt trap exception handling references stack pointer (ER7) saves program counter condition code register. Types Exception Handling Their Priority: Exception handling performed resets, interrupts, trap instructions. Table 2.14 indicates types exception handling their priority. Trap instruction exceptions accepted times program execution state. Table 2.14 Exception Handling Types Priority
Priority High Type Exception Reset Interrupt Detection Timing Synchronized with clock instruction execution exception handling* When TRAPA instruction executed Start Exception Handling Exception handling starts immediately when changes from high When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed
Trap instruction
Note: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling.
Figure 2.11 classifies exception sources. further details about exception sources, vector numbers, vector addresses, section Exception Handling, section Interrupt Controller.
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Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction
Figure 2.11 Classification Exception Sources
release request Program execution state release request Exception Bus-released state exception handling Exception-handling state
SLEEP instruction with SSBY Sleep mode
Interrupt NMI, interrupt
SLEEP instruction with SSBY
Software standby mode
High STBY High, Reset state*1
Hardware standby mode Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2.12 State Transitions
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2.8.4
Exception-Handling Sequences
Reset Exception Handling: Reset exception handling highest priority. reset state entered when signal goes low. Reset exception handling starts after that, when changes from high. When reset exception handling starts fetches start address from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception-handling sequence immediately after ends. Interrupt Exception Handling Trap Instruction Exception Handling: When these exception-handling sequences begin, references stack pointer (ER7) pushes program counter condition code register stack. Next, system control register (SYSCR) sets condition code register cleared sets both condition code register Then fetches start address from exception vector table execution branches that address. Figure 2.13 shows stack after exception-handling sequence.
SP-4 SP-3 SP-2 SP-1 (ER7) Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling starts Legend CCR: Condition code register Stack pointer
Pushed stack
After exception handling ends
Notes: address first instruction executed after return from exception-handling routine. Registers must saved restored word access longword access, starting even address.
Figure 2.13 Stack Structure after Exception Handling
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2.8.5
Bus-Released State
this state released master other than CPU, response request. masters other than controller, refresh controller, external master. While released, halts except internal operations. Interrupt requests accepted. details section 6.3.7, Arbiter Operation. 2.8.6 Reset State
When input goes current processing stops enters reset state. condition code register reset. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details section Watchdog Timer. 2.8.7 Power-Down State
power-down state stops operating conserve power. There three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: transition sleep mode made SLEEP instruction executed while SSBY cleared system control register (SYSCR). operations stop immediately after execution SLEEP instruction, contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SYSCR. clock halt on-chip supporting modules stop operating. on-chip supporting modules reset, long specified voltage supplied contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY input goes low. software standby mode, clocks halt on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained. further information section Power-Down State.
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2.9.1
Basic Operational Timing
Overview
H8/300H operates according system clock interval from rise system clock next rise referred "state." memory cycle cycle consists three states. uses different methods access on-chip memory, on-chip supporting modules, external address space. Access external address space controlled controller. 2.9.2 On-Chip Memory Access Timing
On-chip memory accessed states. data bits wide, permitting both byte word access. Figure 2.14 shows on-chip memory access cycle. Figure 2.15 indicates states.
cycle state Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access) Write data Read data Address state
Figure 2.14 On-Chip Memory Access Cycle
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Address Address
High High impedance
Figure 2.15 States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing
on-chip supporting modules accessed three states. data bits wide, depending register being accessed. Figure 2.16 shows on-chip supporting module access timing. Figure 2.17 indicates states.
cycle state Address Internal read signal Internal data Address state state
Read access
Read data
Internal write signal Write access Internal data Write data
Figure 2.16 Access Cycle On-Chip Supporting Modules
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Address
Address
High High impedance
Figure 2.17 States during Access On-Chip Supporting Modules 2.9.4 Access External Address Space
external address space divided into eight areas (areas Bus-controller settings determine whether each area accessed 8-bit 16-bit bus, whether accessed three states. details section Controller.
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Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8/3052F seven operating modes (modes that selected mode pins (MD2 MD0) indicated table 3.1. input these pins determines size address space initial mode. Table Operating Mode Selection
Mode Pins Operating Mode* Mode Mode Mode Mode Mode Mode Mode Address Space Expanded mode Expanded mode Expanded mode Expanded mode Expanded mode Expanded mode Single-chip advanced mode Description Initial Mode*
On-Chip Disabled Disabled Disabled Disabled Enabled Enabled Enabled
On-Chip Enabled* Enabled* Enabled* Enabled* Enabled* Enabled* Enabled
bits bits bits bits bits bits
Notes: modes 8-bit 16-bit data selected per-area basis settings made area width control register (ABWCR). details section Controller. RAME SYSCR cleared these addresses become external addresses. These operating modes when operating modes when section ROM.
address space size there choices: Mbyte Mbytes. external data either bits wide depending ABWCR settings. 8-bit access selected areas, external data bits wide. details section Controller. Modes externally expanded modes that enable access external memory peripheral devices disable access on-chip ROM. Modes support maximum address space Mbyte. Modes support maximum address space Mbytes.
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Modes externally expanded modes that enable access external memory peripheral devices also enable access on-chip ROM. Mode supports maximum address space Mbyte. Mode supports maximum address space Mbytes. Mode single-chip mode that operates using on-chip ROM, RAM, Internal registers, makes ports available. Mode supports 1-Mbyte address space. H8/3052F used only modes inputs mode pins must select these seven modes. inputs mode pins must changed during operation. 3.1.2 Register Configuration
H8/3052F mode control register (MDCR) that indicates inputs mode pins (MD2 MD0), system control register (SYSCR). Table summarizes these registers. Table
Address* H'FFF1 H'FFF2
Registers
Name Mode control register System control register Abbreviation MDCR SYSCR Initial Value Undetermined H'0B
Note: lower bits address indicated.
Mode Control Register (MDCR)
MDCR 8-bit read-only register that indicates current operating mode H8/3052F.
Initial value Read/Write Reserved bits MDS2 MDS1 MDS0
Reserved bits
Mode select Bits indicating current operating mode
Note: Determined pins
Bits 6-Reserved: Read-only bits, always read Bits 3-Reserved: Read-only bits, always read
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Bits 0-Mode Select (MDS2 MDS0): These bits indicate logic levels pins (the current operating mode). MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits. mode (MD2 MD0) levels latched into these bits when MDCR read.
System Control Register (SYSCR)
SYSCR 8-bit register that controls operation H8/3052F.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG RAME enable Enables disables on-chip Reserved edge select Selects valid edge input User enable Selects whether user interrupt mask Standby timer select These bits select waiting time recovery from software standby mode Software standby Enables transition software standby mode
7-Software Standby (SSBY): Enables transition software standby mode. (For further information about software standby mode section Power-Down State.) When software standby mode exited external interrupt, this remains clear this bit, write
SSBY Description SLEEP instruction causes transition sleep mode SLEEP instruction causes transition software standby mode (Initial value)
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Bits 4-Standby Timer Select (STS2 STS0): These bits select length time on-chip supporting modules wait internal clock oscillator settle when software standby mode exited external interrupt. When using crystal oscillator, these bits that waiting time will least system clock rate. further information about waiting time selection, section 20.4.3, Selection Waiting Time Exit from Software Standby Mode.
STS2 STS1 STS0 Description Waiting time 8,192 states Waiting time 16,384 states Waiting time 32,768 states Waiting time 65,536 states Waiting time 131,072 states Waiting time 1,024 states Illegal setting (Initial value)
3-User Enable (UE): Selects whether condition code register user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge interrupt requested rising edge (Initial value)
1-Reserved: Read-only bit, always read 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized rising edge signal. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
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3.4.1
Operating Mode Descriptions
Mode
Ports function address pins permitting access maximum 1-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. 3.4.2 Mode
Ports function address pins permitting access maximum 1-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. 3.4.3 Mode
Ports part port function address pins permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. valid when written bits release control register (BRCR). this mode always used address output.) 3.4.4 Mode
Ports part port function address pins permitting access maximum 16-Mbyte address space. initial mode after reset bits, with 16-bit access areas. areas designated 8-bit access ABWCR, mode switches bits. valid when written bits BRCR. this mode always used address output.) 3.4.5 Mode
Ports function address pins permitting access maximum 1-Mbyte address space, following reset they input ports. ports address bus, corresponding bits their data direction registers (P1DDR, P2DDR, P5DDR) must initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits.
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3.4.6
Mode
Ports part port function address pins permitting access maximum 16-Mbyte address space, following reset they input ports. ports address bus, corresponding bits their data direction registers (P1DDR, P2DDR, P5DDR) must output, clear bits BRCR this mode always used address output.) initial mode after reset bits, with 8-bit access areas. least area designated 16-bit access ABWCR, mode switches bits. 3.4.7 Mode
This mode operates using on-chip ROM, RAM, registers. ports available. Mode supports 1-Mbyte address space.
Functions Each Operating Mode
functions ports port vary depending operating mode. Table indicates their functions each operating mode. Table
Port Port Port Port Port Port Port
Functions Each Mode
Mode D0*1 Mode P40*1 Mode D0*1 Mode P10* P20* P40*1 P50*2
Mode P40*1
Mode P10* P20* P40*1 P50*2 PA5, A20*3
Mode
PA5*3, PA5*3,
Notes: Initial state. mode switched settings ABWCR. These pins function 8-bit mode, 16-bit mode. Initial state. These pins become address output pins when corresponding bits data direction registers (P1DDR, P2DDR, P5DDR) Initial state. always address output pin. switched over output writing bits BRCR.
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Memory Each Operating Mode
Figure shows memory H8/3052F. address space divided into eight areas. initial mode differs between modes also between modes address locations on-chip on-chip registers differ between 1-Mbyte modes (modes 16-Mbyte modes (modes address range specifiable 16-bit absolute addressing modes (@aa:8 @aa:16) also differs.
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Modes (1-Mbyte expanded modes with on-chip disabled)
Modes (16-Mbyte expanded modes with on-chip disabled) Vector area
Memory-indirect branch addresses
16-bit absolute addresses
H'000FF
H'0000FF
H'07FFF
H'007FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000
Area Area Area Area Area Area Area Area H'7FFFFF H'800000 H'9FFFFF H'A00000 H'5FFFFF H'600000 External address space H'3FFFFF H'400000 H'1FFFFF H'200000
Area
Area
Area
Area
Area H'F8000
16-bit absolute addresses
H'FDF0F H'FDF10
Area H'BFFFFF H'C00000 Area H'DFFFFF H'E00000 Area
H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF
External address space Internal registers
8-bit absolute addresses
On-chip
H'FF8000
H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C H'FFFFFF Note: External addresses accessed disabling on-chip RAM.
External address space Internal registers
Figure H8/3052F Memory Each Operating Mode
Rev. 2.0, 03/01, page
8-bit absolute addresses
On-chip
16-bit absolute addresses
H'FFDF0F H'FFDF10
16-bit absolute addresses
Vector area
Memory-indirect branch addresses
H'00000
H'000000
Mode (1-Mbyte expanded mode with on-chip enabled)
Mode (16-Mbyte expanded mode with on-chip enabled)
Mode (single-chip advanced mode) H'00000
Memory-indirect branch addresses
Memory-indirect branch addresses
16-bit absolute addresses
16-bit absolute addresses
H'000FF On-chip H'07FFF
H'0000FF On-chip H'007FFF
H'000FF On-chip H'07FFF H'7FFFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 H'7FFFF H'80000 External address space H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000
Area Area Area Area Area Area Area Area
H'07FFFF H'080000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000
Area
Area
Area External address space
Area
Area
H'F8000
H'F8000 H'FDF10 H'FFF00 H'FFF0F
16-bit absolute addresses
8-bit absolute addresses
H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF
External address space Internal registers
H'DFFFFF H'E00000
Area
Area H'FF8000
H'FFF1C H'FFFFF
Internal registers
H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C H'FFFFFF
External address space Internal registers
Note: External addresses accessed disabling on-chip RAM.
Figure H8/3052F Memory Each Operating Mode (cont)
8-bit absolute addresses
On-chip
16-bit absolute addresses
H'FFDF0F H'FFDF10
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8-bit absolute addresses
On-chip
H'BFFFFF H'C00000
Area
On-chip
16-bit absolute addresses
H'FDF0F H'FDF10
16-bit absolute addresses
Vector area
Vector area
Vector area
Memory-indirect branch addresses
H'00000
H'000000
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Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 4.1. more exceptions occur simultaneously, they accepted processed priority order. Trap instruction exceptions accepted times program execution state. Table
Priority High
Exception Types Priority
Exception Type Reset Interrupt Start Exception Handling Starts immediately after low-to-high transition Interrupt requests handled when execution current instruction handling current exception completed Started execution trap instruction (TRAPA)
Trap instruction (TRAPA)
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows. program counter (PC) condition code register (CCR) pushed onto stack. interrupt mask vector address corresponding exception source generated, program execution starts from address indicated that address. reset exception, steps above carried out.
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4.1.3
Exception Sources Vector Table
exception sources classified shown figure 4.1. Different vectors assigned different exception sources. Table lists exception sources their vector addresses.
Reset External interrupts: NMI, IRQ5 Exception sources Interrupts Internal interrupts: interrupts from on-chip supporting modules
Trap instruction
Figure Exception Sources
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Table
Exception Vector Table
Vector Number Vector Address* H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'00F0 H'00F3
Exception Source Reset Reserved system
External interrupt (NMI) Trap instruction sources)
External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 Reserved system Internal interrupts*
Notes: Lower bits address. internal interrupt vectors, section 5.3.3, Interrupt Vector Table.
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4.2.1
Reset
Overview
reset highest-priority exception. When goes low, processing halts chip enters reset state. reset initializes internal state registers on-chip supporting modules. Reset exception handling begins when changes from high. chip also reset overflow watchdog timer. details section Watchdog Timer. 4.2.2 Reset Sequence
chip enters reset state when goes low. ensure that chip reset, hold least power-up. reset chip during operation, hold least system clock cycles. appendix D.2, States Reset, states pins reset state. When goes high after being held necessary time, chip starts reset exception handling follows. internal state registers on-chip supporting modules initialized, CCR. contents reset vector address (H'0000 H'0003) read, program execution starts from address indicated vector address. Figure shows reset sequence modes Figure shows reset sequence modes Figure shows reset sequence modes
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Vector fetch
Internal processing
Prefetch first program instruction
Address
High (10)
Figure Reset Sequence (Modes
Address reset vector: H'00000, H'00001, H'00002, H'00003 Start address (contents reset vector) Start address First instruction program
(1), (3), (5), (2), (4), (6), (10)
Rev. 2.0, 03/01, page
Note: After reset, wait-state controller inserts three wait states every cycle.
Vector fetch
Internal processing
Prefetch first program instruction
Address
High
(1), (2),
Address reset vector: H'000000, H'000002 Start address (contents reset vector) Start address First instruction program
Note: After reset, wait-state controller inserts three wait states every cycle.
Figure Reset Sequence (Modes
Rev. 2.0, 03/01, page
Vector fetch
Internal processing
Prefetch first program instruction
Internal address Internal read signal Internal write signal Internal data bits wide)
(1), (2),
Address reset vector ((1) H'000000, H'000002) Start address (contents reset vector) Start address First instruction program
Figure Reset Sequence (Modes 4.2.3 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. first instruction program always executed immediately after reset state ends. This instruction should initialize stack pointer (example: MOV.L #xx:32, SP).
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Interrupts
Interrupt exception handling requested seven external sources (NMI, IRQ0 IRQ5) internal sources on-chip supporting modules. Figure classifies interrupt sources indicates number interrupts each type. on-chip supporting modules that request interrupts watchdog timer (WDT), refresh controller, 16-bit integrated timer unit (ITU), controller (DMAC), serial communication interface (SCI), converter. Each interrupt source separate vector address. highest-priority interrupt always accepted. Interrupts controlled interrupt controller. interrupt controller assign interrupts other than priority levels, arbitrate between simultaneous interrupts. Interrupt priorities assigned interrupt priority registers (IPRA IPRB) interrupt controller. details interrupts section Interrupt Controller.
External interrupts Interrupts
Refresh controller (15) DMAC converter
Internal interrupts
Notes: Numbers parentheses number interrupt sources. When watchdog timer used interval timer, generates interrupt request every counter overflow. When refresh controller used interval timer, generates interrupt request compare match.
Figure Interrupt Sources Number Interrupts
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Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. system control register (SYSCR), exception handling sequence sets CCR. bits both TRAPA instruction fetches start address from vector table entry corresponding vector number from which specified instruction code.
Stack Status after Exception Handling
Figure shows stack after completion trap instruction exception handling interrupt exception handling.
SP-4 SP-3 SP-2 SP-1 (ER7)
Stack area
(ER7) SP+1 SP+2 SP+3 SP+4
Even address
Before exception handling Pushed stack
After exception handling
Legend PCE: Bits program counter (PC) PCH: Bits program counter (PC) PCL: Bits program counter (PC) CCR: Condition code register Stack pointer Notes: indicates address first instruction that will executed after return. Register saving restoration must carried word longword size even addresses.
Figure Stack after Completion Exception Handling
Rev. 2.0, 03/01, page
Notes Stack
When accessing word data longword data, H8/3052F regards lowest address stack should always accessed word access longword access, value stack pointer (SP, ER7) should always kept even. following instructions save registers: PUSH.W MOV.W @-SP) PUSH.L MOV.L ERn, @-SP) following instructions restore registers: POP.W POP.L MOV.W @SP+, MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
H'FFFEFA H'FFFEFB
H'FFFEFC H'FFFEFD
H'FFFEFF
TRAPA instruction executed
MOV. R1L, @-ER7
H'FFFEFF Legend CCR: Condition code register Program counter R1L: General register Stack pointer
Data saved above
contents lost
Note: diagram illustrates modes
Figure Operation when Value
Rev. 2.0, 03/01, page
Section Interrupt Controller
5.1.1
Overview
Features
interrupt controller following features: Interrupt priority registers (IPRs) setting interrupt priorities Interrupts other than assigned priority levels source-by-source module-by-module basis interrupt priority registers (IPRA IPRB). Three-level masking bits condition code register (CCR) Independent vector addresses interrupts independently vectored; interrupt service routine does have identify interrupt source. Seven external interrupt pins highest priority always accepted; either rising falling edge selected. each IRQ0 IRQ5, falling edge level sensing selected independently.
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5.1.2
Block Diagram
Figure shows block diagram interrupt controller.
ISCR input input ADIE input section Priority decision logic IPRA, IPRB
Interrupt request Vector number
Interrupt controller SYSCR Legend ISCR: IER: ISR: IPRA: IPRB: SYSCR: sense control register enable register status register Interrupt priority register Interrupt priority register System control register
Figure Interrupt Controller Block Diagram
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5.1.3
Configuration
Table lists interrupt pins. Table
Name Nonmaskable interrupt External interrupt request
Interrupt Pins
Abbreviation IRQ5 IRQ0 Input Input Function Nonmaskable external interrupt, rising edge falling edge selectable Maskable external interrupts, falling edge level sensing selectable
5.1.4
Register Configuration
Table lists registers interrupt controller. Table
Address* H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFF9
Interrupt Controller Registers
Name System control register sense control register enable register status register Interrupt priority register Interrupt priority register Abbreviation SYSCR ISCR IPRA IPRB R/(W)*
Initial Value H'0B H'00 H'00 H'00 H'00 H'00
Notes: Lower bits address. Only written, clear flags.
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5.2.1
Register Descriptions
System Control Register (SYSCR)
SYSCR 8-bit readable/writable register that controls software standby mode, selects action CCR, selects edge, enables disables on-chip RAM. Only bits described here. other bits, section 3.3, System Control Register (SYSCR). SYSCR initialized H'0B reset hardware standby mode. initialized software standby mode.
Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG RAME
enable Reserved Standby timer select Software standby edge select Selects input edge User enable Selects whether user interrupt mask
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3-User Enable (UE): Selects whether user interrupt mask bit.
Description used interrupt mask used user (Initial value)
2-NMI Edge Select (NMIEG): Selects input edge.
NMIEG Description Interrupt requested falling edge input Interrupt requested rising edge input (Initial value)
5.2.2
Interrupt Priority Registers (IPRA, IPRB)
IPRA IPRB 8-bit readable/writable registers that control interrupt priority.
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Interrupt Priority Register (IPRA): IPRA 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Priority level Selects priority level refresh controller interrupt requests Priority level Selects priority level IRQ4 interrupt requests Priority level Selects priority level interrupt requests Priority level Selects priority level IRQ1 interrupt requests Priority level Selects priority level interrupt requests
IPRA initialized H'00 reset hardware standby mode.
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7-Priority Level (IPRA7): Selects priority level IRQ0 interrupt requests.
IPRA7 Description IRQ0 interrupt requests have priority level (Non-priority) IRQ0 interrupt requests have priority level (Priority) (Initial value)
6-Priority Level (IPRA6): Selects priority level IRQ1 interrupt requests.
IPRA6 Description IRQ1 interrupt requests have priority level (Non-priority) IRQ1 interrupt requests have priority level (Priority) (Initial value)
5-Priority Level (IPRA5): Selects priority level IRQ2 IRQ3 interrupt requests.
IPRA5 Description IRQ2 IRQ3 interrupt requests have priority level (Non-priority) (Initial value) IRQ2 IRQ3 interrupt requests have priority level (Priority)
4-Priority Level (IPRA4): Selects priority level IRQ4 IRQ5 interrupt requests.
IPRA4 Description IRQ4 IRQ5 interrupt requests have priority level (Non-priority) (Initial value) IRQ4 IRQ5 interrupt requests have priority level (Priority)
3-Priority Level (IPRA3): Selects priority level refresh controller interrupt requests.
IPRA3 Description refresh controller interrupt requests have priority level (Non-priority) (Initial value) refresh controller interrupt requests have priority level (Priority)
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2-Priority Level (IPRA2): Selects priority level channel interrupt requests.
IPRA2 Description channel interrupt requests have priority level (Non-priority) (Initial value) channel interrupt requests have priority level (Priority)
1-Priority Level (IPRA1): Selects priority level channel interrupt requests.
IPRA1 Description channel interrupt requests have priority level (Non-priority) (Initial value) channel interrupt requests have priority level (Priority)
0-Priority Level (IPRA0): Selects priority level channel interrupt requests.
IPRA0 Description channel interrupt requests have priority level (Non-priority) (Initial value) channel interrupt requests have priority level (Priority)
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Interrupt Priority Register (IPRB): IPRB 8-bit readable/writable register which interrupt priority levels set.
Initial value Read/Write IPRB7 IPRB6 IPRB5 IPRB3 IPRB2 IPRB1
Reserved Priority level Selects priority level converter interrupt request Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests Reserved
Priority level Selects priority level DMAC interrupt requests (channels Priority level Selects priority level channel interrupt requests Priority level Selects priority level channel interrupt requests
IPRB initialized H'00 reset hardware standby mode.
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7-Priority Level (IPRB7): Selects priority level channel interrupt requests.
IPRB7 Description channel interrupt requests have priority level (low priority) (Initial value) channel interrupt requests have priority level (high priority)
6-Priority Level (IPRB6): Selects priority level channel interrupt requests.
IPRB6 Description channel interrupt requests have priority level (low priority) (Initial value) channel interrupt requests have priority level (high priority)
5-Priority Level (IPRB5): Selects priority level DMAC interrupt requests (channels
IPRB5 Description DMAC interrupt requests (channels have priority level (low priority) (Initial value) DMAC interrupt requests (channels have priority level (high priority)
4-Reserved: This written read, does affect interrupt priority.
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3-Priority Level (IPRB3): Selects priority level channel interrupt requests.
IPRB3 Description SCI0 interrupt requests have priority level (low priority) SCI0 interrupt requests have priority level (high priority) (Initial value)
2-Priority Level (IPRB2): Selects priority level channel interrupt requests.
IPRB2 Description SCI1 interrupt requests have priority level (low priority) SCI1 interrupt requests have priority level (high priority) (Initial value)
1-Priority Level (IPRB1): Selects priority level converter interrupt requests.
IPRB1 Description converter interrupt requests have priority level (low priority) (Initial value) converter interrupt requests have priority level (high priority)
0-Reserved: This written read, does affect interrupt priority.
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5.2.3
Status Register (ISR)
8-bit readable/writable register that indicates status IRQ0 IRQ5 interrupt requests.
Initial value Read/Write IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)*
Reserved bits
IRQ0 flags These bits indicate interrupt request status
Note: Only written, clear flags.
initialized H'00 reset hardware standby mode. Bits 6-Reserved: Read-only bits, always read Bits 0-IRQ5 IRQ0 Flags (IRQ5F IRQ0F): These bits indicate status IRQ5 IRQ0 interrupt requests.
Bits IRQ5F IRQ0F Description [Clearing conditions] (Initial value) written IRQnF after reading IRQnF flag when IRQnF IRQnSC IRQn input high, interrupt exception handling carried out. IRQnSC IRQn interrupt exception handling carried out. [Setting conditions] IRQnSC IRQn input low. IRQnSC falling edge occurs IRQn input Note:
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5.2.4
Enable Register (IER)
8-bit readable/writable register that enables disables IRQ0 IRQ5 interrupt requests.
Initial value Read/Write IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Reserved bits
IRQ0 enable These bits enable disable interrupts
initialized H'00 reset hardware standby mode. Bits 6-Reserved: These bits written read, they enable disable interrupts. Bits 0-IRQ5 IRQ0 Enable (IRQ5E IRQ0E): These bits enable disable IRQ5 IRQ0 interrupts.
Bits IRQ5E IRQ0E Description IRQ5 IRQ0 interrupts disabled IRQ5 IRQ0 interrupts enabled (Initial value)
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5.2.5
Sense Control Register (ISCR)
ISCR 8-bit readable/writable register that selects level sensing falling-edge sensing inputs pins IRQ5 IRQ0.
Initial value Read/Write
IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Reserved bits
IRQ0 sense control These bits select level sensing falling-edge sensing interrupts
ISCR initialized H'00 reset hardware standby mode. Bits 6-Reserved: These bits written read, they select level falling-edge sensing. Bits 0-IRQ5 IRQ0 Sense Control (IRQ5SC IRQ0SC): These bits select whether interrupts IRQ5 IRQ0 requested level sensing pins IRQ5 IRQ0, falling-edge sensing.
Bits IRQ5SC IRQ0SC Description Interrupts requested when IRQ5 IRQ0 inputs Interrupts requested falling-edge input IRQ5 IRQ0 (Initial value)
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Interrupt Sources
interrupt sources include external interrupts (NMI, IRQ0 IRQ5) internal interrupts. 5.3.1 External Interrupts
There seven external interrupts: NMI, IRQ0 IRQ5. these, NMI, IRQ0, IRQ1, IRQ2 used exit software standby mode. NMI: highest-priority interrupt always accepted, regardless states bits CCR. NMIEG SYSCR selects whether interrupt requested rising falling edge input pin. interrupt exception handling vector number IRQ0 IRQ5 Interrupts: These interrupts requested input signals pins IRQ0 IRQ5. IRQ0 IRQ5 interrupts have following features. ISCR settings select whether interrupt requested level input pins IRQ0 IRQ5, falling edge. settings enable disable IRQ0 IRQ5 interrupts. Interrupt priority levels assigned four bits IPRA (IPRA7 IPRA4). status IRQ0 IRQ5 interrupt requests indicated ISR. flags cleared software. Figure shows block diagram interrupts IRQ0 IRQ5.
IRQnSC IRQnF Edge/level sense circuit input Clear signal Note: IRQn interrupt request IRQnE
Figure Block Diagram Interrupts IRQ0 IRQ5
Rev. 2.0, 03/01, page
Figure shows timing setting interrupt flags (IRQnF).
input IRQnF Note:
Figure Timing Setting IRQnF Interrupts IRQ0 IRQ5 have vector numbers These interrupts detected regardless whether corresponding input output. When using external interrupt input, clear chip select output, refresh output, input output. 5.3.2 Internal Interrupts
Thirty internal interrupts requested from on-chip supporting modules. Each on-chip supporting module status flags indicating interrupt status, enable bits enabling disabling interrupts. Interrupt priority levels assigned IPRA IPRB. interrupt requests activate DMAC, which case interrupt request sent interrupt controller, bits disregarded. 5.3.3 Interrupt Exception Vector Table
Table lists interrupt sources, their vector addresses, their default priority order. default priority order, smaller vector numbers have higher priority. priority interrupts other than changed IPRA IPRB. priority order after reset default order shown table 5.3.
Rev. 2.0, 03/01, page
Table
Interrupt Sources, Vector Addresses, Priority
Origin External pins Vector Number Watchdog timer Refresh controller channel Vector Address* H'001C H'001F H'0030 H'0033 H'0034 H0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 IPRA2 IPRA3 IPRA4 IPRA7 IPRA6 IPRA5 Priority High
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved WOVI (interval timer) (compare match) Reserved IMIA0 (compare match/ input capture IMIB0 (compare match/ input capture OVI0 (overflow Reserved IMIA1 (compare match/ input capture IMIB1 (compare match/ input capture OVI1 (overflow Reserved
H'0064 H'0067
channel
H'0068 H'006B H'006C H'006F H'0070 H'0073 IPRA1
H'0074 H'0077
H'0078 H'007B H'007C H'007F
Rev. 2.0, 03/01, page
Interrupt Source IMIA2 (compare match/ input capture IMIB2 (compare match/ input capture OVI2 (overflow Reserved IMIA3 (compare match/ input capture IMIB3 (compare match/ input capture OVI3 (overflow Reserved IMIA4 (compare match/ input capture IMIB4 (compare match/ input capture OVI4 (overflow Reserved DEND0A DEND0B DEND1A DEND1B Reserved
Origin channel
Vector Number
Vector Address* H'0080 H'0083<b
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