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revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
Hitachi 16-Bit Single-Chip Microcomputer
H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series
Hardware Manual
Specifications Common Series
ADE-602-171A Rev. 8/1/03 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series series high-performance microcontrollers with 32-bit H8S/2000 core, on-chip supporting functions required system configuration. H8S/2000 execute basic instructions state, provided with sixteen 16-bit general registers with 32-bit internal configuration, concise optimized instruction set. handle 16-Mbyte linear address space (architecturally Gbytes). Programs based high-level language also efficiently. address space divided into eight areas. data width access states selected each these areas, various kinds memory connected fast easily. Single-power-supply flash memory (F-ZTATTM) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. On-chip supporting functions include 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. addition, on-chip controller (DMAC) data transfer controller (DTC) provided, enabling high-speed data transfer without intervention. H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series enables easy implementation compact, high-performance systems capable processing large volumes data. This manual describes hardware H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series, covering features, specifications, registers operation. should used conjunction with H8S/2339, H8S/2338 Series Reference Manual, H8S/2329, H8S/2328 Series Reference Manual, H8S/2319, H8S/2318 Series Reference Manual which contain information relating H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series hardware- including specifications register descriptions-required system design. Refer H8S/2600 Series, H8S/2000 Series Programming Manual detailed description instruction programming-related information.
Main Revisions Additions this Edition
Page Table1-1 Overview Item Revisions Amendments associated with addition H8S/2339, H8S/2329, H8S/2319, H8S/2315 CPU: clock rate, arithmetic operation speed amended Operating modes: amended according series Table Interrupt Sources, Vector Addresses, Interrupt Priorities Table Interrupt Response Times Figure 4-25 Refresh Timing Figure 4-26 Refresh Timing Figure 4-28 DACK Output Timing when Figure 4-29 DACK Output Timing when Table States Idle Cycle Figure 4-36 Example Timing when Write Data Buffer Function Used Table States Released State Table Overview DMAC Functions Table Overview DMAC Functions interrupt source names amended (RXI0, RXI1, RXI2: receive-data-full Amendment expression "Number wait states until executing instruction ends" Note added Note added Note added Note added Note amended Note added Note added transfer source names amended interrupt) transfer source names amended interrupt)
124, 195,
5.2.4 Control Register (DMACR) Tables Channel Channel transfer source names amended 5.3.4 Control Register (DMACR) Table Block Transfer Mode transfer source names amended Table DMAC Transfer Modes Usage Notes transfer source names amended interrupt) Description added
6.2.8 Vector Register (DTVECR) Note amended description amended Table Interrupt Sources, Vector Addresses, Corresponding DTCEs DMAC interrupt sources added interrupt source name amended
Page
Item 10.2.2 Timer Control/Status Register (TCSR) Table 11-3 Settings Various Rates (Asynchronous Mode) Table 11-4 Settings Various Rates (Synchronous Mode)
Revisions Note added Note deleted Note amended
Table 11-5 Maximum Rate Each Note deleted Frequency (Asynchronous Mode) Table 11-6 Maximum Rate with External Clock Input (Asynchronous Mode) Table 11-7 Maximum Rate with External Clock Input (Synchronous Mode) Table 12-5 Examples Rate (bits/s) Various Settings (When 372) Note deleted
Note deleted
Note amended
Table 12-6 Example Settings Note deleted Rate (bits/s) (When 372) Table 12-7 Maximum Rate Various Frequencies (Smart Card Interface Mode) (When 372) Note deleted
13.6 Usage Notes Vref input range Description added Impedance value amended
Permissible Signal Source Impedance
Figure 13-10 Example Analog Input Impedance value amended Circuit 14.6 Usage Notes Vref input range Description added Amendments associated with addition H8S/2339, H8S/2329, H8S/2319, H8S/2315 Flash memory description divided into following three sections according products: 17.4 17.12 H8S/2339, H8S/2329 17.13 17.21: H8S/2338, H8S/2328, H8S/2318, H8S/2315 17.22 17.30: H8S/2319
Section
542,
Table 17-2 Operating Modes Note added (H8S/2338, H8S/2328, H8S/2318, H8S/2315F-ZTAT Versions)
Page
Item 17.4 17.12 17.13.1 Features Table 17-32 System Clock Frequencies which Automatic Adjustment H8S/2338, H8S/2328, H8S/2318, H8S/2315F-ZTAT Rate Possible 17.15.2 User Program Mode
Revisions Added Programming/erase times: values amended Frequencies amended
Description added When program located external memory,.should located on-chip RAM. Description added When program located external memory,.The DMAC should activated.the flash memory executed. Legend added wait times after bits cleared FLMCR1: Unit overflow period amended Description amended After bytes data.then clear FLMCR1 wait again least
17.16 Programming/Erasing Flash Memory
17.16.1 Program Mode
17.16.2 Program-Verify Mode
Figure 17-42 Program/Program-Verify Amended Flowchart 17.16.3 Erase Mode 17.16.4 Erase-Verify Mode Legend added wait times after bits cleared FLMCR1: Description amended erasure been completed.wait least Wait time after clearing amended Added Note instruction added Note STM/LDM instruction added
Figure 17-43 Erase/Erase-Verify Flowchart 17.22 17.30 Appendix Instruction
Organization H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual
H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual describes operation on-chip functions common H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series, particular, gives detailed description related registers. Information specific individual products, including arrangement, ports, operating modes (memory maps), interrupt vectors, control, electrical characteristics, found Reference Manual relevant product.
product evaluation information, comparative specification information current users Hitachi products
specifications Overview arrangement diagram Block diagrams function modules functions Electrical characteristics Overview Arrangement Section Peripheral Block Diagrams Functions Section Electrical Characteristics
detailed information functions
details operation individual modules port information Interrupts exception handling functions Section Ports Section Exception Handling Interrupt Controller Functions
information operating modes List Detailed descriptions Functions Each Operating Mode Section Operating Modes
design material
information registers List find register from address find register information function Section registers List Registers (Address Order) List Registers Module)
information instructions List Operation description notes Program examples H8S/2600 Series, H8S/2000 Series Programming Manual
Contents
Section Overview
Overview.
Section Exception Handling
Overview. 2.1.1 Exception Handling Types Priority. 2.1.2 Exception Handling Operation 2.1.3 Exception Vector Table Reset. 2.2.1 Overview. 2.2.2 Reset Sequence 2.2.3 Interrupts after Reset. 2.2.4 State On-Chip Supporting Modules after Reset Release. Traces Interrupts Trap Instruction. Stack Status after Exception Handling Notes Stack.
Section Interrupt Controller
Overview. 3.1.1 Features 3.1.2 Block Diagram. 3.1.3 Configuration. 3.1.4 Register Configuration. Register Descriptions 3.2.1 System Control Register (SYSCR). 3.2.2 Interrupt Priority Registers (IPRA IPRK) 3.2.3 Enable Register (IER) 3.2.4 Sense Control Registers (ISCRH, ISCRL) 3.2.5 Status Register (ISR) Interrupt Sources. 3.3.1 External Interrupts 3.3.2 Internal Interrupts. 3.3.3 Interrupt Exception Vector Table Interrupt Operation. 3.4.1 Interrupt Control Modes Interrupt Operation 3.4.2 Interrupt Control Mode 3.4.3 Interrupt Control Mode
3.4.4 Interrupt Exception Handling Sequence 3.4.5 Interrupt Response Times Usage Notes 3.5.1 Contention between Interrupt Generation Disabling 3.5.2 Instructions that Disable Interrupts. 3.5.3 Times when Interrupts Disabled 3.5.4 Interrupts during Execution EEPMOV Instruction DMAC Activation Interrupt. 3.6.1 Overview. 3.6.2 Block Diagram. 3.6.3 Operation
Section Controller
Overview. 4.1.1 Features 4.1.2 Block Diagram. 4.1.3 Configuration. 4.1.4 Register Configuration. Register Descriptions 4.2.1 Width Control Register (ABWCR) 4.2.2 Access State Control Register (ASTCR). 4.2.3 Wait Control Registers (WCRH, WCRL) 4.2.4 Control Register (BCRH) 4.2.5 Control Register (BCRL) 4.2.6 Memory Control Register (MCR) 4.2.7 DRAM Control Register (DRAMCR). 4.2.8 Refresh Timer Counter (RTCNT) 4.2.9 Refresh Time Constant Register (RTCOR). Overview Control 4.3.1 Area Partitioning. 4.3.2 Specifications 4.3.3 Memory Interfaces. 4.3.4 Advanced Mode. 4.3.5 Chip Select Signals Basic Interface 4.4.1 Overview. 4.4.2 Data Size Data Alignment. 4.4.3 Valid Strobes 4.4.4 Basic Timing. 4.4.5 Wait Control. DRAM Interface 4.5.1 Overview. 4.5.2 Setting DRAM Space.
4.5.3 Address Multiplexing. 4.5.4 Data Bus. 4.5.5 Pins Used DRAM Interface 4.5.6 Basic Timing. 4.5.7 Precharge State Control 4.5.8 Wait Control. 4.5.9 Byte Access Control 4.5.10 Burst Operation. 4.5.11 Refresh Control. DMAC Single Address Mode DRAM Interface 4.6.1 When 4.6.2 When Burst Interface. 4.7.1 Overview. 4.7.2 Basic Timing. 4.7.3 Wait Control. Idle Cycle 4.8.1 Operation 4.8.2 States Idle Cycle Write Data Buffer Function 4.10 Release. 4.10.1 Overview. 4.10.2 Operation 4.10.3 States External Released State 4.10.4 Transition Timing 4.10.5 Usage Note. 4.11 Arbitration. 4.11.1 Overview. 4.11.2 Operation 4.11.3 Transfer Timing 4.11.4 External Release Usage Note 4.12 Resets Controller.
Section Controller
Overview. 5.1.1 Features 5.1.2 Block Diagram. 5.1.3 Overview Functions. 5.1.4 Configuration. 5.1.5 Register Configuration. Register Descriptions (Short Address Mode). 5.2.1 Memory Address Registers (MAR). 5.2.2 Address Register (IOAR)
5.2.3 Execute Transfer Count Register (ETCR). 5.2.4 Control Register (DMACR) 5.2.5 Band Control Register (DMABCR) Register Descriptions (Full Address Mode) 5.3.1 Memory Address Register (MAR). 5.3.2 Address Register (IOAR) 5.3.3 Execute Transfer Count Register (ETCR). 5.3.4 Control Register (DMACR) 5.3.5 Band Control Register (DMABCR) Register Descriptions 5.4.1 Write Enable Register (DMAWER). 5.4.2 Terminal Control Register (DMATCR) 5.4.3 Module Stop Control Register (MSTPCR). Operation. 5.5.1 Transfer Modes 5.5.2 Sequential Mode 5.5.3 Idle Mode. 5.5.4 Repeat Mode 5.5.5 Single Address Mode. 5.5.6 Normal Mode. 5.5.7 Block Transfer Mode. 5.5.8 DMAC Activation Sources 5.5.9 Basic DMAC Cycles. 5.5.10 DMAC Cycles (Dual Address Mode). 5.5.11 DMAC Cycles (Single Address Mode) 5.5.12 Write Data Buffer Function 5.5.13 DMAC Multi-Channel Operation 5.5.14 Relation Between DMAC External Requests, Refresh Cycles, DTC. 5.5.15 Interrupts DMAC 5.5.16 Forced Termination DMAC Operation 5.5.17 Clearing Full Address Mode. Interrupts Usage Notes
Section Data Transfer Controller
Overview. 6.1.1 Features 6.1.2 Block Diagram. 6.1.3 Register Configuration. Register Descriptions 6.2.1 Mode Register (MRA) 6.2.2 Mode Register (MRB).
6.2.3 Source Address Register (SAR) 6.2.4 Destination Address Register (DAR) 6.2.5 Transfer Count Register (CRA) 6.2.6 Transfer Count Register (CRB). 6.2.7 Enable Registers (DTCER). 6.2.8 Vector Register (DTVECR) 6.2.9 Module Stop Control Register (MSTPCR). Operation. 6.3.1 Overview. 6.3.2 Activation Sources. 6.3.3 Vector Table 6.3.4 Location Register Information Address Space. 6.3.5 Normal Mode. 6.3.6 Repeat Mode 6.3.7 Block Transfer Mode. 6.3.8 Chain Transfer 6.3.9 Operation Timing. 6.3.10 Number Execution States 6.3.11 Procedures Using DTC. 6.3.12 Examples DTC. Interrupts Usage Notes
Section 16-Bit Timer Pulse Unit (TPU)
Overview. 7.1.1 Features 7.1.2 Block Diagram. 7.1.3 Configuration. 7.1.4 Register Configuration. Register Descriptions 7.2.1 Timer Control Registers (TCR) 7.2.2 Timer Mode Registers (TMDR) 7.2.3 Timer Control Registers (TIOR) 7.2.4 Timer Interrupt Enable Registers (TIER) 7.2.5 Timer Status Registers (TSR) 7.2.6 Timer Counters (TCNT) 7.2.7 Timer General Registers (TGR). 7.2.8 Timer Start Register (TSTR) 7.2.9 Timer Synchro Register (TSYR) 7.2.10 Module Stop Control Register (MSTPCR). Interface Master. 7.3.1 16-Bit Registers 7.3.2 8-Bit Registers
Operation. 7.4.1 Overview. 7.4.2 Basic Functions. 7.4.3 ynchronous Operation. 7.4.4 Buffer Operation 7.4.5 Cascaded Operation 7.4.6 Modes 7.4.7 Phase Counting Mode Interrupts 7.5.1 Interrupt Sources Priorities 7.5.2 DTC/DMAC Activation. 7.5.3 Converter Activation. Operation Timing 7.6.1 Input/Output Timing 7.6.2 Interrupt Signal Timing Usage Notes
Section Programmable Pulse Generator (PPG)
Overview. 8.1.1 Features 8.1.2 Block Diagram. 8.1.3 Configuration. 8.1.4 Registers. Register Descriptions 8.2.1 Next Data Enable Registers (NDERH, NDERL) 8.2.2 Output Data Registers (PODRH, PODRL) 8.2.3 Next Data Registers (NDRH, NDRL) 8.2.4 Notes Access 8.2.5 Output Control Register (PCR) 8.2.6 Output Mode Register (PMR) 8.2.7 Port Data Direction Register (P1DDR). 8.2.8 Port Data Direction Register (P2DDR). 8.2.9 Module Stop Control Register (MSTPCR). Operation. 8.3.1 Overview. 8.3.2 Output Timing 8.3.3 Normal Pulse Output 8.3.4 Non-Overlapping Pulse Output 8.3.5 Inverted Pulse Output 8.3.6 Pulse Output Triggered Input Capture. Usage Notes 8.4.1 Operation Pulse Output Pins 8.4.2 Note Non-Overlapping Output
Section 8-Bit Timers
Overview. 9.1.1 Features 9.1.2 Block Diagram. 9.1.3 Configuration. 9.1.4 Register Configuration. Register Descriptions 9.2.1 Timer Counters (TCNT0, TCNT1). 9.2.2 Time Constant Registers (TCORA0, TCORA1). 9.2.3 Time Constant Registers (TCORB0, TCORB1) 9.2.4 Time Control Registers (TCR0, TCR1) 9.2.5 Timer Control/Status Registers (TCSR0, TCSR1) 9.2.6 Module Stop Control Register (MSTPCR). Operation. 9.3.1 TCNT Incrementation Timing. 9.3.2 Compare Match Timing. 9.3.3 Timing TCNT External Reset 9.3.4 Timing Overflow Flag (OVF) Setting. 9.3.5 Operation with Cascaded Connection Interrupts 9.4.1 Interrupt Sources Activation 9.4.2 Converter Activation. Sample Application. Usage Notes 9.6.1 Contention between TCNT Write Clear 9.6.2 Contention between TCNT Write Increment. 9.6.3 Contention between TCOR Write Compare Match 9.6.4 Contention between Compare Matches 9.6.5 Switching Internal Clocks TCNT Operation 9.6.6 Interrupts Module Stop Mode.
Section Watchdog Timer.
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Configuration. 10.1.4 Register Configuration. 10.2 Register Descriptions 10.2.1 Timer Counter (TCNT). 10.2.2 Timer Control/Status Register (TCSR) 10.2.3 Reset Control/Status Register (RSTCSR) 10.2.4 Notes Register Access. 10.3 Operation.
10.3.1 Operation Watchdog Timer Mode. 10.3.2 Operation Interval Timer Mode. 10.3.3 Timing Overflow Flag (OVF) Setting. 10.3.4 Timing Watchdog Timer Overflow Flag (WOVF) Setting. 10.4 Interrupts 10.5 Usage Notes 10.5.1 Contention between Timer Counter (TCNT) Write Increment 10.5.2 Changing Value CKS2 CKS0 10.5.3 Switching between Watchdog Timer Mode Interval Timer Mode. 10.5.4 System Reset WDTOVF Signal 10.5.5 Internal Reset Watchdog Timer Mode.
Section Serial Communication Interface (SCI)
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration. 11.1.4 Register Configuration. 11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) 11.2.2 Receive Data Register (RDR). 11.2.3 Transmit Shift Register (TSR). 11.2.4 Transmit Data Register (TDR). 11.2.5 Serial Mode Register (SMR) 11.2.6 Serial Control Register (SCR) 11.2.7 Serial Status Register (SSR) 11.2.8 Rate Register (BRR) 11.2.9 Smart Card Mode Register (SCMR). 11.2.10 Module Stop Control Register (MSTPCR). 11.3 Operation. 11.3.1 Overview. 11.3.2 Operation Asynchronous Mode. 11.3.3 Multiprocessor Communication Function 11.3.4 Operation Synchronous Mode 11.4 Interrupts 11.5 Usage Notes
Section Smart Card Interface
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration. 12.1.4 Register Configuration.
viii
12.2 Register Descriptions 12.2.1 Smart Card Mode Register (SCMR). 12.2.2 Serial Status Register (SSR) 12.2.3 Serial Mode Register (SMR) 12.2.4 Serial Control Register (SCR) 12.3 Operation. 12.3.1 Overview. 12.3.2 Connections 12.3.3 Data Format 12.3.4 Register Settings 12.3.5 Clock 12.3.6 Data Transfer Operations. 12.3.7 Operation Mode 12.3.8 Operation Block Transfer Mode 12.4 Usage Notes
Section Converter Analog Input Channel Version).
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration. 13.1.4 Register Configuration. 13.2 Register Descriptions 13.2.1 Data Registers (ADDRA ADDRD). 13.2.2 Control/Status Register (ADCSR) 13.2.3 Control Register (ADCR) 13.2.4 Module Stop Control Register (MSTPCR). 13.3 Interface Master. 13.4 Operation. 13.4.1 Single Mode (SCAN 13.4.2 Scan Mode (SCAN 13.4.3 Input Sampling Conversion Time 13.4.4 External Trigger Input Timing. 13.5 Interrupts 13.6 Usage Notes
Section Converter Analog Input Channel Version)
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration. 14.1.4 Register Configuration. 14.2 Register Descriptions
14.3 14.4
14.5 14.6
14.2.1 Data Registers (ADDRA ADDRD). 14.2.2 Control/Status Register (ADCSR). 14.2.3 Control Register (ADCR) 14.2.4 Module Stop Control Register (MSTPCR). Interface Master. Operation. 14.4.1 Single Mode (SCAN 14.4.2 Scan Mode (SCAN 14.4.3 Input Sampling Conversion Time 14.4.4 External Trigger Input Timing. Interrupts Usage Notes
Section Converter.
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Configuration. 15.1.4 Register Configuration. 15.2 Register Descriptions 15.2.1 Data Registers (DADR0 DADR3). 15.2.2 Control Registers (DACR01, DACR23). 15.2.3 Module Stop Control Register (MSTPCR). 15.3 Operation.
Section RAM.
16.1 Overview. 16.1.1 Block Diagram. 16.1.2 Register Configuration. 16.2 Register Descriptions 16.2.1 System Control Register (SYSCR). 16.3 Operation. 16.4 Usage Note
Section ROM.
17.1 Overview. 17.1.1 Block Diagram. 17.1.2 Register Configuration 17.2 Register Descriptions 17.2.1 Mode Control Register (MDCR) 17.2.2 Control Register (BCRL). 17.3 Operation. 17.4 Overview Flash Memory (H8S/2339, H8S/2329F-ZTAT)
17.5
17.6
17.7
17.8
17.9
17.10 17.11
17.4.1 Features. 17.4.2 Overview. 17.4.3 Flash Memory Operating Modes 17.4.4 On-Board Programming Modes 17.4.5 Flash Memory Emulation RAM. 17.4.6 Differences between Boot Mode User Program Mode. 17.4.7 Block Configuration 17.4.8 Configuration 17.4.9 Register Configuration Register Descriptions 17.5.1 Flash Memory Control Register (FLMCR1). 17.5.2 Flash Memory Control Register (FLMCR2). 17.5.3 Erase Block Register (EBR1) 17.5.4 Erase Block Registers (EBR2). 17.5.5 System Control Register (SYSCR2) 17.5.6 Emulation Register (RAMER) On-Board Programming Modes. 17.6.1 Boot Mode 17.6.2 User Program Mode Programming/Erasing Flash Memory. 17.7.1 Program Mode 17.7.2 Program-Verify Mode 17.7.3 Erase Mode. 17.7.4 Erase-Verify Mode Flash Memory Protection. 17.8.1 Hardware Protection. 17.8.2 Software Protection 17.8.3 Error Protection Flash Memory Emulation 17.9.1 Emulation 17.9.2 Overlap Interrupt Handling when Programming/Erasing Flash Memory Flash Memory Programmer Mode 17.11.1 Programmer Mode Setting 17.11.2 Socket Adapters Memory 17.11.3 Programmer Mode Operation. 17.11.4 Memory Read Mode. 17.11.5 Auto-Program Mode. 17.11.6 Auto-Erase Mode. 17.11.7 Status Read Mode. 17.11.8 Status Polling 17.11.9 Programmer Mode Transition Time. 17.11.10 Notes Memory Programming.
17.12 Flash Memory Programming Erasing Precautions. 17.13 Overview Flash Memory (H8S/2338, H8S/2328, H8S/2318, H8S/2315F-ZTAT). 17.13.1 Features. 17.13.2 Overview. 17.13.3 Flash Memory Operating Modes 17.13.4 On-Board Programming Modes 17.13.5 Flash Memory Emulation RAM. 17.13.6 Differences between Boot Mode User Program Mode. 17.13.7 Block Configuration 17.13.8 Configuration 17.13.9 Register Configuration 17.14 Register Descriptions 17.14.1 Flash Memory Control Register (FLMCR1). 17.14.2 Flash Memory Control Register (FLMCR2). 17.14.3 Erase Block Register (EBR1) 17.14.4 Erase Block Registers (EBR2) 17.14.5 System Control Register (SYSCR2) 17.14.6 Emulation Register (RAMER) 17.15 On-Board Programming Modes. 17.15.1 Boot Mode 17.15.2 User Program Mode 17.16 Programming/Erasing Flash Memory. 17.16.1 Program Mode 17.16.2 Program-Verify Mode 17.16.3 Erase Mode. 17.16.4 Erase-Verify Mode 17.17 Flash Memory Protection. 17.17.1 Hardware Protection. 17.17.2 Software Protection 17.17.3 Error Protection 17.18 Flash Memory Emulation 17.18.1 Emulation 17.18.2 Overlap 17.19 Interrupt Handling when Programming/Erasing Flash Memory 17.20 Flash Memory Programmer Mode 17.20.1 Progremmer Mode Setting 17.20.2 Socket Adapters Memory 17.20.3 Programmer Mode Operation. 17.20.4 Memory Read Mode. 17.20.5 Auto-Program Mode. 17.20.6 Auto-Erase Mode. 17.20.7 Status Read Mode. 17.20.8 Status Polling
17.21 17.22
17.23
17.24
17.25
17.26
17.27
17.28 17.29
17.20.9 Programmer Mode Transition Time. 17.20.10 Notes Memory Programming. Flash Memory Programming Erasing Precautions. Overview Flash Memory (H8S/2319F-ZTAT). 17.22.1 Features. 17.22.2 Overview. 17.22.3 Flash Memory Operating Modes 17.22.4 On-Board Programming Modes 17.22.5 Flash Memory Emulation RAM. 17.22.6 Differences between Boot Mode User Program Mode. 17.22.7 Block Configuration 17.22.8 Configuration 17.22.9 Register Configuration Register Descriptions 17.23.1 Flash Memory Control Register (FLMCR1). 17.23.2 Flash Memory Control Register (FLMCR2). 17.23.3 Erase Block Register (EBR1) 17.23.4 Erase Block Registers (EBR2). 17.23.5 System Control Register (SYSCR2) 17.23.6 Emulation Register (RAMER) On-Board Programming Modes. 17.24.1 Boot Mode 17.24.2 User Program Mode Programming/Erasing Flash Memory. 17.25.1 Program Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). 17.25.2 Program-Verify Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). 17.25.3 Erase Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). 17.25.4 Erase-Verify Mode addresses H'000000 H'03FFFF addresses H'040000 H'07FFFF). Flash Memory Protection. 17.26.1 Hardware Protection. 17.26.2 Software Protection 17.26.3 Error Protection Flash Memory Emulation 17.27.1 Emulation 17.27.2 Overlap Interrupt Handling when Programming/Erasing Flash Memory Flash Memory Programmer Mode 17.29.1 Programmer Mode Setting 17.29.2 Socket Adapters Memory
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17.29.3 Programmer Mode Operation. 17.29.4 Memory Read Mode. 17.29.5 Auto-Program Mode. 17.29.6 Auto-Erase Mode. 17.29.7 Status Read Mode. 17.29.8 Status Polling 17.29.9 Programmer Mode Transition Time. 17.29.10 Notes Memory Programming. 17.30 Flash Memory Programming Erasing Precautions.
Section Clock Pulse Generator
18.1 Overview. 18.1.1 Block Diagram. 18.1.2 Register Configuration 18.2 Register Descriptions 18.2.1 System Clock Control Register (SCKCR) 18.3 Oscillator. 18.3.1 Connecting Crystal Resonator 18.3.2 External Clock Input. 18.4 Duty Adjustment Circuit. 18.5 Medium-Speed Clock Divider 18.6 Master Clock Selection Circuit.
Section Power-Down Modes
19.1 Overview. 19.1.1 Register Configuration 19.2 Register Descriptions 19.2.1 Standby Control Register (SBYCR). 19.2.2 System Clock Control Register (SCKCR) 19.2.3 Module Stop Control Register (MSTPCR). 19.3 Medium-Speed Mode. 19.4 Sleep Mode 19.5 Module Stop Mode 19.5.1 Module Stop Mode 19.5.2 Usage Notes 19.6 Software Standby Mode. 19.6.1 Software Standby Mode 19.6.2 Clearing Software Standby Mode. 19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode. 19.6.4 Software Standby Mode Application Example 19.6.5 Usage Notes 19.7 Hardware Standby Mode 19.7.1 Hardware Standby Mode
19.7.2 Hardware Standby Mode Timing. 19.8 Clock Output Disabling Function
Appendix Instruction
Instruction List Instruction Codes Operation Code Map. Number States Required Instruction Execution. States During Instruction Execution Condition Code Modification
Appendix Internal Registers
Addresses
Section Overview
Overview
H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series series microcomputers (MCUs: microcomputer units), built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with supporting functions on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip supporting functions required system configuration include controller (DMAC) data transfer controller (DTC) masters, memory, 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. high-functionality controller also provided, enabling fast easy connection DRAM other kinds memory. Single-power-supply flash memory (F-ZTATTM*) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching thus speeded processing speed increased. features H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series shown table 1-1. types on-chip modules depend model; reference manual relevant model details. Note: F-ZTAT trademark Hitachi, Ltd.
Table
Item
Overview
Specification General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum clock rate: High-speed arithmetic operations 8/16/32-bit register-register add/subtract: operation) 16-bit register-register multiply: operation) 16-bit register-register divide: operation) Instruction suitable high-speed operation Sixty-five basic instructions 8/16/32-bit move/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions operating mode Advanced mode: 16-Mbyte address space Address space divided into areas, with specifications settable independently each area Chip select output possible each area Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable Maximum 8-Mbyte DRAM directly connectable interval timer possible) External release function Choice short address mode full address mode channels short address mode channels full address mode Transfer possible repeat mode, block transfer mode, etc. Single address mode transfer possible activated internal interrupt activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated
controller controller (DMAC)
Data transfer controller (DTC)
Item 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG)
Specification 6-channel 16-bit timer Pulse processing capability pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with time base Output trigger selectable 4-bit groups Non-overlap margin Direct output inverse output setting possible 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: bits Input: channels High-speed conversion: minimum conversion time operation) Single scan mode selectable Sample-and-hold circuit conversion activated external trigger timer trigger Resolution: bits Output: channels Flash memory, mask High-speed static Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Variable clock division ratio
8-bit timer, channels Watchdog timer Serial communication interface (SCI), channels converter
converter Memory Interrupt controller Power-down state
Item Operating modes
Specification Eight operating modes (H8S/2338, H8S/2328, H8S/2318, H8S/2315F-ZTAT versions) External Data On-Chip Initial Value Maximum Value
Operating Mode Mode Description Advanced User program mode Advanced Boot mode Advanced On-chip disabled expansion mode On-chip enabled expansion mode Single-chip mode
Disabled bits bits Enabled bits
bits bits bits
Enabled
bits
bits
Enabled
bits
bits
Item Operating modes
Specification Four operating modes (ROMless, mask versions, H8S/2339, H8S/2329, H8S/2319F-ZTAT versions) External Data Operating Mode Mode Description Advanced On-chip disabled expansion mode On-chip disabled expansion mode On-chip enabled expansion mode Disabled bits Disabled bits Enabled bits bits bits bits On-Chip Initial Value Maximum Value
Clock pulse generator
Single-chip mode Enabled Note: ROMless version only Modes Built-in duty correction circuit
Section Exception Handling
2.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 2-1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times program execution state. Exception handling sources, stack structure, operation vary depending interrupt control mode INTM0 INTM1 bits SYSCR. Table
Priority High
Exception Types Priority
Exception Type Reset Trace* Interrupt Start Exception Handling Starts immediately after low-to-high transition pin, when watchdog timer overflows. Starts when execution current instruction exception handling ends, trace Starts when execution current instruction exception handling ends, interrupt request been issued*
Trap instruction (TRAPA)*3 Started execution trap instruction (TRAPA)
Notes: Traces enabled only interrupt control mode Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
2.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows: program counter (PC), condition code register (CCR), extend register (EXR) pushed onto stack. interrupt mask bits updated. cleared vector address corresponding exception source generated, program execution starts from that address. reset exception, steps above carried out. 2.1.3 Exception Vector Table
exception sources classified shown figure 2-1. Different vector addresses assigned different exception sources. Table lists exception sources their vector addresses.
Reset Trace Exception sources External interrupts: NMI, IRQ7 IRQ0 Interrupts Internal interrupts: interrupts from on-chip supporting modules
Trap instruction
Figure Exception Sources modes on-chip available after power-on reset 64-kbyte area comprising addresses H'000000 H'00FFFF. Care required when setting vector addresses. this case, clearing BCRL enables 256-kbyte (384 kbytes/512 kbytes)* area comprising addresses H'000000 H'03FFFF H'05FFFF/H'07FFFF) used. Note: Depends model. relevant reference manual details.
Table
Exception Vector Table
Vector Address*
Exception Source Reset Reserved Reserved system
Vector Number
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 H'016C H'016F
Trace Reserved system External interrupt
Trap instruction sources)
Reserved system
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Internal interrupt*
Notes: Lower bits address. details internal interrupt vectors, section 3.3.3, Interrupt Exception Vector Table.
2.2.1
Reset
Overview
reset highest exception priority. When goes low, processing halts chip enters reset state. reset initializes internal state registers on-chip supporting modules. Immediately after reset, interrupt control mode set. Reset exception handling begins when changes from high. reset also caused watchdog timer overflow. details section Watchdog Timer. 2.2.2 Reset Sequence
chip enters reset state when goes low. ensure that chip reset, hold least power-up. reset chip during operation, hold least states. When goes high after being held necessary time, chip starts reset exception handling follows: internal state registers on-chip supporting modules initialized, cleared EXR, CCR. reset exception vector address read transferred program execution starts from address indicated Figure shows example reset sequence.
Vector fetch
Internal Prefetch first processing program instruction
Address HWR,
High
(1), (2),
Reset exception handling vector address ((1) H'000000, H'000002) Start address (contents reset exception vector address) Start address ((5) (2), (4)) First program instruction
Note: program wait states inserted.
Figure Reset Sequence (Mode 2.2.3 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. Since first instruction program always executed immediately after reset state ends, make sure that this instruction initializes stack pointer (example: MOV.L #xx:32, SP). 2.2.4 State On-Chip Supporting Modules after Reset Release
After reset release, MSTPCR initialized H'3FFF modules except DMAC enter module stop mode. Consequently, on-chip supporting module registers cannot read written Register reading writing enabled when module stop mode exited.
Traces
Traces enabled interrupt control mode Trace mode activated interrupt control mode irrespective state bit. details interrupt control modes, section Interrupt Controller. trace mode activated. trace mode, trace exception occurs completion each instruction. Trace mode canceled clearing affected interrupt masking. Table shows state after execution trace exception handling. Interrupts accepted even within trace exception handling routine. saved stack retains value when control returned from trace exception handling routine instruction, trace mode resumes. Trace exception handling carried after execution instruction. Table Status after Trace Exception Handling
Interrupt Control Mode
Trace exception handling cannot used.
Legend Cleared Retains value prior execution.
Interrupts
Interrupt exception handling requested nine external sources (NMI, IRQ7 IRQ0) internal sources on-chip supporting modules. Figure classifies interrupt sources number interrupts each type. on-chip supporting modules that request interrupts include watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), controller (DMAC), converter. Each interrupt source separate vector address. highest-priority interrupt. Interrupts controlled interrupt controller. interrupt controller interrupt control modes assign interrupts other than eight priority/mask levels enable multiplexed interrupt control. details interrupts, section Interrupt Controller.
External interrupts Interrupts
IRQ7 IRQ0 (8)*3
Internal interrupts*3
WDT*1 Refresh timer*2 (26) 8-bit timer (12) DMAC converter
Notes: Numbers parentheses numbers interrupt sources. When watchdog timer used interval timer, generates interrupt request each counter overflow. When refresh timer used interval timer, generates interrupt request each compare match. number external interrupts modules provided on-chip differ from model model; reference manual relevant model details.
Figure Interrupt Sources Number Interrupts
Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. Trap instruction exception handling executed times program execution state. TRAPA instruction fetches start address from vector table entry corresponding vector number from specified instruction code. Table shows status after execution trap instruction exception handling. Table Status after Trap Instruction Exception Handling
Interrupt Control Mode
Legend Cleared Retains value prior execution.
Stack Status after Exception Handling
Figure shows stack after completion trap instruction exception handling interrupt exception handling.
(24bits)
Reserved* (24bits)
Interrupt control mode Note: Ignored return.
Interrupt control mode
Figure Stack Status after Exception Handling (Advanced Modes)
Notes Stack
When accessing word data longword data, chip assumes that lowest address stack should always accessed word transfer instruction longword transfer instruction, value stack pointer (SP, ER7) should always kept even. following instructions save registers:
PUSH.W PUSH.L MOV.W @-SP) MOV.L ERn, @-SP)
following instructions restore registers:
POP.W POP.L MOV.W @SP+, MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD
TRAP instruction executed MOV.B R1L, @-ER7
H'FFFEFF Legend CCR: Condition code register Program counter R1L: General register Stack pointer
Data saved above
Contents lost
Note: This diagram illustrates example which interrupt control mode advanced mode.
Figure Operation when Value
Section Interrupt Controller
3.1.1
Overview
Features
chip controls interrupts means interrupt controller. interrupt controller following features. This chapter assumes maximum number interrupt sources available these series-nine external interrupts internal interrupts. Note: number interrupt sources differs from model model; reference manual relevant model details. interrupt control modes Either interrupt control modes means INTM1 INTM0 bits system control register (SYSCR) Priorities settable with IPRs Interrupt priority registers (IPRs) provided setting interrupt priorities. Eight priority levels each module interrupts except assigned highest priority level accepted times Independent vector addresses interrupt sources assigned independent vector addresses, making unnecessary source identified interrupt handling routine Nine external interrupt pins highest-priority interrupt, accepted times. Rising edge falling edge selected Falling edge, rising edge, both edge detection, level sensing, selected IRQ7 IRQ0 DMAC control DMAC* activation controlled means interrupts Note: Some models have on-chip DMAC; reference manual relevant model details.
3.1.2
Block Diagram
block diagram interrupt controller shown Figure 3-1.
INTM1 INTM0 SYSCR NMIEG input input input unit input unit ISCR Priority determination Interrupt request Vector number
Internal interrupt request SWDTEND
Interrupt controller
Legend ISCR SYSCR
sense control register enable register status register Interrupt priority register System control register
Figure Block Diagram Interrupt Controller
3.1.3
Configuration
Table summarizes pins interrupt controller. Table
Name Nonmaskable interrupt External interrupt requests
Interrupt Controller Pins
Symbol Input Function Nonmaskable external interrupt; rising falling edge selected Maskable external interrupts; rising, falling, both edges, level sensing, selected
IRQ7 IRQ0 Input
3.1.4
Register Configuration
Table summarizes registers interrupt controller. Table
Name System control register sense control register sense control register enable register status register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register
Interrupt Controller Registers
Abbreviation SYSCR ISCRH ISCRL IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/(W)*
Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77
Address* H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
Notes: Lower bits address. only written with flag clearing.
3.2.1
Register Descriptions
System Control Register (SYSCR)
INTM1 INTM0 NMIEG RAME
LWROD IRQPAS
Initial value
SYSCR 8-bit readable/writable register that selects interrupt control mode, detected edge NMI. Only bits described here; details other bits, Operating Modes section reference manual relevant model. SYSCR initialized H'01 reset hardware standby mode. initialized software standby mode. Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select interrupt control modes interrupt controller.
INTM1 INTM0 Interrupt Control Mode Description Interrupts controlled Setting prohibited Interrupts controlled bits Setting prohibited (Initial value)
3-NMI Edge Select (NMIEG): Selects input edge pin.
NMIEG Description Interrupt request generated falling edge input Interrupt request generated rising edge input (Initial value)
1-IRQ Input Select (IRQPAS): Selects switching pins that used input IRQ4 IRQ7. IRQ4 IRQ7 input always performed from ports. Note: Some models have IRQPAS bit, those that pins that used IRQ4 IRQ7 input differ from model model; reference manual relevant model details.
3.2.2
Interrupt Priority Registers (IPRA IPRK)
IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
Initial value
registers eleven 8-bit readable/writable registers that priorities (levels interrupts other than NMI. correspondence between settings interrupt sources shown table 3-3. registers priority (level each interrupt source other than NMI. registers initialized H'77 reset hardware standby mode. Bits 3-Reserved: Read-only bits, always read Table Correspondence between Interrupt Sources Settings
Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Notes: IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer channel channel channel 8-bit timer channel DMAC channel IRQ1 IRQ4 IRQ5 Refresh timer converter channel channel channel 8-bit timer channel channel channel
Interrupt sources depend model; reference manual relevant model details. Reserved bits.
shown table 3-3, multiple interrupts assigned IPR. Setting value range from 3-bit groups bits sets priority corresponding interrupt. lowest priority level, level assigned setting H'0, highest priority level, level setting H'7. When interrupt requests generated, highest-priority interrupt according priority levels registers selected. This interrupt level then compared with interrupt mask level interrupt mask bits extend register (EXR) CPU, priority level interrupt higher than mask level, interrupt request issued CPU. 3.2.3
Enable Register (IER)
IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial value
8-bit readable/writable register that controls enabling disabling interrupt requests IRQ7 IRQ0. initialized H'00 reset hardware standby mode. Bits 0-IRQ7 IRQ0 Enable (IRQ7E IRQ0E): These bits select whether IRQ7 IRQ0 enabled disabled.
IRQnE Description IRQn interrupts disabled IRQn interrupts enabled (Initial value)
3.2.4
ISCRH
Sense Control Registers (ISCRH, ISCRL)
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
Initial value ISCRL
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value
ISCR (composed ISCRH ISCRL) 16-bit readable/writable register that selects rising edge, falling edge, both edge detection, level sensing, input pins IRQ7 IRQ0. ISCR initialized H'0000 reset hardware standby mode. Bits IRQ7 Sense Control (IRQ7SCA, IRQ7SCB) IRQ0 Sense Control (IRQ0SCA, IRQ0SCB)
Bits IRQ7SCB IRQ0SCB IRQ7SCA IRQ0SCA Description Interrupt request generated IRQ7 IRQ0 input level (Initial value) Interrupt request generated falling edge IRQ7 IRQ0 input Interrupt request generated rising edge IRQ7 IRQ0 input Interrupt request generated both falling rising edges IRQ7 IRQ0 input
3.2.5
Status Register (ISR)
IRQ7F IRQ6F R/(W)* IRQ5F R/(W)* IRQ4F R/(W)* IRQ3F R/(W)* IRQ2F R/(W)* IRQ1F R/(W)* IRQ0F R/(W)*
Initial value
R/(W)*
Note: Only written, clear flag.
8-bit readable/writable register that indicates status IRQ7 IRQ0 interrupt requests. initialized H'00 reset hardware standby mode. Bits 0-IRQ7 IRQ0 flags (IRQ7F IRQ0F): These bits indicate status IRQ7 IRQ0 interrupt requests.
IRQnF Description [Clearing conditions] (Initial value)
Cleared reading IRQnF flag when IRQnF then writing IRQnF flag When interrupt exception handling executed when low-level detection (IRQnSCB IRQnSCA IRQn input high When IRQn interrupt exception handling executed when falling, rising, both-edge detection (IRQnSCB IRQnSCA When activated IRQn interrupt, DISEL cleared
[Setting conditions] When IRQn input goes when low-level detection (IRQnSCB IRQnSCA When falling edge occurs IRQn input when falling edge detection (IRQnSCB IRQnSCA When rising edge occurs IRQn input when rising edge detection (IRQnSCB IRQnSCA When falling rising edge occurs IRQn input when both-edge detection (IRQnSCB IRQnSCA
Interrupt Sources
Interrupt sources comprise external interrupts (NMI IRQ7 IRQ0) internal interrupts sources). 3.3.1 External Interrupts
There nine external interrupts: IRQ7 IRQ0. IRQ7 IRQ0 used restore chip from software standby mode. (IRQ7 IRQ3 designated software standby mode clearing sources setting IRQ37S SBYCR Interrupt: highest-priority interrupt, always accepted regardless status interrupt mask bits. NMIEG SYSCR used select whether interrupt requested rising edge falling edge pin. vector number interrupt exception handling IRQ7 IRQ0 Interrupts: Interrupts IRQ7 IRQ0 requested input signal pins IRQ7 IRQ0. Interrupts IRQ7 IRQ0 have following features: Using ISCR, possible select whether interrupt generated level, falling edge, rising edge, both edges, pins IRQ7 IRQ0. Enabling disabling interrupt requests IRQ7 IRQ0 selected with IER. interrupt priority level with IPR. status interrupt requests IRQ7 IRQ0 indicated ISR. flags cleared software. block diagram interrupts IRQ7 IRQ0 shown figure 3-2.
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input IRQn interrupt request
Clear signal Note:
Figure Block Diagram Interrupts IRQ7 IRQ0
Figure shows timing setting IRQnF.
IRQn input
IRQnF
Figure Timing Setting IRQnF vector numbers IRQ7 IRQ0 interrupt exception handling Detection IRQ7 IRQ0 interrupts does depend whether relevant been input output. Therefore, when used external interrupt input pin, clear corresponding another function. pins that used IRQ4 IRQ7 interrupt input switched means IRQPAS SYSCR. Note: switched pins differ from model model; reference manual relevant model details. 3.3.2 Internal Interrupts
There sources internal interrupts from on-chip supporting modules. each on-chip supporting module there flags that indicate interrupt request status, enable bits that select enabling disabling these interrupts. both these particular interrupt source, interrupt request issued interrupt controller. interrupt priority level means IPR. DMAC activated TPU, SCI, other interrupt request. When DMAC activated interrupt, interrupt control mode interrupt mask bits have effect. 3.3.3 Interrupt Exception Vector Table
Table shows interrupt exception handling sources, vector addresses, interrupt priorities. default priorities, lower vector number, higher priority. Priorities among modules means IPR. situation when more modules same priority, priorities within module, fixed shown table 3-4.
Table
Interrupt Sources, Vector Addresses, Interrupt Priorities
Origin Interrupt Source External Vector Number Watchdog timer Refresh controller Vector Address* H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 IPRA6 IPRA2 IPRB6 IPRB2 IPRC6 IPRC2 IPRD6 IPRD2 IPRE6 IPRE2
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software-activated data transfer end) WOVI (interval timer) (compare match) Reserved (A/D conversion end) Reserved
Priority High
TGI0A (TGR0A input capture/ compare match) TGI0B (TGR0B input capture/ compare match) TGI0C (TGR0C input capture/ compare match) TGI0D (TGR0D input capture/ compare match) TCI0V (overflow Reserved
channel
Interrupt Source TGI1A (TGR1A input capture/ compare match) TGI1B (TGR1B input capture/ compare match) TCI1V (overflow TCI1U (underflow TGI2A (TGR2A input capture/ compare match) TGI2B (TGR2B input capture/ compare match) TCI2V (overflow TCI2U (underflow TGI3A (TGR3A input capture/ compare match) TGI3B (TGR3B input capture/ compare match) TGI3C (TGR3C input capture/ compare match) TGI3D (TGR3D input capture/ compare match) TCI3V (overflow Reserved
Origin Interrupt Source channel
Vector Number
Vector Address* H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC
IPRF2
Priority High
channel
IPRG6
channel
IPRG2
TGI4A (TGR4A input capture/ compare match) TGI4B (TGR4B input capture/ compare match) TCI4V (overflow TCI4U (underflow TGI5A (TGR5A input capture/ compare match) TGI5B (TGR5B input capture/ compare match) TCI5V (overflow TCI5U (underflow
channel
IPRH6
channel
IPRH2
Interrupt Source CMIA0 (compare match CMIB0 (compare match OVI0 (overflow Reserved CMIA1 (compare match CMIB1 (compare match OVI1 (overflow Reserved DEND0A (channel 0/channel transfer end) DEND0B (channel transfer end) DEND1A (channel 1/channel transfer end) DEND1B (channel transfer end) Reserved
Origin Interrupt Source 8-bit timer channel
Vector Number
Vector Address* H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C
IPRI6
Priority High
8-bit timer channel
IPRI2
DMAC
IPRJ6
ERI0 (receive error RXI0 (receive-data-full TXI0 (transmit-data-empty TEI0 (transmission ERI1 (receive error RXI1 (receive-data-full TXI1 (transmit-data-empty TEI1 (transmission ERI2 (receive error RXI2 (receive-data-full TXI2 (transmit-data-empty TEI2 (transmission
channel
IPRJ2
channel
IPRK6
channel
IPRK2
Notes: Interrupt sources differ from model model; reference manual relevant model details. Lower bits start address.
3.4.1
Interrupt Operation
Interrupt Control Modes Interrupt Operation
Interrupt operations chip differ depending interrupt control mode. interrupts accepted times except reset state hardware standby state. case interrupts on-chip supporting module interrupts, enable provided each interrupt. Clearing enable disables corresponding interrupt request. Interrupt sources which enable bits controlled interrupt controller. Table shows interrupt control modes. interrupt controller performs interrupt control according interrupt control mode INTM1 INTM0 bits SYSCR, priorities IPR, masking state indicated CPU's CCR, bits EXR. Table Interrupt Control Modes
Interrupt Mask Bits Description Interrupt mask control performed bit. Setting prohibited 8-level interrupt mask control performed bits priority levels with IPR. Setting prohibited
SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers
Figure shows block diagram priority decision circuit.
Interrupt control mode
Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number
Interrupt control mode
Figure Block Diagram Interrupt Control Operation Interrupt Acceptance Control: interrupt control mode interrupt acceptance controlled CCR. Table shows interrupts selected each interrupt control mode. Table Interrupts Selected Each Interrupt Control Mode
Interrupt Mask Bits Interrupt Control Mode Selected Interrupts interrupts interrupts interrupts Don't care
8-Level Control: interrupt control mode 8-level mask level determination performed selected interrupts interrupt acceptance control according interrupt priority level (IPR). interrupt source selected interrupt with highest priority level, whose priority level higher than mask level. Table Interrupts Selected Each Interrupt Control Mode
Selected Interrupts interrupts Highest-priority-level (IPR) interrupt whose priority level greater than mask level (IPR
Interrupt Control Mode
Default Priority Determination: When interrupt selected 8-level control, priority determined vector number generated. same value IPR, acceptance multiple interrupts enabled, only interrupt source with highest priority according preset default priorities selected vector number generated. Interrupt sources with lower priority than accepted interrupt source held pending. Table shows operations control signal functions each interrupt control mode. Table Operations Control Signal Functions Each Interrupt Control Mode
Interrupt Acceptance Control
Interrupt Setting Control Mode INTM1 INTM0
8-Level Control
Default Priority Determination (Trace)
Legend Interrupt operation control performed operation. (All interrupts enabled) Used interrupt mask Sets priority. used. Notes: when interrupt accepted. Keep initial setting.
3.4.2
Interrupt Control Mode
Enabling disabling interrupts on-chip supporting module interrupts means CPU's CCR. Interrupts enabled when cleared disabled when Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. then referenced. cleared interrupt request accepted. only interrupt accepted, other interrupt requests held pending. Interrupt requests sent interrupt controller, highest-ranked interrupt according priority system accepted, other interrupt requests held pending. When interrupt request accepted, interrupt exception handling starts after execution current instruction been completed. saved stack area interrupt exception handling. saved stack shows address first instruction executed after returning from interrupt handling routine. Next, This masks interrupts except NMI. vector address generated accepted interrupt, execution interrupt handling routine starts address indicated contents that vector address.
Program execution state
Interrupt generated?
NMI?
Hold pending
IRQ0?
IRQ1?
TEI2?
Save Read vector address
Branch interrupt handling routine
Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode
3.4.3
Interrupt Control Mode
Eight-level masking implemented interrupts on-chip supporting module interrupts comparing interrupt mask level bits with IPR. Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. When interrupt requests sent interrupt controller, interrupt with highest priority according interrupt priority levels selected, lower-priority interrupt requests held pending. number interrupt requests with same priority generated same time, interrupt request with highest priority according priority system shown table selected. Next, priority selected interrupt request compared with interrupt mask level EXR. interrupt request with priority higher than mask level that time held pending, only interrupt request with priority higher than interrupt mask level accepted. When interrupt request accepted, interrupt exception handling starts after execution current instruction been completed. CCR, saved stack area interrupt exception handling. saved stack shows address first instruction executed after returning from interrupt handling routine. cleared interrupt mask level rewritten with priority level accepted interrupt. accepted interrupt NMI, interrupt mask level H'7. vector address generated accepted interrupt, execution interrupt handling routine starts address indicated contents that vector address.
Program execution state
Interrupt generated? NMI?
Level interrupt? Mask level below?
Level interrupt? Mask level below?
Level interrupt?
Mask level
Save CCR,
Hold pending
Clear
Update mask level
Read vector address
Branch interrupt handling routine
Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode
3.4.4
Interrupt Exception Handling Sequence
Figure shows interrupt exception handling sequence. example shown case where interrupt control mode advanced mode, program area stack area on-chip memory.
Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt handling routine instruction prefetch
Interrupt level determination Wait instruction
Interrupt request signal
Internal address
(11)
(13)
Internal read signal
Internal write signal
(10) (12) (14)
Figure Interrupt Exception Handling
Internal data
Instruction prefetch address (Not executed. This contents saved return address.) (2), Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4
(6), Saved saved (9), (11) Vector address (10), (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) (10), (12)) (14) First instruction interrupt handling routine
3.4.5
Interrupt Response Times
chip capable fast word transfer instruction on-chip memory, program area provided on-chip stack area on-chip RAM, enabling high-speed processing. Table shows interrupt response times-the interval between generation interrupt request execution first instruction interrupt handling routine. execution status symbols used table explained table 3-10. Table Interrupt Response Times
Advanced Mode Item Interrupt priority determination* Number wait states until executing instruction ends* CCR, stack save Vector fetch Instruction fetch*
INTM1
INTM1
Internal processing*
Total (using on-chip memory) Notes:
states case internal interrupt. Refers MULXS DIVXS instructions. Prefetch after interrupt acceptance interrupt handling routine prefetch. Internal processing after interrupt acceptance internal processing after vector fetch.
Table 3-10 Number States Interrupt Handling Routine Execution
Object Access External Device 8-Bit Symbol Instruction fetch Branch address read Stack manipulation Internal Memory 2-State Access 3-State Access 6+2m 16-Bit 2-State Access 3-State Access
Legend Number wait states external device access.
3.5.1
Usage Notes
Contention between Interrupt Generation Disabling
When interrupt enable cleared disable interrupts, disabling becomes effective after execution instruction. other words, when interrupt enable cleared instruction such BCLR MOV, interrupt generated during execution instruction, interrupt concerned will still enabled completion instruction, interrupt exception handling that interrupt will executed completion instruction. However, there interrupt request higher priority than that interrupt, interrupt exception handling will executed higher-priority interrupt, lower-priority interrupt will ignored. same also applies when interrupt source flag cleared. Figure shows example which TGIEA TPU's TIER0 register cleared
TIER0 write cycle TGI0A exception handling
Internal address
TIER0 address
Internal write signal
TGIEA
TGFA
TGI0A interrupt signal
Figure Contention between Interrupt Generation Disabling above contention will occur enable interrupt source flag cleared while interrupt masked.
3.5.2
Instructions that Disable Interrupts
Instructions that disable interrupts LDC, ANDC, ORC, XORC. After these instructions executed, interrupts including disabled next instruction always executed. When these instructions, value becomes valid states after execution instruction ends. 3.5.3 Times when Interrupts Disabled
There times when interrupt acceptance disabled interrupt controller. interrupt controller disables interrupt acceptance 3-state period after updated mask level with LDC, ANDC, ORC, XORC instruction. 3.5.4 Interrupts during Execution EEPMOV Instruction
Interrupt operation differs between EEPMOV.B instruction EEPMOV.W instruction. With EEPMOV.B instruction, interrupt request (including NMI) issued during transfer accepted until move completed. With EEPMOV.W instruction, interrupt request issued during transfer, interrupt exception handling starts break transfer cycle. value saved stack this case address next instruction. Therefore, interrupt generated during execution EEPMOV.W instruction, following coding should used.
EEPMOV.W MOV.W R4,R4
3.6.1
DMAC Activation Interrupt
Overview
DMAC* activated interrupt. this case, following options available. Note: Some models have on-chip DMAC; reference manual relevant model.
Interrupt request Activation request Activation request DMAC Selection number above
details interrupt requests that used with activate DMAC, section Data Transfer Controller, section Controller. 3.6.2 Block Diagram
Figure shows block diagram DTC, DMAC, interrupt controller.
DMAC
Disable signal
Clear signal
Interrupt request interrupt Interrupt source clear signal
Selection circuit Select signal Clear signal DTCER
activation request vector number
Control logic Clear signal
On-chip supporting module
DTVECR SWDTE clear signal Determination priority interrupt request vector number
Interrupt controller
Figure Interrupt Control DMAC
3.6.3
Operation
interrupt controller three main functions DMAC control. Selection Interrupt Source: With DMAC, activation source input directly each channel. activation source each DMAC channel selected with bits DTF3 DTF0 DMACR. Whether selected activation source managed DMAC selected with DMABCR. When interrupt source constituting that DMAC activation source activation source interrupt source. interrupt sources other than interrupts managed DMAC, possible select activation request interrupt request with DTCE DTCERA DTCERF DTC. After data transfer, DTCE cleared interrupt request sent accordance with specification DISEL DTC. When performed specified number data transfers transfer counter value zero, DTCE cleared interrupt request sent after data transfer. Determination Priority: activation source selected accordance with default priority order, affected mask priority levels. section 5.6, Interrupts, section 6.3.3, Vector Table, respective priorities. With DMAC, activation source input directly each channel. Operation Order: same interrupt selected activation source interrupt source, data transfer performed first, followed interrupt exception handling. same interrupt selected DMAC activation source activation source interrupt source, operations performed them independently according their respective operating statuses mastership priorities. Table 3-11 summarizes interrupt source selection interrupt source clearance control according settings DMABCR DMAC, DTCE DTCERA DTCERF DTC, DISEL DTC.
Table 3-11 Interrupt Source Selection Clearing Control
Settings DMAC DTCE DISEL Interrupt Source Selection/Clearing Control DMAC
Legend relevant interrupt used. Interrupt source clearing performed. (The should clear source flag interrupt handling routine.) relevant interrupt used. interrupt source cleared. relevant interrupt cannot used. Don't care
Usage Note: converter interrupt sources cleared when DMAC reads writes prescribed register, dependent upon DISEL bit.
Section Controller
Overview
chip built-in controller (BSC) that manages external address space divided into eight areas. specifications, such width number access states, independently each area, enabling multiple memories connected easily. controller also arbitration function, controls operation internal masters: CPU, controller (DMAC), data transfer controller (DTC). Note: This section describes controller with maximum series specifications; reference manual relevant model details functions. 4.1.1 Features
features controller listed below. Manages external address space area units advanced mode, manages external space areas Mbytes specifications independently each area DRAM/burst interfaces Basic interface Chip select (CS0 CS7) output areas 8-bit access 16-bit access selected each area 2-state access 3-state access selected each area Program wait states inserted each area DRAM interface DRAM interface areas advanced mode) address/column address multiplexed output (8/9/10 bits) 2-CAS access method Burst operation (fast page mode) cycle insertion secure precharging time Choice CAS-before-RAS refreshing self-refreshing Burst interface Burst interface area Choice 2-state burst access
Idle cycle insertion idle cycle inserted case external read cycle between different areas idle cycle inserted when external read cycle immediately followed external write cycle Write buffer functions External write cycle internal access executed parallel DMAC single address mode internal access executed parallel arbitration function Includes arbiter that arbitrates mastership among CPU, DMAC, Other features Refresh counter (refresh timer) used interval timer External release function
4.1.2
Block Diagram
Figure shows block diagram controller.
Area decoder
Internal address
ABWCR External control signals ASTCR BCRH BCRL BREQ BACK BREQO controller Internal control signals mode signal
WAIT
WCRH WCRL
External DRAM signals
DRAM controller
DRAMCR RTCNT RTCOR request signal request signal DMAC request signal acknowledge signal acknowledge signal DMAC acknowledge signal
arbiter
Figure Block Diagram Controller
Internal data
Wait controller
4.1.3
Configuration
Table summarizes pins controller. Note: pins used output various signals differ from model model; reference manual relevant model details. Table
Name Address strobe Read High write/write enable
Controller Pins
Symbol Output Output Output Function Strobe signal indicating that address output address enabled. Strobe signal indicating that external space being read. Strobe signal indicating that external space written, upper half data enabled. 2-CAS DRAM write enable signal. Strobe signal indicating that external space written, lower half data enabled. Strobe signal indicating that area selected. Strobe signal indicating that area selected. Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM space. Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM space. Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM space. Strobe signal indicating that area selected. DRAM address strobe signal when area DRAM space.
write
Output
Chip select Chip select Chip select 2/row address strobe
Output Output Output
Chip select 3/row address strobe
Output
Chip select 4/row address strobe
Output
Chip select 5/row address strobe
Output
Name Chip select Chip select Upper column address strobe Lower column strobe Wait request request acknowledge request output
Symbol LCAS WAIT BREQ BACK Output Output Output Output Input Input Output
Function Strobe signal indicating that area selected. Strobe signal indicating that area selected. 2-CAS DRAM upper column address strobe signal. DRAM lower column address strobe signal. Wait request signal when accessing external 3-state access space. Request signal that releases external device. Acknowledge signal indicating that been released. External request signal used when internal master accesses external space when external released.
BREQO Output
4.1.4
Register Configuration
Table summarizes registers controller. Table Controller Registers
Initial Value Name width control register Access state control register Wait control register Wait control register control register control register Memory control register DRAM control register Refresh timer counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL DRAMCR RTCNT RTCOR Reset H'FF/H'00* H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'00 H'FF Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9
Notes: Lower bits address. Determined operating mode.
4.2.1
Register Descriptions
Width Control Register (ABWCR)
ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
Modes Initial value Mode Initial value
ABWCR 8-bit readable/writable register that designates each area either 8-bit access 16-bit access. ABWCR sets data width external memory space. width on-chip memory internal registers fixed regardless settings ABWCR. After reset hardware standby mode, ABWCR initialized H'FF modes H'00 mode initialized software standby mode. Note: Modes provided ROMless version. Bits 0-Area Width Control (ABW7 ABW0): These bits select whether corresponding area designated 8-bit access 16-bit access.
ABWn Description Area designated 16-bit access Area designated 8-bit access
4.2.2
Access State Control Register (ASTCR)
AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Initial value
ASTCR 8-bit readable/writable register that designates each area either 2-state access space 3-state access space. ASTCR sets number access states external memory space. number access states on-chip memory internal registers fixed regardless settings ASTCR. ASTCR initialized H'FF reset hardware standby mode. initialized software standby mode. Bits 0-Area Access State Control (AST7 AST0): These bits select whether corresponding area designated 2-state access space 3-state access space. Wait state insertion enabled disabled same time.
ASTn Description Area designated 2-state access Wait state insertion area external space disabled Area designated 3-state access Wait state insertion area external space enabled (Initial value)
4.2.3
Wait Control Registers (WCRH, WCRL)
WCRH WCRL 8-bit readable/writable registers that select number program wait states each area. Program waits inserted case on-chip memory internal registers. WCRH WCRL initialized H'FF reset hardware standby mode. They initialized software standby mode. WCRH
Initial value
Bits 6-Area Wait Control (W71, W70): These bits select number program wait states when area external space accessed while AST7 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 4-Area Wait Control (W61, W60): These bits select number program wait states when area external space accessed while AST6 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 2-Area Wait Control (W51, W50): These bits select number program wait states when area external space accessed while AST5 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 0-Area Wait Control (W41, W40): These bits select number program wait states when area external space accessed while AST4 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
WCRL
Initial value
Bits 6-Area Wait Control (W31, W30): These bits select number program wait states when area external space accessed while AST3 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 4-Area Wait Control (W21, W20): These bits select number program wait states when area external space accessed while AST2 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 2-Area Wait Control (W11, W10): These bits select number program wait states when area external space accessed while AST1 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
Bits 0-Area Wait Control (W01, W00): These bits select number program wait states when area external space accessed while AST0 ASTCR
Description Program wait inserted when external space area accessed program wait state inserted when external space area accessed program wait states inserted when external space area accessed program wait states inserted when external space area accessed (Initial value)
4.2.4
Control Register (BCRH)
ICIS1 ICIS0 RMTS2 RMTS1 RMTS0
BRSTRM BRSTS1 BRSTS0
Initial value
BCRH 8-bit readable/writable register that selects enabling disabling idle cycle insertion, memory interface areas area BCRH initialized H'D0 reset hardware standby mode. initialized software standby mode.
7-Idle Cycle Insert (ICIS1): Selects whether idle cycle state inserted between cycles when successive external read cycles performed different areas.
ICIS1 Description Idle cycle inserted case successive external read cycles different areas Idle cycle inserted case successive external read cycles different areas (Initial value)
6-Idle Cycle Insert (ICIS0): Selects whether idle cycle state inserted between cycles when successive external read external write cycles performed
ICIS0 Description Idle cycle inserted case successive external read external write cycles Idle cycle inserted case successive external read external write cycles (Initial value)
5-Burst Enable (BRSTRM): Selects whether area used burst interface area.
BRSTRM Description Area basic interface area Area burst interface area (Initial value)
4-Burst Cycle Select (BRSTS1): Selects number burst cycles burst interface.
BRSTS1 Description Burst cycle comprises state Burst cycle comprises states (Initial value)
3-Burst Cycle Select (BRSTS0): Selects number words that accessed burst interface burst access.
BRSTS0 Description Max. words burst access Max. words burst access (Initial value)
Bits 0-RAM Type Select (RMTS2 RMTS0): These bits select memory interface areas advanced mode. When DRAM space selected, relevant area designated DRAM interface area.
RMTS2 RMTS1 RMTS0 Description Area Normal space Normal space Normal space DRAM space DRAM space DRAM space Area Area Area
Note: LCAS used LCAS signal 2-CAS DRAM interface. wished BREQO output WAIT input when using LCAS signal, with another specified means WAITPS BREQOPS bits PFCR2. Switching these pins differs from model model; reference manual relevant model details.
4.2.5
Control Register (BCRL)
BRLE BREQOE WDBE WAITE
Initial value
BCRL 8-bit readable/writable register that performs selection external bus-released state protocol, DMAC single address transfer, enabling disabling write data buffer function, enabling disabling WAIT input. BCRL initialized H'3C reset hardware standby mode. initialized software standby mode.
7-Bus Release Enable (BRLE): Enables disables external release.
BRLE Description External release disabled. BREQ, BACK, BREQO pins used ports (Initial value) External release enabled
6-BREQO Enable (BREQOE): Outputs signal that requests external master drop request signal (BREQ) external release state, when internal master performs external space access, when refresh request generated.
BREQOE Description BREQO output disabled. BREQO used port BREQO output enabled (Initial value)
5-External Address Enable (EAE): Selects whether addresses H'010000 H'03FFFF*1 internal addresses external addresses.
Notes: Description Addresses H'010000 H'03FFFF* on-chip Addresses H'010000 H'03FFFF* external addresses (external expansion mode) reserved area* (single-chip mode) (Initial value) on-chip area differs from model model; reference manual relevant model details. Reserved areas should accessed.
4-Reserved 3-DACK Timing Select (DDS): Selects DMAC single address transfer timing DRAM interface.
Description When DMAC single address transfer performed DRAM space, full access always executed DACK signal goes from cycle Burst access possible when DMAC single address transfer performed DRAM space DACK signal goes from cycle (Initial value)
2-Reserved 1-Write Data Buffer Enable (WDBE): Selects whether write buffer function used external write cycle DMAC single address cycle.
WDBE Description Write data buffer function used Write data buffer function used (Initial value)
0-WAIT Enable (WAITE): Selects enabling disabling wait input WAIT pin.
WAITE Description Wait input WAIT disabled. WAIT used port Wait input WAIT enabled (Initial value)
4.2.6
Memory Control Register (MCR)
RCDM MXC1 MXC0 RLW1 RLW0
Initial value
8-bit readable/writable register that selects DRAM strobe control method, number precharge cycles, access mode, address multiplexing shift size, number wait states inserted during refreshing, when areas designated DRAM interface areas. initialized H'00 reset hardware standby mode. initialized software standby mode. 7-TP Cycle Control (TPC): Selects whether 1-state 2-state precharge cycle (TP) used when areas designated DRAM space accessed.
Description 1-state precharge cycle inserted 2-state precharge cycle inserted (Initial value)
6-Burst Access Enable (BE): Selects enabling disabling burst access areas designated DRAM space. DRAM space burst access performed fast page mode.
Description Burst disabled (always full access) DRAM space access, access fast page mode (Initial value)
5-RAS Down Mode (RCDM): When areas designated DRAM space access DRAM interrupted, RCDM selects whether next DRAM access waited with signal held (RAS down mode), signal driven high again (RAS mode).
RCDM Description DRAM interface: mode selected DRAM interface: down mode selected (Initial value)
4-Reserved Bits 2-Multiplex Shift Count (MXC1, MXC0): These bits select size shift lower half address address/column address multiplexing DRAM interface. burst operation DRAM interface, these bits also select address used comparison.
MXC1 MXC0 Description 8-bit shift (Initial value) When 8-bit access space designated: address used comparison When 16-bit access space designated: address used comparison 9-bit shift When 8-bit access space designated: address used comparison When 16-bit access space designated: address used comparison 10-bit shift When 8-bit access space designated: address used comparison When 16-bit access space designated: address used comparison
Bits 0-Refresh Cycle Wait Control (RLW1, RLW0): These bits select number wait states inserted DRAM interface CAS-before-RAS refresh cycle. This setting used areas designated DRAM space. Wait input WAIT disabled.
RLW1 RLW0 Description wait state inserted wait state inserted wait states inserted wait states inserted (Initial value)
4.2.7
DRAM Control Register (DRAMCR)
RFSHE RMODE CMIE CKS2 CKS1 CKS0
Initial value
DRAMCR 8-bit readable/writable register that selects DRAM refresh mode refresh counter clock, controls refresh timer. DRAMCR initialized H'00 reset hardware standby mode. initialized software standby mode. 7-Refresh Control (RFSHE): Selects whether refresh control performed. When refresh control performed, refresh timer used interval timer.
RFSHE Description Refresh control performed Refresh control performed (Initial value)
6-RAS-CAS Wait (RCW): Controls wait state insertion DRAM interface CAS-beforeRAS refreshing.
Description Wait state insertion CAS-before-RAS refreshing disabled falls cycle wait state inserted CAS-before-RAS refreshing falls TRc1 cycle (Initial value)
5-Refresh Mode (RMODE): When refresh control performed (RFSHE selects whether self-refresh control performed software standby mode.
RMODE Description Self-refreshing performed software standby mode Self-refreshing performed software standby mode (Initial value)
4-Compare Match Flag (CMF): Status flag that indicates match between values RTCNT RTCOR. When refresh control performed (RFSHE should written when writing DRAMCR.
Description [Clearing condition] Cleared reading flag when then writing flag (Initial value) [Setting condition] when RTCNT RTCOR
3-Compare Match Interrupt Enable (CMIE): Enables disables interrupt requests (CMI) flag when flag DRAMCR When refresh control performed (RFSHE CMIE always cleared
CMIE Description Interrupt request (CMI) flag disabled Interrupt request (CMI) flag enabled (Initial value)
Bits 0-Refresh Counter Clock Select (CKS2 CKS0): These bits select clock input RTCNT from among internal clocks obtained dividing system clock When input clock selected with bits CKS2 CKS0, RTCNT begins counting
CKS2 CKS1 CKS0 Description Count operation disabled Count uses Count uses Count uses Count uses Count uses Count uses Count uses (Initial value)
4.2.8
Refresh Timer Counter (RTCNT)
Initial value
RTCNT 8-bit readable/writable up-counter. RTCNT counts using internal clock selected bits CKS2 CKS0 DRAMCR. When RTCNT matches RTCOR (compare match), flag DRAMCR RTCNT cleared H'00. RFSHE DRAMCR this time, refresh cycle started. Also, CMIE DRAMCR compare match interrupt (CMI) generated. RTCNT initialized H'00 reset hardware standby mode. initialized software standby mode. 4.2.9
Refresh Time Constant Register (RTCOR)
Initial value
RTCOR 8-bit readable/writable register that sets period compare match operations with RTCNT. values RTCOR RTCNT constantly compared, they match, flag DRAMCR RTCNT cleared H'00. RTCOR initialized H'FF reset hardware standby mode. initialized software standby mode.
4.3.1
Overview Control
Area Partitioning
advanced mode, controller partitions 16-Mbyte address space into eight areas, 2-Mbyte units, performs control external space area units. Figure shows outline memory map. Chip select signals (CS0 CS7) output each area.
H'000000 Area Mbytes) H'1FFFFF H'200000 Area Mbytes) H'3FFFFF H'400000 Area Mbytes) H'5FFFFF H'600000 Area Mbytes) H'7FFFFF H'800000 Area Mbytes) H'9FFFFF H'A00000 Area Mbytes) H'BFFFFF H'C00000 Area Mbytes) H'DFFFFF H'E00000 Area Mbytes) H'FFFFFF Advanced mode
Figure Overview Area Partitioning
4.3.2
Specifications
external space specifications consist three elements: width, number access states, number program wait states. width number access states on-chip memory internal registers fixed, affected controller. Width: width bits selected with ABWCR. area which 8-bit selected functions 8-bit access space, area which 16-bit selected functions a16-bit access space. areas designated 8-bit access, 8-bit mode set; area designated 16-bit access, 16-bit mode set. When burst interface designated, 16-bit mode always set. Number Access States: three access states selected with ASTCR. area which 2-state access selected functions 2-state access space, area which 3-state access selected functions 3-state access space. With DRAM interface burst interface, number access states determined without regard ASTCR. When 2-state access space designated, wait insertion disabled. Number Program Wait States: When 3-state access space designated ASTCR, number program wait states inserted automatically selected with WCRH WCRL. From program wait states selected. Table shows specifications each basic interface area.
Table
Specifications Each Area (Basic Interface)
WCRH, WCRL Specifications (Basic Interface) Width Program Wait Access States States
ABWCR ABWn
ASTCR ASTn
4.3.3
Memory Interfaces
chip's memory interfaces comprise basic interface that allows direct connection ROM, SRAM, DRAM interface that allows direct connection DRAM; burst interface that allows direct connection burst ROM. interface selected independently each area. area which basic interface designated functions normal space, area which DRAM interface designated functions DRAM space, area which burst interface designated functions burst space.
4.3.4
Advanced Mode
initial state each area basic interface, 3-state access space. initial width selected according operating mode. specifications described here cover basic items only, sections each memory interface (4.4, 4.5, 4.7) should referred further details. Area Area includes on-chip ROM*, ROM-disabled expansion mode, area external space. ROM-enabled expansion mode, space excluding on-chip ROM* external space. When area external space accessed, signal output. Either basic interface burst interface selected area Note: Only applies versions with ROM. Areas external expansion mode, area area external space. When area external space accessed, signals respectively output. Only basic interface used areas Areas external expansion mode, area area external space. When area external space accessed, signals output. Basic interface DRAM interface selected areas With DRAM interface, signals used signals. Area Area includes on-chip internal registers. external expansion mode, space excluding on-chip internal registers external space. on-chip enabled when RAME system control register (SYSCR) when RAME cleared on-chip disabled corresponding space becomes external space When area external space accessed, signal output. Only basic interface used area memory interface.
4.3.5
Chip Select Signals
chip output chip select signals (CS0 CS7) areas signal being driven when corresponding external space area accessed. Figure shows example output timing. Enabling disabling signal performed setting data direction register (DDR) port corresponding particular pin. ROM-disabled expansion mode, placed output state after power-on reset. Pins placed input state after power-on reset, corresponding bits should when outputting signals CS7. ROM-enabled expansion mode, pins placed input state after power-on reset, corresponding bits should when outputting signals CS7. details, Reference Manual, Ports section. When areas designated DRAM space, outputs used signals.
cycle
Address
Area external address
Figure Signal Output Timing
4.4.1
Basic Interface
Overview
basic interface enables direct connection ROM, SRAM, specifications selected with ABWCR, ASTCR, WCRH, WCRL (see table 43). 4.4.2 Data Size Data Alignment
Data sizes other internal masters byte, word, longword. controller data alignment function, when accessing external space, controls whether upper data (D15 lower data used according specifications area being accessed (8-bit access space 16-bit access space) data size. 8-Bit Access Space: Figure illustrates data alignment control 8-bit access space. With 8-bit access space, upper data (D15 always used accesses. amount data that accessed time byte: word transfer instruction performed byte accesses, longword transfer instruction, four byte accesses.
Upper data Lower data Byte size cycle cycle cycle Longword size cycle cycle cycle
Word size
Figure Access Sizes Data Alignment Control (8-Bit Access Space)
16-Bit Access Space: Figure illustrates data alignment control 16-bit access space. With 16-bit access space, upper data (D15 lower data used accesses. amount data that accessed time byte word, longword transfer instruction executed word transfer instructions. byte access, whether upper lower data used determined whether address even odd. upper data used even address, lower data address.
Upper data Lower data Byte size Byte size Word size Longword size cycle cycle Even address address
Figure Access Sizes Data Alignment Control (16-Bit Access Space)
4.4.3
Valid Strobes
Table shows data buses used valid strobes access spaces. read, signal valid without discrimination between upper lower halves data bus. write, signal valid upper half data bus, signal lower half. Table
Area 8-bit access space
Data Buses Used Valid Strobes
Access Read/ Size Write Byte Read Write Read Address Even Write Even Word Read Write Valid Strobe Valid Invalid Valid Hi-Z Valid Upper Data (D15 Valid Lower Data Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid
16-bit access Byte space
HWR, Valid
Note: Hi-Z: High impedance Invalid: Input state; input value ignored.
4.4.4
Basic Timing
8-Bit 2-State Access Space: Figure shows timing 8-bit 2-state access space. When 8-bit access space accessed, upper half (D15 data used. fixed high. Wait states cannot inserted.
cycle
Address
Read
Valid
Invalid
Write
High
Valid
High impedance
Note:
Figure Timing 8-Bit 2-State Access Space
8-Bit 3-State Access Space: Figure shows timing 8-bit 3-state access space. When 8-bit access space accessed, upper half (D15 data used. fixed high. Wait states inserted.
cycle
Address
Read
Valid
Invalid
Write
High
Valid High impedance
Note:
Figure Timing 8-Bit 3-State Access Space
16-Bit 2-State Access Space: Figures 4-10 show timings 16-bit 2-state access space. When 16-bit access space accessed, upper half (D15 data used even address, lower half address. Wait states cannot inserted.
cycle
Address
Read
Valid
Invalid
Write
High
Valid
High impedance
Note:
Figure Timing 16-Bit 2-State Access Space (Even Address Byte Access)
cycle
Address
Read
Invalid
Valid
High
Write High impedance
Valid
Note:
Figure Timing 16-Bit 2-State Access Space (Odd Address Byte Access)
cycle
Address
Read
Valid
Valid
Write Valid
Valid
Note:
Figure 4-10 Timing 16-Bit 2-State Access Space (Word Access)
16-Bit 3-State Access Space: Figures 4-11 4-13 show timings 16-bit 3-state access space. When 16-bit access space accessed upper half (D15 data used even address, lower half address. Wait states inserted.
cycle
Address
Read
Valid
Invalid
Write
High
Valid High impedance
Note:
Figure 4-11 Timing 16-Bit 3-State Access Space (Even Address Byte Access)
cycle
Address
Read
Invalid
Valid
High
Write High impedance
Note:
Valid
Figure 4-12 Timing 16-Bit 3-State Access Space (Odd Address Byte Access)
cycle
Address
Read
Valid
Valid
Write Valid
Note:
Valid
Figure 4-13 Timing 16-Bit 3-State Access Space (Word Access)
4.4.5
Wait Control
When accessing external space, H8S/2338 Series, H8S/2328 Series, H8S/2318 Series extend cycle inserting more wait states There ways inserting wait states: program wait insertion wait insertion using WAIT pin. Program Wait Insertion: From wait states inserted automatically between state state individual area basis 3-state access space, according settings WCRH WCRL. Wait Insertion: Setting WAITE BCRL enables wait insertion means WAIT pin. When external space accessed this state, program wait insertion first carried according settings WCRH WCRL. Then WAIT falling edge last state, state inserted. WAIT held low, states inserted until goes high. This useful when inserting four more states, when changing number states different external devices. WAITE setting applies areas*. Note: With some models that used wait input switched means WAITPS bit; reference manual relevant model check availability this function.
Figure 4-14 shows example wait state insertion timing.
program wait WAIT
WAIT
Address
Read Data Read data
HWR, Write Data Write data
Note:
indicates timing WAIT sampling.
Figure 4-14 Example Wait State Insertion Timing settings after power-on reset are: 3-state access, program wait state insertion, WAIT input disabled.
4.5.1
DRAM Interface
Overview
When chip advanced mode, external space areas designated DRAM space, DRAM interfacing performed. With DRAM interface, DRAM directly connected chip. DRAM space Mbytes means bits RMTS2 RMTS0 BCRH. Burst operation also possible, using fast page mode. 4.5.2 Setting DRAM Space
Areas designated DRAM space setting bits RMTS2 RMTS0 BCRH. relation between settings bits RMTS2 RMTS0 DRAM space shown table 4-5. Possible DRAM space settings are: area (area areas (areas four areas (areas Table
RMTS2
Settings Bits RMTS2 RMTS0 Corresponding DRAM Spaces
RMTS1 RMTS0 Area Normal space Normal space DRAM space DRAM space Area Area Area DRAM space
4.5.3
Address Multiplexing
With DRAM space, address column address multiplexed. address multiplexing, size shift address selected with bits MXC1 MXC0 MCR. Table shows relation between settings MXC1 MXC0 shift size. Table Address Multiplexing Settings Bits MXC1 MXC0
Column address Address Pins
Shift MXC1 MXC0 Size address bits bits bits
Setting prohibited
4.5.4
Data
ABWCR corresponding area designated DRAM space that area designated 8-bit DRAM space; cleared area designated 16-bit DRAM space. 16-bit DRAM space, configuration DRAM connected directly. 8-bit DRAM space upper half data bus, enabled, while 16-bit DRAM space both upper lower halves data bus, enabled. Access sizes data alignment same basic interface: section 4.4.2, Data Size Data Alignment. 4.5.5 Pins Used DRAM Interface
Table shows pins used DRAM interfacing their functions. Table DRAM Interface Pins
With DRAM Setting
Name Write enable
Function
Output When 2-CAS system set, write enable DRAM space access
LCAS
LCAS RAS2
Lower column address strobe Output Lower column address strobe 16-bit DRAM space access address strobe Output address strobe when area designated DRAM space Output address strobe when area designated DRAM space Output address strobe when area designated DRAM space Output address strobe when area designated DRAM space
RAS3
address strobe
RAS4
address strobe
RAS5
address strobe
WAIT
UCAS WAIT
Upper column address strobe Output Upper column address strobe DRAM space access Wait Address pins Data pins Input Wait request signal Output address/column address multiplexed output Data input/output pins
4.5.6
Basic Timing
Figure 4-15 shows basic access timing DRAM space. basic DRAM access timing states. Unlike basic interface, corresponding bits ASTCR control only enabling disabling wait insertion, affect number access states. When corresponding ASTCR cleared wait states cannot inserted DRAM access cycle. states basic timing consist (precharge cycle) state, (row address output cycle), (column address output cycle) states,
Column
(RAS)
CAS, LCAS
(WE) Read
(WE) Write
Note:
Figure 4-15 Basic Access Timing
4.5.7
Precharge State Control
When DRAM accessed, precharging time must secured. With chip, state always inserted when DRAM space accessed. This changed states setting appropriate number cycles according DRAM connected operating frequency chip. Figure 4-16 shows timing when states inserted. When states also used refresh cycles.
Column
(RAS)
CAS, LCAS (WE) Read HWR, (WE) Write
Note:
Figure 4-16 Timing with 2-State Precharge Cycle
4.5.8
Wait Control
There ways inserting wait states DRAM access cycle: program wait insertion wait insertion using WAIT pin. Program Wait Insertion: When ASTCR corresponding area designated DRAM space from wait states inserted automatically between state state, according settings WCRH WCRL. Wait Insertion: When WAITE BCRH wait input means WAIT enabled regardless setting ASTCR. When DRAM space accessed this state, program wait first inserted. WAIT falling edge last state, another state inserted. WAIT held low, states inserted until goes high. Note: wait input differs from model model; reference manual relevant model details. Figure 4-17 shows example wait state insertion timing.
program wait
WAIT
WAIT*
Address
(RAS)
Read Data Read data
Write Data Write data
Notes:
indicates timing WAIT sampling. that used wait input, setting conditions, differ from model model; reference manual relevant model details.
Figure 4-17 Example Wait State Insertion Timing
4.5.9
Byte Access Control
When DRAM with configuration connected, 2-CAS system used control signals required byte access. Figure 4-18 shows control timing 2-CAS system, figure 4-19 shows example 2-CAS type DRAM connection.
Column
(RAS)
Byte control LCAS
(WE)
Note:
Figure 4-18 2-CAS System Control Timing (Upper Byte Write Access)
Chip (Address shift size bits) (RAS) LCAS (WE)
2-CAS type 4-Mbit DRAM 256-kbyte 16-bit configuration 9-bit column address UCAS LCAS address input: Column address input:
Figure 4-19 Example 2-CAS DRAM Connection
4.5.10
Burst Operation
With DRAM, addition full access (normal access) which data accessed outputting address each access, fast page mode also provided which used when making number consecutive accesses same address. This mode enables fast (burst) access data simply changing column address after address been output. Burst access selected setting Burst Access (Fast Page Mode) Operation Timing: Figure 4-20 shows operation timing burst access. When there consecutive access cycles DRAM space, signal column address output cycles (two states) continue long address same consecutive access cycles. address used comparison with bits MXC1 MXC0 MCR.
(RAS)
Column
Column
CAS, LCAS (WE) Read (WE) Write
Note:
Figure 4-20 Operation Timing Fast Page Mode cycle also extended burst access inserting wait states. wait state insertion method timing same full access. details, section 4.5.8, Wait Control.
Down Mode Mode: Even when burst operation selected, happen that access DRAM space continuous, interrupted access another space. this case, signal held during access other space, burst operation resumed when same address DRAM space accessed again. down mode select down mode, RCDM access DRAM space interrupted another space accessed, signal held during access other space, burst access performed address next DRAM space access same address previous DRAM space access. Figure 4-21 shows example timing down mode. Note, however, that signal will high refresh operation interrupts down mode.
External space access
DRAM access
DRAM access
(RAS)
CAS, LCAS
Note:
Figure 4-21 Example Operation Timing Down Mode
mode select mode, clear RCDM Each time access DRAM space interrupted another space accessed, signal goes high again. Burst operation only performed DRAM space continuous. Figure 4-22 shows example timing mode. case burst space access, signal restored high level.
External space access
DRAM access
DRAM access
(RAS)
CAS, LCAS
Note:
Figure 4-22 Example Operation Timing Mode
4.5.11
Refresh Control
chip provided with DRAM refresh control function. Either refreshing methods selected: CAS-before-RAS (CBR) refreshing, self-refreshing. CAS-before-RAS (CBR) Refreshing: select refreshing, RFSHE DRAMCR clear RMODE With refreshing, RTCNT counts using input clock selected bits CKS2 CKS0 DRAMCR, when count matches value RTCOR (compare match), refresh control performed. same time, RTCNT reset starts counting again from H'00. Refreshing thus repeated fixed intervals determined RTCOR bits CKS2 CKS0. value RTCOR bits CKS2 CKS0 that will meet refreshing interval specification DRAM used. When bits CKS2 CKS0 set, RTCNT starts counting RTCNT RTCOR settings should therefore completed before setting bits CKS2 CKS0. clear flag when refresh control being performed (RFSHE RTCNT operation shown figure 4-23, compare match timing figure 4-24, refresh timing figure 4-25. Access other normal space performed during refresh interval.
RTCNT RTCOR
H'00 Refresh request
Figure 4-23 RTCNT Operation
RTCNT
H'00
RTCOR
Refresh request signal setting signal
Figure 4-24 Compare Match Timing
TRc1
TRc2
(RAS)
CAS, LCAS
Note:
Figure 4-25 Refresh Timing When signal output delayed cycle. width signal should adjusted with bits RLW1 RLW0. These bits only enabled refresh operations.
Figure 4-26 shows timing when
TRc1 TRc2
(RAS)
CAS, LCAS
Note:
Figure 4-26 Refresh Timing (When RLW1 RLW0 Self-Refreshing: self-refresh mode (battery backup mode) provided DRAM kind
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