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Hitachi 16-Bit Single-Chip Microcomputer
H8S/2194 Series, H8S/2194C Series, H8S/2194 F-ZTATTM, H8S/2194C F-ZTATH8S/2194, HD6432194, HD64F2194, H8S/2193, HD6432193 H8S/2192, HD6432192 H8S/2191, HD6432191 H8S/2194C, HD6432194C, HD64F2194C, H8S/2194B, HD6432194B H8S/2194A, HD6432194A
Hardware Manual
ADE-602-160A Rev. 11/10/00 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Main Revisions Additions this Edition
Page pages this manual Overview Differences between H8S/2194C Series H8S/2194 Series Item Revisions (See Manual Details) Amendments introduction H8S/2194C series Table Features Memory Product lineup amended Added
pages section 2.6.1 Overview Address Each Operating Mode Overview
Notes instruction added Table Instruction Classification Notes added Address maps H8S/2194C series added Table Internal Chip Status Each Mode Timer PSU, 12-bit added Sleep Watch modes amended Description amended Other supporting modules (excluding servo circuit 12-bit PWM) stop. Table MSTP Bits Corresponding On-Chip Supporting Modules Module corresponding MSTP1 amended Table Interrupt Response Times Note amended Added Figure Flash Memory Mode Transitions Amended Figure Boot Mode Amended 7.3.1 Flash Memory Control Register (FLMCR1) Description amended FLMCR1 initialized reset, power-down state (excluding medium-speed mode, module stop mode, sleep mode), when level input pin.
4.4.1 Sleep Mode
4.5.1 Module Stop Mode
6.4.5 Interrupt Response Times 6.5.4 When Disabled 7.2.3 Flash Memory Operating Modes
Rev. 2.0, 11/00, page
Page
Item 7.3.2 Flash Memory Control Register (FLMCR2)
Revisions (See Manual Details) Description amended bits cleared powerdown state (excluding medium-speed mode, module stop mode, sleep mode), hardware protect mode, software protect mode.
7.3.3 Erase Block Registers Description amended (EBR1, EBR2) EBR1 EBR2 each initialized H'00 reset, power-down state (excluding mediumspeed mode, module stop mode, sleep mode), when level input pin, when high level input FLMCR1 set. Table Flash Memory Erase Blocks address amended
On-Board Programming Modes 7.4.1 Boot Mode
Table Setting On-Board Programming Modes level program mode amended Figure Boot Mode Execution Procedure Flow amended Table System Clock Frequencies which Automatic Adjustment This Rate Possible 2400-bps transfer rate deleted Figure 7.10 Areas Boot Mode Programming control program area amended
7.5.1 Program Mode 7.5.2 Program-Verify Mode 7.5.3 Erase Mode 7.5.4 Erase-Verify Mode 7.6.1 Hardware Protection 7.6.3 Error Protection
Description amended (For details, flowchart figure 7.12.) Description amended (For details, flowchart figure 7.12.) Description amended (For details, flowchart figure 7.13.) Description amended (For details, flowchart figure 7.13.) Table Hardware Protection Reset/standby protection description amended FLER setting condition amended Figure 7.14 Flash Memory State Transitions amended Note amended
Interrupt Handling when Programming/Erasing Flash Memory 7.8.2 Socket Adapters Memory
Table Socket Adapter Product Codes amended
Rev. 2.0, 11/00, page
Page
Item 7.8.9 Programmer Mode Transition Time
Revisions (See Manual Details) Figure 7.23 Oscillation Stabilization Time, Boot Program Transfer Time, Power Supply Fall Sequence timing amended
7.10 Note Switching from Added F-ZTAT Version Mask Version Section (H8S/2194C Series) Overview 14.1.2 Block Diagram Added Description amended introduction H8S/2194C series Figure 14.1 Block Diagram Timer /1024 clock source (for H8S/2194C series) added
311, 531,
14.2.1 Timer Mode Register Bits (TMJ) Description amended 14.2.2 Timer Control Register (TMJC) 16.2.1 Timer Mode Register (TMRM1) description amended description amended
20.2.1 12-Bit Control Initialization description amended Registers (CPWCR, DPWCR) 20.2.2 12-Bit Data Initialization description amended Registers (CPWDR, DPWDR) 20.2.3 Module stop Control Register (MSTPCR) 23.1.2 Block Diagram Added Figure 23.1 Block Diagram SCI1 Register names amended
23.2.7 Serial Status Register (SSR1) Clearing conditions amended 25.1.4 Register Configuration Table 25.2 Register Configuration Note description amended 25.2.1 Data Register (ICDR) 25.2.5 Control Register (ICCR) 25.2.6 Status Register (ICSR) 25.2.7 Serial/Timer Control Register (STCR)
Description amended description amended description amended description amended description amended
Rev. 2.0, 11/00, page
Page 565,
Item 25.3.2 Master Transmit Operation 25.3.3 Master Receive Operation 25.3.5 Slave Transmit Operation 25.3.8 Sample Flowcharts
Revisions (See Manual Details) Description amended
Figure 25.14 Flowchart Master Transmit Mode (Example) amended Figure 25.15 Flowchart Master Receive Mode (Example) amended
25.3.9 Initialization Internal Added State 25.4 Usage Notes 27.3.7 Instruction Description added Figure 27.15 Instruction Description amended Stack storing Figure 28.1 Block Diagram Servo Circuits Amended Gain Control Register (CTLGR) Bits Amplifier Gain Setting Bits (CTLGR3 values output gain amended Figure 28.6 REF30 Signal Generator amended Reference Period Mode Register (RFM2) Selection Description amended FIFO Output Pattern Register (FPDRA) FIFO Output Pattern Register (FPDRB) Descriptions bits these registers added Reference Register (DFCRB) Descriptions bits added (11) Reference Count Register (DFCTR) Initial value amended descriptions added Completely Amended Drum Speed Error Detection Control Register (DFVCR) Descriptions bits amended
28.1.2 Block Diagram 28.2.5 Register Descriptions
28.3.2 Block Diagram 28.3.4 Register Descriptions
663,
28.4.5 Register Descriptions
667,
28.4.5 Register Descriptions
669,
28.4.6 Description Operation 28.6.4 Register Descriptions
Rev. 2.0, 11/00, page
Page
Item 28.8.4 Register Descriptions
Revisions (See Manual Details) Capstan Speed Error Detection Control Register (CFVCR) Descriptions bits amended Figure 28.46 Additional Pulse Negative Polarity Specified Value amended
28.12.5 Additional Pulse Signal
1017
28.13.5 Register Descriptions Duty Register (DI/O) Descriptions Mark Detect Mode amended 28.13.8 Duty Discriminator 28.14.2 Frequency Divider 28.17 Module Stop Control Register (MSTPCR) Electrical Characteristics Appendix Instruction Function List Values duty amended Figure 28.63 Frequency Divider amended Added Description amended introduction H8S/2194C series Notes instruction added Following list registers amended H'D097: RFM2 H'D0A4: CTLGR H'D13A: H'D13B: TMJC H'D148: SMR1 H'D14C: H'D158: ICCR H'D159: ICSR H'FFF8: FLMCR1 H'FFF9: FLMCR2 H'FFFA: EBR1 H'FFFB: EBR2
1019 1031 Circuit Diagrams 1035
Table Circuit Diagrams Completely amended
Sample External Circuits Figure Sample External Circuit Servo Section Amended Figure Example External Circuit Sync Signal Detection Circuit Section Amended
1036
Appendix List Product Codes
Figure Product Codes List H8S/2194 series H8S/2194C series
Rev. 2.0, 11/00, page
Contents
Section Overview.
Overview Internal Block Diagram Arrangement Functions. 1.3.1 Arrangement 1.3.2 Functions. Differences between H8S/2194C Series H8S/2194 Series.
Section
Overview 2.1.1 Features. 2.1.2 Differences between H8S/2600 H8S/2000 CPU. 2.1.3 Differences from H8/300 CPU. 2.1.4 Differences from H8/300H Operating Modes Address Space. Register Configuration 2.4.1 Overview. 2.4.2 General Registers 2.4.3 Control Registers. 2.4.4 Initial Register Values Data Formats 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction Set. 2.6.1 Overview. 2.6.2 Instructions Addressing Modes. 2.6.3 Table Instructions Classified Function. 2.6.4 Basic Instruction Formats 2.6.5 Notes Bit-Manipulation Instructions. Addressing Modes Effective Address Calculation 2.7.1 Addressing Mode 2.7.2 Effective Address Calculation. Processing States. 2.8.1 Overview. 2.8.2 Reset State. 2.8.3 Exception-Handling State 2.8.4 Program Execution State. 2.8.5 Power-Down State.
Rev. 2.0, 11/00, page xviii
Basic Timing 2.9.1 Overview 2.9.2 On-Chip Memory (ROM, RAM). 2.9.3 On-Chip Supporting Module Access Timing. 2.10 Usage Note
Section Operating Modes
Overview. 3.1.1 Operating Mode Selection 3.1.2 Register Configuration. Register Descriptions 3.2.1 Mode Control Register (MDCR). 3.2.2 System Control Register (SYSCR). Operating Mode Descriptions. 3.3.1 Mode Address Map.
Section Power-Down State
Overview. 4.1.1 Register Configuration. Register Descriptions 4.2.1 Standby Control Register (SBYCR) 4.2.2 Low-Power Control Register (LPWRCR) 4.2.3 Timer Register (TMA) 4.2.4 Module Stop Control Register (MSTPCR) Medium-Speed Mode. Sleep Mode. 4.4.1 Sleep Mode 4.4.2 Clearing Sleep Mode Module Stop Mode 4.5.1 Module Stop Mode Standby Mode. 4.6.1 Standby Mode 4.6.2 Clearing Standby Mode 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode Watch Mode 4.7.1 Watch Mode. 4.7.2 Clearing Watch Mode. Subsleep Mode 4.8.1 Subsleep Mode 4.8.2 Clearing Subsleep Mode Subactive Mode 4.9.1 Subactive Mode.
Rev. 2.0, 11/00, page xviii
4.9.2 Clearing Subactive Mode. 4.10 Direct Transition. 4.10.1 Overview Direct Transition
Section Exception Handling
Overview 5.1.1 Exception Handling Types Priority. 5.1.2 Exception Handling Operation 5.1.3 Exception Sources Vector Table Reset 5.2.1 Overview. 5.2.2 Reset Sequence. 5.2.3 Interrupts after Reset Interrupts Trap Instruction Stack Status after Exception Handling Notes Stack
Section Interrupt Controller.
Overview 6.1.1 Features. 6.1.2 Block Diagram 6.1.3 Configuration 6.1.4 Register Configuration. Register Descriptions 6.2.1 System Control Register (SYSCR). 6.2.2 Interrupt Control Registers (ICRA ICRD) 6.2.3 Enable Register (IENR). 6.2.4 Edge Select Registers (IEGR). 6.2.5 Status Register (IRQR). 6.2.6 Port Mode Register (PMR1) Interrupt Sources. 6.3.1 External Interrupts 6.3.2 Internal Interrupts 6.3.3 Interrupt Exception Vector Table Interrupt Operation. 6.4.1 Interrupt Control Modes Interrupt Operation. 6.4.2 Interrupt Control Mode 6.4.3 Interrupt Control Mode 6.4.4 Interrupt Exception Handling Sequence 6.4.5 Interrupt Response Times Usage Notes. 6.5.1 Contention between Interrupt Generation Disabling
Rev. 2.0, 11/00, page xviii
6.5.2 6.5.3 6.5.4
Instructions that Disable Interrupts. Interrupts during Execution EEPMOV Instruction. When Disabled
Section (H8S/2194 Series)
Overview. 7.1.1 Block Diagram Overview Flash Memory. 7.2.1 Features. 7.2.2 Block Diagram 7.2.3 Flash Memory Operating Modes. 7.2.4 Configuration 7.2.5 Register Configuration. Flash Memory Register Descriptions 7.3.1 Flash Memory Control Register (FLMCR1) 7.3.2 Flash Memory Control Register (FLMCR2) 7.3.3 Erase Block Registers (EBR1, EBR2). 7.3.4 Serial/Timer Control Register (STCR) On-Board Programming Modes. 7.4.1 Boot Mode 7.4.2 User Program Mode Programming/Erasing Flash Memory 7.5.1 Program Mode. 7.5.2 Program-Verify Mode 7.5.3 Erase Mode 7.5.4 Erase-Verify Mode Flash Memory Protection 7.6.1 Hardware Protection. 7.6.2 Software Protection 7.6.3 Error Protection. Interrupt Handling when Programming/Erasing Flash Memory. Flash Memory Programmer Mode 7.8.1 Programmer Mode Setting 7.8.2 Socket Adapters Memory 7.8.3 Programmer Mode Operation. 7.8.4 Memory Read Mode. 7.8.5 Auto-Program Mode. 7.8.6 Auto-Erase Mode 7.8.7 Status Read Mode. 7.8.8 Status Polling 7.8.9 Programmer Mode Transition Time 7.8.10 Notes Memory Programming Flash Memory Programming Erasing Precautions
Rev. 2.0, 11/00, page xviii
7.10 Note Switching from F-ZTAT Version Mask Version.
Section (H8S/2194C Series)
Overview 8.1.1 Block Diagram Overview Flash Memory. 8.2.1 Features. 8.2.2 Block Diagram 8.2.3 Flash Memory Operating Modes. 8.2.4 Configuration 8.2.5 Register Configuration. Flash Memory Register Descriptions 8.3.1 Flash Memory Control Register (FLMCR1) 8.3.2 Flash Memory Control Register (FLMCR2) 8.3.3 Erase Block Registers (EBR1) 8.3.4 Erase Block Registers (EBR2) 8.3.5 Serial/Timer Control Register (STCR) On-Board Programming Modes. 8.4.1 Boot Mode 8.4.2 User Program Mode. Programming/Erasing Flash Memory 8.5.1 Program Mode addresses H'0000 H'1FFFF addresses H'20000 H'3FFFF) 8.5.2 Program-Verify Mode addresses H'00000 H'1FFFF addresses H'20000 H'3FFFF) 8.5.3 Erase Mode addresses H'00000 H'1FFFF address H'20000 H'3FFFF) 8.5.4 Erase-Verify Mode addresses H'00000 H'1FFFF address H'20000 H'3FFFF) Flash Memory Protection 8.6.1 Hardware Protection 8.6.2 Software Protection 8.6.3 Error Protection. Interrupt Handling when Programming/Erasing Flash Memory. Flash Memory Programmer Mode 8.8.1 Programmer Mode Setting 8.8.2 Socket Adapters Memory 8.8.3 Programmer Mode Operation. 8.8.4 Memory Read Mode 8.8.5 Auto-Program Mode. 8.8.6 Auto-Erase Mode 8.8.7 Status Read Mode. 8.8.8 Status Polling
Rev. 2.0, 11/00, page xviii
8.8.9 Programmer Mode Transition Time 8.8.10 Notes Memory Programming Flash Memory Programming Erasing Precautions 8.10 Note Switching from F-ZTAT Version Mask Version
Section RAM.
Overview. 9.1.1 Block Diagram
Section Clock Pulse Generator.
10.1 Overview. 10.1.1 Block Diagram 10.1.2 Register Configuration. 10.2 Register Descriptions 10.2.1 Standby Control Register (SBYCR) 10.2.2 Low-Power Control Register (LPWRCR) 10.3 Oscillator. 10.3.1 Connecting Crystal Resonator 10.3.2 External Clock Input. 10.4 Duty Adjustment Circuit 10.5 Medium-Speed Clock Divider 10.6 Master Clock Selection Circuit 10.7 Subclock Oscillator Circuit 10.7.1 Connecting 32.768 Crystal Resonator 10.7.2 External Clock Input. 10.7.3 When Subclock Needed. 10.8 Subclock Waveform Shaping Circuit. 10.9 Notes Resonator
Section Port
11.1 Overview. 11.1.1 Port Functions 11.1.2 Port Input 11.1.3 Pull-Up Transistors 11.2 Port 11.2.1 Overview 11.2.2 Register Configuration. 11.2.3 Functions 11.2.4 States 11.3 Port 11.3.1 Overview 11.3.2 Register Configuration. 11.3.3 Functions
Rev. 2.0, 11/00, page xviii
11.3.4 States 11.4 Port 11.4.1 Overview. 11.4.2 Register Configuration. 11.4.3 Functions. 11.4.4 States 11.5 Port 11.5.1 Overview. 11.5.2 Register Configuration. 11.5.3 Functions. 11.5.4 States 11.6 Port 11.6.1 Overview. 11.6.2 Register Configuration. 11.6.3 Functions. 11.6.4 States 11.7 Port 11.7.1 Overview. 11.7.2 Register Configuration. 11.7.3 Functions. 11.7.4 States 11.8 Port 11.8.1 Overview. 11.8.2 Register Configuration. 11.8.3 Functions. 11.8.4 Operation 11.8.5 States 11.9 Port 11.9.1 Overview. 11.9.2 Register Configuration. 11.9.3 Functions. 11.9.4 States 11.10 Port 11.10.1 Overview. 11.10.2 Register Configuration. 11.10.3 Functions. 11.10.4 States
Section Timer
12.1 Overview 12.1.1 Features. 12.1.2 Block Diagram 12.1.3 Register Configuration.
Rev. 2.0, 11/00, page xviii
12.2 Descriptions Respective Registers 12.2.1 Timer Mode Register (TMA) 12.2.2 Timer Counter (TCA) 12.2.3 Module Stop Control Register (MSTPCR) 12.3 Operation. 12.3.1 Operation Interval Timer. 12.3.2 Operation Timer Clocks. 12.3.3 Initializing Counts.
Section Timer
13.1 Overview. 13.1.1 Features. 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration. 13.2 Descriptions Respective Registers 13.2.1 Timer Mode Register (TMB). 13.2.2 Timer Counter (TCB). 13.2.3 Timer Load Register (TLB). 13.2.4 Port Mode Register (PMR5) 13.2.5 Module Stop Control Register (MSTPCR) 13.3 Operation. 13.3.1 Operation Interval Timer. 13.3.2 Operation Auto Reload Timer 13.3.3 Event Counter
Section Timer
14.1 Overview. 14.1.1 Features. 14.1.2 Block Diagram 14.1.3 Configuration 14.1.4 Register Configuration. 14.2 Descriptions Respective Registers 14.2.1 Timer Mode Register (TMJ). 14.2.2 Timer Control Register (TMJC) 14.2.3 Timer Status Register (TMJS) 14.2.4 Timer Counter (TCJ). 14.2.5 Timer Counter (TCK) 14.2.6 Timer Load Register (TLJ). 14.2.7 Timer Load Register (TLK) 14.2.8 Module Stop Control Register (MSTPCR) 14.3 Operation. 14.3.1 8-bit Reload Timer (TMJ-1).
Rev. 2.0, 11/00, page viii xviii
14.3.2 8-bit Reload Timer (TMJ-2). 14.3.3 Remote Controlled Data Transmission
Section Timer
15.1 Overview 15.1.1 Features. 15.1.2 Block Diagram 15.1.3 Register Configuration. 15.2 Descriptions Respective Registers 15.2.1 Timer Mode Register (LMR). 15.2.2 Linear Time Counter (LTC). 15.2.3 Reload/Compare Match Register (RCR). 15.2.4 Module Stop Control Register (MSTPCR) 15.3 Operation. 15.3.1 Compare Match Clear Operation.
Section Timer
16.1 Overview 16.1.1 Features. 16.1.2 Block Diagram 16.1.3 Configuration 16.1.4 Register Configuration. 16.2 Descriptions Respective Registers 16.2.1 Timer Mode Register (TMRM1). 16.2.2 Timer Mode Register (TMRM2). 16.2.3 Timer Control/Status Register (TMRCS) 16.2.4 Timer Capture Register (TMRCP1) 16.2.5 Timer Capture Register (TMRCP2) 16.2.6 Timer Load Register (TMRL1). 16.2.7 Timer Load Register (TMRL2). 16.2.8 Timer Load Register (TMRL3). 16.2.9 Module Stop Control Register (MSTPCR) 16.3 Operation. 16.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1. 16.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2. 16.3.3 Reload Counter Timer TMRU-3 16.3.4 Mode Identification 16.3.5 Reeling Controls. 16.3.6 Acceleration Braking Processes Capstan Motor. 16.3.7 Slow Tracking Mono-multi Function 16.4 Interrupt Cause 16.5 Exemplary Settings Respective Functions 16.5.1 Mode Identification
Rev. 2.0, 11/00, page xviii
16.5.2 Reeling Controls. 16.5.3 Slow Tracking Mono-multi Function 16.5.4 Acceleration Braking Processes Capstan Motor.
Section Timer
17.1 Overview. 17.1.1 Features. 17.1.2 Block Diagram 17.1.3 Configuration 17.1.4 Register Configuration. 17.2 Descriptions Respective Registers 17.2.1 Free Running Counter (FRC). 17.2.2 Output Comparing Register (OCRA OCRB) 17.2.3 Input Capture Register Through (ICRA Through ICRD) 17.2.4 Timer Interrupt Enabling Register (TIER). 17.2.5 Timer Control/Status Register (TCSRX) 17.2.6 Timer Control Register (TCRX). 17.2.7 Timer Output Comparing Control Register (TOCR) 17.2.8 Module Stop Control Register (MSTPCR) 17.3 Operation. 17.3.1 Operation Timer 17.3.2 Counting Timing 17.3.3 Output Comparing Signal Outputting Timing. 17.3.4 Clearing Timing 17.3.5 Input Capture Signal Inputting Timing. 17.3.6 Input Capture Flag (ICFA through ICFD) Setting Timing 17.3.7 Output Comparing Flag (OCFA OCFB) Setting Timing 17.3.8 Overflow Flag (CVF) Setting Timing 17.4 Operation Mode Timer 17.5 Interrupt Causes. 17.6 Exemplary Uses Timer 17.7 Precautions when Using Timer 17.7.1 Competition between Writing Clearing with 17.7.2 Competition between Writing Counting with FRC. 17.7.3 Competition between Writing Comparing Match with 17.7.4 Changing Over Internal Clocks Counter Operations
Section Watchdog Timer (WDT)
18.1 Overview. 18.1.1 Features. 18.1.2 Block Diagram 18.1.3 Register Configuration. 18.2 Register Descriptions
Rev. 2.0, 11/00, page xviii
18.2.1 Watchdog Timer Counter (WTCNT). 18.2.2 Watchdog Timer Control/Status Register (WTCSR). 18.2.3 System Control Register (SYSCR). 18.2.4 Notes Register Access. 18.3 Operation. 18.3.1 Watchdog Timer Operation. 18.3.2 Interval Timer Operation 18.3.3 Timing Setting Overflow Flag (OVF) 18.4 Interrupts 18.5 Usage Notes. 18.5.1 Contention between Watchdog Timer Counter (WTCNT) Write Increment. 18.5.2 Changing Value CKS2 CKS0 18.5.3 Switching between Watchdog Timer Mode Interval Timer Mode
Section 8-Bit
19.1 Overview 19.1.1 Features. 19.1.2 Block Diagram 19.1.3 Configuration 19.1.4 Register Configuration. 19.2 Register Descriptions 19.2.1 Data Registers (PWR0, PWR1, PWR2, PWR3) 19.2.2 8-bit Control Register (PW8CR) 19.2.3 Port Mode Register (PMR3). 19.2.4 Module Stop Control Register (MSTPCR) 19.3 8-Bit Operation
Section 12-Bit
20.1 Overview 20.1.1 Features. 20.1.2 Block Diagram 20.1.3 Configuration 20.1.4 Register Configuration. 20.2 Register Descriptions 20.2.1 12-Bit Control Registers (CPWCR, DPWCR) 20.2.2 12-Bit Data Registers (CPWDR, DPWDR) 20.2.3 Module Stop Control Register (MSTPCR) 20.3 Operation. 20.3.1 Output Waveform.
Section 14-Bit
21.1 Overview
Rev. 2.0, 11/00, page xviii
21.1.1 Features. 21.1.2 Block Diagram 21.1.3 Configuration 21.1.4 Register Configuration. 21.2 Register Descriptions 21.2.1 Control Register (PWCR) 21.2.2 Data Registers (PWDRU, PWDRL). 21.2.3 Module Stop Control Register (MSTPCR) 21.3 14-Bit Operation
Section Prescalar Unit.
22.1 Overview. 22.1.1 Features. 22.1.2 Block Diagram 22.1.3 Configuration 22.1.4 Register Configuration. 22.2 Registers. 22.2.1 Input Capture Register (ICR1) 22.2.2 Prescalar Unit Control/Status Register (PCSR). 22.2.3 Port Mode Register (PMR1) 22.3 Noise Cancel Circuit 22.4 Operation. 22.4.1 Prescalar (PSS). 22.4.2 Prescalar (PSW). 22.4.3 Stable Oscillation Wait Time Count 22.4.4 8-Bit PWM. 22.4.5 8-Bit Input Capture Using 22.4.6 Frequency Division Clock Output
Section Serial Communication Interface (SCI1)
23.1 Overview. 23.1.1 Features. 23.1.2 Block Diagram 23.1.3 Configuration 23.1.4 Register Configuration. 23.2 Register Descriptions 23.2.1 Receive Shift Register (RSR). 23.2.2 Receive Data Register (RDR1) 23.2.3 Transmit Shift Register (TSR) 23.2.4 Transmit Data Register (TDR1) 23.2.5 Serial Mode Register (SMR1). 23.2.6 Serial Control Register (SCR1). 23.2.7 Serial Status Register (SSR1).
Rev. 2.0, 11/00, page xviii
23.2.8 Rate Register (BRR1) 23.2.9 Serial Interface Mode Register (SCMR1) 23.2.10 Module Stop Control Register (MSTPCR) 23.3 Operation. 23.3.1 Overview. 23.3.2 Operation Asynchronous Mode. 23.3.3 Multiprocessor Communication Function. 23.3.4 Operation Clock Synchronous Mode 23.4 SCI1 Interrupts 23.5 Usage Notes.
Section Serial Communication Interface (SCI2)
24.1 Overview 24.1.1 Features. 24.1.2 Block Diagram 24.1.3 Configuration 24.1.4 Register Configuration. 24.2 Register Descriptions 24.2.1 Starting Address Register (STAR) 24.2.2 Ending Address Register (EDAR). 24.2.3 Serial Control Register (SCR2) 24.2.4 Serial Control Status Register (SCSR2). 24.2.5 Module Stop Control Register (MSTPCR) 24.3 Operation. 24.3.1 Clock 24.3.2 Data Transfer Format. 24.3.3 Data Transfer Operations 24.4 Interrupt Sources.
Section Interface (IIC)
25.1 Overview 25.1.1 Features. 25.1.2 Block Diagram 25.1.3 Configuration 25.1.4 Register Configuration. 25.2 Register Descriptions 25.2.1 Data Register (ICDR). 25.2.2 Slave Address Register (SAR) 25.2.3 Second Slave Address Register (SARX) 25.2.4 Mode Register (ICMR) 25.2.5 Control Register (ICCR) 25.2.6 Status Register (ICSR) 25.2.7 Serial/Timer Control Register (STCR)
Rev. 2.0, 11/00, page xiii xviii
25.2.8 Module Stop Control Register (MSTPCR) 25.3 Operation. 25.3.1 Data Format. 25.3.2 Master Transmit Operation 25.3.3 Master Receive Operation. 25.3.4 Slave Receive Operation. 25.3.5 Slave Transmit Operation 25.3.6 IRIC Setting Timing Control 25.3.7 Noise Canceler 25.3.8 Sample Flowcharts 25.3.9 Initialization Internal State. 25.4 Usage Notes.
Section Converter.
26.1 Overview. 26.1.1 Features. 26.1.2 Block Diagram 26.1.3 Configuration 26.1.4 Register Configuration. 26.2 Register Descriptions 26.2.1 Software-Triggered Result Register (ADR) 26.2.2 Hardware-Triggered Result Register (AHR) 26.2.3 Control Register (ADCR). 26.2.4 Control/Status Register (ADCSR) 26.2.5 Trigger Select Register (ADTSR) 26.2.6 Port Mode Register (PMR0) 26.2.7 Module Stop Control Register (MSTPCR) 26.3 Interface Master 26.4 Operation. 26.4.1 Software-Triggered Conversion. 26.4.2 Hardware- External-Triggered Conversion 26.5 Interrupt Sources.
Section Address Trap Controller (ATC).
27.1 Overview. 27.1.1 Features. 27.1.2 Block Diagram 27.1.3 Register Configuration. 27.2 Register Descriptions 27.2.1 Address Trap Control Register (ATCR) 27.2.2 Trap Address Register (TAR2 TAR0) 27.3 Precautions Usage. 27.3.1 Basic Operations
Rev. 2.0, 11/00, page xviii
27.3.2 27.3.3 27.3.4 27.3.5 27.3.6 27.3.7 27.3.8 27.3.9
Enable Instruction Instruction. Instruction Instruction Instruction SLEEP Instruction. Competing Interrupt
Section Servo Circuits.
28.1 Overview 28.1.1 Functions. 28.1.2 Block Diagram 28.2 Servo Port. 28.2.1 Overview. 28.2.2 Block Diagram 28.2.3 Configuration 28.2.4 Register Configuration. 28.2.5 Register Descriptions. 28.2.6 DFG/DPG Input Signals 28.3 Reference Signal Generators 28.3.1 Overview. 28.3.2 Block Diagram 28.3.3 Register Configuration. 28.3.4 Register Descriptions. 28.3.5 Description Operation. 28.4 (Head-switch) Timing Generator. 28.4.1 Overview. 28.4.2 Block Diagram 28.4.3 Composition. 28.4.4 Register Configuration. 28.4.5 Register Descriptions. 28.4.6 Description Operation. 28.4.7 Interrupt 28.4.8 Cautions 28.5 Four-head High-speed Switching Circuit Special Playback. 28.5.1 Overview. 28.5.2 Block Diagram 28.5.3 Configuration 28.5.4 Register Description 28.6 Drum Speed Error Detector. 28.6.1 Overview. 28.6.2 Block Diagram
Rev. 2.0, 11/00, page xviii
28.7
28.8
28.9
28.10
28.11
28.12
28.13
28.6.3 Register Configuration. 28.6.4 Register Descriptions. 28.6.5 Description Operation 28.6.6 Correction Trick Play Mode Drum Phase Error Detector 28.7.1 Overview 28.7.2 Block Diagram 28.7.3 Register Configuration. 28.7.4 Register Descriptions. 28.7.5 Description Operation 28.7.6 Phase Comparison Capstan Speed Error Detector 28.8.1 Overview 28.8.2 Block Diagram 28.8.3 Register Configuration. 28.8.4 Register Descriptions. 28.8.5 Description Operation Capstan Phase Error Detector. 28.9.1 Overview 28.9.2 Block Diagram 28.9.3 Register Configuration. 28.9.4 Register Descriptions. 28.9.5 Description Operation X-Value Tracking Adjustment Circuit. 28.10.1 Overview 28.10.2 Block Diagram 28.10.3 Register Descriptions. Digital Filters. 28.11.1 Overview 28.11.2 Block Diagram 28.11.3 Arithmetic Buffer 28.11.4 Register Configuration. 28.11.5 Register Descriptions. 28.11.6 Filter Characteristics. 28.11.7 Operations Case Transient Response. 28.11.8 Initialization Additional Signal Generator 28.12.1 Overview 28.12.2 Configuration 28.12.3 Register Configuration. 28.12.4 Register Description 28.12.5 Additional Pulse Signal. Circuit
Rev. 2.0, 11/00, page xviii
28.14
28.15
28.16
28.17
28.13.1 Overview. 28.13.2 Block Diagram 28.13.3 Configuration 28.13.4 Register Configuration. 28.13.5 Register Descriptions. 28.13.6 Operation 28.13.7 Input Section 28.13.8 Duty Discriminator. 28.13.9 Output Section. 28.13.10 Trapezoid Waveform Circuit. 28.13.11 Note Interrupt Frequency Dividers. 28.14.1 Overview. 28.14.2 Frequency Divider. 28.14.3 Frequency Divider. 28.14.4 Noise Removal Circuit Sync Signal Detector. 28.15.1 Overview. 28.15.2 Block Diagram 28.15.3 Configuration 28.15.4 Register Configuration. 28.15.5 Register Descriptions. 28.15.6 Noise Detection. 28.15.7 Sync Signal Detector Activation Servo Interrupt 28.16.1 Overview. 28.16.2 Register Configuration. 28.16.3 Register Description Module Stop Control Reigster (MSTPCR).
Section Electrical Characteristics.
29.1 Absolute Maximum Ratings 29.2 Electrical Characteristics HD64F2194 29.2.1 Characteristics HD64F2194. 29.2.2 Allowable Output Currents HD64F2194, HD64F2194C. 29.2.3 Characteristics HD64F2194, HD64F2194C 29.2.4 Serial Interface Timing HD64F2194, HD64F2194C. 29.2.5 Converter Characteristics HD64F2194, HD64F2194C 29.2.6 Servo Section Electrical Characteristics HD64F2194, HD64F2194C 29.2.7 FLASH Memory Characteristics 29.2.8 Usage Note. 29.3 Electrical Characteristics HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A.
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29.3.1 Characteristics HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A 29.3.2 Allowable Output Currents HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A. 29.3.3 Characteristics HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A 29.3.4 Serial Interface Timing HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A. 29.3.5 Converter Characteristics HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A. 29.3.6 Servo Section Electrical Characteristics HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, HD6432194A
Appendix Instruction Set.
Instructions. Instruction Codes Operation Code Map. Number Execution States Status During Instruction Execution Change Condition Codes.
Appendix Internal Registers
Addresses Function List.
Appendix Circuit Diagrams. 1018
Circuit Diagrams. 1018
Appendix Port States Difference Processing States. 1032
Circuit Diagrams. 1032
Appendix Usage Notes 1033
Power Supply Rise Fall Order. 1033 Handling When High-Speed Switching Circuit Four-Head Special Playback Used. 1034 Sample External Circuits. 1035
Appendix List Product Codes 1036 Appendix External Dimensions. 1037
Rev. 2.0, 11/00, page xviii xviii
Section Overview
Overview
H8S/2194 Series, H8S/2194C Series comprise microcomputers (MCUs) built around H8S/2000 CPU, employing Hitachi's proprietary architecture, equipped with supporting modules on-chip. H8S/2000 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. H8S/2194 Series, H8S/2194C Series incorporated with digital servo circuit, ROM, RAM, seven types timers, three types PWM, types serial communication interface, interface, converter, port on-chip supporting modules. on-chip either flash memory (F-ZTATTM*) mask ROM, with capacity 256, 192, 160, 128, 112, kbytes. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching been speeded processing speed increased. features H8S/2194 Series, H8S/2194C Series shown table 1.1. Note: F-ZTATis trademark Hitachi, Ltd.
Rev. 2.0, 11/00, page 1037
Table
Item
Features
Specifications General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Maximum operating frequency: MHz/4 Operable subclock High-speed arithmetic operations 8/16/32-bit register-register add/subtract: operation) 16-bit register-register multiply: 2000 operation) 16-bit register-register divide: 2000 operation) Sixty-five basic instructions 8/16/32-bit transfer/arithmetic logic instructions Unsigned/signed multiply divide instructions Powerful bit-manipulation instructions Advanced mode: 16-Mbyte address space
High-speed operation suitable real-time control
Instruction suitable high-speed operation Timer
operating modes Seven types timer incorporated Timer 8-bit interval timer Clock source selected among types internal clock which frequencies divided from system clock subclock (SUB) Functions clock time base subclock input Functions 8-bit interval timer reload timer Clock source selected among types internal clock external event input Functions 8-bit down counters 16-bit down counter (reload timer/event counter timer/timer output, etc., types operation modes) Remote controlled transmit function Take up/Supply Reel Pulse Frequency division
Timer
Timer
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Item Timer
Specifications Timer 8-bit up/down counter Clock source selected among types internal clock, frequency division signal, REC-CTL (control pulse) Compare-match clearing function/auto reload function Three reload timers Mode discrimination Reel control Capstan motor acceleration/deceleration detection function Slow tracking mono-multi 16-bit free-running counter Clock source selected among types internal clock DVCFG output compare outputs Four input capture inputs Functions watchdog timer 8-bit interval timer Generates reset signal overflow Divides system clock frequency generates frequency division clock supporting module functions Divides subclock frequency generates input clock Timer (clock time base) Generates 8-bit frequency duty period 8-bit input capture external signal edge Frequency division clock output enabled
Timer
Timer
Watchdog timer
Prescaler unit
Three types incorporated 14-bit PWM: Pulse resolution type channel 8-bit PWM: Duty control type channels 12-bit PWM: Pulse pitch control type channels
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Item Serial communication interface (SCI)
Specifications types serial communication interface incorporated SCI1 Asynchronous mode synchronous mode selectable Desired rate selectable with built-in baud rate generator Multiprocessor communication function 32-byte data automatically transferrable Transfer clock selectable among seven types internal/external clock Conforms Phillips interface standard Single master mode/slave mode Arbitration lost condition identified Supports slave addresses Resolution: bits Input: channels High-speed conversion: 13.4 minimum conversion time operation) Sample-and-hold function conversion activated software external trigger Interrupt occurs when preset address found during cycle To-be-trapped addresses individually three different locations input/output pins input-only pins switched each supporting module Input output circuits Error detection circuit Phase gain compensation separately detect horizontal vertical sync signals Noise detection function
SCI2
interface
converter
Address trap controller
port
Servo circuit
Digital servo circuits on-chip
Sync signal detector
On-chip sync signal detection circuit
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Item Memory
Specifications Flash memory mask High-speed static Product Name H8S/2194C H8S/2194B H8S/2194A H8S/2194 H8S/2193 H8S/2192 H8S/2191 kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes
Power-down state
Medium-speed mode Sleep mode Module stop mode Standby mode Subclock operation Subactive mode, watch mode, subsleep mode Seven external interrupt pins (10,, ,54) internal interrupt sources Three priority levels settable System clock pulse generator: Subclock pulse generator: 32.768 112-pin plastic (FP-112) Product Code Series H8S/2194C Mask Versions HD6432194C HD6432194B HD6432194A H8S/2194 HD6432194 HD6432193 HD6432192 HD6432191 F-ZTAT Versions HD64F2194C HD64F2194 ROM/RAM (bytes) Packages FP-112 FP-112 FP-112 FP-112 FP-112 FP-112 FP-112
Interrupt controller
Clock pulse generator
types clock pulse generator on-chip
Packages Product lineup
Rev. 2.0, 11/00, page 1037
Internal Block Diagram
internal block diagram chip shown figure 1.1.
OSC1 OSC2
External address
External address
External data
External data
P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 P17/TMOW P16/IC P15/IRQ5 P14/IRQ4 P13/IRQ3 P12/IRQ2 P11/IRQ1 P10/IRQ0 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVCC AVSS P83/SV2 P82/SV1 P81/EXCAP P80/EXTTRG
Port
Internal data Internal address controller Address trap controller Prescaler unit
Port
H8S/2000
P37/TMO P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/STRB P30/CS P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/PWM14 P53/TRIG P52/TMBI P50/ADTRG P67/RP7 P66/RP6 P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 P77/PPG7 P76/PPG6 P75/PPG5 P74/PPG4 P73/PPG3 P72/PPG2 P71/PPG1 P70/PPG0
Port
Subclock pulse generator System clock pulse generator
Interrupt controller 8-bit Watchdog timer
Port
Timer Timer SCI1 SCI2 Timer
analog port
interface converter
Timer
Timer Servo circuit
14-bit
Port
Sync signal detection
Servo pins (CTL input/output amplifier, three-level output, etc.)
SVCC SVSS
Figure Internal Block Diagram H8S/2194 Series
Rev. 2.0, 11/00, page 1037
H.Amp SW/PS1 C.Rotary/PS0 COMP/PS2 DPG/PS3 EXCTL/PS4 DRMPWM CAPPWM AUDIO VIDEO Vpulse CLT(+) CLT(-) CTLBias CTLAmp(o) CTLSMT(i) CTLFB
Csync
Port
Port
Port
Timer
Port
1.3.1
Arrangement Functions
Arrangement
arrangement chip shown figure 1.2.
P72/PPG2 P71/PPG1 P70/PPG0 P67/RP7 P66/RP6 P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 OSC2 OSC1 P17/TMOW P16/IC P15/IRQ5 P14/IRQ4 P13/IRQ3
P73/PPG3 P74/PPG4 P75/PPG5 P76/PPG6 P77/PPG7 P80/EXTTRG P81/EXCAP P82/SV1 P83/SV2 Csync AUDIO VIDEO C.Rotary/PS0 H.Amp sw/PS1 COMP/PS2 EXCTL/PS4 DPG/PS3 Vpulse CTLREF
FP-112 (Top view)
P12/IRQ2 P11/IRQ1 P10/IRQ0 P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 P37/TMO P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/STRB P30/CS P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA
CTL(+) SVSS CTL(-) CTLBias CTLFB CTLAmp(o) CTLSMT(i) SVCC AVCC P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 AVSS P50/ADTRG P52/TMBI P53/TRIG P40/PWM14
Figure Arrangement H8S/2194 Series
Rev. 2.0, 11/00, page 1037
1.3.2
Functions
Table summarizes functions chip's pins. Table
Type Power supply
Functions
Symbol Input Name Function Power supply: pins should connected system power supply (+5V) Ground: pins should connected system power supply (0V) Servo power supply: SVcc should connected servo analog power supply (+5V) Servo ground: SVss should connected servo analog power supply (0V) Analog power supply: Power supply converter. should connected system power supply (+5V) when converter used Analog ground: Ground converter. should connected system power supply (0V) Connected crystal oscillator. also input external clock. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input Connected 32.768 crystal oscillator. section Clock Pulse Generator, typical connection diagrams Mode pins: These pins operating mode. These pins should changed while operation
Input
SVcc
Input
SVss
Input
AVcc
Input
AVss
Input
Clock
OSC1 OSC2
Input Output
Operating mode control
Input Output Input
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Type System control
Symbol
Input Input
Name Function Reset input: When this driven low, chip reset Flash memory enable: Enables/disables flash memory programming. This available only with with flash memory on-chip. mask type, connect anything this External interrupt request External interrupt input which rising edge sense, falling edge sense both edges sense selectable External interrupt requests External interrupt input pins which rising falling edge sense selectable
Interrupts
Input
Input
Input
Nonmaskable interrupt: Nonmaskable interrupt input which rising edge sense, falling edge sense both edges sense selectable Input capture input: Input capture input prescaler unit Frequency division clock output: Output clock which frequency divided prescaler Timer event input: Input events input Timer counter Timer event input: Input events input Timer RDT1or RDT-2 counter Timer timer output: Output toggle underflow RDT-1 Timer remote controlled transmit data Timer buzzer output: Output toggle which selectable among fixed frequency, frequency divided from subclock kHz), frequency division signal
Prescaler unit
TMOW
Input Output
Timers
TMBI
Input
Input
Output
BUZZ
Output
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Type Timers
Symbol
Input
Name Function Timer input capture: Input input capture Timer TMRU-1 TMRU-2 Timer output compare output: Output output compare Timer Timer input capture input: Input input capture Timer 8-bit square waveform output: Output waveform generated 8-bit 14-bit square waveform output: Output waveform generated 14-bit clock input/output: Clock input pins receive data input: Receive data input pins transmit data output: Transmit data output pins SCI2 strobe output: This outputs strobe pulse each byte transmit SCI2 SCI2 chip select input: This controls transfer start SCI2 interface clock input/output: Clock input/output interface interface data input/output: Data input/output interface
FTOA FTOB FTIA FTIB FTIC FTID PWM0 PWM1 PWM2 PWM3 PWM14
Output
Input
Output
Output
Serial communication interface (SCI)
SCK1 SCK2 STRB
Input /output Input Output Output
interface
Input Input /output Input /output
Rev. 2.0, 11/00, page 1037
Type converter
Symbol
Input
Name Function Analog input channels Analog data input pins. conversion started software triggering Analog input channels Analog data input pins. conversion started external, hardware, software triggering conversion external trigger input: input external trigger start conversion Audio Output audio head switching signal Video Output video head switching signal Capstan mix: 12-bit output giving result capstan speed error phase error after filtering Drum mix: 12-bit output giving result drum speed error phase error after filtering Additional pulse: Three-level output additional signal synchronized Video signal Color rotary signal: Output color signal processing control signal four-head special-effects playback Head-amp switch: Output preamplifier output select signal four-head special-effects playback. This also used general port when used Compare input: Input signal giving result preamplifier output comparison four-head special-effects playback. This also used general port when used head pins: pins signals primary bias supply: Bias supply primary
Input
$'75*
Input
Servo circuits
AUDIO VIDEO CAPPWM
Output Output Output
DRMPWM
Output
Vpulse
Output
C.Rotary /PS0 H.AmpSW /PS1
Output, input/ output Output, input/ output Input, input/ output
COMP /PS2
Bias
Input /output Input
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Type Servo circuits
Symbol CTLFB
Output Input Input
Name Function output: Output Schmitt input: Input Schmitt feedback input: Input high-range characteristics control reference voltage output: Output 1/2Vcc (SV) Capstan input: Schmitt comparator input signal Drum input: Schmitt input signal Drum input: Schmitt input signal. This also used general port when used External input: Input external signal. This also used general port when used Mixed sync signal input: Input mixed sync signal Capstan external sync signal input: Signal input external synchronization capstan phase control External trigger signal input: Signal input synchronization with reference signal generator Servo monitor output Output servo module internal signal Servo monitor output Output servo module internal signal PPG: Output timing generator. used when head switching required well Audio Video
CTLREF DPG/PS3
Output Input Input Input, input/ output Input, input/ output Input Input
EXCTL /PS4 Csync EXCAP
EXTTRG
Input
PPG7 PPG0
Output Output Output
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Type port
Symbol
Input Input /output Input /output Input /output Input /output Input /output Input /output Input /output Input /output Output Input
Name Function Port 8-bit input pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Port 4-bit pins Port 8-bit pins Port 8-bit pins Port 8-bit pins Realtime output port: 8-bit realtime output pins Realtime output port trigger input: Input realtime output port trigger
TRIG
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Differences between H8S/2194C Series H8S/2194 Series
Though H8S/2194C series compatible with H8S/2194 series their supporting modules almost identical, there some differences between them shown below. details, following sections. Table Differences between H8S/2194C series H8S/2194 series
H8S/2194C Series H8S/2194C: kbytes H8S/2194B: kbytes H8S/2194A: kbytes H8S/2194C: kbytes H8S/2194B: kbytes H8S/2194A: kbytes Timer Five operating modes: TMJ-2 input clock sources: PSS=/16384, /2048, /1024; underflow TMJ-1, external clock (IRQ2) reference signal generator, servo circuit selects whether reference signals generated with when mode, freerun kbytes When flash control flag set, (erase) (program) flash memory control register (FMLCR1). H8S/2194 Series H8S/2194: kbytes H8S/2193: kbytes H8S/2192: kbytes H8S/2191: kbytes H8S/2194: kbytes H8S/2193: kbytes H8S/2192: kbytes H8S/2191: kbytes Four operating modes: TMJ-2 input clock sources: PSS=/16384 /2048; underflow TMJ-1, external clock (IRQ2) reference signal generator, when servo circuit mode, reference signals generated free-run kbytes When flash control flag set, (erase) (program) flash memory control register (FMLCR2).
Servo circuit
Flash
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Section
Overview
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2000 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally) High-speed operation frequently-used instructions execute states Maximum clock rate: 8/16/32-bit register-register add/subtract: 8-bit register-register multiply: 1200
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8-bit register-register divide: 1200 16-bit register-register multiply: 2000 16-bit register-register divide: 2000 operating modes Normal mode*/Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection Note: Normal mode available this LSI. 2.1.2 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. Number execution states number execution states MULXU MULXS instructions differ follows.
Number Execution States Instruction MULXU MULXS Mnemonic MULXU.B MULXU.W MULXS.B MULXS.W H8S/2600 H8S/2000
There also differences address space, register functions, power-down state, etc., depending product. 2.1.3 Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit extended registers, 8-bit control register, have been added.
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Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing mode addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.4 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
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Operating Modes
H8S/2000 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum total address space Gbytes, with maximum Mbytes program area maximum Gbytes data area). mode selected mode pins microcontroller.
Maximum kbytes program data areas combined
Normal mode*
operating mode
Advanced mode Note: Normal mode available this LSI.
Maximum Mbytes program data areas combined
Figure Operating Modes Normal Mode exception vector table stack have same structure H8/300 CPU. Address Space maximum address space kbytes accessed. Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with predecrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction instructions addressing modes used. Only lower bits effective addresses (EA) valid.
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Exception Vector Table Memory Indirect Branch Addresses normal mode area starting H'0000 allocated exception vector table. branch address stored bits. configuration exception vector table normal mode shown figure 2.2. details exception vector table, section Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16-bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
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Stack Structure When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.3. extended control register (EXR) pushed onto stack. details, section Exception Handling.
bits)
CCR* bits)
Subroutine Branch Note: Ignored when returning.
Exception Handling
Figure Stack Structure Normal Mode Advanced Mode Address Space Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction instructions addressing modes used.
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Exception Vector Table Memory Indirect Branch Addresses advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2.4). details exception vector table, section Exception Handling.
H'00000000
Reserved
Reset exception vector
H'00000003 H'00000004
Reserved
H'00000007 H'00000008
Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
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Stack Structure advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.5. extended control register (EXR) pushed onto stack. details, section Exception Handling.
Reserved bits)
bits)
Subroutine Branch
Exception Handling
Figure Stack Structure Advanced Mode
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Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'0000 H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot used with this
H'FFFFFFFF Normal mode* Advanced mode
Note: Normal mode available this LSI.
Figure Memory
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2.4.1
Register Configuration
Overview
internal registers shown figure 2.7. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) EXR* [Legend]
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: Does affect operation this LSI.
Figure Registers
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2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers
8-bit registers
registers (extended registers) registers (ER0 ER7) registers registers (R0L R7L) registers (R0H R7H)
Figure Usage General Registers General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
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Free area (ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR). Program Counter (PC) This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR) 8-bit register. this LSI, this register does affect operation. Trace This reserved. this LSI, this does affect operation. Bits Reserved These bits reserved. They always read Bits Interrupt Mask Bits These bits reserved. this LSI, these bits affect operation. Condition: Code Register (CCR) This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. Interrupt Mask Masks interrupts other than when (NMI accepted regardless setting.) hardware start exception-handling sequence. details, section Interrupt Controller.
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User Interrupt Mask (UI) written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details, section Interrupt Controller. Half-Carry Flag When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. User written read software using LDC, STC, ANDC, ORC, XORC instructions. Negative Flag Stores value most significant (sign bit) data. Zero Flag indicate zero data, cleared indicate non-zero data. Overflow Flag when arithmetic overflow occurs, cleared otherwise. Carry Flag when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store carry carry flag also used accumulator bit-manipulation instructions. Some instructions leave some flag bits unchanged. action each instruction flag bits, section Appendix A.1, List Instructions. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
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Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4bit data. 2.5.1 General Register Data Formats
Figure 2.10 shows data formats general registers.
Data type
General Register
Data Format Don't care
1-bit data
1-bit data Don't care
4-bit data
Don't care
Upper digit Lower digit
4-bit data
Don't care
Upper digit Lower digit
Byte data
Don't care
Byte data
Don't care
Figure 2.10 General Register Data Formats
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Data Type
General Register
Data format
Word data
Word data
Longword data
[Legend] General register General register General register
General register General register Most significant Least significant
Figure 2.10 General Register Data Formats
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2.5.2
Memory Data Formats
Figure 2.11 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address
Data Format
Byte data
Address
Word data
Address Address 2M+1
Longword data
Address Address 2N+1 Address 2N+2 Address 2N+3
Figure 2.11 Memory Data Formats When (SP) used address register access stack, operand size should word size longword size.
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2.6.1
Instruction
Overview
H8S/2000 types instructions. instructions classified function table 2.1. Table
Function Data transfer
Instruction Classification
Instructions PUSH LDM, SMOVFPE MOVTPE
Size
Types
Arithmetic
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*4
Logic operations Shift manipulation
AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR RSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Branch System control Block data transfer
Total: types
Notes: byte size; word size; longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. available this LSI. Only register ER0, ER1, ER4, should used when using instruction. Rev. 2.0, 11/00, page 1037
2.6.2
Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2000 use. Table Combinations Instructions Addressing Modes
Addressing Modes
@-ERn/@ERn+ Function @(d:16, ERn) @(d:32, ERn) @(d:8, @(d:16,
@aa:16
@aa:24
@aa:32
@aa:8
@ERn
@@aa:8
Instruction
POP, PUSH LDM, SMOVFPE, MOVTPE*1 ADD, ADDX, SUBX ADDS, SUBS INC, DAA, MULXU, DIVXU MULXS, DIVXS EXTU, EXTS TAS*2 AND,
Data transfer
Shift manipulation Bcc, Branch JMP, TRAPA SLEEP ANDC, ORC, XORC Block data transfer
System control
Logic operation
Arithmetic operations
[Legend] Byte Work Longword Note: Cannot used this LSI. Only register ER0, ER1, ER4, should used when using instruction.
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2.6.3
Table Instructions Classified Function
Table 2.10 summarize instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM Disp :8/:16/:24/:32 Note: General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
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Table
Instruction
Data Transfer Instructions
Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register
MOVFPE MOVTPE
Cannot used this Cannot used this @SP+ Pops general register from stack POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+,
PUSH
@-SP Pushes general register onto stack PUSH.W identical MOV.W @-SP PUSH.L identical MOV.L ERn, @-SP
SNote:
@SP+ (register list) Pops more general registers from stack (register list) @-SP Pushes more general registers onto stack
Size refers operand size. Byte Word Longword
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Table
Instruction
Arithmetic Instructions
Size*1 B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction) #IMM Performs addition subtraction with carry byte data general registers, immediate data data general register B/W/L Increments decrements general register (Byte operands incremented decremented only) Adds subtracts value from data 32-bit register decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data Performs unsigned multiplication data general registers: either bits bits bits bits bits bits
ADDX SUBX
ADDS SUBS MULXU
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits
DIVXU
Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder
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Instruction DIVXS
Size*1
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder
B/W/L
#IMM Compares data general register with data another general register with immediate data, sets bits according result
B/W/L
Takes two's complement (arithmetic complement) data general register
EXTU
(zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left
EXTS
(sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign
@ERd (<bit @ERd)
Tests memory contents, sets most significant (bit Note: Size refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
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Table
Instruction
Logic Instructions
Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data
B/W/L
#IMM Performs logical operation general register another general register immediate data
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data
B/W/L
Takes one's complement (logical complement) general register contents
Note:
Size refers operand size. Byte Word Longword
Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note:
Shift Instructions
Size* B/W/L Function (shift) Performs arithmetic shift general register contents 1-bit 2-bit shift possible B/W/L (shift) Performs logical shift general register contents 1-bit 2-bit shift possible B/W/L (rotate) Rotates general register contents 1-bit 2-bit rotation possible B/W/L (rotate) Rotates general register contents through carry flag 1-bit 2-bit rotation possible Size refers operand size. Byte Word Longword
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Table
Instruction BSET
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register
BAND
(<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag
BIAND
[~(<bit-No.> <EAd>)] ANDs carry flag with inverse specified general register memory operand stores result carry flag number specified 3-bit immediate data
(<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag
BIOR
[~(<bit-No.> <EAd>)] carry flag with inverse specified general register memory operand stores result carry flag number specified 3-bit immediate data
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Instruction BOXR
Size*
Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag
BIXOR
(<bit-No.> <EAd>)] Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag number specified 3-bit immediate data
(<bit-No.> <EAd>) Transfers specified general register memory operand carry flag
BILD
(<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag number specified 3-bit immediate data
(<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand
BIST
(<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand number specified 3-bit immediate data
Note:
Size refers operand size. Byte
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Table
Instruction
Branch Instructions
Size* Function Branches specified address specified condition true branching conditions listed below Mnemonic (BT) (BF) (BHS) (BLO) Description Always (True) Never (False) HIgh Same Carry Clear (High Same) Carry (LOw) Equal EQual oVerflow Clear oVerflow PLus MInus Greater Equal Less Than Greater Than Less Equal Condition Always Never NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
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Table
Instruction TRAPA SLEEP
System Control Instructions
Size* Function Starts trap-instruction exception handling Returns from exception-handling routine Causes transition power-down state (EAs) CCR, (EAs) Moves contents general register memory immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid
(EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid
ANDC XORC
#IMM CCR, #IMM Logically ANDs contents with immediate data #IMM CCR, #IMM Logically contents with immediate data #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data
Note:
Only increments program counter
Size refers operand size. Byte Word
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Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size* Function then Repeat @ER5+@er6+ R4L-1R4L Until else next; then Repeat @ER5+@er6+ R4-1R4 Until else next; Transfers data block according parameters general registers ER5, size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed
EEPMOV.W
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2.6.4
Basic Instruction Formats
instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Figure 2.12 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, etc. MOV.B@(d:16, Rn), etc.
Figure 2.12 Instruction Formats (Examples) Operation Field Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension Eight, bits specifying immediate data, absolute address, displacement. Condition Field Specifies branching condition instructions.
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2.6.5
Notes Bit-Manipulation Instructions
BSET, BCLR, BNOT, BST, BIST instructions read byte data, carry manipulation, then write back byte data. Caution therefore required when using these instructions register containing write-only bits, port. BCLR instruction used clear internal register flags this case, relevant flag need read beforehand clear that been interrupt handling routine, etc.
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2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2.11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. Bit-manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2.11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/#@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Register Direct-Rn register field instruction code specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32bit registers. Register Indirect-@Ern register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn) 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
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Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word access, longword access. word longword access, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word access, longword access. word longword access, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32 instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table 2.12 indicates accessible absolute address ranges. Table 2.12 Absolute Address Access Ranges
Absolute Address Data address bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) Normal Mode H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
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Immediate-#xx:8, #xx:16, #xx:32 instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8 This mode used instructions. instruction code contains 8bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, section Exception Handling.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode
Advanced Mode
Figure 2.13 Branch Address Specification Memory Indirect Mode
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address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table 2.13 indicates effective addresses calculated each addressing mode. normal mode upper bits effective address ignored order generate 16-bit address.
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Table 2.13 Effective Address Calculation
Addressing Mode Instruction Format Register direct (Rn)
Effective Address Calculation
Effective Address (EA) Operand general register contents
Register indirect (@ERn)
General register contents Don't care
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
General register contents disp Sign extension disp Don't care
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
General register contents Don't care
Register indirect with pre-decrement @-ERn
General register contents Operand Size Byte Word Longword Value Added Don't care
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Addressing Mode Instruction Format Absolute address
@aa:8
Effective Address Calculation
Effective Address (EA)
H'FFFF
Don't care
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate #xx:8/#xx:16/#xx:32
Operand immediate data
Program-counter relative @(d:8, PC)/@(d:16,
contents
disp
Sign extension
disp
Don't care
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Addressing Mode Instruction Format Memory indirect @@aa:8 Normal mode*
Effective Address Calculation
Effective Address (EA)
H'000000
Don't care Memory contents
H'00
Advanced mode
H'000000
Memory contents
Don't care
Note:
available this LSI.
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2.8.1
Processing States
Overview
four main processing states: reset state, exception-handling state, program execution state, power-down state. Figure 2.14 shows diagram processing states. Figure 2.15 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt trap instruction. Processing states Program execution state executes program instructions sequence.
Sleep mode Power-down state operation stopped conserve power.* Standby mode
Note: power-down state also includes medium-speed mode, modue stop mode, sub-active mode,
sub-sleep mode watch mode.
Figure 2.14 Processing States
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Program execution state
ling
stru
Sleep mode
stru
Exception-handling state
External interrupt request
Standby mode
Power-down state High
Reset state
Notes:
From state, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. power-down state also includes watch mode, subactive mode, subsleep mode, etc. details, section Power-Down State.
Figure 2.15 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. interrupts disabled reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, section Watchdog Timer.
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2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority Exception handling performed resets, interrupts, trap instructions. Table 2.14 indicates types exception handling their priority. Trap instruction exception handling always accepted program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table 2.14 Exception Handling Types Priority
Priority High Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed*2
Interrupt
instruction execution exception-handling sequence*1 When TRAPA instruction executed
Trap instruction
Notes: Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted program execution state.
Reset Exception Handling After gone reset state been entered, when goes high again, reset exception handling starts. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Interrupt Exception Handling Trap Instruction Exception Handling When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address. Figure 2.16 shows stack after exception handling ends.
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Normal Mode
Advanced Mode
CCR*1 bits)
bits)
Notes:
Ignored when returning. Normal mode available this LSI.
Figure 2.16 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State
this state executes program instructions sequence.
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2.8.5
Power-Down State
power-down state includes both modes which stops operating modes which does stop. There five modes which stops operating: sleep mode, standby mode, subsleep mode, watch mode. There also three other power-down modes: medium-speed mode, module stop mode, subactive mode. medium-speed mode, operates medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. Subactive mode, subsleep mode, watch mode power-down modes that subclock input. details, section Power-Down State. Sleep Mode transition sleep mode made SLEEP instruction executed while software standby (SSBY) standby control register (SBYCR) LSON lowpower control register (LPWRCR) both cleared sleep mode, operations stop immediately after execution SLEEP instruction. contents registers retained. Standby Mode transition standby mode made SLEEP instruction executed while SSBY SBYCR LSON LPWRCR TMA3 (timer both cleared standby mode, clock halt operations stop. long specified voltage supplied, contents registers on-chip retained.
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2.9.1
Basic Timing
Overview
driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists states. Different methods used access on-chip memory on-chip supporting modules.
2.9.2
On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2.17 shows on-chip memory access cycle.
cycle
Internal address Internal read signal Read access Internal data Internal write signal Write access Internal data
Address
Read data
Write data
Figure 2.17 On-Chip Memory Access Cycle
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2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2.18 shows access timing on-chip supporting modules.
cycle
Internal address Internal read signal Read access Internal data Internal write signal Write access Internal data
Address
Read data
Write data
Figure 2.18 On-Chip Supporting Module Access Cycle
2.10
Usage Note
Only register ER0, ER1, ER4, should used when using instruction. instruction generated Hitachi H8/300 series C/C++ compilers. instruction used user-defined intrinsic function, ensure that only register ER0, ER1, ER4, used.
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Section Operating Modes
3.1.1
Overview
Operating Mode Selection
This operating mode (mode This mode selected depending settings mode (MD0). Table lists operating modes. Table Operating Mode Selection
Operating Mode Advanced Description Single-chip mode
Operating Mode
CPU's architecture allows Gbytes address space, this actually accesses maximum Mbytes. Mode operation starts single-chip mode after reset release. This only used mode This means that mode pins must mode changes inputs mode pins during operation.
3.1.2
Register Configuration
This mode control register (MDCR) that indicates inputs mode (MD0) system control register (SYSCR) that controls operation this LSI. Table summarizes these registers. Table
Name Mode control register System control register Note:
Registers
Abbreviation MDCR SYSCR Initial Value Undetermined H'09 Address* H'FFE9 H'FFE8
Lower bits address.
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3.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS0
Initial value
Note: Determined
MDCR 8-bit read-only register monitors current operating mode this LSI. Reserved. These bits cannot modified always Mode Select (MDS0) This indicates value which reflects input levels mode (MD0) (the current operating mode). MDS0 corresponds pin. read-only cannot written mode (MD0) input levels latched into these bits when MDCR read. 3.2.2 System Control Register (SYSCR)
Initial value INTM1 INTM0 XRST
NMIEG1 NMIEG0
Bits Reserved.
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Bits Interrupt control modes (INTM1, INTM0) These bits selecting interrupt control mode interrupt controller. details interrupt control modes, section 6.4, Interrupt Operation.
INTM1 INTM0 Interrupt Control Mode
Description Interrupt controlled Cannot used this Cannot used this (Initial value)
Interrupt controlled bits
External Reset (XRST) Indicates reset source. When watchdog timer used, reset generated watchdog timer overflow well external reset input. XRST read-only bit. external reset cleared watchdog timer overflow.
XRST Description reset generated watchdog timer overflow reset generated external reset (Initial value)
Bits edge select (NMIG1, Select input edge interrupt.
NIMIEG1 Note: NIMIEG0 Don't care Description interrupt request occurs falling edge input interrupt request occurs rising edge input interrupt request occurs rising falling edge input (Initial value)
Reserved.
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3.3.1
Operating Mode Descriptions
Mode
access Mbyte address space advanced mode.
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Address
H8S/2191 H'000000 Vector area H'0000FF On-chip kbytes) H'007FFF H'013FFF H'017FFF H8S/2192
Absolute address, bits
Memory indirect branch address
H'000000 Vector area
On-chip kbytes)
H'FF8000
H'FFF3B0
Absolute address, bits
H'FFD000 Internal register H'FFD2FF
H'FFD000 Internal register H'FFD2FF
H'FFF3B0
kbytes
H'FFFF00 H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Absolut address, bits
On-chip (3kbytes)
On-chip (3kbytes)
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Figure Address
Rev. 2.0, 11/00, page 1037
H8S/2193 H'000000 Vector area H'000000
H8S/2194
Vector area
On-chip (112 kbytes)
On-chip (128 kbytes)
H'01BFFF H'01FFFF
H'FFD000 Internal register H'FFD2FF
H'FFD000 Internal register H'FFD2FF
H'FFF3B0
H'FFF3B0
On-chip (3kbytes)
On-chip (3kbytes)
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Figure Address
Rev. 2.0, 11/00, page 1037
H8S/2191A H'000000 Vector area H'0000FF On-chip (160 kbytes) H'007FFF H'027FFF H'02FFFF
H8S/2194B
Absolute address, bits
Memory indirect branch address
H'000000 Vector area
On-chip (192 kbytes)
H'FF8000
H'FFE7B0
Absolute address, bits
H'FFD000 Internal register H'FFD2FF
H'FFD000 Internal register H'FFD2FF
H'FFE7B0
kbytes
H'FFFF00 H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Absolute address, bits
On-chip kbytes)
On-chip kbytes)
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Figure Address
Rev. 2.0, 11/00, page 1037
H8S/2194C H'000000 Vector area
On-chip (256 kbytes)
H'03FFFF
H'FFD000 Internal register H'FFD2FF
H'FFE7B0
On-chip kbytes)
H'FFFFAF H'FFFFB0 Internal register H'FFFFFF
Figure Address
Rev. 2.0, 11/00, page 1037
Section Power-Down State
Overview
addition normal program execution state, this power-down state which operation oscillator halted power dissipation reduced. Low-power operation achieved individually controlling CPU, on-chip supporting modules, This operating modes follows: High-speed mode Medium-speed mode Subactive mode Sleep mode Subsleep mode Watch mode Module stop mode Standby mode
these, power-down modes. Certain combinations these modes set. After reset, high-speed mode. Table shows internal chip states each mode, table shows conditions transition various modes. Figure shows mode transition diagram.
Rev. 2.0, 11/00, page 1037
Table
Function System clock Subclock pulse generator operation External interrupts
Internal Chip States Each Mode
HighSpeed MediumSpeed Sleep Module Stop Watch Subactive Halted Subsleep Halted Standby Halted
Functioning Functioning Functioning Functioning Halted
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Retained Functioning Halted Retained Subclock operation Halted Retained Halted Retained
Instructions Functioning Mediumspeed Registers NIMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Halted
Halted
Functioning Halted
On-chip supporting module operation
Timer
Functioning Functioning Functioning Functioning Subclock /halted operation (retained) Functioning Functioning Functioning Functioning Halted /halted (retained) (retained)
Subclock operation Halted (retained)
Subclock operation Halted (retained)
Halted (retained) Halted (retained)
Timer Timer Timer Timer Timer
Functioning Halted /halted (reset) (reset) Functioning Functioning Functioning Functioning Halted (retained) Functioning Functioning Functioning Functioning Subclock operation Functioning Halted /halted (reset) (reset) Functioning Halted /halted (retained) (retained) Functioning Halted /halted (reset) (reset) Functioning Functioning Retained Functioning Halted Functioning Halted /halted (reset) (reset)
Halted (reset) Halted (retained) Subclock operation Halted (reset) Halted (retained)
Halted (reset) Halted (retained) Subclock operation Halted (reset) Halted (retained)
Halted (reset) Halted (retained) Halted Halted (reset) Halted (retained)
Watchdog timer SCI1 SCI2 14-bit 8-bit
Halted (reset)
Halted (reset)
Halted (reset) Halted Halted (reset)
Functioning Retained Halted (reset) Halted (reset)
12-bit Functioning Functioning Halted (reset) Servo
Notes: "Halted (retained)" means that internal register values retained. internal state "operation suspended." "Halted (reset)" means that internal register values internal states initialized. module stop mode, only modules which stop setting been made halted (reset retained). power-down mode, analog section servo circuits turned off, therefore (Servo) current does low. When power-down needed, externally shut down analog system power.
Rev. 2.0, 11/00, page 1037
Reset state Program-halted state Program execution state Program-halted state
Standby mode
SLEEP instruction Interrupt SLEEP instruction Interrupt SLEEP instruction
Active (high-speed) mode
SLEEP instruction
SLEEP instruction Interrupt SLEEP instruction
Sleep (high-speed) mode
Interrupt
SLEEP instruction
Active (medium-speed) mode
SLEEP instruction
SLEEP instruction Interrupt
Sleep (medium-speed) mode
SLEEP Interrupt instruction SLEEP instruction Interrupt
Watch mode
Subactive mode
SLEEP instruction Interrupt
Subsleep mode
Power-down mode
Conditions mode transition
Flag LSON SSBY TMA3 DTON
Conditions mode transition
Interruption factor
NMI, IRQ0 NMI, IRQ0 Timer interruption interruption (excluding servo system) NMI, IRQ0 Timer interruption
SCK1 SCK1 (either
Note: Don't care
Note: When transition made between modes means interrupt, transition cannot made interrupt source generation alone. Ensure that interrupt handling performed after accepting interrupt request
Figure Mode Transitions
Rev. 2.0, 11/00, page 1037
Table
Power-Down Mode Transition Conditions
Control States Time Transition SSBY TMA3 LSON DTON
State before Transition High-speed /mediumspeed
State after Transition SLEEP Instruction Sleep Standby Watch Watch Subactive Subsleep Watch Watch High-speed /medium-speed*2
State after Return Interrupt High-speed /medium-speed*1 High-speed /medium-speed*1 High-speed /medium-speed*1 Subactive Subactive High-speed /medium-speed*2 Subactive
Subactive
Notes: Don't care set. Returns state before transition. Mode varies depending state SCK1 SCK0.
Rev. 2.0, 11/00, page 1037
4.1.1
Register Configuration
power-down state controlled SBYCR, LPWRCR, (Timer MSTPCR registers. Table summarizes these registers. Table
Name Standby control register Low-power control register Module stop control register Timer mode register Note:
Power-Down State Registers
Abbreviation SBYCR LPWRCR MSTPCRH MSTPCRL Lower bits address. Initial Value H'00 H'00 H'FF H'FF H'30 Address* H'FFEA H'FFEB H'FFEC H'FFED H'FFBA
Rev. 2.0, 11/00, page 1037
4.2.1
Register Descriptions
Standby Control Register (SBYCR)
SSBY Initial value STS2 STS1 STS0 SCK1 SCK0
SBYCR 8-bit readable/writable register that performs power-down mode control. SBYCR initialized H'00 reset. Software Standby (SSBY) Determines operating mode, combination with other control bits, when power-down mode transition made executing SLEEP instruction. SSBY setting changed mode transition interrupt, etc.
SSBY Description Transition sleep mode after execution SLEEP instruction high-speed mode medium-speed mode Transition subsleep mode after execution SLEEP instruction subactive mode (Initial value) Transition standby mode, subactive mode, watch mode after execution SLEEP instruction high-speed mode medium-speed mode Transition watch mode high-speed mode after execution SLEEP instruction subactive mode
Bits Standby Timer Select (STS2 STS0) These bits select time waits clock stabilize when standby mode, watch mode, subactive mode cleared transition made high-speed mode mediumspeed mode means specific interrupt instruction. With crystal oscillation, table make selection according operating frequency that standby time least (the oscillation settling time). With external clock, selection made. (With FLASH version, standby time states.)
Rev. 2.0, 11/00, page 1037
STS2
STS1
STS0 Description Standby time 8192 states Standby time 16384 states Standby time 32768 states Standby time 65536 states Standby time 131072 states Standby time 262144 states Standby time states
Notes: Don't care With FLASH version, standby time states. standby time states when transited medium-speed mode (SCK1=1, SCK0=0).
Reserved. These bits cannot modified always read Bits System Clock Select (SCK1, SCK0) These bits select clock master high-speed mode medium-speed mode.
SCK1 SCK0 Description master high-speed mode (Initial value) Medium-speed clock Medium-speed clock Medium-speed clock
Rev. 2.0, 11/00, page 1037
4.2.2
Low-Power Control Register (LPWRCR)
DTON Initial value LSON NESEL
LPWRCR 8-bit readable/writable register that performs power-down mode control. LPWRCR initialized H'00 reset. Direct-Transfer Flag (DTON) Specifies whether direct transition made between high-speed mode, medium-speed mode, subactive mode when making power-down transition executing SLEEP instruction. operating mode which transition made after SLEEP instruction execution determined combination other control bits.
DTON Description When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode, standby mode, watch mode When SLEEP instruction executed subactive mode, transition made subsleep mode watch mode (Initial value) When SLEEP instruction executed high-speed mode medium-speed mode, transition made directly subactive mode, transition made sleep mode standby mode When SLEEP instruction executed subactive mode, transition made directly high-speed mode, transition made subsleep mode
Low-Speed Flag (LSON) Determines operating mode combination with other control bits when making powerdown transition executing SLEEP instruction. Also controls whether transition made high-speed mode subactive mode when watch mode cleared.
Rev. 2.0, 11/00, page 1037
LSON Description When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode, standby mode, watch mode When SLEEP instruction executed subactive mode, transition made watch mode, directly high-speed mode After watch mode cleared, transition made high-speed mode (Initial value) When SLEEP instruction executed high-speed mode transition made watch mode, subactive mode, sleep mode standby mode When SLEEP instruction executed subactive mode, transition made subsleep mode watch mode After watch mode cleared, transition made subactive mode
Noise Elimination Sampling Frequency Select (NESEL) Selects frequency which subclock generated subclock pulse generator sampled with clock generated system clock oscillator. When higher, clear this
NESEL Description Sampling divided Sampling divided
Bits Reserved. These bits cannot modified always read Subactive mode clock select (SA1, SA0) These bits select operating clock subactive mode. These bits cannot modified subactive mode.
Note: Don't care Description Operating clock Operating clock Operating clock (Initial value)
Rev. 2.0, 11/00, page 1037
4.2.3
Timer Register (TMA)
TMAOV TMAIE TMA3 TMA2 TMA1 TMA0
Initial value
R/(W)*
Note: Only written, clear flag.
timer register (TMA) controls timer interrupts selects input clock. Only explained here. details other bits, section 12.2.1, Timer Mode Register readable/writable register which initialized H'30 reset. Clock source, prescaler select (TMA3) Selects Timer clock source between PSW. Also controls transition operation power-down mode. operation mode which transited after SLEEP instruction execution determined combination with other control bits than this bit. details, description Clock Select section 12.2.1, Timer Mode Register
TMA3 Description Timer counts -based prescaler (PSM) divided clock pulses When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode software standby mode (Initial value) Timer counts w-based prescaler (PSM) divided clock pulses When SLEEP instruction executed high-speed mode medium-speed mode, transition made sleep mode, watch mode, subactive mode When SLEEP instruction executed subactive mode, transition made subsleep mode, watch mode, high-speed mode
Rev. 2.0, 11/00, page 1037
4.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH MSTPCRL
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
MSTPCR comprises 8-bit readable/writable registers that perform module stop mode control. MSTPCR initialized H'FFFF reset. MSTRCRH MSTPCRL Bits Module Stop (MSTP MSTP These bits specify module stop mode. table method selecting on-chip supporting modules.
MSTPCRH, MSTPCRL Bits MSTP MSTP Description Module stop mode cleared Module stop mode (Initial value)
Rev. 2.0, 11/00, page 1037
Medium-Speed Mode
When SCK1 SCK0 bits SBYCR high-speed mode, operating mode changes medium-speed mode cycle. medium-speed mode, operates operating clock (16, specified SCK1 SCK0 bits. on-chip supporting modules other than always operate high-speed clock medium-speed mode, access executed specified number states with respect master operating clock. example, selected operating clock, onchip memory accessed states, internal registers states. Medium-speed mode cleared clearing both bits SCK1 SCK0 transition made high-speed mode medium-speed mode cleared current cycle. SLEEP instruction executed when SSBY SBYCR LSON LPWRCR cleared transition made sleep mode. When sleep mode cleared interrupt, medium-speed mode restored. SLEEP instruction executed when SSBY SBYCR LSON LPWRCR TMA3 (Timer both cleared transition made software standby mode. When standby mode cleared external interrupt, medium-speed mode restored. When driven low, transition made reset state, medium-speed mode cleared. same applies case reset caused overflow watchdog timer. Figure shows timing transition clearance medium-speed mode.
Medium-speed mode Internal supporting module clock
clock
Internal address
SBYCR
SBYCR
Internal write signal
Figure Medium-Speed Mode Transition Clearance Timing
Rev. 2.0, 11/00, page 1037
4.4.1
Sleep Mode
Sleep Mode
SLEEP instruction executed when SSBY SBYCR LSON LPWRCR both cleared enters sleep mode. sleep mode, operation stops contents CPU's internal registers retained. Other supporting modules (excluding servo circuit 12-bit PWM) stop. 4.4.2 Clearing Sleep Mode
Sleep mode cleared interrupt, with pin. Clearing with Interrupt When interrupt request signal input, sleep mode cleared interrupt exception handling started. Sleep mode will cleared interrupts disabled, interrupts other than have been masked CPU. Clearing with When driven low, reset state entered. When driven high after prescribed reset input period, begins reset exception handling.
Rev. 2.0, 11/00, page 1037
4.5.1
Module Stop Mode
Module Stop Mode
Module stop mode individual on-chip supporting modules. When corresponding MSTP MSTPCR module operation stops cycle transition made module stop mode. continues operating independently. Table shows MSTP bits on-chip supporting modules. When corresponding MSTP cleared module stop mode cleared module starts operating again cycle. module stop mode, internal states modules other than SCI1, converter, Timer Servo circuit, retained. After reset release, modules module stop mode. When on-chip supporting module module stop mode, read/write access registers disabled. Table
Register MSTPCRH
MSTP Bits Corresponding On-Chip Supporting Modules
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Module Timer Timer Timer Timer Timer Timer Serial communication interface (SCI1) Serial communication interface (SCI2) interface (IIC) 14-bit 8-bit converter Servo circuit, 12-bit
MSTPCRL
MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Rev. 2.0, 11/00, page 1037
4.6.1
Standby Mode
Standby Mode
SLEEP instruction executed when SSBY SBYCR LSON LPWRCR cleared TMA3 (Timer cleared standby mode entered. this mode, CPU, on-chip supporting modules, oscillator (except subclock oscillator) stop. However, contents CPU's internal registers data built-in well functions SCII, timer built-in
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