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H8/3867 Series
H8/3867 H8/3866 H8/3865 H8/3864 H8/3863 H8/3862 HD6473867, HD6433867 HD6433866 HD6433865 HD6433864 HD6433863 HD6433862
H8/3827 Series
H8/3827 H8/3826 H8/3825 H8/3824 H8/3823 H8/3822 HD6473827, HD6433827 HD6433826 HD6433825 HD6433824 HD6433823 HD6433822
Hardware Manual
ADE-602-142B Rev. 3/15/03 Hitachi Ltd.
revision list viewed directly clicking title page. revision list summarizes locations revisions additions. Details should always checked referring relevant text.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
List Items Revised Added This Version
Page Item Table Features Table Features Clock pulse generators Table Features drive power supply Figure Block Diagram Description Change High-speed calculation specification Change specification Addition Modification
Table Functions Power source Modification stabilization capacitance 2.1.1 Features Figure Typical Connection Crystal Oscillator Figure Typical Connection Ceramic Oscillator Figure Typical Connection 32.768kHz/38.4 Crystal Oscillator (Subclock) Change High-speed operation Addition recommended value Addition recommended value Addition description
Figure Connection when Using Modification Subclock Table Operating Modes Modification subsleep mode/watch mode descriptions
Table Internal State Each Operating Modification Note Mode 5.1.1 System Control Registers System control register (SYSCR1) System control register (SYSCR2) Sleep Mode Addition Notes Bits Modification contents Addition description
5.3.3 Oscillator Settling Timer after Stanby Addition description Mode Cleared 5.5.2 Clearing Subsleep Mode Clearing interrupt Addition description
5.7.1 Transition Active (Medium-Speed) Addition description Mode Table 8.10 Port States Table 9.13 Timer Operation Modes 9.7.5 Application Notes Figure 10.1 SCI3 Block Diagram Modification Addition description Notes Addition modification descriptions Modification
Page
Item
Description
10.2.5 Serial Mode Register (SMR) Bits Addition description Notes Table 10.4 Relation between Clock Table 10.5 Maximum Rate Each Frequency (Asynchronous Mode) Table 10.7 Relation between Clock 10.2.9 Clock Stop Register (CKSTPR1) 10.5 Application Notes 14.2 When Using Internal Power Supply Step-Down Circuit 15.2.1 Power Supply Voltage Operating Range Table 15.2 Characteristics Table 15.3 Control Signal Timing Table 15.4 Serial Interface (SCI3-1, SCI3-2) Timing Table 15.5 Converter Characteristics Addition description Notes Modification Notes Addition description Notes Addition description Notes Bits Addition Modification description Modification Addition modification Addition modification Addition Notes Modification
Table 15.7 Characteristics External Addition Segment Expansion Figure 15.6 SCI-3 Synchronous Mode Input/Output Timing Figure 15.7 Segment Expansion Signal Timing Modification Notes Addition
Preface
H8/300L Series single-chip microcomputers high-speed H8/300L core, with many necessary peripheral functions on-chip. H8/300L instruction compatible with H8/300 CPU. H8/3867 Series H8/3827 Series have system-on-a-chip architecture that includes such peripheral functions controller/driver, timers, 14-bit PWM, two-channel serial communication interface, converter. This allows H8/3867 Series devices used embedded microcomputers systems requiring display. H8/3867 Series incorporates drive power supply step-up constant power supply enabling fixed voltage obtained independently This manual describes hardware H8/3867 Series H8/3827 Series. details H8/3864 Series instruction set, refer H8/300L Series Programming Manual.
Contents
Section
Overview.
Overview. Internal Block Diagram Arrangement Functions 1.3.1 Arrangement 1.3.2 Functions.
Section
CPU.
Overview. 2.1.1 Features 2.1.2 Address Space 2.1.3 Register Configuration Register Descriptions. 2.2.1 General Registers. 2.2.2 Control Registers. 2.2.3 Initial Register Values Data Formats. 2.3.1 Data Formats General Registers. 2.3.2 Memory Data Formats. Addressing Modes 2.4.1 Addressing Modes. 2.4.2 Effective Address Calculation. Instruction Set. 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations. 2.5.5 Manipulations 2.5.6 Branching Instructions. 2.5.7 System Control Instructions 2.5.8 Block Data Transfer Instruction Basic Operational Timing. 2.6.1 Access On-Chip Memory (RAM, ROM) 2.6.2 Access On-Chip Peripheral Modules States 2.7.1 Overview 2.7.2 Program Execution State 2.7.3 Program Halt State. 2.7.4 Exception-Handling State
Memory 2.8.1 Memory Map. Application Notes. 2.9.1 Notes Data Access. 2.9.2 Notes Manipulation 2.9.3 Notes EEPMOV Instruction
Section
Exception Handling.
Overview. Reset 3.2.1 Overview 3.2.2 Reset Sequence. 3.2.3 Interrupt Immediately after Reset Interrupts. 3.3.1 Overview 3.3.2 Interrupt Control Registers 3.3.3 External Interrupts. 3.3.4 Internal Interrupts 3.3.5 Interrupt Operations. 3.3.6 Interrupt Response Time Application Notes. 3.4.1 Notes Stack Area Use. 3.4.2 Notes Rewriting Port Mode Registers.
Section
Clock Pulse Generators.
Overview. 4.1.1 Block Diagram. 4.1.2 System Clock Subclock System Clock Generator. Subclock Generator Prescalers Note Oscillators
Section
Power-Down Modes
Overview. 5.1.1 System Control Registers Sleep Mode. 5.2.1 Transition Sleep Mode 5.2.2 Clearing Sleep Mode 5.2.3 Clock Frequency Sleep (Medium-Speed) Mode. Standby Mode. 5.3.1 Transition Standby Mode 5.3.2 Clearing Standby Mode.
5.3.3 Oscillator Settling Time after Standby Mode Cleared. 5.3.4 Standby Mode Transition States. Watch Mode 5.4.1 Transition Watch Mode. 5.4.2 Clearing Watch Mode 5.4.3 Oscillator Settling Time after Watch Mode Cleared Subsleep Mode 5.5.1 Transition Subsleep Mode. 5.5.2 Clearing Subsleep Mode Subactive Mode 5.6.1 Transition Subactive Mode 5.6.2 Clearing Subactive Mode 5.6.3 Operating Frequency Subactive Mode Active (Medium-Speed) Mode. 5.7.1 Transition Active (Medium-Speed) Mode 5.7.2 Clearing Active (Medium-Speed) Mode. 5.7.3 Operating Frequency Active (Medium-Speed) Mode. Direct Transfer. 5.8.1 Overview Direct Transfer 5.8.2 Direct Transition Times. Module Standby Mode 5.9.1 Setting Module Standby Mode. 5.9.2 Clearing Module Standby Mode
Section
.117
Overview. 6.1.1 Block Diagram. H8/3867 H8/3827 PROM Mode. 6.2.1 Setting PROM Mode. 6.2.2 Socket Adapter Arrangement Memory H8/3867 H8/3827 Programming 6.3.1 Writing Verifying 6.3.2 Programming Precautions Reliability Programmed Data.
Section
.129
Overview. 7.1.1 Block Diagram.
Section
Ports.131
Overview. Port 8.2.1 Overview
8.2.2 Register Configuration Description. 8.2.3 Functions. 8.2.4 States 8.2.5 Input Pull-Up Port 8.3.1 Overview 8.3.2 Register Configuration Description. 8.3.3 Functions. 8.3.4 States 8.3.5 Input Pull-Up Port 8.4.1 Overview 8.4.2 Register Configuration Description. 8.4.3 Functions. 8.4.4 States Port 8.5.1 Overview 8.5.2 Register Configuration Description. 8.5.3 Functions. 8.5.4 States 8.5.5 Input Pull-Up Port 8.6.1 Overview 8.6.2 Register Configuration Description. 8.6.3 Functions. 8.6.4 States 8.6.5 Input Pull-Up Port 8.7.1 Overview 8.7.2 Register Configuration Description. 8.7.3 Functions. 8.7.4 States Port 8.8.1 Overview 8.8.2 Register Configuration Description. 8.8.3 Functions. 8.8.4 States Port 8.9.1 Overview 8.9.2 Register Configuration Description. 8.9.3 Functions. 8.9.4 States 8.10 Port
8.10.1 Overview 8.10.2 Register Configuration Description. 8.11 Input/Output Data Inversion Function. 8.11.1 Overview 8.11.2 Register Configuration Descriptions 8.11.3 Note Modification Serial Port Control Register.
Section
Timers.175
Overview. Timer 9.2.1 Overview 9.2.2 Register Descriptions. 9.2.3 Timer Operation 9.2.4 Timer Operation States. Timer 9.3.1 Overview 9.3.2 Register Descriptions. 9.3.3 Timer Operation 9.3.4 Timer Operation States Timer 9.4.1 Overview 9.4.2 Register Descriptions. 9.4.3 Interface 9.4.4 Operation 9.4.5 Application Notes. Timer 9.5.1 Overview 9.5.2 Register Descriptions. 9.5.3 Noise Canceler. 9.5.4 Operation 9.5.5 Application Notes. 9.5.6 Timer Application Example Watchdog Timer. 9.6.1 Overview 9.6.2 Register Descriptions. 9.6.3 Timer Operation 9.6.4 Watchdog Timer Operation States Asynchronous Event Counter (AEC) 9.7.1 Overview 9.7.2 Register Descriptions. 9.7.3 Operation 9.7.4 Asynchronous Event Counter Operation Modes. 9.7.5 Application Notes.
Section Serial Communication Interface .251
10.1 Overview. 10.1.1 Features 10.1.2 Block diagram 10.1.3 configuration 10.1.4 Register configuration 10.2 Register Descriptions. 10.2.1 Receive shift register (RSR). 10.2.2 Receive data register (RDR) 10.2.3 Transmit shift register (TSR). 10.2.4 Transmit data register (TDR) 10.2.5 Serial mode register (SMR). 10.2.6 Serial control register (SCR3) 10.2.7 Serial status register (SSR). 10.2.8 rate register (BRR). 10.2.9 Clock stop register (CKSTPR1). 10.2.10 Serial Port Control Register (SPCR). 10.3 Operation 10.3.1 Overview 10.3.2 Operation Asynchronous Mode. 10.3.3 Operation Synchronous Mode. 10.3.4 Multiprocessor Communication Function. 10.4 Interrupts. 10.5 Application Notes.
Section 14-Bit PWM.309
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Control Register (PWCR). 11.2.2 Data Registers (PWDRU, PWDRL). 11.2.3 Clock Stop Register (CKSTPR2). 11.3 Operation 11.3.1 Operation 11.3.2 Operation Modes.
Section Converter.317
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram.
12.2
12.3
12.4 12.5 12.6
12.1.3 Configuration 12.1.4 Register Configuration Register Descriptions. 12.2.1 Result Registers (ADRRH, ADRRL). 12.2.2 Mode Register (AMR). 12.2.3 Start Register (ADSR). 12.2.4 Clock Stop Register (CKSTPR1). Operation 12.3.1 Conversion Operation. 12.3.2 Start Conversion External Trigger Input. 12.3.3 Converter Operation Modes Interrupts. Typical Use. Application Notes.
Section Controller/Driver .329
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Port Control Register (LPCR) 13.2.2 Control Register (LCR) 13.2.3 Control Register (LCR2). 13.2.4 Clock Stop Register (CKSTPR2). 13.3 Operation 13.3.1 Settings Display. 13.3.2 Relationship between Display 13.3.3 Luminance Adjustment Function Pin) 13.3.4 Step-Up Constant-Voltage Power Supply 13.3.5 Low-Power-Consumption Drive System 13.3.6 Operation Power-Down Modes. 13.3.7 Boosting Drive Power Supply 13.3.8 Connection HD66100.
Section Power Supply Circuit.359
14.1 Overview. 14.2 When Using Internal Power Supply Step-Down Circuit 14.3 When Using Internal Power Supply Step-Down Circuit.
Section Electrical Characteristics .361
15.1 H8/3867 Series H8/3827 Series Absolute Maximum Ratings.
viii
15.2 H8/3867 Series H8/3827 Series Electrical Characteristics. 15.2.1 Power Supply Voltage Operating Range. 15.2.2 Characteristics. 15.2.3 Characteristics. 15.2.4 Converter Characteristics 15.2.5 Characteristics 15.3 Operation Timing 15.4 Output Load Circuit. 15.5 Resonator Equivalent Circuit
Appendix Instruction Set.383
Instructions Operation Code Map. Number Execution States.
Appendix Internal Registers.399
Addresses. Functions.
Appendix Port Block Diagrams .454
Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagrams Port Block Diagram Port Block Diagram Port
Appendix Port States Different Processing States .474 Appendix List Product Codes .475 Appendix Package Dimensions .477
Section Overview
Overview
H8/300L Series series single-chip microcomputers (MCU: microcomputer unit), built around high-speed H8/300L equipped with peripheral system functions on-chip. Within H8/300L Series, H8/3867 Series H8/3827 Series comprise single-chip microcomputers equipped with controller/driver. Other on-chip peripheral functions include timers, 14-bit pulse width modulator (PWM), serial communication interface channels, converter. Together, these functions make H8/3864 Series ideally suited embedded applications systems requiring power consumption display. Models H8/3867 H8/3827 Series H8/3862 H8/3822, with on-chip 16-kbyte 1kbyte RAM, H8/3863 H8/3823, with 24-kbyte 1-kbyte RAM, H8/3864 H8/3824, with 32-kbyte 2-kbyte RAM, H8/3865 H8/3825, with 40-kbyte 2-kbyte RAM, H8/3866 H8/3826, with 48-kbyte 2-kbyte RAM, H8/3867 H8/3827, with 60-kbyte 2-kbyte RAM. H8/3867 H8/3827 also available ZTATTM* version with on-chip PROM which programmed required user. Table summarizes features H8/3867 Series H8/3827 Series. Note: ZTAT (Zero Turn Around Time) trademark Hitachi, Ltd.
Table
Item
Features
Description High-speed H8/300L General-register architecture General registers: Sixteen 8-bit registers (can used eight 16-bit registers) Operating speed Max. operating speed: Add/subtract: 0.67 (operating MHz) Multiply/divide: 4.67 (operating MHz) 32.768 38.4 subclock Instruction compatible with H8/300 Instruction length bytes bytes Basic arithmetic operations between registers instruction data transfer between memory registers Typical instructions Multiply bits bits) Divide bits bits) accumulator Register-indirect designation position
Interrupts
interrupt sources external interrupt sources (IRQ WKP0) internal interrupt sources
Clock pulse generators on-chip clock pulse generators Power-down modes System clock pulse generator: Subclock pulse generator: 32.768 kHz, 38.4
Seven power-down modes Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode
Table
Item Memory
Features (cont)
Description Large on-chip memory H8/3862, H8/3822: 16-kbyte ROM, 1-kbyte H8/3863, H8/3823: 24-kbyte ROM, 1-kbyte H8/3864, H8/3824: 32-kbyte ROM, 2-kbyte H8/3865, H8/3825: 40-kbyte ROM, 2-kbyte H8/3866, H8/3826: 48-kbyte ROM, 2-kbyte H8/3867, H8/3827: 60-kbyte ROM, 2-kbyte
ports
pins pins input pins
Timers
on-chip timers Timer 8-bit timer Count-up timer with selection eight internal clock signals divided from system clock four clock signals divided from watch clock Asynchronous event counter: 16-bit timer Count-up timer able count asynchronous external events independently MCU's internal clocks Timer 8-bit timer Count-up/down timer with selection seven internal clock signals event input from external Auto-reloading Timer 16-bit timer used independent 8-bit timers Count-up timer with selection four internal clock signals event input from external Provision toggle output means compare-match function Timer 8-bit timer Count-up timer with selection four internal clock signals Incorporates input capture function (built-in noise canceler) Watchdog timer Reset signal generated overflow 8-bit counter
Note: section Clock Pulse Generator, definition
Table
Item
Features (cont)
Description serial communication interface channels chip SCI3-1: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function SCI3-2: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function
Serial communication interface
14-bit
Pulse-division output reduced ripple used 14-bit converter connecting external low-pass filter.
converter
Successive approximations using resistance ladder 8-channel analog input pins Conversion time: channel
controller/driver
controller/driver equipped with maximum segment pins four common pins Choice four duty cycles (static, 1/2, 1/3, 1/4) Segment pins switched general-purpose port function 8bit units
drive power supply Step-up constant-voltage power supply allows display (H8/3867 Series only)
Table
Item
Features (cont)
Specification Product Code Mask Version HD6433862H, HD6433822H HD6433862F, HD6433822F HD6433862W, HD6433822W HD6433863H, HD6433823H HD6433863F, HD6433823F HD6433863W, HD6433823W HD6433864H, HD6433824H HD6433864F, HD6433824F HD6433864W, HD6433824W HD6433865H, HD6433825H HD6433865F, HD6433825F HD6433865W, HD6433825W HD6433866H, HD6433826H HD6433866F, HD6433826F HD6433866W, HD6433826W HD6433867H, HD6433827H HD6433867F, HD6433827F HD6433867W, HD6433827W ZTAT Version HD6473867H, HD6473827H HD6473867F, HD6473827F HD6473867W, HD6473827W Package 80-pin (FP-80A) 80-pin (FP-80B) 80-pin TQFP (TFP-80C) 80-pin (FP-80A) 80-pin (FP-80B) 80-pin TQFP (TFP-80C) 80-pin (FP-80A) 80-pin (FP-80B) 80-pin TQFP (TFP-80C) 80-pin (FP-80A) 80-pin (FP-80B) 80-pin TQFP (TFP-80C) 80-pin (FP-80A) 80-pin (FP-80B) 80-pin TQFP (TFP-80C) 80-pin (FP-80A) 80-pin (FP-80B) 80-pin TQFP (TFP-80C) kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbyte ROM/RAM Size kbytes kbyte
Product lineup
Internal Block Diagram
Figure shows block diagram H8/3867 Series H8/3827 Series.
TEST OSC1 OSC2 CVCC
P30/PWM P31/UD P32/RESO P33/SCK31 P34/RXD31 P35/TXD31 P36/AEVH P37/AEVL P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8
(60k/48k/40k/32k 24k/16k)
Port
(2k/1k) Serial communication interface Serial communication interface 14-bit
Port
P10/TMOW P11/TMOFL P12/TMOFH P13/TMIG P14/IRQ4/ADTRG P15/IRQ1/TMIC P16/IRQ2 P17/IRQ3/TMIF
System Clock
Power Supply
Clock
Port
H8/300L
PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P87/SEG32/CL1 P86/SEG31/CL2 P85/SEG30/DO P84/SEG29/M P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9
Timer
Timer
Port
Timer
Port Port
Timer
Port
Asynchronous counter (10bit)
Controller Port
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
AVCC
Figure Block Diagram
AVSS
Port
1.3.1
Arrangement Functions
Arrangement
H8/3867 Series H8/3827 Series arrangement shown figures 1.3.
P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 P54/WKP4/SEG5
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P80/SEG25 P81/SEG26 P82/SEG27 P83/SEG28 P84/SEG29/M P85/SEG30/DO P86/SEG31CL2 P87/SEG32CL1 P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVCC PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 CVCC P37/AEVL P36/AEVH P35/TXD31 P34/RXD31 P33/SCK31
P14/IRQ4/ADTRG
P60/SEG9
P15/IRQ1/TMIC
P17/IRQ3/TMIF
P10/TMOW
P11/TMOFL
P12/TMOFH
Figure Arrangement (FP-80A, TFP-80C: View)
P32/RESO
P16/IRQ2
P30/PWM
PB7/AN7
P13/TMIG
P31/UD
AVSS
OSC2
OSC1
TEST
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
P54/WKP4/SEG5
P53/WKP3/SEG4
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P82/SEG27 P83/SEG28 P84/SEG29/M P85/SEG30/DO P86/SEG31/CL2 P87/SEG32/CL1 P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 AVCC PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 P51/WKP1/SEG2 P50/WKP0/SEG1 PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 CVCC P37/AEVL P36/AEVH P35/TXD31
P14/IRQ4/ADTRG
P60/SEG9
P15/IRQ1/TMIC
P17/IRQ3/TMIF
P32/RESO
P16/IRQ2
P12/TMOFH
P10/TMOW
P11/TMOFL
Figure Arrangement (FP-80B: View)
P34/RXD31
P33/SCK31
P30/PWM
PB5/AN5
PB6/AN6
PB7/AN7
P13/TMIG
P31/UD
OSC2
OSC1
TEST
AVSS
P52/WKP2/SEG3
1.3.2
Functions
Table outlines functions H8/3864 Series. Table Functions
Type Symbol FP-80A TFP-80C FP-80B Input Name Functions Power supply: pins should connected system power supply. section Power Supply Circuit. Ground: pins should connected system power supply Analog power supply: This power supply converter. When converter used, connect this system power supply. Analog ground: This converter ground pin. should connected system power supply (0V).
Power source pins
Input
AVCC
Input
AVSS
Input
Clock pins
Output power supply: These Input power supply pins controller/driver. They incorporate power supply split-resistance, normally used with shorted. These pins connect crystal
Input
Output ceramic oscillator, used input external clock. section Clock Pulse Generators, typical connection diagram. Input These pins connect 32.768-kHz
Output 38.4-kHz crystal oscillator. section Clock Pulse Generators, typical connection diagram. Input Reset: When this driven low, chip reset
System control
RESO
Output Reset output: Outputs internal reset signal.
Table
Functions (cont)
Type System control Interrupt pins
Symbol TEST
FP-80A TFP-80C
FP-80B
Name Functions
Output Test pin: This reserved cannot used. should connected VSS. Input interrupt request These input pins edge-sensitive external interrupts, with selection rising falling edge Wakeup interrupt request These input pins rising fallingedge-sensitive external interrupts.
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
Input
Timer pins
TMOW
Output Clock output: This output waveforms generated timer output circuit. Input Asynchronous event counter event input: This event input input asynchronous event counter. Timer event input: This event input input timer counter. Timer up/down select: This selects down-counting timer counter. counter operates up-counter when this high, down-counter when low. Timer event input: This event input input timer counter.
AEVL AEVH
TMIC
Input Input
TMIF TMOFL
Input
Output Timer output: This output waveforms generated timer output compare function. Output Timer output: This output waveforms generated timer output compare function. Input Timer capture input: This input timer input capture.
TMOFH
TMIG
Table
Functions (cont)
Type 14-bit ports
Symbol
FP-80A TFP-80C
FP-80B
Name Functions
Output 14-bit output: This output waveforms generated 14bit Input Input Port This 8-bit input port. Port (bit This 1-bit input port. Port (bits This 3-bit port. Input output designated each means port control register (PCR4). Port This 4-bit port. Input output designated each means port control register (PCRA). Port This 8-bit port. Input output designated each means port control register (PCR1). Port This 8-bit port. Input output designated each means port control register (PCR3). Port This 8-bit port. Input output designated each means port control register (PCR5). Port This 8-bit port. Input output designated each means port control register (PCR6). Port This 8-bit port. Input output designated each means port control register (PCR7). Port This 8-bit port. Input output designated each means port control register (PCR8).
Table
Functions (cont)
Type Serial communication interface (SCI)
Symbol RXD31 TXD31 RXD32 TXD32
FP-80A TFP-80C
FP-80B
Input
Name Functions SCI3-1 receive data input: This SCI31 data input pin.
Output SCI3-1 transmit data output: This SCI31 data output pin. Input SCI3-1 clock I/O: This SCI31 clock pin. SCI3-2 receive data input: This SCI32 data input pin.
Output SCI3-2 transmit data output: This SCI32 data output pin. Input SCI3-2 clock I/O: This SCI32 clock pin. Analog input channels These analog data input channels converter converter trigger input: This external trigger input converter
converter
ADTRG
Input
controller/ driver
COM4 COM1 SEG32 SEG1
Output common output: These common output pins. Output segment output: These segment output pins. Output latch clock: This output segment external expansion display data latch clock. Output shift clock: This output segment external expansion display data shift clock. Output serial data output: This output segment external expansion serial display data. Output alternation signal: This output segment external expansion alternation signal.
Section
Overview
H8/300L sixteen 8-bit general registers, which also paired eight 16-bit registers. concise instruction designed high-speed operation. 2.1.1 Features
Features H8/300L listed below. General-register architecture Sixteen 8-bit general registers, also usable eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment pre-decrement Absolute address Immediate Program-counter relative Memory indirect 64-kbyte address space High-speed operation frequently used instructions executed four states High-speed arithmetic logic operations 16-bit register-register subtract: 0.67 8-bit multiply: 4.67 8-bit divide: 4.67 Note: These values MHz. Low-power operation modes SLEEP instruction transfer low-power operation
2.1.2
Address Space
H8/300L supports address space kbytes storing program code data. 2.8, Memory Map, details memory map. 2.1.3 Register Configuration
Figure shows register structure H8/300L CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack pointer
Control registers (CR) Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used data registers, they accessed 16-bit registers R7), high bytes (R0H R7H) bytes (R0L R7L) accessed separately 8-bit registers. When used address registers, general registers accessed 16-bit registers R7). also functions stack pointer (SP), used implicitly hardware exception processing subroutine calls. When functions stack pointer, indicated figure 2.2, (R7) points stack.
Lower address side [H'0000] Unused area (R7) Stack area
Upper address side [H'FFFF]
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. instructions fetched bits word) time, least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. These bits read written software (using LDC, STC, ANDC, ORC, XORC instructions). flags used branching conditions conditional branching (Bcc) instructions.
7-Interrupt Mask (I): When this interrupts masked. This automatically start exception handling. interrupt mask read written software. further details, section 3.3, Interrupts. 6-User (U): used freely user. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. flag used implicitly instructions. When ADD.W, SUB.W, CMP.W instruction executed, flag there carry borrow cleared otherwise. 4-User (U): used freely user. 3-Negative Flag (N): Indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): indicate zero result, cleared indicate non-zero result. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. Refer H8/300L Series Programming Manual action each instruction flag bits. 2.2.3 Initial Register Values
When reset, program counter (PC) initialized value stored address H'0000 vector table, other bits general registers initialized. particular, stack pointer (R7) initialized. stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300L process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand arithmetic logic instructions except ADDS SUBS operate byte data. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data. instructions perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit.
2.3.1
Data Formats General Registers
Data sizes above stored general registers shown figure 2.3.
Data Type Register
Data Format
1-bit data
don't care
1-bit data
don't care
Byte data
don't care
Byte data
don't care
Word data
Upper digit
Lower digit
4-bit data
don't care
Upper digit
Lower digit
4-bit data
don't care
Notation: RnH: Upper byte general register RnL: Lower byte general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. H8/300L access word data stored memory (MOV.W instruction), word data must always begin even address. word data starting address accessed, least significant address regarded word data starting preceding address accessed. same applies instruction codes.
Data Type Address Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
CCR: Condition code register Note: Ignored return
Figure Memory Data Formats When stack accessed using address register, word access should always performed. When pushed stack, identical copies pushed make complete word. When they restored, lower byte ignored.
2.4.1
Addressing Modes
Addressing Modes
H8/300L supports eight addressing modes listed table 2.1. Each instruction uses subset these addressing modes. Table
Addressing Modes
Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register Indirect-@Rn: register field instruction specifies 16-bit general register containing address operand memory. Register Indirect with Displacement-@(d:16, Rn): instruction second word (bytes containing displacement which added contents specified general register obtain operand address memory. This mode used only instructions. MOV.W instruction, resulting address must even.
Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with post-increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. register field instruction specifies 16-bit general register containing address operand. After operand accessed, register incremented MOV.B MOV.W. MOV.W, original contents 16-bit general register must even. Register indirect with pre-decrement-@-Rn @-Rn mode used with instructions that store register contents memory. register field instruction specifies 16-bit general register which decremented obtain address operand memory. register retains decremented value. size decrement MOV.B MOV.W. MOV.W, original contents register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. absolute address bits long (@aa:8) bits long (@aa:16). MOV.B manipulation instructions 8-bit absolute addresses. MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. 8-bit absolute address, upper bits assumed (H'FF). address range H'FF00 H'FFFF (65280 65535). Immediate-#xx:8 #xx:16: instruction contains 8-bit operand (#xx:8) second byte, 16-bit operand (#xx:16) third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data second fourth byte instruction, specifying number. Program-Counter Relative-@(d:8, PC): This mode used instructions. 8-bit displacement byte instruction code sign-extended bits added program counter contents generate branch destination address. possible branching range -126 +128 bytes (-63 words) from current address. displacement should even number. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address. word located this address contains branch destination address. upper bits absolute address assumed (H'00), address range from H'0000 H'00FF 255). Note that with H8/300L Series, lower address area also used vector area. 3.3, Interrupts, details vector area. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. 2.3.2, Memory Data Formats, further information.
2.4.2
Effective Address Calculation
Table shows effective addresses calculated each addressing modes. Arithmetic logic instructions register direct addressing (1). ADD.B, ADDX, SUBX, CMP.B, AND, instructions also immediate addressing (6). Data transfer instructions addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), 8-bit absolute addressing specify operand. Register indirect (BSET, BCLR, BNOT, BTST instructions) 3-bit immediate addressing used independently specify position operand.
Table Effective Address Calculation
Effective Address Calculation Method
Addressing Mode Instruction Format Effective Address (EA)
Register direct,
Contents bits) register indicated
Operand contents registers indicated rm/rn
Register indirect,
Contents bits) register indicated
Register indirect with displacement, @(d:16, disp
disp
Register indirect with post-increment, @Rn+
Contents bits) register indicated
Register indirect with pre-decrement, @-Rn
Contents bits) register indicated
Incremented decremented operand byte size, word size
Effective Address Calculation Method
Table Effective Address Calculation (cont)
Effective Address (EA)
H'FF
Addressing Mode Instruction Format
Absolute address @aa:8
@aa:16
Immediate #xx:8 Operand 2-byte immediate data
#xx:16
Program-counter relative @(d:8,
contents
Sign extension
disp
disp
Table Effective Address Calculation (cont)
Effective Address Calculation Method Effective Address (EA)
Addressing Mode Instruction Format
Memory indirect, @@aa:8
H'00
Memory contents bits)
Notation: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300L Series total instructions, which grouped function table 2.3. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer
Instruction
Instructions MOV, PUSH
Number Total:
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, same applies machine language. conditional branch instruction which represents condition code.
following sections give concise summary instructions each category, indicate patterns their object code. notation used defined next.
Notation (EAd), <EAd> (EAs), <EAs> #IMM disp General register (destination) General register (source) General register Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move Logical negation (logical complement) 3-bit length 8-bit length 16-bit length Contents operand indicated effective address
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, @Rn+ addressing modes available word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes.
@SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
PUSH
@-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP.
Notes:
Size: Operand size Byte Word
Certain precautions required data access. 2.9.1, Notes Data Access, details.
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, @-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
Notation: Operation field Register field disp: Displacement abs: Absolute address IMM: Immediate data
PUSH, @SP+ @-SP
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. Table
Instruction
Arithmetic Instructions
Size* Function #IMM Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers.
ADDX SUBX
#IMM Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register.
Increments decrements general register Adds subtracts from general register decimal adjust Decimal-adjusts (adjusts 4-bit BCD) addition subtraction result general register referring
ADDS SUBS
MULXU
Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result
DIVXU
Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder
#IMM Compares data general register with data another general register with immediate data, indicates result CCR. Word data compared only between general registers.
Obtains two's complement (arithmetic complement) data general register
Notes:
Size: Operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. Table
Instruction
Logic Operation Instructions
Size* Function #IMM Performs logical operation general register another general register immediate data
#IMM Performs logical operation general register another general register immediate data
#IMM Performs logical exclusive operation general register another general register immediate data
Obtains one's complement (logical complement) general register contents
Notes:
Size: Operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Notes:
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents shift Performs logical shift operation general register contents rotate Rotates general register contents Size: Operand size Byte rotate through carry Rotates general register contents through (carry)
Figure shows instruction code format arithmetic, logic, shift instructions.
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#XX:8)
AND, (Rm)
AND, (#xx:8)
Notation: Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory number specified 3-bit immediate data lower three bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory number specified 3-bit immediate data lower three bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory. number specified 3-bit immediate data lower three bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
BAND
(<bit-No.> <EAd>) ANDs flag with specified general register memory, stores result flag.
BIAND
(<bit-No.> <EAd>)] ANDs flag with inverse specified general register memory, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) flag with specified general register memory, stores result flag.
BIOR
(<bit-No.> <EAd>)] flag with inverse specified general register memory, stores result flag. number specified 3-bit immediate data.
Notes:
Size: Operand size Byte
Table
Instruction BXOR
Bit-Manipulation Instructions (cont)
Size* Function (<bit-No.> <EAd>) XORs flag with specified general register memory, stores result flag.
BIXOR
[~(<bit-No.> <EAd>)] XORs flag with inverse specified general register memory, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies specified general register memory flag. (<bit-No.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies flag specified general register memory. (<bit-No.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BILD
BIST
Notes:
Size: Operand size Byte
Certain precautions required manipulation. 2.9.2, Notes Manipulation, details.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: register indirect (@Rn) No.:
register direct (Rm)
Operand: absolute (@aa:8) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Notation: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Notation: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches designated address condition true. branching conditions given below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Notation: Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table 2.10 describes system control instructions. Figure shows their object code formats. Table 2.10 System Control Instructions
Instruction SLEEP Size* Function Returns from exception-handling routine Causes transition from active mode power-down mode. section Power-Down Modes, details. CCR, #IMM Moves immediate data general register contents condition code register Copies condition code register specified general register ANDC #IMM Logically ANDs condition code register with immediate data #IMM Logically condition code register with immediate data XORC #IMM Logically exclusive-ORs condition code register with immediate data Notes: Size: Operand size Byte Only increments program counter
RTE, SLEEP,
LDC, (Rn)
ANDC, ORC, XORC, (#xx:8)
Notation: Operation field Register field IMM: Immediate data
Figure System Control Instruction Codes 2.5.8 Block Data Transfer Instruction
Table 2.11 describes block data transfer instruction. Figure 2.10 shows object code format. Table 2.11 Block Data Transfer Instruction
Instruction EEPMOV Size Function then repeat until else next; Block transfer instruction. Transfers number data bytes specified from locations starting address indicated locations starting address indicated After transfer, next instruction executed. @R5+ @R6+
Certain precautions required using EEPMOV instruction. 2.9.3, Notes EEPMOV Instruction, details.
Notation: Operation field
Figure 2.10 Block Data Transfer Instruction Code
Basic Operational Timing
operation synchronized system clock subclock details these clock signals section Clock Pulse Generators. period from rising edge next rising edge called state. cycle consists states three states. cycle differs depending whether access on-chip memory on-chip peripheral modules. 2.6.1 Access On-Chip Memory (RAM, ROM)
Access on-chip memory takes place states. data width bits, allowing access byte word size. Figure 2.11 shows on-chip memory access cycle.
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
2.6.2
Access On-Chip Peripheral Modules
On-chip peripheral modules accessed states three states. data width bits, access byte size only. This means that accessing word data, instructions must used. Figures 2.12 2.13 show on-chip peripheral module access cycle. Two-state access on-chip peripheral modules
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
Three-state access on-chip peripheral modules
cycle state state state
Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access)
Address
Read data
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7.1
States
Overview
There four states: reset state, program execution state, program halt state, exception-handling state. program execution state includes active (high-speed mediumspeed) mode subactive mode. program halt state there sleep (high-speed medium-speed) mode, standby mode, watch mode, sub-sleep mode. These states shown figure 2.14. Figure 2.15 shows state transitions.
state
Reset state initialized Program execution state
Active (high speed) mode executes successive program instructions high speed, synchronized system clock Active (medium speed) mode executes successive program instructions reduced speed, synchronized system clock Subactive mode executes successive program instructions reduced speed, synchronized subclock
Low-power modes
Program halt state state which some chip functions stopped conserve power
Sleep (high-speed) mode Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state transient state which changes processing flow reset interrupt Note: section Power-Down Modes, details modes their transitions.
Figure 2.14 Operation States
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source occurs
Interrupt source occurs
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.15 State Transitions 2.7.2 Program Execution State
program execution state executes program instructions sequence. There three modes this state, active modes (high speed medium speed) subactive mode. Operation synchronized with system clock active mode (high speed medium speed), with subclock subactive mode. section Power-Down Modes details these modes. 2.7.3 Program Halt State
program halt state there five modes: sleep modes (high speed medium speed), standby mode, watch mode, subsleep mode. section Power-Down Modes details these modes. 2.7.4 Exception-Handling State
exception-handling state transient state occurring when exception handling started reset interrupt changes normal processing flow. exception handling caused interrupt, (R7) referenced values saved stack. details interrupt handling, section 3.3, Interrupts.
2.8.1
Memory
Memory
memory H8/3862 H8/3822 shown figure 2.16 (1), that H8/3863 H8/3823 figure 2.16 (2), that H8/3864 H8/3824 figure 2.16 (3), that H8/3865 H8/3825 figure 2.16 (4), that H8/3866 H8/3826 figure 2.16 (5), that H8/3867 H8/3827 figure 2.16 (6).
H'0000 Interrupt vector area H'0029 H'002A
kbytes On-chip (16384 bytes)
H'3FFF
used
H'F740 bytes) H'F75F used H'F780 On-chip H'FB7F used H'FF90 Internal registers (112 bytes) H'FFFF 1024 bytes
Figure 2.16 H8/3862 H8/3822 Memory
H'0000 Interrupt vector area H'0029 H'002A
kbytes On-chip (24576 bytes)
H'5FFF
used
H'F740 bytes) H'F75F used H'F780 On-chip H'FB7F used H'FF90 Internal registers (112 bytes) H'FFFF 1024 bytes
Figure 2.16 H8/3863 H8/3823 Memory
H'0000 Interrupt vector area H'0029 H'002A
kbytes On-chip (32768 bytes)
H'7FFF
used
H'F740 bytes) H'F75F used H'F780 On-chip H'FF7F used H'FF90 Internal registers (112 bytes) H'FFFF 2048 bytes
Figure 2.16 H8/3864 H8/3824 Memory
H'0000 H'0029 H'002A Interrupt vector area
kbytes On-chip (40960 bytes)
H'9FFF
used
H'F740 H'F75F
bytes)
used H'F780
On-chip H'FF7F used H'FF90 Internal registers (112 bytes) H'FFFF
2048 bytes
Figure 2.16 H8/3865 H8/3825 Memory
H'0000 Interrupt vector area H'0029 H'002A
kbytes On-chip (49152 bytes)
H'BFFF used
H'F740 H'F75F
bytes) used
H'F780
On-chip
2048 bytes
H'FF7F used H'FF90 Internal registers (112 bytes) H'FFFF
Figure 2.16 H8/3866 H8/3826 Memory
H'0000 Interrupt vector area H'0029 H'002A
kbytes On-chip (60928 bytes)
H'EDFF
used
H'F740 H'F75F
bytes)
used H'F780 On-chip H'FF7F used H'FF90 Internal registers (112 bytes) H'FFFF 2048 bytes
Figure 2.16 H8/3867 H8/3827 Memory
2.9.1
Application Notes
Notes Data Access
Access Empty Areas: address space H8/300L includes empty areas addition RAM, registers, areas available user. these empty areas mistakenly accessed application program, following results will occur. Data transfer from empty area: transferred data will lost. This action also cause misoperate. Data transfer from empty area CPU: Unpredictable data transferred. Access Internal Registers: Internal data transfer from on-chip modules other than areas makes 8-bit data width. word access attempted these areas, following results will occur. Word access from register area: Upper byte: Will written register. Lower byte: Transferred data will lost. Word access from register CPU: Upper byte: Will written upper part register. Lower byte: Unpredictable data will written lower part register. Byte size instructions should therefore used when transferring data from registers other than on-chip areas. Figure 2.17 shows data size number states which on-chip peripheral modules accessed.
Access States Word H'0000 H'0029 H'002A 32kbytes On-chip Interrupt vector area bytes) Byte
H'7FFF
used
H'F740 bytes) H'F75F used H'F780 On-chip H'FF7F*2 used H'FF90 Internal registers (112 bytes) H'FFFF Notes: example H8/3864 H8/3824 shown here. This address H'3FFF H8/3862 H8/3822 (16-kbyte on-chip ROM), H'5FFF H8/3863 H8/3823 (24-kbyte on-chip ROM), H'9FFF H8/3865 H8/3825 (40-kbyte on-chip ROM), H'BFFF H8/3866 H8/3826 (48-kbyte on-chip ROM), H'EDFF H8/3867 H8/3827 (60-kbyte on-chip ROM). This address H'FB7F H8/3862, H8/3822, H8/3863, H8/3823 (1024 bytes on-chip RAM). H'FF98 H'FF9F H'FFA8 H'FFAF 2048 bytes
Figure 2.17 Data Size Number States Access from On-Chip Peripheral Modules
2.9.2
Notes Manipulation
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify data, then write data byte again. Special care required when using these instructions cases where registers assigned same address, case registers that include writeonly bits, when instruction accesses port.
Order Operation Read Modify Write Operation Read byte data designated address Modify designated read data Write altered byte data designated address
manipulation registers assigned same address Example timer load register timer counter Figure 2.18 shows example which timer registers share same address. When manipulation instruction accesses timer load register timer counter reloadable timer, since these registers share same address, following operations take place.
Order Operation Read Modify Write Operation Timer counter data read (one byte) modifies (sets resets) designated instruction altered byte data written timer load register
timer counter counting, value read necessarily same value timer load register. result, bits other than intended timer load register modified timer counter value.
Read Count clock Timer counter
Reload Write Timer load register
Internal
Figure 2.18 Timer Configuration Example
Example BSET instruction executed designating port designated input pins, with low-level signal input high-level signal remaining pins, P30, output pins output low-level signals. this example, BSET instruction used change high-level output. Prior executing BSET]
Input/output Input state PCR3 PDR3 Input Output Output Output Output Output Output
level High level level level level level level level
BSET instruction executed] BSET @PDR3 BSET instruction executed designating port
After executing BSET]
Input/output Input state PCR3 PDR3 Input Output Output Output Output Output Output
level High level level level level level level High level
Explanation BSET operates] When BSET instruction executed, first reads port Since input pins, reads states (low-level high-level input). output pins, reads value PDR3. this example PDR3 value H'80, value read H'40. Next, sets read data changing PDR3 data H'41. Finally, writes this value (H'41) PDR3, completing execution BSET. result this operation, PDR3 becomes outputs high-level signal. However, bits PDR3 with different values. avoid this problem, store copy PDR3 data work area memory. Perform manipulation data work area, then write this data PDR3.
Prior executing BSET] MOV. MOV. MOV. #80, R0L, R0L,
Input/output Input state PCR3 PDR3 RAM0
@RAM0 @PDR3
Input
PDR3 value (H'80) written work area memory (RAM0) well PDR3
Output
Output
Output
Output
Output
Output
level High level level level level level level level
BSET instruction executed] BSET @RAM0 BSET instruction executed designating PDR3 work area (RAM0).
After executing BSET] MOV. MOV. @RAM0, R0L, @PDR3
Input/output Input state PCR3 PDR3 RAM0 Input
work area (RAM0) value written PDR3.
Output
Output
Output
Output
Output
Output
level High level level level level level level High level
manipulation register containing write-only Example BCLR instruction executed designating port control register PCR3 examples above, input pins, with low-level signal input high-level signal P36. remaining pins, P30, output pins that output low-level signals. this example, BCLR instruction used change input port. assumed that high-level signal will input this input pin. Prior executing BCLR]
Input/output Input state PCR3 PDR3 Input Output Output Output Output Output Output
level High level level level level level level level
BCLR instruction executed] BCLR @PCR3 BCLR instruction executed designating PCR3.
After executing BCLR]
Input/output Output state PCR3 PDR3 Output Output Output Output Output Output Input
level High level level level level level level High level
Explanation BCLR operates] When BCLR instruction executed, first reads PCR3. Since PCR3 write-only register, reads value H'FF, even though PCR3 value actually H'3F. Next, clears read data changing data H'FE. Finally, this value (H'FE) written PCR3 BCLR instruction execution ends. result this operation, PCR3 becomes making input port. However, bits PCR3 change that change from input pins output pins. avoid this problem, store copy PCR3 data work area memory. Perform manipulation data work area, then write this data PCR3.
Prior executing BCLR] MOV. MOV. MOV. #3F, R0L, R0L,
Input/output Input state PCR3 PDR3 RAM0
@RAM0 @PCR3
Input
PCR3 value (H'3F) written work area memory (RAM0) well PCR3.
Output
Output
Output
Output
Output
Output
level High level level level level level level level
BCLR instruction executed] BCLR @RAM0 BCLR instruction executed designating PCR3 work area (RAM0).
After executing BCLR] MOV. MOV. @RAM0, R0L, @PCR3
Input/output Input state PCR3 PDR3 RAM0 Input
work area (RAM0) value written PCR3.
Output
Output
Output
Output
Output
Output
level High level level level level level level High level
Table 2.12 lists pairs registers that share identical addresses. Table 2.13 lists registers that contain write-only bits. Table 2.12 Registers with Shared Addresses
Register Name Timer counter timer load register Port data register Port data register Port data register Port data register Port data register Port data register Port data register Port data register Abbreviation TCC/TLC PDR1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDRA Address H'FFB5 H'FFD4 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDD
Note: Port data registers have same addresses input pins.
Table 2.13 Registers with Write-Only Bits
Register Name Port control register Port control register Port control register Port control register Port control register Port control register Port control register Port control register Timer control register control register data register data register Abbreviation PCR1 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCRA TCRF PWCR PWDRU PWDRL Address H'FFE4 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFED H'FFB6 H'FFD0 H'FFD1 H'FFD2
2.9.3
Notes EEPMOV Instruction
EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
Section Exception Handling
Overview
Exception handling performed H8/3864 Series when reset interrupt occurs. Table shows priorities these types exception handling. Table
Priority High
Exception Handling Types Priorities
Exception Source Reset Interrupt Time Start Exception Handling Exception handling starts soon reset state cleared When interrupt requested, exception handling starts after execution present instruction exception handling progress completed
3.2.1
Reset
Overview
reset highest-priority exception. internal state registers onchip peripheral modules initialized. 3.2.2 Reset Sequence
soon goes low, processing stopped chip enters reset state. make sure chip reset properly, observe following precautions. power Hold until clock pulse generator output stabilizes. Resetting during operation: Hold least system clock cycles. Reset exception handling takes place follows. internal state registers on-chip peripheral modules initialized, with condition code register (CCR) loaded from reset exception handling vector address (H'0000 H'0001), after which program starts executing from address indicated
When system power turned off, should held low. Figure shows reset sequence starting from input.
Reset cleared Program initial instruction prefetch Vector fetch Internal processing
Internal address Internal read signal Internal write signal Internal data (16-bit)
Reset exception handling vector address (H'0000) Program start address First instruction program
Figure Reset Sequence
3.2.3
Interrupt Immediately after Reset
After reset, interrupt were accepted before stack pointer (SP: initialized, would pushed onto stack correctly, resulting program runaway. prevent this, immediately after reset exception handling interrupts masked. this reason, initial program instruction always executed immediately after reset. This instruction should initialize stack pointer (e.g. MOV.W #xx: SP).
3.3.1
Interrupts
Overview
interrupt sources include external interrupts (IRQ4 IRQ0, WKP7 WKP0) internal interrupts from on-chip peripheral modules. Table shows interrupt sources, their priorities, their vector addresses. When more than interrupt requested, interrupt with highest priority processed. interrupts have following features: Internal external interrupts masked CCR. When interrupt request flags interrupts accepted. IRQ4 IRQ0 WKP0 either rising edge sensing falling edge sensing.
Table
Interrupt Sources Their Priorities
Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 Timer overflow Asynchronous counter overflow Timer overflow underflow Timer compare match Timer overflow Timer compare match Timer overflow Timer input capture Timer overflow Vector Number Vector Address H'0000 H'0001 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 Priority High
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 Timer Asynchronous counter Timer Timer Timer Timer SCI3-1
H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023
SCI3-1 transmit SCI3-1 transmit data empty SCI3-1 receive data full SCI3-1 overrrun error SCI3-1 framing error SCI3-1 parity error SCI3-2 transmit SCI3-2 transmit data empty SCI3-2 receive data full SCI3-2 overrun error SCI3-2 framing error SCI3-2 parity error conversion Direct transfer
SCI3-2
H'0024 H'0025
(SLEEP instruction executed)
H'0026 H'0027 H'0028 H'0029
Note: Vector addresses H'0002 H'0007 H'0014 H'0015 reserved cannot used.
3.3.2
Interrupt Control Registers
Table lists registers that control interrupts. Table
Name edge select register Interrupt enable register Interrupt enable register Interrupt request register Interrupt request register Wakeup interrupt request register Wakeup edge select register
Interrupt Control Registers
Abbreviation IEGR IENR1 IENR2 IRR1 IRR2 IWPR WEGR R/W* R/W* R/W* Initial Value H'E0 H'00 H'00 H'20 H'00 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9 H'FF90
Note: Write enabled only writing clear flag.
edge select register (IEGR)
Initial value Read/Write IEG4 IEG3 IEG2 IEG1 IEG0
IEGR 8-bit read/write register used designate whether pins IRQ4 IRQ0 rising edge sensing falling edge sensing. Bits Reserved bits Bits reserved: they always read cannot modified. IRQ4 edge select (IEG4) selects input sensing IRQ4 ADTRG pin.
IEG4 Description Falling edge IRQ4 ADTRG input detected Rising edge IRQ4 ADTRG input detected (initial value)
IRQ3 edge select (IEG3) selects input sensing IRQ3 TMIF pin.
IEG3 Description Falling edge IRQ3 TMIF input detected Rising edge IRQ3 TMIF input detected (initial value)
IRQ2 edge select (IEG2) selects input sensing IRQ2.
IEG2 Description Falling edge IRQ2 input detected Rising edge IRQ2 input detected (initial value)
IRQ1 edge select (IEG1) selects input sensing IRQ1 TMIC pin.
IEG1 Description Falling edge IRQ1 TMIC input detected Rising edge IRQ1 TMIC input detected (initial value)
IRQ0 edge select (IEG0) selects input sensing IRQ0.
IEG0 Description Falling edge IRQ0 input detected Rising edge IRQ0 input detected (initial value)
Interrupt enable register (IENR1)
Initial value Read/Write IENTA IENWP IEN4 IEN3 IEN2 IEN1 IEN0
IENR1 8-bit read/write register that enables disables interrupt requests. Timer interrupt enable (IENTA) enables disables timer overflow interrupt requests.
IENTA Description Disables timer interrupt requests Enables timer interrupt requests (initial value)
Reserved readable/writable reserved bit. initialized reset. Wakeup interrupt enable (IENWP) enables disables WKP7 WKP0 interrupt requests.
IENWP Description Disables interrupt requests Enables interrupt requests (initial value)
Bits IRQ4 IRQ0 interrupt enable (IEN4 IEN0) Bits enable disable IRQ4 IRQ0 interrupt requests.
IENn Description Disables interrupt requests from IRQn Enables interrupt requests from IRQn (initial value)
Interrupt enable register (IENR2)
Initial value Read/Write IENDT IENAD IENTG IENTC IENEC
IENTFH IENTFL
IENR2 8-bit read/write register that enables disables interrupt requests. Direct transfer interrupt enable (IENDT) enables disables direct transfer interrupt requests.
IENDT Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value)
converter interrupt enable (IENAD) enables disables converter interrupt requests.
IENAD Description Disables converter interrupt requests Enables converter interrupt requests (initial value)
Reserved readable/writable reserved bit. initialized reset. Timer interrupt enable (IENTG) enables disables timer input capture overflow interrupt requests.
IENTG Description Disables timer interrupt requests Enables timer interrupt requests (initial value)
Timer interrupt enable (IENTFH) enables disables timer compare match overflow interrupt requests.
IENTFH Description Disables timer interrupt requests Enables timer interrupt requests (initial value)
Timer interrupt enable (IENTFL) enables disables timer compare match overflow interrupt requests.
IENTFL Description Disables timer interrupt requests Enables timer interrupt requests (initial value)
Timer interrupt enable (IENTC) enables disables timer overflow underflow interrupt requests.
IENTC Description Disables timer interrupt requests Enables timer interrupt requests (initial value)
Asynchronous event counter interrupt enable (IENEC) enables disables asynchronous event counter interrupt requests.
IENEC Description Disables asynchronous event counter interrupt requests Enables asynchronous event counter interrupt requests (initial value)
details SCI3-1 SCI3-2 interrupt control, Serial control register (SCR3) section 10.4.2.
Interrupt request register (IRR1)
Initial value Read/Write IRRTA IRRI4 IRRI3 IRRI2 IRRI1 IRRI0
Note: Only write flag clearing possible
IRR1 8-bit read/write register, which corresponding flag when timer IRQ4 IRQ0 interrupt requested. flags cleared automatically when interrupt accepted. necessary write clear each flag. Timer interrupt request flag (IRRTA)
IRRTA Description Clearing conditions: When IRRTA cleared writing Setting conditions: When timer counter value overflows from H'FF H'00 (initial value)
Reserved readable/writable reserved bit. initialized reset. Reserved reserved; always read cannot modified. Bits IRQ4 IRQ0 interrupt request flags (IRRI4 IRRI0)
IRRIn Description Clearing conditions: When IRRIn cleared writing (initial value)
Setting conditions: When IRQn designated interrupt input designated signal edge input
Interrupt request register (IRR2)
Initial value Read/Write IRRDT IRRAD IRRTG IRRTC IRREC
IRRTFH IRRTFL
Note: Only write flag clearing possible
IRR2 8-bit read/write register, which corresponding flag when direct transfer, converter, Timer Timer Timer Timer interrupt requested. flags cleared automatically when interrupt accepted. necessary write clear each flag. Direct transfer interrupt request flag (IRRDT)
IRRDT Description Clearing conditions: When IRRDT cleared writing (initial value)
Setting conditions: When direct transfer made executing SLEEP instruction while DTON SYSCR2
converter interrupt request flag (IRRAD)
IRRAD Description Clearing conditions: When IRRAD cleared writing Setting conditions: When conversion completed ADSF cleared ADSR (initial value)
Reserved readable/writable reserved bit. initialized reset.
Timer interrupt request flag (IRRTG)
IRRTG Description Clearing conditions: When IRRTG cleared writing (initial value)
Setting conditions: When TMIG designated TMIG input designated signal edge input, when overflows while OVIE
Timer interrupt request flag (IRRTFH)
IRRTFH Description Clearing conditions: When IRRTFH cleared writing (initial value)
Setting conditions: When TCFH OCRFH match 8-bit timer mode, when (TCFL, TCFH) OCRF (OCRFL, OCRFH) match 16-bit timer mode
Timer interrupt request flag (IRRTFL)
IRRTFL Description Clearing conditions: When IRRTFL= cleared writing Setting conditions: When TCFL OCRFL match 8-bit timer mode (initial value)
Timer interrupt request flag (IRRTC)
IRRTC Description Clearing conditions: When IRRTC= cleared writing (initial value)
Setting conditions: When timer counter value overflows (from H'FF H'00) underflows (from H'00 H'FF)
Asynchronous event counter interrupt request flag (IRREC)
IRREC Description Clearing conditions: When IRREC cleared writing (initial value)
Setting conditions: When overflows 16-bit counter mode, overflows 8-bit counter mode
Wakeup Interrupt Request Register (IWPR)
Initial value Read/Write IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Note: Only write flag clearing possible
IWPR 8-bit read/write register containing wakeup interrupt request flags. When pins WKP7 WKP0 designated wakeup input rising falling edge input that pin, corresponding flag IWPR flag cleared automatically when corresponding interrupt accepted. Flags must cleared writing Bits Wakeup interrupt request flags (IWPF7 IWPF0)
IWPFn Description Clearing conditions: When IWPFn= cleared writing (initial value)
Setting conditions: When designated wakeup input rising falling edge input that
Wakeup Edge Select Register (WEGR)
Initial value Read/Write
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
WEGR 8-bit read/write register that specifies rising falling edge sensing pins WKPn. WEGR initialized H'00 reset. WKPn edge select (WKEGSn) selects WKPn input sensing.
WKEGSn Description WKPn falling edge detected WKPn rising edge detected (initial value)
3.3.3
External Interrupts
There external interrupts: IRQ0 WKP0. Interrupts WKP0 Interrupts WKP0 requested either rising falling edge input pins WKP7 WKP0. When these pins designated pins WKP7 WKP0 port mode register rising falling edge input, corresponding IWPR requesting interrupt. Recognition wakeup interrupt requests disabled clearing IENWP IENR1. These interrupts masked setting CCR. When WKP0 interrupt exception handling initiated, CCR. Vector number assigned interrupts WKP7 WKP0. eight interrupt sources have same vector number, interrupt-handling routine must discriminate interrupt source.
Interrupts IRQ0 Interrupts IRQ0 requested input signals pins IRQ4 IRQ0. These interrupts detected either rising edge sensing falling edge sensing, depending settings bits IEG4 IEG0 IEGR. When these pins designated pins IRQ4 IRQ0 port mode register designated edge input, corresponding IRR1 requesting interrupt. Recognition these interrupt requests disabled individually clearing bits IEN4 IEN0 IENR1. These interrupts masked setting CCR. When IRQ0 interrupt exception handling initiated, CCR. Vector numbers assigned interrupts IRQ4 IRQ0. order priority from IRQ0 (high) IRQ4 (low). Table gives details. 3.3.4 Internal Interrupts
There internal interrupts that requested on-chip peripheral modules. When peripheral module requests interrupt, corresponding IRR1 IRR2 Recognition individual interrupt requests disabled clearing corresponding IENR1 IENR2. these interrupts masked setting CCR. When internal interrupt handling initiated, CCR. Vector numbers from assigned these interrupts. Table shows order priority interrupts from on-chip peripheral modules.
3.3.5
Interrupt Operations
Interrupts controlled interrupt controller. Figure shows block diagram interrupt controller. Figure shows flow interrupt acceptance.
Interrupt controller
External internal interrupts
Priority decision logic
Interrupt request
External interrupts internal interrupt enable signals
(CPU)
Figure Block Diagram Interrupt Controller Interrupt operation described follows. When interrupt condition while interrupt enable register interrupt request signal sent interrupt controller. When interrupt controller receives interrupt request, sets interrupt request flag. From among interrupts with interrupt request flags interrupt controller selects interrupt request with highest priority holds others pending. (Refer table list interrupt priorities.) interrupt controller checks CCR. selected interrupt request accepted; interrupt request held pending.
interrupt accepted, after processing current instruction completed, both pushed onto stack. state stack this time shown figure 3.4. value pushed onto stack address first instruction executed upon return from interrupt handling. masking further interrupts. vector address corresponding accepted interrupt generated, interrupt handling routine located address indicated contents vector address executed. Notes: When disabling interrupts clearing bits interrupt enable register, when clearing bits interrupt request register, always while interrupts masked above clear operations performed while result conflict arises between clear instruction interrupt request, exception processing interrupt will executed after clear instruction been executed.
Program execution state
IRRI0 IEN0
IRRI1 IEN1
IRRI2 IEN2
IRRDT IENDT
contents saved contents saved Branch interrupt handling routine
Notation: Program counter CCR: Condition code register
Figure Flow Interrupt Acceptance
(R7) Stack area
(R7)
Even address
Prior start interrupt exception handling
Notation: PCH: Upper bits program counter (PC) Lower bits program counter (PC) PCL: CCR: Condition code register Stack pointer
saved stack
After completion interrupt exception handling
Notes: shows address first instruction executed upon return from interrupt handling routine. Register contents must always saved restored word access, starting from even-numbered address. Ignored return.
Figure Stack State after Completion Interrupt Exception Handling Figure shows typical interrupt sequence.
Interrupt accepted Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction Internal interrupt-handling routine processing (10)
Interrupt level decision wait instruction
Interrupt request signal
Internal address
Internal read signal
Figure Interrupt Sequence
Internal write signal
Internal data bits)
Instruction prefetch address (Instruction executed. Address saved contents, becoming return address.) (2)(4) Instruction code (not executed) Instruction prefetch address (Instruction executed.) Vector address Starting address interrupt-handling routine (contents vector) (10) First instruction interrupt-handling routine
3.3.6
Interrupt Response Time
Table shows number wait states after interrupt request flag until first instruction interrupt handler executed. Table
Item Waiting time completion executing instruction* Saving stack Vector fetch Instruction fetch Internal processing Note: including EEPMOV instruction.
Interrupt Wait States
States Total
3.4.1
Application Notes
Notes Stack Area
When word data accessed H8/3864 Series, least significant address regarded Access stack always takes place word size, stack pointer (SP: should never indicate address. PUSH (MOV.W @-SP) (MOV.W @SP+, save restore register values. Setting address cause program crash. example shown figure 3.6.
H'FEFC H'FEFD H'FEFF
instruction H'FEFF
MOV. R1L, @-R7 Contents lost
Stack accessed beyond
Notation: PCH: Upper byte program counter PCL: Lower byte program counter R1L: General register Stack pointer
Figure Operation when Address When contents saved stack during interrupt exception handling restored when executed, this also takes place word size. Both upper lower bytes word data saved stack; return, even address contents restored while address contents ignored.
3.4.2
Notes Rewriting Port Mode Registers
When port mode register rewritten switch functions external interrupt pins, following points should observed. When external interrupt function switched rewriting port mode register that controls pins IRQ4 IRQ0, WKP7 WKP0, interrupt request flag time function switched, even valid interrupt input pin. sure clear interrupt request flag after switching functions. Table shows conditions under which interrupt request flags this way. Table Conditions under which Interrupt Request Flag
Conditions When PMR1 IRQ4 changed from while IRQ4 IEGR IEG4 When PMR1 IRQ4 changed from while IRQ4 IEGR IEG4 IRRI3 When PMR1 IRQ3 changed from while IRQ3 IEGR IEG3 When PMR1 IRQ3 changed from while IRQ3 IEGR IEG3 IRRI2 When PMR1 IRQ2 changed from while IRQ2 IEGR IEG2 When PMR1 IRQ2 changed from while IRQ2 IEGR IEG2 IRRI1 When PMR1 IRQ1 changed from while IRQ1 IEGR IEG1 When PMR1 IRQ1 changed from while IRQ1 IEGR IEG1 IRRI0 When PMR3 IRQ0 changed from while IRQ0 IEGR IEG0 When PMR3 IRQ0 changed from while IRQ0 IEGR IEG0 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 When PMR5 WKP7 changed from while low. When PMR5 WKP6 changed from while low. When PMR5 WKP5 changed from while low. When PMR5 WKP4 changed from while low. When PMR5 WKP3 changed from while low. When PMR5 WKP2 changed from while low. When PMR5 WKP1 changed from while low. When PMR5 WKP0 changed from while low.
Interrupt Request Flags IRR1 IRRI4
Figure shows procedure setting port mode register clearing interrupt request flag. When switching function, mask interrupt before setting port mode register. After accessing port mode register, execute least instruction (e.g., NOP), then clear interrupt request flag from instruction clear flag executed immediately after port mode register access without executing intervening instruction, flag will cleared. alternative method avoid setting interrupt request flags when functions switched keeping pins high level that conditions table occur.
Interrupts masked. (Another possibility disable relevant interrupt interrupt enable register
port mode register Execute instruction Clear interrupt request flag After setting port mode register bit, first execute least instruction (e.g., NOP), then clear interrupt request flag
Interrupt mask cleared
Figure Port Mode Register Setting Interrupt Request Flag Clearing Procedure
Section Clock Pulse Generators
Overview
Clock oscillator circuitry (CPG: clock pulse generator) provided on-chip, including both system clock pulse generator subclock pulse generator. system clock pulse generator consists system clock oscillator system clock dividers. subclock pulse generator consists subclock oscillator circuit subclock divider. 4.1.1 Block Diagram
Figure shows block diagram clock pulse generators.
System clock oscillator
OSC)
System clock divider (1/2) System clock divider Prescaler bits) /128
System clock pulse generator Subclock oscillator
Subclock divider (1/2, 1/4, 1/8)
Subclock pulse generator
Prescaler bits)
Figure Block Diagram Clock Pulse Generators 4.1.2 System Clock Subclock
basic clock signals that drive on-chip peripheral modules Four clock signals have names: system clock, subclock, oscillator clock, watch clock. clock signals available peripheral modules /16, /32, /64, /128. clock requirements differ from module another.
System Clock Generator
Clock pulses supplied system clock divider either connecting crystal ceramic oscillator, providing external clock input. Connecting crystal oscillator Figure shows typical method connecting crystal oscillator.
±20% Crystal oscillator Recommendation value Products Name ±10% ±20% NR-18 (NDK45) NR-18 (NDK03)
Frequency
Figure Typical Connection Crystal Oscillator Figure shows equivalent circuit crystal oscillator. oscillator having characteristics given table should used.
Figure Equivalent Circuit Crystal Oscillator Table Crystal Oscillator Parameters
4.193
Frequency (MHz) (pF)
Connecting ceramic oscillator Figure shows typical method connecting ceramic oscillator.
Frequency Ceramic oscillator Murata Murata ±20% Recommendation value Products Name ±10% ±10% 1000J 4.00MG
Figure Typical Connection Ceramic Oscillator Notes board design When generating clock pulses connecting crystal ceramic oscillator, careful attention following points. Avoid running signal lines close oscillator circuit, since oscillator adversely affected induction currents. (See figure 4.5.) board should designed that oscillator load capacitors located close possible pins OSC1 OSC2.
avoided Signal Signal
Figure Board Design Oscillator Circuit
External clock input method Connect external clock signal OSC1, leave OSC2 open. Figure shows typical connection.
External clock input
Open
Figure External Clock Input (Example)
Frequency Duty cycle Oscillator Clock
Note: circuit parameters above recommended crystal ceramic oscillator manufacturer. circuit parameters affected crystal ceramic oscillator floating capacitance when designing board. When using oscillator, consult with crystal ceramic oscillator manufacturer determine circuit parameters.
Subclock Generator
Connecting 32.768-kHz/38.4 crystal oscillator Clock pulses supplied subclock divider connecting 32.768-kHz/38.4 crystal oscillator, shown figure 4.7. Follow same precautions noted under notes board design system clock 4.2.
(typ.) Frequency 38.4 Crystal oscillator Products Name MX73P
32.768
Seiko Instrument Inc. VTC-200
Figure Typical Connection 32.768-kHz/38.4 Crystal Oscillator (Subclock) Figure shows equivalent circuit 32.768-kHz/38.4 crystal oscillator.
32.768 kHz/38.4kHz
Figure Equivalent Circuit 32.768-kHz/38.4 Crystal Oscillator
connection when using subclock When subclock used, connect leave open, shown figure 4.9.
Open
Figure Connection when Using Subclock External clock input Connect external clock leave open, shown figure 4.10.
External clock input
Open
Figure 4.10 Connection when Inputting External Clock
Frequency Duty Subclock
Prescalers
H8/3864 Series equipped with on-chip prescalers having different input clocks (prescaler prescaler Prescaler 13-bit counter using system clock input clock. prescaled outputs provide internal clock signals on-chip peripheral modules. Prescaler 5-bit counter using 32.768-kHz 38.4 signal divided input clock. prescaled outputs used timer time base timekeeping. Prescaler (PSS) Prescaler 13-bit counter using system clock input clock. incremented once clock period. Prescaler initialized H'0000 reset, starts counting exit from reset state. standby mode, watch mode, subactive mode, subsleep mode, system clock pulse generator stops. Prescaler also stops initialized H'0000. cannot read write prescaler output from prescaler shared timer timer timer timer SCI3-1, SC3-2, converter, controller, watchdog timer, 14-bit PWM. divider ratio separately each on-chip peripheral function. active (medium-speed) mode clock input prescaler Prescaler (PSW) Prescaler 5-bit counter using 32.768 kHz/38.4 signal divided input clock. Prescaler initialized H'00 reset, starts counting exit from reset state. Even standby mode, watch mode, subactive mode, subsleep mode, prescaler continues functioning long clock signals supplied pins Prescaler reset setting bits TMA3 TMA2 timer mode register (TMA). Output from prescaler used drive timer which case timer functions time base timekeeping.
Note Oscillators
Oscillator characteristics closely related board design should carefully evaluated user mask ZTATversions, referring examples shown this section. Oscillator circuit constants will differ depending oscillator element, stray capacitance interconnecting circuit, other factors. Suitable constants should determined consultation with oscillator element manufacturer. Design circuit that oscillator element never receives voltages exceeding maximum rating.
Section Power-Down Modes
Overview
H8/3864 Series nine modes operation after reset. These include eight power-down modes, which power dissipation significantly reduced. Table gives summary eight operating modes. Table Operating Modes
Description on-chip peripheral functions operable system clock high-speed operation on-chip peripheral functions operable system clock low-speed operation operable subclock low-speed operation halts. On-chip peripheral functions operable system clock halts. On-chip peripheral functions operate frequency 1/64, 1/32, 1/16, system clock frequency halts. time-base function timer timer timer timer F,WDT, SCI3-1, SCI3-2, controller/driver operable subclock halts. time-base function timer timer timer controller/driver operable subclock on-chip peripheral functions halt Individual on-chip peripheral functions specified software enter standby mode halt
Operating Mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Sleep (high-speed) mode Sleep (medium-speed) mode
Subsleep mode
Watch mode
Standby mode Module standby mode
these nine operating modes, active (high-speed) mode power-down modes. this section active modes (high-speed medium speed) will referred collectively active mode.
Figure shows transitions among these operation modes. Table indicates internal states each mode.
Program execution state Active (high-speed) mode SLEEP instruction*a
Reset state
Program halt state Sleep (high-speed) mode
Program halt state
uctio
Standby mode
instr uctio
SLEE ctio
Active (medium-speed) mode
ctio inin SLEEP instruction*b
SLEEP instruction*g
SLEEP instruction*f
Sleep (medium-speed) mode
SLEEP instruction*h
Watch mode
SLEEP instruction*e
SLEEP instruction*i
ctio
Subactive mode
SLEE ctio
SLEEP instruction*c
Subsleep mode
Power-down modes Mode Transition Conditions LSON MSON SSBY TMA3 DTON Mode Transition Conditions Interrupt Sources Timer Timer Timer interrupt, IRQ0 interrupt, WKP7 WKP0 interrupts Timer Timer Timer Timer SCI3-1, SCI3-2 interrupt, IRQ4 IRQ0 interrupts, WKP7 WKP0 interrupts, interrupts IRQ1 IRQ0 interrupt, WKP7 WKP0 interrupts
Don't care Notes: transition between different modes cannot made occur simply because interrupt request generated. Make sure that interrupt handling performed after interrupt accepted. Details mode transition conditions given explanations each mode, sections through 5-8.
Figure Mode Transition Diagram
Table
Internal State Each Operating Mode
Active Mode Sleep Mode HighSpeed MediumSpeed Watch Mode Subactive Mode Halted Functions Functions Subsleep Mode Halted Functions Halted Retained Standby Mode Halted Functions Halted Retained Retained*1 Functions Functions Functions Functions Functions Retained*6 Retained*6 Functions Functions Functions HighSpeed MediumSpeed
Function System clock oscillator Subclock oscillator Instructions
Functions Functions Functions Functions Halted Functions Functions Functions Functions Functions Functions Functions Halted Retained Halted Retained Halted Retained
operations Registers ports External interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Peripheral functions Timer Asynchronous counter Timer Timer Timer SCI3-1 SCI3-2 converter Notes:
Functions Functions Functions Functions Functions
Functions
Functions
Functions
Functions Functions Functions Functions Functions*5 Functions*5 Functions Retained
Functions*5 Functions Functions/ Retained*2 Retained Functions/ Retained*9 Functions/
Retained Functions*8 Retained
Functions Functions/ Retained*2 Functions/ Retained*7
Functions/ Retained*9 Reset
Functions/ Retained*9 Functions/ Retained*3
Reset
Retained Retained Functions/ Retained*4
Retained Retained Functions/ Retained*4
Retained Retained Functions/ Retained*4
Retained Retained Retained
Register contents retained, output high-impedance state. Functions external clock internal clock selected; otherwise halted retained. Functions selected internal clock; otherwise halted retained. Functions selected operating clock; otherwise halted retained. Functions timekeeping time-base function selected. External interrupt requests ignored. Interrupt request register contents altered. Functions selected internal clock; otherwise halted retained. Incrementing possible, interrupt generation not. Functions external clock internal clock selected; otherwise halted retained.
5.1.1
System Control Registers
operation mode selected using system control registers described table 5.3. Table
Name System control register System control register
System Control Registers
Abbreviation SYSCR1 SYSCR2 Initial Value H'07 H'F0 Address H'FFF0 H'FFF1
System control register (SYSCR1)
Initial value Read/Write SSBY STS2 STS1 STS0 LSON
SYSCR1 8-bit read/write register control power-down modes. Upon reset, SYSCR1 initialized H'07. Software standby (SSBY) This designates transition standby mode watch mode.
SSBY Description When SLEEP instruction executed active mode, transition made sleep mode (initial value)
When SLEEP instruction executed subactive mode, transition made subsleep mode When SLEEP instruction executed active mode, transition made standby mode watch mode When SLEEP instruction executed subactive mode, transition made watch mode
Bits Standby timer select (STS2 STS0) These bits designate time peripheral modules wait stable clock operation after exiting from standby mode watch mode active mode interrupt. designation should made according operating frequency that waiting time least equal oscillation settling time.
STS2 STS1 STS0 Description Wait time 8,192 states Wait time 16,384 states Wait time 32,768 states Wait time 65,536 states Wait time 131,072 states Wait time states Wait time states Wait time states (External clock mode) (initial value)
Note: case that external clock input, "Standby timer select" selection External clock mode before Mode Transition. Also, external clock mode, case that does external clock.
speed flag (LSON) This chooses system clock subclock operating clock when watch mode cleared. resulting operation mode depends combination other control bits interrupt input.
LSON Description operates system clock operates subclock (initial value)
Bits Reserved bits reserved: always read cannot modified.
Bits Active (medium-speed) mode clock select (MA1, MA0) Bits choose /128, /64, /32, operating clock active (mediumspeed) mode sleep (medium-speed) mode. should written active (highspeed) mode subactive mode.
Description (initial value)
System control register (SYSCR2)
Initial value Read/Write NESEL DTON MSON
SYSCR2 8-bit read/write register power-down mode control. Bits Reserved bits These bits reserved; they always read cannot modified. Noise elimination sampling frequency select (NESEL) This selects frequency which watch clock signal generated subclock pulse generator sampled, relation oscillator clock generated system clock pulse generator. When MHz, clear NESEL
NESEL Description Sampling rate OSC/16 Sampling rate OSC/4 (initial value)
Direct transfer flag (DTON) This designates whether make direct transitions among active (high-speed), active (medium-speed) subactive mode when SLEEP instruction executed. mode which transition made after SLEEP instruction executed depends combination this other control bits.
DTON Description When SLEEP instruction executed active mode, transition made standby mode, watch mode, sleep mode (initial value)
When SLEEP instruction executed subactive mode, transition made watch mode subsleep mode When SLEEP instruction executed active (high-speed) mode, direct transition made active (medium-speed) mode SSBY MSON LSON subactive mode SSBY TMA3 LSON When SLEEP instruction executed active (medium-speed) mode, direct transition made active (high-speed) mode SSBY MSON LSON subactive mode SSBY TMA3 LSON When SLEEP instruction executed subactive mode, direct transition made active (high-speed) mode SSBY TMA3 LSON MSON active (medium-speed) mode SSBY TMA3 LSON MSON
Medium speed flag (MSON) After standby, watch, sleep mode cleared, this selects active (high-speed) active (medium-speed) mode.
MSON Description Operation active (high-speed) mode Operation active (medium-speed) mode (initial value)
Bits Subactive mode clock select (SA1 SA0) These bits select clock rate subactive mode. cannot modified subactive mode.
Description Don't care (initial value)
5.2.1
Sleep Mode
Transition Sleep Mode
Transition sleep (high-speed) mode system goes from active mode sleep (high-speed) mode when SLEEP instruction executed while SSBY LSON bits SYSCR1 cleared MSON DTON bits SYSCR2 cleared sleep mode operation halted on-chip peripheral functions. register contents retained. Transition sleep (medium-speed) mode system goes from active mode sleep (medium-speed) mode when SLEEP instruction executed while SSBY LSON bits SYSCR1 cleared MSON SYSCR2 DTON SYSCR2 cleared sleep (medium-speed) mode, sleep (high-speed) mode, operation halted on-chip peripheral functions operational. clock frequency sleep (medium-speed) mode determined bits SYSCR1. register contents retained. Furthermore, sometimes acts with half state early timing time transition sleep (medium-speed) mode. 5.2.2 Clearing Sleep Mode
Sleep mode cleared interrupt (timer timer timer timer asynchronous counter, IRQ4 IRQ0, WKP7 WKP0, SCI3-1, SCI3-2, converter, or), input pin. Clearing interrupt When interrupt requested, sleep mode cleared interrupt exception handling starts. transition made from sleep (high-speed) mode active (high-speed) mode, from sleep (medium-speed) mode active (medium-speed) mode. Sleep mode cleared condition code register (CCR) particular interrupt disabled interrupt enable register. Interrupt signal system clock mutually asynchronous. Synchronization error time maximum (s). Clearing input When goes low, goes into reset state sleep mode cleared.
5.2.3
Clock Frequency Sleep (Medium-Speed) Mode
Operation sleep (medium-speed) mode clocked frequency designated bits SYSCR1.
5.3.1
Standby Mode
Transition Standby Mode
system goes from active mode standby mode when SLEEP instruction executed while SSBY SYSCR1 LSON SYSCR1 cleared TMA3 cleared standby mode clock pulse generator stops, on-chip peripheral modules stop functioning, long rated voltage supplied, contents registers, on-chip RAM, some on-chip peripheral module registers retained. On-chip contents will further retained down minimum data retention voltage. ports high-impedance state. 5.3.2 Clearing Standby Mode
Standby mode cleared interrupt (IRQ1 IRQ0), WKP0 input pin. Clearing interrupt When interrupt requested, system clock pulse generator starts. After time bits STS2 STS0 SYSCR1 elapsed, stable system clock signal supplied entire chip, standby mode cleared, interrupt exception handling starts. Operation resumes active (high-speed) mode MSON SYSCR2, active (medium-speed) mode MSON Standby mode cleared particular interrupt disabled interrupt enable register. Clearing input When goes low, system clock pulse generator starts. After pulse generator output stabilized, driven high, starts reset exception handling. Since system clock signals supplied entire chip soon system clock pulse generator starts functioning, should kept level until pulse generator output stabilizes.
5.3.3
Oscillator Settling Time after Standby Mode Cleared
Bits STS2 STS0 SYSCR1 should follows. When crystal oscillator used table below gives settings various operating frequencies. bits STS2 STS0 waiting time least long oscillation settling time. Table
STS2
Clock Frequency Settling Time (times
STS1 STS0 Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states states (Use prohibited) states states 16.4 32.8 65.5 0.001 0.004 0.008 16.4 32.8 65.5 131.1 0.002 0.008 0.016 16.4 32.8 65.5 131.1 262.1 0.004 0.016 0.032
When external clock used STS2 STS1 STS0 should set. Other values possible use, sometimes will start operation before waiting time completion.
5.3.4
Standby Mode Transition States
When SLEEP instruction executed active (high-speed) mode active (medium-speed) mode while SSBY LSON cleared SYSCR1, TMA3 cleared TMA, transition made standby mode. same time, pins highimpedance state (except pins which pull-up designated on). Figure shows timing this case.
Internal data
SLEEP instruction fetch
Fetch next instruction Internal processing High-impedance Standby mode
SLEEP instruction execution Pins Port output Active (high-speed) mode active (medium-speed) mode
Figure Standby Mode Transition States
5.4.1
Watch Mode
Transition Watch Mode
system goes from active subactive mode watch mode when SLEEP instruction executed while SSBY SYSCR1 TMA3 watch mode, operation on-chip peripheral modules halted except timer timer timer controller/driver (for which operation halting set) halted. long minimum required voltage applied, contents registers, on-chip some registers on-chip peripheral modules, retained. ports keep same states before transition. 5.4.2 Clearing Watch Mode
Watch mode cleared interrupt (timer timer timer WKP7 WKP0) input pin. Clearing interrupt When watch mode cleared interrupt, mode which transition made depends settings LSON SYSCR1 MSON SYSCR2. both LSON MSON cleared transition active (high-speed) mode; LSON MSON transition active (medium-speed) mode; LSON transition subactive mode. When transition active mode, after time SYSCR1 bits STS2 STS0 elapsed, stable clock signal supplied entire chip, watch mode cleared, interrupt exception handling starts. Watch mode cleared particular interrupt disabled interrupt enable register. Clearing input Clearing same standby mode; Clearing 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode Cleared
waiting time same standby mode; 5.3.3, Oscillator Settling Time after Standby Mode Cleared.
5.5.1
Subsleep Mode
Transition Subsleep Mode
system goes from subactive mode subsleep mode when SLEEP instruction executed while SSBY SYSCR1 cleared LSON SYSCR1 TMA3 subsleep mode, operation on-chip peripheral modules other than converter halted. long minimum required voltage applied, contents registers, on-chip some registers on-chip peripheral modules retained. ports keep same states before transition. 5.5.2 Clearing Subsleep Mode
Subsleep mode cleared interrupt (timer timer timer timer asynchronous counter, SCI3-2, SCI3-1, IRQ4 IRQ0, WKP7 WKP0) input pin. Clearing interrupt When interrupt requested, subsleep mode cleared interrupt exception handling starts. Subsleep mode cleared particular interrupt disabled interrupt enable register. Interrupt signal system clock mutually asynchronous. Synchronization error time maximum (s). Clearing input Clearing same standby mode; Clearing 5.3.2, Clearing Standby Mode.
5.6.1
Subactive Mode
Transition Subactive Mode
Subactive mode entered from watch mode timer timer timer IRQ0, WKP7 WKP0 interrupt requested while LSON SYSCR1 From subsleep mode, subactive mode entered timer timer timer timer asynchronous counter, SCI3-1, SCI3-2, IRQ4 IRQ0, WKP7 WKP0 interrupt requested. transition subactive mode does take place particular interrupt disabled interrupt enable register. 5.6.2 Clearing Subactive Mode
Subactive mode cleared SLEEP instruction input pin. Clearing SLEEP instruction SLEEP instruction executed while SSBY SYSCR1 TMA3 subactive mode cleared watch mode entered. SLEEP instruction executed while SSBY LSON SYSCR1 TMA3 TMA, subsleep mode entered. Direct transfer active mode also possible; 5.8, Direct Transfer, below. Clearing Clearing same standby mode; Clearing 5.3.2, Clearing Standby Mode. 5.6.3 Operating Frequency Subactive Mode
operating frequency subactive mode bits SYSCR2. choices
5.7.1
Active (Medium-Speed) Mode
Transition Active (Medium-Speed) Mode
driven low, active (medium-speed) mode entered. LSON SYSCR2 while LSON SYSCR1 cleared transition active (medium-speed) mode results from IRQ0, IRQ1 WKP7 WKP0 interrupts standby mode, timer timer timer IRQ0 WKP0 interrupts watch mode, interrupt sleep mode. transition active (medium-speed) mode does take place particular interrupt disabled interrupt enable register. Furthermore, sometimes acts with half state early timing time transition active (medium-speed) mode. 5.7.2 Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode cleared SLEEP instruction. Clearing SLEEP instruction transition standby mode takes place SLEEP instruction executed while SSBY SYSCR1 LSON SYSCR1 cleared TMA3 cleared system goes watch mode SSBY SYSCR1 TMA3 when SLEEP instruction executed. When both SSBY LSON cleared SYSCR1 SLEEP instruction executed, sleep mode entered. Direct transfer active (high-speed) mode subactive mode also possible. 5.8, Direct Transfer, below details. Clearing When driven low, transition made reset state active (medium-speed) mode cleared. 5.7.3 Operating Frequency Active (Medium-Speed) Mode
Operation active (medium-speed) mode clocked frequency designated bits SYSCR1.
5.
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