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Hitachi Single-Chip Microcomputer
H8/3318
H8/3318
HD6473318, HD6433318
Hardware Manual
ADE-602-097A Rev. 3/6/03 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8/3318 comprises high-performance microcontrollers with fast H8/300 core on-chip supporting functions optimized embedded control. These include ROM, RAM, three types timers, programmable timing pattern controller, data transfer unit (with 256-byte DPRAM function), parallel buffer interface, serial communication interface, converter, ports, other functions needed control system configurations, that compact, highperformance systems implemented easily. H8/3318 includes H8/3318, with 60kbyte 4-kbyte RAM. ZTAT(Zero Turn Around Time) version H8/3318 also available, with userprogrammable PROM, providing quick flexible response under sorts production conditions, even applications with frequently-changing specifications. This manual describes hardware H8/3318. Refer H8/300 Series Programming Manual detailed description instruction set.
Contents
Section
Overview Overview Block Diagram. Assignments Functions. 1.3.1 Arrangement 1.3.2 Assignments Each Operating Mode 1.3.3 Functions.
Section
CPU. Overview 2.1.1 Features 2.1.2 Address Space 2.1.3 Register Configuration Register Descriptions. 2.2.1 General Registers 2.2.2 Control Registers. 2.2.3 Initial Register Values Data Formats 2.3.1 Data Formats General Registers. 2.3.2 Memory Data Formats Addressing Modes. 2.4.1 Addressing Mode 2.4.2 Calculation Effective Address Instruction 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations 2.5.5 Manipulations. 2.5.6 Branching Instructions 2.5.7 System Control Instructions. 2.5.8 Block Data Transfer Instruction. States. 2.6.1 Overview 2.6.2 Program Execution State 2.6.3 Exception-Handling State. 2.6.4 Power-Down State Access Timing Cycle. 2.7.1 Access On-Chip Memory (RAM ROM).
2.7.2
Access On-Chip Register Field External Devices.
Section
Operating Modes Address Space.
Overview 3.1.1 Mode Selection. 3.1.2 Mode System Control Registers System Control Register (SYSCR) Mode Control Register (MDCR). Address Space Each Operating Mode.
Section
Exception Handling
Overview Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Disabling Interrupts after Reset Interrupts 4.3.1 Overview 4.3.2 Interrupt-Related Registers 4.3.3 External Interrupts. 4.3.4 Internal Interrupts. 4.3.5 Interrupt Handling 4.3.6 Interrupt Response Time 4.3.7 Precaution. Note Stack Handling.
Section
Data Transfer Unit
Overview 5.1.1 Features 5.1.2 Block Diagram 5.1.3 Input Output Pins. 5.1.4 Register Configuration Register Descriptions. 5.2.1 Control Register (IOCR). 5.2.2 Data Transfer Control Registers (DTCRA, DTCRB, DTCRC). 5.2.3 Data Transfer Address Register (DTARH) 5.2.4 Data Transfer Address Registers (DTARA, DTARB, DTARC) 5.2.5 Reload Address Registers (RLARA, RLARB, RLARC). 5.2.6 Compare Address Register (CPARB) 5.2.7 Serial/Timer Control Register (STCR) 5.2.8 DPRAM Data Registers (DPDRWH, DPDRWL, DPDRRH, DPDRRL) 5.2.9 DPRAM Data Register Read Query (DPDRRQ). 5.2.10 Parallel Communication Control/Status Register (PCCSR)
5.2.11 System Control Register (SYSCR) Operation 5.3.1 Operation. 5.3.2 Initialization 5.3.3 Transfer Operations 5.3.4 Buffer Query DPRAM Mode. 5.3.5 Operation DPRAM Bound Buffer Mode 5.3.6 Operation DPRAM Direct Word Mode 5.3.7 Operation Handshake Mode. Application Notes. 5.4.1 Processing Time
Section
Wait-State Controller Overview 6.1.1 Features 6.1.2 Block Diagram 6.1.3 Input/Output Pins 6.1.4 Register Configuration Register Description 6.2.1 Wait-State Control Register (WSCR) Wait Modes Clock Pulse Generator
Overview 7.1.1 Block Diagram 7.1.2 Wait-State Control Register (WSCR) Oscillator Circuit 7.2.1 Connecting External Crystal 7.2.2 Input External Clock Signal. Duty Adjustment Circuit Prescaler
Section
Section
Ports Overview Port 8.2.1 Overview 8.2.2 Register Configuration Descriptions 8.2.3 Functions Each Mode 8.2.4 Input Pull-Up Transistors. Port 8.3.1 Overview 8.3.2 Register Configuration Descriptions 8.3.3 Functions Each Mode
8.3.4 Input Pull-Up Transistors. Port 8.4.1 Overview 8.4.2 Register Configuration Descriptions 8.4.3 Functions Each Mode 8.4.4 Input Pull-Up Transistors. Port 8.5.1 Overview 8.5.2 Register Configuration Descriptions 8.5.3 Functions Each Mode Port 8.6.1 Overview 8.6.2 Register Configuration Descriptions 8.6.3 Functions Each Mode Port 8.7.1 Overview 8.7.2 Register Configuration Descriptions 8.7.3 Functions Each Mode. Port 8.8.1 Overview 8.8.2 Register Configuration Descriptions Port 8.9.1 Overview 8.9.2 Register Configuration Descriptions 8.9.3 Functions Each Mode 8.10 Port 8.10.1 Overview 8.10.2 Register Configuration Descriptions 8.10.3 Functions Each Mode 8.11 Application Notes. 8.11.1 Processing when Ports Used
Section
16-Bit Free-Running Timer Overview 9.1.1 Features 9.1.2 Block Diagram 9.1.3 Input Output Pins. 9.1.4 Register Configuration Register Descriptions. 9.2.1 Free-Running Counter (FRC). 9.2.2 Output Compare Registers (OCRA OCRB) 9.2.3 Input Capture Registers (ICRA ICRD) 9.2.4 Timer Interrupt Enable Register (TIER)
9.2.5 Timer Control/Status Register (TCSR) 9.2.6 Timer Control Register (TCR) 9.2.7 Timer Output Compare Control Register (TOCR) Interface Operation 9.4.1 Incrementation Timing 9.4.2 Output Compare Timing 9.4.3 Clear Timing. 9.4.4 Input Capture Timing. 9.4.5 Timing Input Capture Flag (ICF) Setting 9.4.6 Setting Output Compare Flags (OCFA OCFB) 9.4.7 Setting Overflow Flag (OVF) Interrupts Sample Application Application Notes.
Section 16-Bit Free-Running Timer
10.1 Overview 10.1.1 Features 10.1.2 Block Diagram 10.1.3 Input Output Pins. 10.1.4 Register Configuration 10.2 Register Descriptions. 10.2.1 Free-Running Counter (FRC). 10.2.2 Output Compare Registers (OCRA OCRB) 10.2.3 Input Capture Register (ICR) 10.2.4 Timer Control Register (TCR) 10.2.5 Timer Control/Status Register (TCSR) 10.3 Interface 10.4 Operation 10.4.1 Incrementation Timing 10.4.2 Output Compare Timing 10.4.3 Clear Timing. 10.4.4 Input Capture Timing. 10.4.5 Timing Input Capture Flag (ICF) Setting 10.4.6 Setting Overflow Flag (OVF) 10.5 Interrupts 10.6 Sample Application 10.7 Application Notes.
Section 8-Bit Timers
11.1 Overview 11.1.1 Features
11.2
11.3
11.4 11.5 11.6
11.1.2 Block Diagram 11.1.3 Input Output Pins. 11.1.4 Register Configuration Register Descriptions. 11.2.1 Timer Counter (TCNT) 11.2.2 Time Constant Registers (TCORA TCORB) 11.2.3 Timer Control Register (TCR) 11.2.4 Timer Control/Status Register (TCSR) 11.2.5 Serial/Timer Control Register (STCR) Operation 11.3.1 TCNT Incrementation Timing 11.3.2 Compare-Match Timing. 11.3.3 External Reset TCNT. 11.3.4 Setting TCSR Overflow Flag (OVF) Interrupts Sample Application Application Notes. 11.6.1 Contention between TCNT Write Clear. 11.6.2 Contention between TCNT Write Increment 11.6.3 Contention between TCOR Write Compare-Match 11.6.4 Contention between Compare-Match Compare-Match 11.6.5 Incrementation Caused Changing Internal Clock Source.
Section Programmable Timing Pattern Controller.
12.1 Overview 12.1.1 Features 12.1.2 Block Diagram 12.1.3 Pins. 12.1.4 Registers. 12.2 Register Descriptions. 12.2.1 Port Data Direction Register (P1DDR). 12.2.2 Port Data Register (P1DR) 12.2.3 Port Data Direction Register (P2DDR). 12.2.4 Port Data Register (P2DR) 12.2.5 Next Data Register (NDRA) 12.2.6 Next Data Register (NDRB). 12.2.7 Next Data Enable Register (NDER1) 12.2.8 Next Data Enable Register (NDER2) 12.2.9 Output Control Register (TPCR) 12.2.10 Output Mode Register (TPMR) 12.3 Operation 12.3.1 Overview 12.3.2 Output Timing
12.3.3 Normal Output 12.3.4 Non-Overlapping Output 12.4 Application Notes. 12.4.1 Operation Output Pins 12.4.2 Note Non-Overlapping Output.
Section Watchdog Timer
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Register Configuration 13.2 Register Descriptions. 13.2.1 Timer Counter (TCNT) 13.2.2 Timer Control/Status Register (TCSR) 13.2.3 Register Access 13.3 Operation 13.3.1 Watchdog Timer Mode 13.3.2 Interval Timer Mode 13.3.3 Setting Overflow Flag 13.4 Application Notes. 13.4.1 Contention between TCNT Write Increment 13.4.2 Changing Clock Select Bits (CKS2 CKS0) 13.4.3 Recovery from Software Standby Mode
Section Serial Communication Interface
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Input Output Pins. 14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Receive Shift Register (RSR). 14.2.2 Receive Data Register (RDR) 14.2.3 Transmit Shift Register (TSR) 14.2.4 Transmit Data Register (TDR). 14.2.5 Serial Mode Register (SMR). 14.2.6 Serial Control Register (SCR). 14.2.7 Serial Status Register (SSR). 14.2.8 Rate Register (BRR). 14.2.9 Serial/Timer Control Register (STCR) 14.2.10 Serial Communication Mode Register (SCMR) 14.3 Operation 14.3.1 Overview
14.3.2 Asynchronous Mode 14.3.3 Synchronous Mode. 14.4 Interrupts 14.5 Application Notes.
Section Converter
15.1 Overview 15.1.1 Features 15.1.2 Block Diagram 15.1.3 Input Pins 15.1.4 Register Configuration 15.2 Register Descriptions. 15.2.1 Data Registers (ADDRA ADDRD) 15.2.2 Control/Status Register (ADCSR) 15.2.3 Control Register (ADCR). 15.3 Interface 15.4 Operation 15.4.1 Single Mode (SCAN 15.4.2 Scan Mode (SCAN 15.4.3 Input Sampling Conversion Time 15.4.4 External Trigger Input Timing 15.5 Interrupts 15.6 Usage Notes.
Section
16.1 Overview 16.1.1 Block Diagram 16.1.2 Enable (RAME) System Control Register (SYSCR). 16.2 Operation 16.2.1 Expanded Modes (Modes 16.2.2 Single-Chip Mode (Mode 16.3 Application Notes. 16.3.1 Note Initial Values
Section
17.1 Overview 17.1.1 Block Diagram 17.2 PROM Mode (H8/3318). 17.2.1 PROM Mode Setup 17.2.2 Socket Adapter Assignments Memory 17.3 Programming. 17.3.1 Programming Verification. 17.3.2 Notes Programming.
viii
17.3.3 Reliability Programmed Data 17.3.4 Erasing Data 17.4 Handling Windowed Packages 17.4.1 Glass Erasing Window. 17.4.2 Handling after Programming 17.4.3 84-Pin Package
Section Power-Down State
18.1 Overview 18.1.1 System Control Register (SYSCR) 18.2 Sleep Mode. 18.2.1 Transition Sleep Mode 18.2.2 Exit from Sleep Mode 18.3 Software Standby Mode 18.3.1 Transition Software Standby Mode 18.3.2 Exit from Software Standby Mode. 18.3.3 Clock Settling Time Exit from Software Standby Mode 18.3.4 Sample Application Software Standby Mode. 18.3.5 Application Note 18.4 Hardware Standby Mode. 18.4.1 Transition Hardware Standby Mode 18.4.2 Recovery from Hardware Standby Mode. 18.4.3 Timing Relationships
Section Electrical Specifications
19.1 Absolute Maximum Ratings. 19.2 Electrical Characteristics. 19.2.1 Characteristics 19.2.2 Characteristics 19.2.3 Converter Characteristics 19.3 Operational Timing 19.3.1 Timing. 19.3.2 Control Signal Timing 19.3.3 16-Bit Free-Running Timer Timing. 19.3.4 8-Bit Timer Timing 19.3.5 Serial Communication Interface Timing. 19.3.6 Port Timing 19.3.7 Timing Pattern Controller Timing 19.3.8 DPRAM Timing. 19.3.9 External Clock Output Timing.
Appendix Instruction
Instruction List
Operation Code Number States Required Execution.
Appendix Register Field.
Register Addresses Names Register Descriptions.
Appendix Port Block Diagrams
Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagram. Port Block Diagrams Port Block Diagrams
Appendix States.
Port States Each Mode
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode Product Code Lineup.
Appendix Package Dimensions
Revisions Additions this Edition
Page Item H8/3315 deleted Table Assignments Each Operating Mode Table Functions 3.1.1 Mode Selection Figure H8/3318 Address Space Section Data Transfer Unit 6.2.1 Wait-State Control Register (WSCR) Amended Operating mode control amended Description added Mode amended Totally amended initial value Read/Write specification amended initial value Read/Write specification amended Amended Added Amended Amended Amended Notes added amended Amended Description added Description added Totally amended Revision
7.1.2 Wait-State Control Register (WSCR)
Figure 8.20 Functions Mode (Port 8.11 Application Notes Figure Timing Output Compare Figure 10.5 Timing Output Compare Figure 12.5 Normal Output Example (Five-Phase Pulse Output) 13.2.2 Timer Control/Status Register (TCSR) Figure 14.1 Block Diagram Serial Communication Interface 14.2.7 Serial Status Register (SSR), 14.2.7 Serial Status Register (SSR),
Table 14.3 Examples Settings Asynchronous Mode (When Table 14.6 Examples Settings Synchronous Mode (When Figure 14.5 Sample Flowchart Transmitting Serial Data Figure 14.8 Example Receive Operation (8-Bit Data with Parity Stop Bit) Figure 14.11 Example Receive Operation (Eight-Bit Data with Multiprocessor Stop Bit)
Description added Amended Amended
Page
Item Figure 14.16 Example Receive Operation Figure 14.17 Sample Flowchart Serial Transmitting Receiving
Revision Amended Note added Totally amended Added Amended, note added Amended Amended Amended Description added Amended Amended Amended Amended Added Amended
15.6 Usage Notes 16.3 Application Notes Figure 17.6 Recommended Screening Procedure Table 19.8 Control Signal Timing Figure 19.5 Basic Cycle (with Wait State) Expanded Modes (Modes Figure 19.23 Receive Timing Handshake Mode Register Descriptions SSR-Serial Status Register Register Descriptions WSCR-Wait-State Control Register Register Descriptions DTCRB-Data Transfer Control Register Register Descriptions DTCRC-Data Transfer Control Register Figure Port Block Diagram (Pin P97) Appendix Product Code Lineup
Appendix Package Dimensions
Section Overview
Overview
H8/3318 consists single-chip microcomputer units (MCUs) featuring H8/300 core complement on-chip supporting modules implementing variety system functions. H8/300 high-speed processor with architecture featuring powerful bitmanipulation instructions, ideally suited realtime control applications. on-chip supporting modules implement peripheral functions needed system configurations. These include ROM, RAM, three types timers (16-bit free-running timers, 8-bit timers, watchdog timer), programmable timing pattern controller (TPC), data transfer unit (DTU) with parallel buffer interface (PBI) supporting 256-byte DPRAM function, serial communication interface (SCI), converter, ports. H8/3318 operate single-chip mode expanded modes, depending requirements application. H8/3318 available masked version, ZTAT* version with electrically programmable that programmed user site. Note: ZTAT trademark Hitachi, Ltd. Table lists features H8/3318
Table
Item
Features
Description Two-way general register configuration Eight 16-bit registers, Sixteen 8-bit registers
High-speed operation Maximum clock rate: MHz/5 MHz/4 MHz/3 clock) Add/subtract: operation), operation), operation) Multiply/divide: operation), 1167 operation), 1400 operation)
Streamlined, concise instruction Memory Data transfer unit (DTU) channels) 16-bit freerunning timer channels) Instruction length: bytes Register-register arithmetic logic operations instruction data transfer between registers memory
Instruction features Multiply instruction bits bits) Divide instruction bits bits) Bit-accumulator instructions Register-indirect specification positions 60-kbyte 4-kbyte channel transfer (single address) channel transfer (dual address) channels either transfer 16-bit free-running counter channel (can also count external events) output-compare lines channel Channel four input capture lines (can buffered) Channel input capture line
Table
Item 8-bit timer channels)
Features (cont)
Description Each channel 8-bit up-counter (can also count external events) time constant registers Maximum 16-bit pulse output, using time base four 4-bit pulse output groups 16-bit group, 8-bit groups) Non-overlap mode available Output data transferred Overflow interrupt reset chip Also usable interval timer Asynchronous synchronous mode (selectable) Full duplex: transmit receive simultaneously On-chip baud rate generator 10-bit resolution Eight channels: single scan mode (selectable) Start conversion externally triggered Sample-and-hold function input/output lines which drive LEDs) Eight input-only lines Nine external interrupt lines: NMI, IRQ0 IRQ7 on-chip interrupt sources Expanded mode with on-chip disabled (mode Expanded mode with on-chip enabled (mode Single-chip mode (mode Sleep mode Software standby mode Hardware standby mode On-chip oscillator
Programmable timing pattern controller (TPC)
Watchdog timer (WDT) channel) Serial communication interface (SCI) channels) converter
ports
Interrupts
Operating modes
Power-down modes
Other features
Table
Item Series lineup
Features (cont)
Description
Model Version MHz) Version MHz) HD6473318CG16 HD6473318CP16 HD6473318F16 HD6473318TF16 H8/3318 HD6433318CP16 HD6433318CP12 HD6433318F16 HD6433318F12 HD6433318TF16 HD6433318TF12
Product Name H8/3318 ZTAT
Version MHz) HD6473318CG16 HD6473318CP16 HD6473318F16 HD6473318TF16
Package 84-pin windowed (CG-84) 84-pin PLCC (CP-84) 80-pin (FP-80A) 80-pin TQFP (TFP-80C)
PROM
HD6433318VCP10 84-pin PLCC (CP-84) HD6433318VF10 HD6433318VTF10 80-pin (FP-80A) 80-pin TQFP (TFP-80C)
Mask
Block Diagram
Figure shows block diagram H8/3318.
XTAL EXTAL STBY Clock pulse generator H8/300
Data (high)
P10/A0/TP0 P11/A1/TP1 P12/A2/TP2 P13/A3/TP3 P14/A4/TP4 P15/A5/TP5 P16/A6/TP6 P17/A7/TP7 P20/A8/TP8 P21/A9/TP9 P22/A10/TP10 P23/A11/TP11 P24/A12/TP12 P25/A13/TP13 P26/A14/TP14 P27/A15/TP15 P60/FTCI/ETMCI0 P61/FTOA0 P62/FTIA/FTI P63/FTIB/ETMRI0 P64/FTIC/ETMO0 P65/FTID/ETMCI1 P66/FTOB0/IRQ6/ETMRI1 P67/IRQ7/ETMO1
Data (low) Port
Address
P90/ADTRG/IRQ2 P91/IRQ1/XCS P92/IRQ0 P93/RD/CS P94/WR/OE P95/AS/RDY P97/WAIT/WE P30/D0/DDB0 P31/D1/DDB1 P32/D2/DDB2 P33/D3/DDB3 P34/D4/DDB4 P35/D5/DDB5 P36/D6/DDB6 P37/D7/DDB7 P80/RS0 P81/RS1 P82/RS2 P83/WRQ/XRDY P84/TxD1/IRQ3/XWE P85/RxD1/IRQ4 P86/SCK1/IRQ5/XOE
Watchdog timer Port Timing pattern controller 16-bit free-running timer channels)
Data transfer unit, DPRAM function Serial communication interface channels) 10-bit converter channels) Port Port P50/TxD0 P51/RxD0 P52/SCK0 Port
Port
8-bit timer channels)
Port P40/TMCI0/XDDB0 P41/TMO0/XDDB1 P42/TMRI0/XDDB2 P43/TMCI1/XDDB3 P44/TMO1/XDDB4 P45/TMRI1/XDDB5 P46/FTOA1/XDDB6 P47/FTOB1/XDDB7
Port P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVSS
Note: CP-84 CG-84 only.
Figure Block Diagram
Port
1.3.1
Assignments Functions
Arrangement
Figure shows arrangement CP-84 CG-84 packages. Figure shows arrangement FP-80A TFP-80C packages.
P86/SCK1/IRQ5/XOE P85/RxD1/IRQ4 P84/TxD1/IRQ3/XWE P83/WRQ/XRDY P82/RS2 P81/RS1 P80/RS0 P37/D7/DDB7 P36/D6/DDB6 P35/D5/DDB5 P34/D4/DDB4 P33/D3/DDB3 P32/D2/DDB2 P31/D1/DDB1 P30/D0/DDB0 P10/A0/TP0 P11/A1/TP1 P12/A2/TP2 P13/A3/TP3
XTAL EXTAL STBY P52/SCK0 P51/RxD0 P50/TxD0 P97/WAIT/WE P95/AS/RDY P94/WR/OE P93/RD/CS P92/IRQ0 P91/IRQ1/XCS P90/ADTRG/IRQ2
P14/A4/TP4 P15/A5/TP5 P16/A6/TP6 P17/A7/TP7 P20/A8/TP8 P21/A9/TP9 P22/A10/TP10 P23/A11/TP11 P24/A12/TP12 P25/A13/TP13 P26/A14/TP14 P27/A15/TP15 P47/FTOB1/XDDB7 P46/FTOA1/XDDB6 P45/TMRI1/XDDB5 P44/TMO1/XDDB4 P43/TMCI1/XDDB3 P42/TMRI0/XDDB2
Figure Arrangement (CP-84 CG-84, View)
P60/FTCI/ETMCI0 P61/FTOA0 P62/FTIA/FTI P63/FTIB/ETMRI0 P64/FTIC/ETMO0 P65/FTID/ETMCI1 P66/FTOB0/IRQ6/ETMRI1 P67/IRQ7/ETMO1 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0/XDDB0 P41/TMO0/XDDB1
XTAL EXTAL STBY P52/SCK0 P51/RxD0 P50/TxD0 P97/WAIT/WE P95/AS/RDY P94/WR/OE P93/RD/CS P92/IRQ0 P91/IRQ1/XCS P90/ADTRG/IRQ2
P86/SCK1/IRQ5/XOE P85/RxD1/IRQ4 P84/TxD1/IRQ3/XWE P83/WRQ/XRDY P82/RS2 P81/RS1 P80/RS0 P37/D7/DDB7 P36/D6/DDB6 P35/D5/DDB5 P34/D4/DDB4 P33/D3/DDB3 P32/D2/DDB2 P31/D1/DDB1 P30/D0/DDB0 P10/A0/TP0 P11/A1/TP1 P12/A2/TP2 P13/A3/TP3
P14/A4/TP4 P15/A5/TP5 P16/A6/TP6 P17/A7/TP7 P20/A8/TP8 P21/A9/TP9 P22/A10/TP10 P23/A11/TP11 P24/A12/TP12 P25/A13/TP13 P26/A14/TP14 P27/A15/TP15 P47/FTOB1/XDDB7 P46/FTOA1/XDDB6 P45/TMRI1/XDDB5 P44/TMO1/XDDB4 P43/TMCI1/XDDB3 P42/TMRI0/XDDB2
Figure Arrangement (FP-80A TFP-80C, View)
P60/FTCI/ETMCI0 P61/FTOA0 P62/FTIA/FTI P63/FTIB/ETMRI0 P64/FTIC/ETMO0 P65/FTID/ETMCI1 P66/FTOB0/IRQ6/ETMRI1 P67/IRQ7/ETMO1 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0/XDDB0 P41/TMO0/XDDB1
1.3.2
Assignments Each Operating Mode
Table lists assignments pins CP-84, CG-84, FP-80A, TFP-80C packages each operating mode. Table Assignments Each Operating Mode
Expanded Modes CP-84 CG-84 FP-80A Enabled TFP-80C (DPME P85/RxD1/ IRQ4 XTAL EXTAL STBY P52/SCK0 Mode Disabled (DPME Mode Disabled (DPME P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 XTAL EXTAL STBY P52/SCK0 Single-Chip Mode Mode Disabled (DPME P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 XTAL EXTAL STBY P52/SCK0 Enabled (DPME DDB6 DDB7 P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 XTAL EXTAL STBY P52/SCK0 PROM Mode
WRQ/XRDY P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 XTAL EXTAL STBY P52/SCK0
Note: Pins marked should left unconnected. details PROM mode, refer 17.2, PROM Mode.
Table
Assignments Each Operating Mode (cont)
Expanded Modes Single-Chip Mode Mode Disabled (DPME P51/RxD0 P50/TxD0 WAIT P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI P61/FTOA0 P62/FTIA/ P63/FTIB P64/FTIC P65/FTID P66/FTOB0/ IRQ6 P67/IRQ7 Mode Disabled (DPME P51/RxD0 P50/TxD0 P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI P61/FTOA0 P62/FTIA/ P63/FTIB P64/FTIC P65/FTID P66/FTOB0/ IRQ6 P67/IRQ7 Enabled (DPME P51/RxD0 P50/TxD0 P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI P61/FTOA0 P62/FTIA/ P63/FTIB P64/FTIC P65/FTID P66/FTOB0/ IRQ6 P67/IRQ7 PROM Mode EA15 EA16
CP-84 CG-84 FP-80A Enabled TFP-80C (DPME P51/RxD0 P50/TxD0 WAIT P92/IRQ0 P90/IRQ2/ ADTRG
Mode Disabled (DPME P51/RxD0 P50/TxD0 WAIT P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG
P60/ETMCI0/ P60/FTCI FTCI P61/FTOA0 P62/FTIA/ P61/FTOA0 P62/FTIA/
P63/ETMRI0/ P63/FTIB FTIB P64/ETMO0/ FTIC P64/FTIC
P65/ETMCI1/ P65/FTID FTID P66/ETMRI1/ P66/FTOB0/ FTOB0/IRQ6 IRQ6 P67/ETMO1/ IRQ7 P67/IRQ7
Note: Pins marked should left unconnected. details PROM mode, refer 17.2, PROM Mode.
Table
Assignments Each Operating Mode (cont)
Expanded Modes Single-Chip Mode Mode Disabled (DPME AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 P27/A /TP15 P26/A /TP14 P25/A /TP13 P24/A /TP12 P23/A /TP11 Mode Disabled (DPME AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 P27/TP15 P26/TP14 P25/TP13 P24/TP12 P23/TP11 Enabled (DPME AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 P27/TP15 P26/TP14 P25/TP13 P24/TP12 P23/TP11 PROM Mode EA14 EA13 EA12 EA11
CP-84 CG-84 FP-80A Enabled TFP-80C (DPME AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS XDDB0 XDDB1 XDDB2 XDDB3 XDDB4 XDDB5 XDDB6 XDDB7
Mode Disabled (DPME AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1
Note: Pins marked should left unconnected. details PROM mode, refer 17.2, PROM Mode.
Table
Assignments Each Operating Mode (cont)
Expanded Modes Single-Chip Mode Mode Disabled (DPME P22/A /TP10 P21/A 9/TP9 P20/A 8/TP8 P17/A 7/TP7 P16/A 6/TP6 P15/A 5/TP5 P14/A 4/TP4 P13/A 3/TP3 P12/A 2/TP2 P11/A 1/TP1 P10/A 0/TP0 Mode Disabled (DPME P22/TP10 P21/TP9 P20/TP8 P17/TP7 P16/TP6 P15/TP5 P14/TP4 P13/TP3 P12/TP2 P11/TP1 P10/TP0 Enabled (DPME P22/TP10 P21/TP9 P20/TP8 P17/TP7 P16/TP6 P15/TP5 P14/TP4 P13/TP3 P12/TP2 P11/TP1 P10/TP0 DDB0 DDB1 DDB2 DDB3 DDB4 DDB5 PROM Mode EA10
CP-84 CG-84 FP-80A Enabled TFP-80C (DPME
Mode Disabled (DPME
Note: Pins marked should left unconnected. details PROM mode, refer 17.2, PROM Mode.
1.3.3
Functions
Table gives description function each pin. Table Functions
Type Power Symbol CP-84 CG-84 FP-80A TFP-80C Name Function Power: Connected power supply. Connect both pins system power supply. Ground: Connected ground Connect pins system ground Crystal: Connected crystal oscillator. crystal frequency should same desired system clock frequency. When external clock input from EXTAL pin, inverse-phase clock should input XTAL pin. External crystal: Connected crystal oscillator external clock. frequency external clock should same desired system clock frequency. section 7.2, Oscillator Circuit, examples connections crystal external clock. System clock: Supplies system clock peripheral devices. Reset: input causes chip reset. Standby: transition hardware standby mode power-down state) occurs when input received STBY pin. Address bus: Address output pins.
Clock
XTAL
EXTAL
System control STBY
Address Data
Data bus: 8-bit bidirectional data bus.
Table
Functions (cont)
Type control
Symbol WAIT
CP-84 CG-84
FP-80A TFP-80C
Name Function Wait: Requests insert wait states into cycle when external address accessed. Read: Goes indicate that reading external address. Write: Goes indicate that writing external address. Address strobe: Goes indicate that there valid address address bus. Non-maskable interrupt: Highestpriority interrupt request. NMIEG system control register determines whether interrupt recognized rising falling edge input. Interrupt request Maskable interrupt request pins. Mode: Input pins setting operating mode according table below. These pins must changed during operation. Mode Mode Mode Description Setting prohibited Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Interrupt signals
IRQ0 IRQ7 Operating mode control MD1,
Mode
Mode
Table
Functions (cont)
Type 16-bit freerunning timer (FRT)
Symbol FTCI
CP-84 CG-84
FP-80A TFP-80C
Name Function counter clock input: Input external clock signal freerunning counter (FRC) FRT0 FRT1. output compare Output output compare FRT0 FRT1. output compare Output output compare FRT0 FRT1. input capture Input input capture FRT0, input input capture FRT1. input capture Input input capture FRT0. input capture Input input capture FRT0. input capture Input input capture FRT0. 8-bit timer output (channels Compare-match output pins 8-bit timers. 8-bit timer counter clock input (channels External clock input pins 8-bit timer counters. 8-bit timer counter reset input (channels Inputs these pins reset 8-bit timer counters. 8-bit timer output (channels Compare-match output pins 8-bit timers. 8-bit timer counter clock input (channels External clock input pins 8-bit timers. 8-bit timer counter reset input (channels Inputs these pins reset 8-bit timer counters.
FTOA0, FTOA1 FTOB0, FTOB1 FTIA, FTIB FTIC FTID 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 8-bit timer (pins used expanded modes when enabled) ETMO0, ETMO1 ETMCI0, ETMCI1 ETMRI0, ETMRI1
Table
Functions (cont)
Type
Symbol
CP-84 CG-84
FP-80A TFP-80C
Name Function output Pulse output pins.
Programmable timing pattern controller (TPC) Serial communication interface (SCI) TxD0, TxD1 RxD0, RxD1 converter ADTRG AVCC
Transmit data (channels Data output pins serial communication interface. Receive data (channels Data input pins serial communication interface. Serial clock (channels Input/output pins serial clock. Analog input: Analog signal input pins converter. trigger: External trigger input starting converter. Analog reference voltage: Reference voltage converter. converter used, connect AVCC system power supply. Refer section Electrical Specifications. Analog ground: Ground converter. Connect system ground DPRAM data bus: 8-bit bidirectional data DPRAM access external CPU. Chip select: Chip select input selecting DPRAM. Register select: Address input pins accessing DPRAM. Output enable: Output enable input reading DPRAM. Write enable: Write enable input writing DPRAM.
AVSS
Dual-port (DPRAM)
DDB7 DDB0
Table
Functions (cont)
Type Dual-port (DPRAM)
Symbol
CP-84 CG-84
FP-80A TFP-80C
Name Function Ready: Ready output sending interrupt requests external CPU. NMOS open-drain output. Wait request: Output sending wait requests external CPU. DPRAM data bus: 8-bit bidirectional data DPRAM access external CPU. Chip select: Chip select input selecting DPRAM. Register select: Address input accessing DPRAM. Output enable: Output enable input reading DPRAM. Write enable: Write enable input writing DPRAM. Ready/wait request: Output sending interrupt requests external CPU. Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P1DDR). Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P2DDR). Port 8-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P3DDR).
Dual-port (DPRAM) (pin functions expanded modes when enabled) XDDB7 XDDB0 WRQ/ XRDY ports
Table
Functions (cont)
Type ports
Symbol
CP-84 CG-84
FP-80A TFP-80C
Name Function Port 8-bit input/output port. direction each selected port data direction register (P4DDR). Port 3-bit input/output port. direction each selected port data direction register (P5DDR). Port 8-bit input/output port. direction each selected port data direction register (P6DDR). Port 8-bit input port. Port 7-bit input/output port. direction each selected port data direction register (P8DDR). Port 8-bit input/output port. direction each (except selected port data direction register (P9DDR).
Section
Overview
H8/300 fast central processing unit with eight 16-bit general registers (also configurable eight-bit registers) concise instruction designed high-speed operation. 2.1.1 Features
main features H8/300 listed below. Two-way register configuration Sixteen 8-bit general registers, Eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment pre-decrement (@Rn+ @-Rn) Absolute address (@aa:8 @aa:16) Immediate (#xx:8 #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) Maximum 64-kbyte address space High-speed operation frequently-used instructions executed four states maximum clock rate MHz/5 MHz/4 MHz/3 clock) 16-bit register-register subtract: operation), operation), operation) 8-bit multiply: operation), 1167 operation), 1400 operation) 8-bit divide: operation), 1167 operation), 1400 operation) Power-down mode SLEEP instruction
2.1.2
Address Space
H8/300 supports address space with maximum size kbytes program code data combined. memory differs depending mode (mode details, section 3.4, Address Space Each Operating Mode. 2.1.3 Register Configuration
Figure shows internal register structure H8/300 CPU. There groups registers: general registers control registers.
General registers (Rn) Control registers UHUNZ Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User (SP) Stack pointer
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used address registers, general registers accessed 16-bit registers R7). When used data registers, they accessed 16-bit registers, high bytes accessed separately 8-bit registers (R0H R7L). also functions stack pointer, used implicitly hardware processing interrupts subroutine calls. assembly-language coding, also denoted letters indicated figure 2.2, (SP) points stack.
Unused area (R7) Stack area
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. Each instruction accessed bits word), least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), half-carry flags interrupt mask (I). 7-Interrupt Mask (I): When this interrupts except masked. This automatically reset start interrupt handling.
6-User (U): This written read software (using LDC, STC, ANDC, ORC, XORC instructions). 5-Half-Carry Flag (H): This flag when ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, CMP.B instruction causes carry borrow cleared otherwise. Similarly, when ADD.W, SUB.W, CMP.W instruction causes carry borrow cleared otherwise. used implicitly instructions. 4-User (U): This written read software (using LDC, STC, ANDC, ORC, XORC instructions). 3-Negative Flag (N): This flag indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): This flag indicate zero result cleared indicate nonzero result. 1-Overflow Flag (V): This flag when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): This flag used subtract instructions, indicate carry borrow most significant result Shift rotate instructions, store value shifted most significant least significant manipulation load instructions, accumulator LDC, STC, ANDC, ORC, XORC instructions enable load store CCR, clear selected bits logic operations. flags used conditional branching instructions (Bcc). action each instruction flag bits, H8/300 Series Programming Manual. 2.2.3 Initial Register Values
When reset, program counter (PC) loaded from vector table interrupt mask other bits general registers initialized. particular, stack pointer (R7) initialized. stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300 process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand. arithmetic logic instructions except ADDS SUBS operate byte data. instructions perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data.
2.3.1
Data Formats General Registers
Data sizes above stored general registers shown figure 2.3.
Data Type Register
Data Format
1-bit data
Don't care
1-bit data
Don't care
Byte data
Don't care
Byte data
Don't care
Word data
Upper digit
Lower digit
4-bit data
Don't care
Upper digit
Lower digit
4-bit data
Don't care
Legend RnH: Upper digit general register RnL: Lower digit general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. Word data stored memory must always begin even address. word access least significant address regarded address specified, address error occurs access performed preceding even address. This rule affects MOV.W instructions branching instructions, implies that only even addresses should stored vector table.
Data Type Address Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
Note: Ignored return Legend CCR: Condition code register
Figure Memory Data Formats When stack addressed register must always accessed word time. When pushed stack, identical copies pushed make complete word. When they restored, lower byte ignored.
2.4.1
Addressing Modes
Addressing Mode
H8/300 supports eight addressing modes. Each instruction uses subset these addressing modes. Table
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Absolute address Immediate Program-counter-relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. most cases general register accessed 8-bit register. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register indirect-@Rn: register field instruction specifies 16-bit general register containing address operand. Register Indirect with Displacement-@(d:16, Rn): This mode, which used only instructions, similar register indirect instruction second word (bytes which added contents specified general register obtain operand address. MOV.W instruction, resulting address must even. Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register Indirect with Post-Increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. similar register indirect mode, 16-bit general register specified register field instruction incremented after operand accessed. size increment depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even.
Register Indirect with Pre-Decrement-@-Rn @-Rn mode used with instructions that store register contents memory. similar register indirect mode, 16-bit general register specified register field instruction decremented before operand accessed. size decrement depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. MOV.B instruction uses 8-bit absolute address form H'FFxx. upper bits assumed possible address range H'FF00 H'FFFF (65280 65535). MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. Immediate-#xx:8 #xx:16: instruction contains 8-bit operand second byte, 16-bit operand third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data (#xx:3) second fourth byte instruction, specifying number. Program-Counter-Relative-@(d:8, PC): This mode used generate branch addresses instructions. 8-bit value byte instruction code added sign-extended value program counter contents. result must even number. possible branching range -126 +128 bytes (-63 words) from current address. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address from H'0000 H'00FF 255). word located this address contains branch address. upper bits absolute address (H'00), thus branch address limited values from (H'0000 H'00FF). Note that some addresses this area also located vector table. section 3.4, Address Space Each Operating Mode, details. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. section 2.3.2, Memory Data Formats, further information.
2.4.2
Calculation Effective Address
Table shows H8/300 calculates effective addresses each addressing mode. Arithmetic, logic, shift instructions register direct addressing (1). ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, XOR.B instructions also immediate addressing (6). instruction uses addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), 8-bit absolute addressing identify byte operand, 3-bit immediate addressing identify within byte. BSET, BCLR, BNOT, BTST instructions also register direct addressing identify bit.
Table
Effective Address Calculation
Effective Address Calculation Effective Address
Addressing Mode Instruction Format Register direct,
regm regm regn
regn
Operands contained registers regm regn
Register indirect,
16-bit register contents
Register indirect with displacement, @(d:16,
16-bit register contents
disp
disp
Register indirect with post-increment, @Rn+
16-bit register contents
Register indirect with pre-decrement, @-Rn
16-bit register contents
Note: byte operand, word operand
Table
Effective Address Calculation (cont)
Effective Address Calculation Effective Address
Addressing Mode Instruction Format Absolute address @aa:8
H'FF
@aa:16
Immediate #xx:8
Operand 2-byte immediate data
#xx:16
PC-relative @(d:8,
contents
Sign extension
disp
disp
Table
Effective Address Calculation (cont)
Effective Address Calculation Effective Address
Addressing Mode Instruction Format Memory indirect, @@aa:8
H'00
Memory contents bits) Legend reg: General register Operation code disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300 types instructions, which classified function table 2.3. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer
Instruction Classification
Instructions MOV, MOVTPE* MOVFPE* PUSH* POP*
Types Total
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, conditional branch instruction which represents condition code. supported H8/3318.
following sections give concise summary instructions each category, indicate patterns their object code. notation used defined next. Operation Notation
(EAd) (EAs) #imm #xx:3 #xx:8 #xx:16 disp General register (destination) General register (source) General register Destination operand Source operand Stack pointer Program counter Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Immediate data 3-bit immediate data 8-bit immediate data 16-bit immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:8 #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes.
MOVTPE MOVFPE PUSH
supported H8/3318. supported H8/3318. @-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP.
@SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
Note: Size: Operand size Byte Word
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, Rn@-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
MOVFPE, MOVTPE
Legend Operation field Register field disp: Displacement abs: Absolute address IMM: Immediate data
POP, PUSH
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. figure section 2.5.4, Shift Operations their object codes. Table
Instruction
Arithmetic Instructions
Size* Function #imm Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #imm Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register. Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed BCD) addition subtraction result general register referring CCR. Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result.
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder.
#imm Compares data general register with data another general register with immediate data. Word data compared only between general registers.
Obtains two's complement (arithmetic complement) data general register.
Note: Size: Operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. figure section 2.5.4, Shift Operations, their object codes. Table
Instruction
Logic Operation Instructions
Size* Function #imm Performs logical operation general register another general register immediate data.
#imm Performs logical operation general register another general register immediate data.
#imm Performs logical exclusive operation general register another general register immediate data.
(Rd) (Rd) Obtains one's complement (logical complement) general register contents.
Note: Size: Operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Figure shows object code formats arithmetic, logic, shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: Size: Operand size Byte
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents. shift Performs logical shift operation general register contents. rotate Rotates general register contents. rotate through carry Rotates general register contents through (carry) bit.
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#xx:8)
AND, (Rm)
AND, (#xx:8)
Legend Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit no.> <EAd>) Sets specified general register memory specified number, given 3-bit immediate data lower three bits general register.
BCLR
(<bit no.> <EAd>) Clears specified general register memory specified number, given 3-bit immediate data lower three bits general register.
BNOT
(<bit no.> <EAd>) (<bit no.> <EAd>) Inverts specified general register memory. specified number, given 3-bit immediate data lower three bits general register
BTST
(<bit no.> <EAd>) Tests specified general register memory sets clears flag accordingly. specified number, given 3-bit immediate data lower three bits general register.
BAND BIAND
(<bit no.> <EAd>) ANDs flag with specified general register memory. (<bit no.> <EAd>)] ANDs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) flag with specified general register memory. (<bit no.> <EAd>)] flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) XORs flag with specified general register memory.
BIOR
BXOR
Note: Size: Operand size Byte
Table
Instruction BIXOR
Bit-Manipulation Instructions (cont)
Size* Function [(<bit no.> <EAd>)] XORs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) Copies specified general register memory flag. (<bit no.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit no.> <EAd>) Copies flag specified general register memory. (<bit no.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BILD
BIST
Note: Size: Operand size Byte
Notes Manipulation Instructions: BSET, BCLR, BNOT, BST, BIST readmodify-write instructions. They read byte data, modify byte, then write byte back. Care required when these instructions applied registers with write-only bits port registers.
Step Read Modify Write Description Read data byte specified address Modify data byte Write modified data byte back specified address
Example BCLR executed clear port data direction register (P4DDR) under following conditions. Input pin, Input pin, high Output pins, intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction
Input/output state Input Input High Output Output Output Output Output Output
Execution BCLR Instruction BCLR @P4DDR clear data direction register
After Execution BCLR Instruction
Input/output state Output Output High Output Output Output Output Output Input High
Explanation: execute BCLR instruction, begins reading P4DDR. Since P4DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P4DDR complete BCLR instruction. result, P40DDR cleared making input pin. addition, P47DDR P46DDR making output pins.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: register indirect (@Rn) No.:
register direct (Rm)
Operand: absolute (@aa:8) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Legend Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Legend Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches condition true. Mnemonic (BT) (BF) (BHS) (BLO) field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High same Carry clear (High same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified displacement from current address. Returns from subroutine.
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Legend Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table 2.10 describes system control instructions. Figure shows their object code formats. Table 2.10 System Control Instructions
Instruction SLEEP Size* Function Returns from exception-handling routine. Causes transition power-down state. CCR, #imm Moves immediate data general register contents condition code register. Copies condition code register specified general register. ANDC #imm Logically ANDs condition code register with immediate data. #imm Logically condition code register with immediate data. XORC #imm Logically exclusive-ORs condition code register with immediate data. Only increments program counter. Note: Size: Operand size Byte
RTE, SLEEP,
LDC, (Rn)
Legend Operation field Register field IMM: Immediate data
ANDC, ORC, XORC, (#xx:8)
Figure System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes EEPMOV instruction. Figure 2.10 shows object code format. Table 2.11 Block Data Transfer Instruction/EEPROM Write Operation
Instruction EEPMOV Size Function then repeat until else next; Moves data block according parameters general registers R4L, R4L: size block (bytes) starting source address starting destination address Execution next instruction starts soon block transfer completed. @R5+ @R6+
Legend Operation field
Figure 2.10 Block Data Transfer Instruction/EEPROM Write Operation Code
Notes EEPMOV Instruction EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
2.6.1
States
Overview
three states: program execution state, exception-handling state, power-down state. power-down state further divided into three modes: sleep mode, software standby mode, hardware standby mode. Figure 2.11 summarizes these states, figure 2.12 shows state transitions.
State
Program execution state executes successive program instructions. Exception-handling state transient state triggered reset interrupt. executes hardware sequence that includes loading program counter from vector table. Power-down state state which some chip functions stopped conserve power. Sleep mode Software standby mode Hardware standby mode
Figure 2.11 Operating States
Exception handing request Exceptionhandling state
Program execution state Exception handing Interrupt request
SLEEP instruction with SSBY SLEEP instruction
Sleep mode
NMI, IRQ0 IRQ2, IRQ6
Software standby mode
Reset state
STBY
Hardware standby mode Power-down state
Notes: transition reset state occurs when goes low, except when chip hardware standby mode. transition from state hardware standby mode occurs when STBY goes low.
Figure 2.12 State Transitions 2.6.2 Program Execution State
this state executes program instructions. 2.6.3 Exception-Handling State
exception-handling state transient state that occurs when reset interrupted changes normal processing flow. interrupt exception handling, references stack pointer (R7) saves program counter condition code register stack. further details section Exception Handling.
2.6.4
Power-Down State
power-down state includes three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: entered when SLEEP instruction executed. halts, register contents remain unchanged on-chip supporting modules continue function. Software Standby Mode: entered SLEEP instruction executed while SSBY (software standby) system control register (SYSCR) on-chip supporting modules halt. on-chip supporting modules initialized, contents on-chip registers remain unchanged long specified voltage supplied. port outputs also remain unchanged. Hardware Standby Mode: entered when input STBY goes low. chip functions halt, including port output. on-chip supporting modules initialized, onchip contents held. section Power-Down State, further information.
Access Timing Cycle
driven system clock period from rising edge system clock next referred "state." Memory access performed two- three-state cycle. On-chip memory, on-chip supporting modules, external devices accessed different cycles described below. 2.7.1 Access On-Chip Memory (RAM ROM)
On-chip accessed cycle states designated Either byte word data accessed, 16-bit data bus. Figure 2.13 shows on-chip memory access cycle. Figure 2.14 shows associated states.
cycle
state
state
Internal address
Address
Internal read signal
Internal data (read)
Read data
Internal write signal
Internal data (write)
Write data
Figure 2.13 On-Chip Memory Access Cycle
cycle
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2.14 States during On-Chip Memory Access Cycle
2.7.2
Access On-Chip Register Field External Devices
on-chip supporting module registers external devices accessed cycle consisting three states: Only byte data accessed cycle, 8-bit data bus. Access word data instruction codes requires consecutive cycles (six states). Figure 2.15 shows access cycle on-chip register field. Figure 2.16 shows associated states. Figures 2.17 show read write access timing external devices.
cycle
state Internal address Internal read signal Internal data (read) Internal write signal Internal data (write)
state
state
Address
Read data
Write data
Figure 2.15 On-Chip Register Field Access Cycle
cycle
state
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2.16 States during On-Chip Register Field Access Cycle
Read cycle
state
state
state
Address
Address
High Data
Read data
Figure 2.17 External Device Access Timing (Read)
Write cycle
state
state
state
Address
Address
High
Data
Write data
Figure 2.17 External Device Access Timing (Write)
Section Operating Modes Address Space
3.1.1
Overview
Mode Selection
H8/3318 operates three modes numbered mode selected inputs mode pins (MD1 when chip comes reset. table 3.1. Table
Mode Mode Mode Mode Mode
Operating Modes
High High High High Address Space Expanded Expanded Single-chip On-Chip Disabled Enabled Enabled On-Chip Enabled* Enabled* Enabled
Note: RAME system control register (SYSCR) cleared off-chip memory accessed instead.
Modes expanded modes that permit access off-chip memory peripheral devices. maximum address space supported these externally expanded modes kbytes. mode (single-chip mode), only on-chip on-chip register field used. ports available general-purpose input output. Mode inoperative H8/3318. Avoid setting mode pins mode addition, mode pins must changed during operation. 3.1.2 Mode System Control Registers
Table lists registers related chip's operating mode: system control register (SYSCR) mode control register (MDCR). mode control register indicates inputs mode pins Table
Name System control register Mode control register
Mode System Control Registers
Abbreviation SYSCR MDCR Read/Write Address H'FFC4 H'FFC5
System Control Register (SYSCR)
SSBY STS2 STS1 STS0 XRST NMIEG DPME RAME
Initial value Read/Write
system control register (SYSCR) 8-bit register that controls operation chip. 7-Software Standby (SSBY): Enables transition software standby mode. details, section Power-Down State. recovery from software standby mode external interrupt, SSBY remains cleared writing
SSBY Description SLEEP instruction causes transition sleep mode SLEEP instruction causes transition software standby mode (Initial value)
Bits 4-Standby Timer Select (STS2 STS0): These bits select clock settling time when chip recovers from software standby mode external interrupt. During selected time on-chip supporting modules continue stand These bits should according clock frequency that settling time least specific settings, section 18.3.3, Clock Settling Time Exit from Software Standby Mode.
STS2 STS1 STS0 Description Settling time 8,192 states Settling time 16,384 states Settling time 32,768 states Settling time 65,536 states Settling time 131,072 states Prohibited (Initial value)
3-External Reset (XRST): Indicates source reset. reset triggered external reset input, watchdog timer overflow when watchdog timer operation. XRST external reset, cleared watchdog timer overflow.
XRST Description Reset generated watchdog timer overflow Reset generated external reset input (Initial value)
2-NMI Edge (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge input interrupt requested rising edge input (Initial value)
1-Dual-Port Mode Enable (DPME): Selects whether chip into slave mode.
DPME Description chip into slave mode chip into slave mode (Initial value)
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized rising edge signal, initialized software standby mode.
RAME Description on-chip disabled on-chip enabled (Initial value)
Mode Control Register (MDCR)
MDS1 MDS0
Initial value Read/Write
Note: Initialized according inputs.
mode control register (MDCR) 8-bit register that indicates operating mode chip. Bits 5-Reserved: These bits cannot modified always read Bits 3-Reserved: These bits cannot modified always read 2-Reserved: This cannot modified always read Bits 0-Mode Select (MDS1 MDS0): These bits indicate values mode pins (MD1 MD0), thereby indicating current operating mode chip. MDS1 corresponds MDS0 MD0. These bits read written. When mode control register read, levels mode pins (MD1 latched these bits.
Address Space Each Operating Mode
Figure shows memory H8/3318 modes
Mode Expanded mode without on-chip H'0000 Vector table H'0059 H'005A H'0059 H'005A H'0000 Vector table H'0059 H'005A Mode Expanded mode with on-chip H'0000 Vector table Mode Single-chip mode
External address space
On-chip ROM, kbytes
On-chip ROM, kbytes
H'E77F H'E780 H'EF7F H'EF80 H'EF7F H'EF80
External address space
H'EF7F H'EF80
On-chip RAM*, kbyte
On-chip RAM*, kbytes
On-chip RAM, kbytes
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
H'FF7F H'FF7F H'FF80 External address space H'FF87 H'FF88 H'FF88 On-chip register field On-chip register field H'FFFF H'FFFF
Note: External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3318 Address Space
Section Exception Handling
Overview
H8/3318 recognizes only kinds exceptions: interrupts reset. Table indicates their priority timing their hardware exception-handling sequence. Table
Priority High
Hardware Exception-Handling Sequences Priority
Type Exception Reset Interrupt Detection Timing Clock synchronous completion instruction execution* Timing Exception-Handling Sequence hardware exception-handling sequence begins soon changes from high. When interrupt requested, hardware exception-handling sequence begins current instruction, current hardware exception-handling sequence.
Note: detected case ANDC, ORC, XORC, instructions.
4.2.1
Reset
Overview
reset highest exception-handling priority. When goes watchdog timer overflows (when watchdog timer reset option selected), current processing stops chip enters reset state. internal state registers on-chip supporting modules initialized. When returns from high after watchdog timer reset pulses have stopped, reset exception-handling sequence starts. 4.2.2 Reset Sequence
reset state begins when goes there watchdog timer reset. ensure correct resetting, power-on should held least reset during operation, should held least system clock cycles. Watchdog timer reset pulse widths must system clock cycles. states during reset, appendix States. When reset occurs, hardware carries following reset exception-handling sequence.
internal state registers on-chip supporting modules initialized, condition code register (CCR) loads program counter with first word vector table (stored addresses H'0000 H'0001) starts program execution. should held when power switched off, well when power switched Figure indicates timing reset sequence modes Figure indicates timing mode
Vector Internal Instruction fetch processing prefetch RES/watchdog reset (internal) Internal address Internal read signal Internal write signal Internal data bits) Reset vector address (H'0000) Starting address program First instruction program
Figure Reset Sequence (Mode Program Stored On-Chip ROM)
Vector fetch
Internal processing
Instruction prefetch
RES/watchdog reset (internal)
(high)
Figure Reset Sequence (Mode
bits)
(1), (2), (5), (6),
Reset vector address: H'0000, H'0001 Starting address program (contents reset vector): upper byte, lower byte Starting address program: (4), First instruction program: first byte, second byte
4.2.3
Disabling Interrupts after Reset
After reset, interrupt were accepted before initialization stack pointer (SP: R7), program counter condition code register might saved correctly, leading program crash. prevent this, interrupts, including NMI, disabled immediately after reset. first program instruction therefore always executed. This instruction should initialize stack pointer (example: MOV.W #xx:16, SP). confirm contents after reset exception handling, manipulation instruction executed before instruction that initializes stack pointer. interrupts, including NMI, disabled immediately after execution manipulation instruction. next instruction should instruction that initializes stack pointer.
4.3.1
Interrupts
Overview
interrupt sources include nine input pins external interrupts (NMI, IRQ0 IRQ7) internal sources on-chip supporting modules. Table lists interrupt sources priority order gives their vector addresses. When more interrupts requested, interrupt with highest priority served first. features these interrupts are: highest priority always accepted. internal external interrupts except masked CCR. When interrupts other than accepted. IRQ0 IRQ7 sensed falling edge input signal, level-sensed. type sensing selected each interrupt individually. edge-sensed, either rising falling edge selected. interrupts individually vectored. software interrupt-handling routine does have determine what type interrupt occurred. watchdog timer used generate either interrupt interrupt, needed. Refer section Watchdog Timer, details.
Table
Interrupts
Vector ICIA0 ICIB0 ICIC0 ICID0 (interrupt capture (interrupt capture (interrupt capture (interrupt capture Vector Address H'0000 H'0001 H'0002 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'0032 H'0033 H'0034 H'0035 H'0036 H'0037 H'0038 H'0039 H'003A H'003B H'003C H'003D H'003E H'003F H'0040 H'0041 Priority High
Interrupt Source Reset Reserved IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16-bit free-running timer
OCIA0 (output compare OCIB0 (output compare FOVI0 16-bit free-running timer ICI1 (overflow) (input capture)
OCIA1 (output compare OCIB1 (output compare FOVI1 (overflow)
8-bit timer
CMI0A (compare match CMI0B (compare match OVI0 (overflow)
8-bit timer
CMI1A (compare match CMI1B (compare match OVI1 (overflow) (receive error) (receive end) (TDR empty) (TSR empty)
Serial communication interface
ERI0 RXI0 TXI0 TEI0
Table
Interrupts (cont)
Vector ERI1 RXI1 TXI1 TEI1 (receive error) (receive end) (TDR empty) (TSR empty) (conversion end) (write end) (read end) (transfer (transfer (transfer (overrun error) (watchdog overflow) Vector Address H'0042 H'0043 H'0044 H'0045 H'0046 H'0047 H'0048 H'0049 H'004A H'004B H'004C H'004D H'004E H'004F H'0050 H'0051 H'0052 H'0053 H'0054 H'0055 H'0056 H'0057 H'0058 H'0059 Priority High
Interrupt Source Serial communication interface
converter Data transfer unit
MWEI MREI DTIA DTIB DTIC CMPI
Watchdog timer
Notes: Reset vectors located H'0000 H'0001. H'0002 H'0005 reserved area unavailable user.
4.3.2
Interrupt-Related Registers
interrupt-related registers system control register (SYSCR), sense control register (ISCR), enable register (IER). Table
Name System control register sense control register enable register
Registers Read Interrupt Controller
Abbreviation SYSCR ISCR Read/Write Address H'FFC4 H'FFC6 H'FFC7
System Control Register (SYSCR)
SSBY Initial value Read/Write STS2 STS1 STS0 XRST NMIEG DPME RAME
valid edge line controlled (NMIEG) system control register. 2-NMI Edge (NMIEG): Determines whether nonmaskable interrupt generated falling rising edge input signal.
NMIEG Description interrupt generated falling edge interrupt generated rising edge (Initial state)
section 3.2, System Control Register, information other SYSCR bits. Sense Control Register (ISCR)
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write
Bits 0-IRQ7 IRQ0 Sense Control (IRQ7SC IRQ0SC): These bits determine whether IRQ7 IRQ0 level-sensed sensed falling edge.
Bits IRQ7SC IRQ0SC Description interrupt generated when IRQ7 IRQ0 inputs (Initial state)
interrupt generated falling edge IRQ7 IRQ0 inputs
Enable Register (IER)
IRQ7E Initial value Read/Write IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Bits 0-IRQ7 IRQ0 Enable (IRQ7E IRQ0E): These bits enable disable IRQ7 IRQ0 interrupts individually.
Bits IRQ7E IRQ0E Description IRQ7 interrupt requests disabled IRQ7 interrupt requests enabled (Initial state)
When edge sensing selected setting bits IRQ7SC IRQ0SC possible interrupt-handling routine executed even though corresponding enable (IRQ7E IRQ0E) cleared interrupt disabled. interrupt requested while enable (IRQ7E IRQ0E) request will held pending until served. enable cleared while request still pending, request will remain pending, although requests will recognized. interrupt mask cleared interrupt-handling routine executed even though enable execution interrupt-handling routines under these conditions desired, avoided using following procedure disable clear interrupt requests. CCR, masking interrupts. Note that automatically when execution jumps interrupt vector. Clear desired bits from IRQ7E IRQ0E disable interrupt requests. Clear corresponding IRQ7SC IRQ0SC bits then them again. Pending IRQn interrupt requests cleared when CCR, IRQnSC IRQnE
4.3.3
External Interrupts
nine external interrupts IRQ0 IRQ7. NMI, IRQ2, IRQ6 used recover from software standby mode. NMI: nonmaskable interrupt generated rising falling edge input signal regardless whether (interrupt mask) CCR. valid edge selected NMIEG system control register. vector number hardware exception-handling sequence IRQ0 IRQ7: These interrupt signals level-sensed sensed falling edge input, selected ISCR bits IRQ0SC IRQ7SC. These interrupts masked collectively CCR, enabled disabled individually setting clearing bits IRQ0E IRQ7E enable register. When these interrupts accepted, IRQ0 IRQ7 have interrupt vector numbers They prioritized order from (low) IRQ0 (high). details, table 4.2. Interrupts IRQ7 depend whether pins IRQ0 IRQ7 input output pins. When using external interrupts IRQ0 IRQ7, clear corresponding bits these pins input state, these pins input output pins timers, serial communication interface, converter. 4.3.4 Internal Interrupts
Thirty-three internal interrupts requested on-chip supporting modules. Each interrupt source vector number, interrupt-handling routine does have determine which interrupt occurred. internal interrupts masked when When these interrupts accepted, mask further interrupts (except NMI). vector numbers priority order, table 4.2.
4.3.5
Interrupt Handling
Interrupts controlled interrupt controller that arbitrates between simultaneous interrupt requests, commands start hardware interrupt exception-handling sequence, furnishes necessary vector number. Figure shows block diagram interrupt controller.
interrupt IRQ0 flag IRQ0E IRQ0 interrupt Priority decision
Interrupt controller
Interrupt request
Vector number
ADIE
interrupt
(CCR)
Note: edge-sensed interrupts, these gates change circuit shown below. IRQ0 edge IRQ0E IRQ0 flag
IRQ0 interrupt
Figure Block Diagram Interrupt Controller interrupts interrupts from on-chip supporting modules have corresponding enable bits (except watchdog timer reset option). When enable cleared interrupt signal sent interrupt controller, interrupt ignored. These interrupts also masked setting CPU's interrupt mask Accordingly, these interrupts accepted only when their enable cleared
nonmaskable interrupt (NMI) always accepted, except reset state hardware standby mode. When another enabled interrupt requested, interrupt controller transfers interrupt request indicates corresponding vector number. (When more interrupts requested, interrupt controller selects vector number interrupt with highest priority.) When notified interrupt request, current instruction current hardware exception-handling sequence, starts hardware exception-handling sequence interrupt latches vector number. Figure flowchart interrupt (and reset) operations. Figure shows interrupt timing sequence case which software interrupt-handling routine on-chip stack on-chip RAM. interrupt request sent interrupt controller when interrupt occurs, when interrupt occurs input line on-chip supporting module provided enable that interrupt interrupt controller checks accepts interrupt request cleared only requests accepted; other interrupt requests remain pending. Among accepted interrupt requests, interrupt controller selects request with highest priority passes CPU. Other interrupt requests remain pending. When receives interrupt request, waits until completion current instruction hardware exception-handling sequence, then starts hardware exceptionhandling sequence interrupt latches interrupt vector number. hardware exception-handling sequence, first pushes onto stack. figure 4.5. stacked indicates address first instruction that will executed return from software interrupt-handling routine. Next masking further interrupts except NMI. vector address corresponding vector number generated, vector table entry this vector address loaded into program counter, execution branches software interrupt-handling routine address indicated that entry.
Program execution
Interrupt requested? NMI? IRQ0?
Pending
IRQ1? OVF? Latch vector
Save
Reset
Save
Read vector address
Branch software interrupt-handling routine
Figure Hardware Interrupt-Handling Sequence
(R7) Stack area
SP(R7)
CCR* (upper byte) (lower byte) Even address
Before interrupt accepted
Pushed onto stack
After interrupt accepted
Program counter CCR: Condition code register Stack pointer Notes: contains address first instruction executed after return. Registers must saved restored word access even address. Ignored return.
Figure Usage Stack Interrupt Handling Although consists only byte, treated word data when pushed stack. hardware interrupt exception-handling sequence, identical bytes pushed onto stack make complete word. When popped from stack instruction, loaded from byte stored even address. byte stored address ignored.
Interrupt accepted Interrupt priority decision. Wait Instruction Internal instruction. prefetch processing Interrupt request signal Vector fetch
Stack
Instruction prefetch (first instruction Internal interrupt-handling process- routine)
Internal address
Internal read signal Internal write signal
Internal 16-bit data
(10)
Instruction prefetch address (Pushed stack. Instruction executed return from interrupt-handling routine.) Instruction code (Not executed) Instruction prefetch address (Not executed) SP-2 SP-4 Address vector table entry Vector table entry (address first instruction interrupt-handling routine) (10) First instruction interrupt-handling routine
Figure Timing Interrupt Sequence
4.3.6
Interrupt Response Time
Table indicates number states that elapse from interrupt request signal until first instruction software interrupt-handling routine executed. Since on-chip memory accessed bits time, very fast interrupt service obtained placing interrupt-handling routines on-chip stack on-chip RAM. Table Number States before Interrupt Service
Number States Reason Wait Interrupt priority decision Wait completion current instruction* Save Fetch vector Fetch instruction Internal processing Total On-Chip Memory
External Memory
Notes: These values apply current instruction EEPMOV. wait states inserted external memory access, number wait states. internal interrupts.
4.3.7
Precaution
Note that following type contention occur interrupt handling. When software clears enable interrupt disable interrupt, interrupt becomes disabled after execution clearing instruction. enable cleared BCLR instruction, example, interrupt requested during execution that instruction, instant when instruction ends interrupt still enabled, after execution instruction, hardware exception-handling sequence executed interrupt. higher-priority interrupt requested same time, however, hardware exception-handling sequence executed higher-priority interrupt interrupt that disabled ignored. Similar considerations apply when interrupt request flag cleared Figure shows example which OCIAE cleared
write cycle TIER Internal address TIER address
OCIA interrupt handling
Internal write signal OCIAE OCFA OCIA interrupt signal
Figure Contention between Interrupt Disabling Instruction above contention does occur enable flag cleared while interrupt mask
Note Stack Handling
word access, least significant address always assumed stack always accessed word access. Care should taken keep even value stack pointer (general register R7). PUSH MOV.W @-SP MOV.W @SP+, instructions push registers stack. Setting stack pointer value cause programs crash. Figure shows example damage caused when stack pointer contains address.
H'FECC H'FECD
H'FECF
instruction
MOV.B R1L, @-R7
H'FECF
improperly stored beyond stack
lost
PCH: PCL: R1L:
Upper byte program counter Lower byte program counter General register Stack pointer
Figure Example Damage Caused Setting Address
Section Data Transfer Unit
Overview
H8/3318 Series on-chip data transfer unit (DTU) with four direct memory access (DMA) channels, on-chip 8-bit parallel buffer interface (PBI). When combined, these functions enable bytes on-chip easily accessed (read write) from outside chip. transfer, perform data transfer automatically between on-chip registers serial communication interface (SCI), 16-bit free-running timer (FRT), programmable timing pattern controller (TPC), converter (ADC), response interrupt request. transfer, implement large dual-port (DPRAM) enabling bytes on-chip accessed from external master CPU. DPRAM mode, buffer that queried read byte from specified address. While accepting buffer queries, also operate bound buffer mode, which provides sequential read/write access starting from specified address, direct word mode, which does on-chip RAM. operate handshake mode well DPRAM mode. 5.1.1 Features
Features transfer, DPRAM mode, handshake mode listed below. Transfer (Figure 5.1) three channels with transfer capability (channels perform independently. selectable types transfer are: (TDR), (RDR) RAM; (OCRA, OCRB); (NDR); (ADDRA) RAM. number bytes transferred controlled setting starting address boundary. Each channel generate independent interrupt when designated number bytes have been transferred. maximum 256-byte area used (maximum bytes channel). Data specified area transferred repeatedly designating repeat mode. Channel operate ring buffer mode (FIFO mode).
Supporting module Halted register Interrupt
Temporary data register*
Note: Different from DPDRR DPDRW
Figure Concept Transfer DPRAM Mode master access on-chip randomly buffer, using channel read (buffer query). master access on-chip sequentially pair buffers, using channel read channel write (bound buffer mode). Without using DTU, master also access buffers each channel dual-port (direct word mode). maximum 256-byte area used (maximum bytes each channel Internal interrupts generated when designated number bytes have been transferred (master read end, master write end). single-chip mode, master interrupt requests issued from pin, wait requests from pin. expanded modes, these types requests generated: master interrupt requests issued from pin, wait requests issued from pin. Buffer query operation (Figure 5.2) 1-byte address/data register available. writing on-chip address, master read byte 256-byte on-chip area.
DPRAM data register (query read) Slave Halted DDB0 DDB7
Figure Concept Buffer Queries Bound buffer mode (Figure 5.3) pairs 8-bit data registers available, read write. master these buffers transfer data from 256-byte on-chip area with wait time. number bytes transferred designated setting starting address boundary. Each channel generate internal interrupt when designated number bytes have been transferred. read operation master CPU, data transferred from addresses specified internal CPU. write operation master CPU, data transferred addresses specified master CPU.
DPRAM data register (write)
Halted DPRAM data register (read) DDB0 DDB7
Figure Concept Bound Buffer Mode
Direct word mode (Figure 5.4) pairs 8-bit data registers available, read write. These used dual-port exchange data with master CPU. Channels using bound buffer mode automatically placed direct word mode.
DPRAM data register (write) Slave DPRAM data register (read) DDB0 DDB7
Figure Concept Direct Word Mode Handshake Mode (Figure 5.5) Handshaking carried using input signals output signals. internal interrupt generated rise input (output data processing completed) rise input (input data valid). output signals used send interrupt requests data input/output requests master CPU.
reception DPRAM data register (write) Slave transmission DPRAM data register (read) DDB0 DDB7
Figure Concept Handshake Mode
5.1.2
Block Diagram
Figure shows block diagram PBI.
Internal address
request
Internal data
Internal data interface control register (IOCR) Data transfer address register (DTARH) Reload address register (RLARC)
Data transfer address register (DTARC) Data transfer control register (DTCRC) Internal address interface, incrementer, boundary decoder Reload address register (RLARB)
Data transfer address register (DTARB) Module master data
Comparator
control circuit
Compare address register (CPARB) Data transfer control register (DTCRB) Reload address register (RLARA)
Data transfer address register (DTARA) Data transfer control register (DTCRA) DPRAM data register read query (DPDRRQ) DPRAM data register write (DPDRWH) DPRAM data register write (DPDRWL) DPRAM data register read (DPDRRH) OCIB OCIA DPRAM data register read (DPDRRL) Parallel communication control/status register (PCCSR) control circuit DPRAM data interface DDB7 DDB0
Figure Block Diagram
Module data
5.1.3
Input Output Pins
Table lists input output pins. RDY, active only single-chip mode. expanded mode, XCS, XOE, XWE, XRDY, XDDB become active instead. Table
Name Chip select Register select Output enable Write enable Ready Wait request DPRAM data
Input Output Pins
Abbreviation* RDY, XRDY DDB7 XDDB7 XDDB Input Input Input Input Output Output Input/ output Function (DPRAM Mode) Selects Used master select register* Used master read register Used master write register Sends interrupt request master Sends wait request master 8-bit data providing parallel interface between master
Notes: Unless specifically noted, XCS, XOE, XWE, XRDY, XDDB will referred RDY, DDB, respectively. registers selected register select signals listed table 5.2.
5.1.4
Register Configuration
Table lists registers Table Registers
Address
Name Parallel communication control/status register (PCCSR)
control register DPRAM data register read query Data transfer address register Data transfer control register Data transfer address register Reload address register Data transfer control register Data transfer address register Reload address register Compare address register Data transfer control register Data transfer address register Reload address register DPRAM data register write DPRAM data register write DPRAM data register read DPRAM data register read Serial/timer control register System control register
Abbreviation PCCSR
Initial Value H'04
Internal H'FFF0
Description
IOCR DPDRRQ DTARH DTCRA DTARA RLARA DTCRB DTARB RLARB CPARB DTCRC DTARC RLARC DPDRWH DPDRWL DPDRRH DPDRRL STCR SYSCR
H'03 Undetermined Undetermined H'00 Undetermined Undetermined H'00 Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'1C H'09
H'FFF1 H'FFF5 H'FFF6 H'FFF7 H'FFF2 H'FFF8 H'FFF9 H'FFF3 H'FFF4 H'FFFA H'FFFB H'FFFC H'FFFD H'FFFE H'FFFF H'FFC3 H'FFC4
Note: Register read/write specifications given table 5.3, Transfer Modes Register Configuration.
Register accessibility differs depending transfer mode. Table lists register access conditions each transfer mode, table shows each transfer mode selected.
Table
Transfer Modes Register Configuration
DPRAM Mode Transfer Transfer Buffer Query* Master
Bound Buffer Mode Master Internal R/W*5 R/W*5
Direct Word Mode Master
Handshake Mode* Internal Initial Value H'04 H'03 H'00 H'00 H'00
Address Internal H'FFF0 H'FFF1 H'FFF5 H'FFF6 H'FFF7 H'FFF2 H'FFF8 H'FFF9 H'FFF3 H'FFF4 H'FFFA H'FFFB
Chan- Abbrenel viation PCCSR IOCR DPDRRQ DTARH DTCRA DTARA RLARA DTCRB DTARB RLARB CPARB DTCRC DTARC RLARC
Internal
Internal
R/W*5
DPDRWH DPDRWL DPDRRH DPDRRL
H'FFFC H'FFFD H'FFFE H'FFFF
Legend Must accessed (write access will affect operations other functions). accessed, effect operation. Cannot accessed. Undetermined Notes: Buffer queries made parallel with bound buffer mode direct word mode. DTARH IOCR used these modes, care required modifying their contents. handshake mode, master write DPDRWL. internal output DPDRRL contents master CPU. Must accessed used bound buffer mode. Cannot accessed used transfer. Must accessed used transfer.
Table
Transfer Mode Selection
Basically, transfer mode started channels time setting However, channels assigned transfer bound buffer mode, depending IOCR setting. (See table section 5.3.3.)
transfer mode
DPRAM mode Buffer queries Channel used exclusively. buffer query function operates when DPME SYSCR HSCE IOCR. (See table section 5.3.4.) Channel used reads master. This mode used when DPME (SYSCR), HSCE (IOCR), DPEA (IOCR). Channel used writes from master. This mode used when DPME (SYSCR), HSCE (IOCR), DPEB (IOCR). (See table section 5.3.5.) Channel used reads master. This mode used when DPME (SYSCR), HSCE (IOCR), DPEA (IOCR). Channel used writes from master. This mode used when DPME (SYSCR), HSCE (IOCR), DPEB (IOCR). (See table section 5.3.6.) This mode used when DPME SYSCR HSCE IOCR. (See table section 5.3.7.)
Bound buffer mode
Direct word mode
Handshake mode
Register Descriptions
registers described below. Abbreviations shown boxes after register name indicate modes which register used. meaning these abbreviations follows: I/O: H/S: transfer Buffer queries Bound buffer mode Direct word mode Handshake mode
5.2.1
Control Register (IOCR)
HSCE
DPEA
DPEB
RPEA
RPEB
RPEC
Initial value Read/Write
IOCR selects operating modes, controls DTU. 7-Parallel Handshake Enable (HSCE) Bits 5-DPRAM Enable (DPEA, DPEB) operating modes selected DPME SYSCR, HSCE, DPEA, DPEB bits IOCR. Table lists mode selections. Table lists corresponding functions. Table DTU/PBI Operating Mode Settings
Bound Buffer Mode (DTU Channel Bound Buffer Mode (DTU Channel
Buffer Query Hand- (DTU DPME shake Channel (SYSCR) HSCE DPEA DPEB Mode (read) (read) (read) (read)
Direct Word Mode (DPDRRH/L)
Direct Word Mode (DPDRWH/L) Handshake (write)
transfer* transfer* Handshake transfer* transfer* (read) (read)
transfer* Bound buffer (write) (read) Bound buffer
transfer* (write) (read) (write)
Bound buffer Bound buffer
transfer* transfer*
used Cannot used Undetermined Used transfer mode
Note: transfer, DTCRA, DTCRB, DTCRC. Handshake mode operation supported only single-chip mode. HSCE expanded modes.
Table
DPME
Functions
HSCE Mode Name CS/XCS, OE/XOE, WE/XWE Control input RDY/ XRDY Control output Control output port function, depending EWRQ (PCCSR) Port function Port function Port function Port function data DDB7 DDB0/ XDDB XDDB0 Data input/output
(SYSCR)
Handshake
mode DPRAM mode
Port
function Control input Port function
Note: "Port function" means that port functions, supporting-module functions, extended functions multiplexed with DPRAM pins available.
Bits 2-Repeat Enable (RPEA, RPEB, RPEC): These bits valid only transfers. They select repeat mode normal mode channels normal mode, DTCRA, DTCRB, DTCRC cleared when transfer reaches boundary. repeat mode, when transfer reaches boundary, DTCRA, DTCRB, DTCRC cleared data area defined DTARA, DTARB, DTARC boundary transferred repeatedly. Channels also have reload address registers, channel furthermore operate ring buffer mode. usage boundary, normal mode, repeat mode, section 5.3, Operation.
Bits RPEA, Description Transfer normal mode Transfer repeat mode (Initial value)
Bits 0-Reserved: These bits cannot modified always read
5.2.2
Data Transfer Control Registers (DTCRA, DTCRB, DTCRC)
DTIE BUD2 BUD1 BUD0 SOS2 SOS1 SOS0 Initial value Mode transfer Register DTCRA DTCRB DTCRC DTCRA Internal Read/Write
transfer DPRAM bound buffer mode
Internal Master
Read/Write Read/Write Read/Write Read/Write
(R/W)
(R/W) (R/W) (R/W)
DTCRB
Internal Master
used. Cannot modified. Always reads (R/W): written, effect operation.
These registers used transfers, transfers DPRAM bound buffer mode. transfers, DTCRA, DTCRB, DTCRC serve control registers channels respectively. transfers DPRAM bound buffer mode, DTCRA controls read access master CPU, DTCRB controls write access master CPU. 7-Data Transfer Enable (DTE): Used transfers. used transfers. When channel begins waiting transfer request. transfer activated interrupt request signal selected source select bits (SOS2, SOS1, SOS0). boundary overflow internal clears transfer suspended. DTIE interrupt also requested. internal sets again, transfer resumes from state which suspended.
Description Indicates that transfer halted [Clearing conditions] written transfer terminates boundary normal mode (Initial value)
Indicates that transfer progress [Setting condition] Read DTCR while then write
6-Data Transfer Interrupt Enable (DTIE): Used transfers. used transfers. This enables disables interrupt generated when cleared
DTIE Description Disables interrupt requested when cleared (DTI) Enables interrupt requested when cleared (DTI) (Initial value)
Bits 3-Boundary (BUD2, BUD1, BUD0): These bits carry-control boundary data transfer address register (DTAR), which register that gives lower byte on-chip address. DTAR 8-bit counter that increments each time byte word transferred. incrementing held within selected boundary. When carry occurs boundary, causing DTAR overflow, bits above boundary retain their existing values, while bits below boundary reset their initial value. initial value value stored reload register, depending channel operating mode.
BUD2 BUD1 BUD0
DTAR Overflow Timing each byte transfer Carry from DTAR Carry from DTAR Carry from DTAR Carry from DTAR Carry from DTAR Carry from DTAR Carry from DTAR
Maximum Bytes Transferred*
DTAR
Note: Number bytes transferred when bits below boundary initially cleared
Figure Settings Boundary Positions Bits 0-Source Select (SOS2, SOS1, SOS0): Used transfers, transfers. These bits select interrupt source that activates transfer DTU. When selected interrupt request signal regarded transfer request. When selected interrupt request signal sent interrupt controller. Table lists transfer activation sources transfers they request. Some transfers clear activation source while others not. using combination these types, possible perform consecutive transfer operations with single activation source. this case, transfers performed alphabetical channel order (channel then then channel channel executes transfer operation number table 5.7, activation source cleared, channel stopped. stopped channel automatically cleared completion transfer operation stoppage transfer operation completion operation operation stopped channel also cleared dummy write data transfer control register (DTCR).
Table
Selection Activation Sources Resulting Transfers
Clearing (Channel Source SOS2 SOS1 SOS0 (Channel SOS2 SOS1 SOS0 (Channel SOS2 SOS1 SOS0
Interrupt Source Module Transfer RXI0 TXI0 OCIB1 OCIA1 OCIB1 OCIA1 OCIA1 OCIA1 OCIB1 SCI0 SCI0 FRT1 FRT1 FRT1 (byte) (byte)
ADDRA (word) NDRB (word) NDRB (word) NDRA (byte) NDRA (byte)
OCRA (word) OCRA (word) OCRB (word)
Note: When SOS2 SOS1 SOS0 activation source selected.
5.2.3
Data Transfer Address Register (DTARH)
Initial value Read/Write
DTARH used whenever function used. used both transfers transfers DPRAM mode, including buffer queries transfers bound buffer mode. DTARH register that specifies upper bits on-chip address. DTARH paired with DTARA, DTARB, DTARC generate 16-bit address.
5.2.4
Data Transfer Address Registers (DTARA, DTARB, DTARC)
Initial value Mode transfer Register DTARA DTARB DTARC DTARA Internal Read/Write
transfer DPRAM bound buffer mode
Internal Master
Read/Write Read/Write Read/Write Read/Write
(R/W) (R/W) (R/W)
DTARB
Internal Master
DTAR registers used when function used transfers, transfers DPRAM bound buffer mode. DTARA, DTARB, DTARC pair with DTARH generate 16-bit on-chip addresses which indicate transfer addresses. boundary DTAR registers bits, that DTAR registers increment only range boundary. transfer, these registers used lower 8-bit address registers each channel. transfer DPRAM bound buffer mode, DTARA lower 8-bit address register read access master CPU, DTARB lower 8-bit address register write access master CPU.
5.2.5
Reload Address Registers (RLARA, RLARB, RLARC)
Initial value Read/Write
RLAR registers used when function used transfers, transfers DPRAM bound buffer mode. RLAR registers store data initializing DTAR registers when boundary overflow occurs. Writes RLAR registers performed automatically master internal writes. DTAR value then successively incremented, boundary overflow occurs, DTAR register will initialized value RLAR register. ring buffer mode, RLARB functions auxiliary ring buffer pointer. DTARB main pointer, indicating transfer address. series transfers suspended stored data becomes invalid, DTARB initialized value RLARB (loading). series transfers ends normally stored data valid, contents DTARB copied RLARB (marking). Note, however, that repeat mode value RLARB copied DTARB automatically when boundary overflow occurs. 5.2.6 Compare Address Register (CPARB)
Initial value Read/Write
CPARB auxiliary pointer used ring buffer mode. contents CPARB constantly compared with DTARB. When they match, interrupt request generated. CPARB should updated software that always indicates unprocessed data ring buffer. Then ring buffer becomes full unprocessed data, causing overrun error, CPARB DTARB will match interrupt request will occur.
5.2.7
Serial/Timer Control Register (STCR)
RING
CMPF R/(W)*
CMPIE
LOAD
MARK
ICKS1
ICKS0
Initial value Read/Write
Note: Software write clear flag, cannot write this bit.
STCR 8-bit readable/writable register that controls channel selects operating mode TCNT clock source. STCR initialized H'1C reset. 7-Ring Buffer Mode (RING): Setting this places channel ring buffer mode. ring buffer mode also necessary REPB IOCR.
RING Description channel does operate ring buffer mode channel operates ring buffer mode (Initial value)
6-Compare Interrupt Flag (CMPF): Overrun error interrupt request flag ring buffer. This flag indicates that contents CPARB DTARB match after DTARB incremented occurrence cycle.
CMPF Description [Clearing condition] Read STCR while CMPF then write CMPF Ring buffer overrun error [Setting condition] When DTARB contents match CPARB contents after being incremented cycle occurrence (Initial value)
5-Compare Interrupt Enable (CMPIE): Enables disables interrupt (CMPI) requested when CMPF
CMPIE
Description Interrupt request (CMPI) CMPF disabled Interrupt request (CMPI) CMPF enabled (Initial value)
4-Pointer Load (LOAD): Controls copying contents auxiliary pointer (RLARB) into ring buffer pointer (DTARB). There latch retain value LOAD bit. load operation executed when LOAD cleared
LOAD Cleared Description RLARB contents copied DTARB operation (Initial value)
3-Pointer Mark (MARK): Controls copying contents ring buffer pointer (DTARB) into auxiliary pointer (RLARB). There latch retain value MARK bit. mark operation executed when MARK cleared
MARK Cleared Description DTARB contents copied RLARB operation (Initial value)
2-Reserved: This cannot modified always read Bits 0-Internal Clock Source Select (ICKS1 ICKS0): These bits, together with bits CKS2 CKS0 TCR, select TCNT clock source. details section 8-Bit Timers. 5.2.8 DPRAM Data Registers (DPDRWH, DPDRWL, DPDRRH, DPDRRL)
DPRAM data registers (DPDR registers) provide four bytes, which master write bytes (DPDRW) read bytes (DPDRR). These data registers used DPRAM bound buffer mode, DPRAM direct word mode, handshake mode. They used buffer queries DPRAM mode, transfers. Read write access DPDR registers sets interrupt flags (MWEF, MREF), activates DTU, changes levels control signals (RDY, WRQ) sent master CPU. details these operations, section 5.3, Operation.
DPRAM Data Register Write (DPDRWH, DPDRWL): These data registers reserved write access master DPRAM bound buffer mode, DPRAM direct word mode, handshake mode. They used buffer queries DPRAM mode, transfers.
Initial value Mode Register Internal Master Internal Master Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
DRAM bound DPDRWH buffr mode DPDRWL DRAM direct word mode Handshake mode DPDRWH DPDRWL
DPDRWL*3 Internal Master
Notes: Transferred on-chip automatically DTU. Data lines latched rising edge input. handshake mode, master cannot access DPDRWH.
DPDRW bytes should used each mode follows. DPRAM Bound Buffer Mode DPDRWH DPDRWL reserved write access master CPU. Data written these registers transferred automatically on-chip RAM. master addresses these bytes, write access both bytes operates same way. DPRAM Direct Word Mode Read write access DPDRWL generates interrupt request internal master CPU. both bytes used, read write access should performed DPDRWH first, then DPDRWL. only byte used, DPDRWL. Handshake Mode DPDRWL.
DPRAM Data Register Read (DPDRRH, DPDRRL): These data registers reserved read access master DPRAM bound buffer mode, DPRAM direct word mode, handshake mode. They used buffer queries DPRAM mode, transfers.
Initial value Mode Register Internal Master Internal Master
DRAM bound DPDRRH buffr mode DPDRRL DRAM direct word mode Handshake mode DPDRRH DPDRRL DPDRRL*
Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Internal Master
Notes: Transferred from on-chip automatically DTU. Data output lines when input low. handshake mode, master cannot access DPDRRH.
DPDRR bytes should used each mode follows. DPRAM Bound Buffer Mode DPDRRH DPDRRL reserved read access master CPU. read data transferred automatically from on-chip RAM. master addresses these bytes, read access both bytes operates same way. DPRAM Direct Word Mode Read write access DPDRRL generates interrupt request internal master CPU. both bytes used, DPDRRH should accessed first, then DPDRRL. only byte used, DPDRRL. Handshake Mode DPDRRL.
5.2.9
DPRAM Data Register Read Query (DPDRRQ)
This register used query buffer DPRAM mode.
Initial value Internal Master Read/Write Read/Write
Note: Transferred automatically from on-chip DTU.
DPDRRQ reserved read write access master CPU. When write access DPDRRQ occurs, data stored on-chip address given DTARH (upper byte) DPDRRQ (lower byte) transferred DPDRRQ. 5.2.10 Parallel Communication Control/Status Register (PCCSR)
This register used DPRAM mode handshake mode. used transfers. PCCSR written read both internal master CPU. controls data transfer between internal master CPU, indicates status.
EMRI
QREF EWRQ Initial value Mode modes except handshake mode Handshake mode Internal Master Internal Read/Write Read/Write Read/Write
EWAKAR ERAKAR
MWEF MREF EMWI
R/(W)* R/(W)*
R/(W)* R/(W)*
Note: Only write after read available.
7-Query Read Flag (QREF): Indicates whether DPDRRQ contains on-chip address data. This flag useful buffer query operations DPRAM mode.
QREF Description DPDRRQ contains data [Clearing condition] writes on-chip data DPDRRQ DPDRRQ contains lower byte on-chip address [Setting condition] master writes lower byte on-chip address DPDRRQ (Initial value)
6-Enable Wait Request (EWRQ): Enables operation pin. 5-Enable Write Acknowledge Request (EWAKAR): Enables operation response master write access. 4-Enable Read Acknowledge Request (ERAKAR): Enables operation response master read access. Table lists states single-chip mode. Table lists states expanded modes.
Table
Condition DPME HSCE
States Single-Chip Mode with PCCSR Conditions
EWRQ EWAKAR ERAKAR P95/RDY High level output (high impedance) output enabled master write output enabled master read output enabled master write master read Depends value ERAKAR EWAKAR above output enabled output enabled Port function output enabled Port function output enabled P83/WRQ/XRDY Depends value EWRQ below
DPME HSCE
Table
Condition DPME HSCE
States Expanded Modes with PCCSR Conditions
EWRQ EWAKAR ERAKAR P95/RDY output output output output output output output P83/WRQ/XRDY High level output XRDY output enabled master write XRDY output enabled master read XRDY output enabled master write master read output enabled XRDY output enabled output enabled
DPME HSCE
Table 5.10 describes output operations. Table 5.11 describes operations. Table 5.10 Output Operations
Mode DPRAM bound buffer mode DPRAM direct word mode Handshake mode Master read Master write Master read Master write Conditions High Level Output* Master reads DTARA Master writes DTARB Master reads DPDRRL Conditions Level Output Internal clears MREF Internal clears MWEF Internal writes DP
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