Cautions Keep safety first your circuit designs! Renesas Technolo
|
|
|
Top Searches for this datasheet
Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
Hitachi Single-Chip Microcomputer H8/3217 Series H8/3217, H8/3216 H8/3214, H8/3212 H8/3202 Hardware Manual
27/2/03
Notice
When using this document, keep following mind: This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission. Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit according this document. Circuitry other examples described herein meant merely indicate characteristics performance Hitachi's semiconductor products. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples described herein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products authorized MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support systems. Buyers Hitachi's products requested notify relevant Hitachi sales offices when planning products MEDICAL APPLICATIONS.
Preface
H8/3217 Series family high-performance single-chip microcomputers ideally suited embedded control industrial equipment. chips built around H8/300 core: high-speed processor. On-chip supporting modules provide ROM, RAM, four types timers, ports, serial communication interface, interface, host interface easy implementation compact, high-speed control systems. H8/3217 Series offers selection on-chip memory. H8/3217: H8/3216: H8/3214: H8/3212: 60-kbyte ROM; 48-kbyte ROM; 32-kbyte ROM; 16-kbyte ROM; 2-kbyte 2-kbyte 1-kbyte 512-byte
H8/3217 H8/3214 chips available with electrically programmable ROM. Manufacturers electrically programmable ZTAT(Zero Turn-Around Time*) version production fast start make software changes quickly. This manual describes H8/3217 Series hardware. Refer H8/300 Series Programming Manual detailed description instruction set. Note: ZTAT trademark Hitachi, Ltd.
Contents
Section Overview
Overview Block Diagram. Assignments Functions. 1.3.1 Arrangement 1.3.2 Functions.
Section
Overview 2.1.1 Features 2.1.2 Address Space 2.1.3 Register Configuration Register Descriptions 2.2.1 General Registers 2.2.2 Control Registers. 2.2.3 Initial Register Values Data Formats 2.3.1 Data Formats General Registers. 2.3.2 Memory Data Formats Addressing Modes. 2.4.1 Addressing Modes. 2.4.2 Effective Address Calculation. Instruction 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations 2.5.5 Manipulations. 2.5.6 Branching Instructions 2.5.7 System Control Instructions. 2.5.8 Block Data Transfer Instruction. States. 2.6.1 Program Execution State 2.6.2 Exception-Handling State 2.6.3 Power-Down State Access Timing Cycle. 2.7.1 Access On-Chip Memory (RAM ROM). 2.7.2 Access On-Chip Register Field External Devices.
Section Operating Modes Address Space
Overview 3.1.1 Operating Modes 3.1.2 Mode System Control Registers. System Control Register (SYSCR) Mode Control Register (MDCR). Mode Descriptions. Address Space Maps Each Operating Mode
Section Exception Handling
Overview Reset 4.2.1 Overview 4.2.2 Reset Sequence. 4.2.3 Disabling Interrupts after Reset Interrupts 4.3.1 Overview 4.3.2 Interrupt-Related Registers 4.3.3 External Interrupts. 4.3.4 Internal Interrupts. 4.3.5 Interrupt Handling 4.3.6 Interrupt Response Time 4.3.7 Precaution. Note Stack Handling. Notes Key-Sense Interrupts
Section Wait-State Controller.
Overview 5.1.1 Features 5.1.2 Block Diagram 5.1.3 Input/Output Pins 5.1.4 Register Configuration Register Description 5.2.1 Wait-State Control Register (WSCR) Wait Modes
Section Clock Pulse Generator.
Overview 6.1.1 Block Diagram 6.1.2 Wait-State Control Register (WSCR) Oscillator Circuit Duty Adjustment Circuit Prescaler.
Section Ports.
Overview Port 7.2.1 Overview 7.2.2 Register Configuration Descriptions 7.2.3 Functions Each Mode 7.2.4 Input Pull-Ups. Port 7.3.1 Overview 7.3.2 Register Configuration Descriptions 7.3.3 Functions Each Mode 7.3.4 Input Pull-Ups. Port 7.4.1 Overview 7.4.2 Register Configuration Descriptions 7.4.3 Functions Each Mode 7.4.4 Input Pull-Up Transistors. Port 7.5.1 Overview 7.5.2 Register Configuration Descriptions 7.5.3 Functions. Port 7.6.1 Overview 7.6.2 Register Configuration Descriptions 7.6.3 Functions. Port 7.7.1 Overview 7.7.2 Register Configuration Descriptions 7.7.3 Functions. Port 7.8.1 Overview 7.8.2 Register Configuration Descriptions 7.8.3 Functions.
Section Timers
Overview 8.1.1 Features 8.1.2 Block Diagram 8.1.3 Input Output Pins. 8.1.4 Register Configuration Register Descriptions. 8.2.1 Data Registers (PWDR0 PWDR15) 8.2.2 Data Polarity Registers (PWDPRA PWDPRB)
8.2.3 Output Enable Registers (PWOERA PWOERB). 8.2.4 Port Data Direction Register (P1DDR). 8.2.5 Port Data Direction Register (P2DDR). 8.2.6 Port Data Register (P1DR) 8.2.7 Port Data Register (P2DR) 8.2.8 Serial/Timer Control Register (STCR). Operation 8.3.1 Correspondence between Data Register Contents Output Waveform.
Section 16-Bit Free-Running Timer
Overview 9.1.1 Features 9.1.2 Block Diagram 9.1.3 Input Output Pins. 9.1.4 Register Configuration Register Descriptions. 9.2.1 Free-Running Counter (FRC)-H'FF92. 9.2.2 Output Compare Registers (OCRA OCRB)-H'FF94 H'FF96. 9.2.3 Input Capture Register (ICR)-H'FF98. 9.2.4 Timer Control Register (TCR)-H'FF90. 9.2.5 Timer Control/Status Register (TCSR)-H'FF91 Interface Operation 9.4.1 Incrementation Timing 9.4.2 Output Compare Timing 9.4.3 Clear Timing. 9.4.4 Input Capture Timing. 9.4.5 Timing Input Capture Flag (ICF) Setting 9.4.6 Setting Overflow Flag (OVF) Interrupts Sample Application Application Notes.
Section 8-Bit Timers
10.1 Overview 10.1.1 Features 10.1.2 Block Diagram 10.1.3 Input Output Pins. 10.1.4 Register Configuration
10.2 Register Descriptions. 10.2.1 Timer Counter (TCNT)-H'FFCC (TMR0), H'FFD4 (TMR1), H'FF9E (TMRX) 10.2.2 Time Constant Registers (TCORA TCORB)-H'FFCA H'FFCB (TMR0), H'FFD2 H'FFD3 (TMR1), H'FF9C H'FF9D (TMRX). 10.2.3 Timer Control Register (TCR)-H'FFC8 (TMR0), H'FFD0 (TMR1), H'FF9A (TMRX). 10.2.4 Timer Control/Status Register (TCSR)-H'FFC9 (TMR0), H'FFD1 (TMR1), H'FF9B (TMRX). 10.2.5 Serial/Timer Control Register (STCR) 10.3 Operation 10.3.1 TCNT Incrementation Timing 10.3.2 Compare Match Timing 10.3.3 External Reset TCNT. 10.3.4 Setting TCSR Overflow Flag. 10.4 Interrupts 10.5 Sample Application 10.6 Application Notes. 10.6.1 Contention between TCNT Write Clear. 10.6.2 Contention between TCNT Write Increment 10.6.3 Contention between TCOR Write Compare-Match 10.6.4 Contention between Compare-Match Compare-Match 10.6.5 Incrementation Caused Changing Internal Clock Source.
Section Timer Connection.
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Input Output Pins. 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Timer Connection Register (TCONR) 11.2.2 Serial/Timer Control Register (STCR) 11.2.3 Edge Sense Register (SEDGR) 11.3 Operation 11.3.1 Decoding. 11.3.2 Clamp Waveform Generation 11.3.3 Measurement 8-Bit Timer Divided Waveform Period
Section Watchdog Timer
12.1 Overview 12.1.1 Features
12.1.2 Block Diagram 12.1.3 Register Configuration 12.2 Register Descriptions. 12.2.1 Timer Counter (TCNT) 12.2.2 Timer Control/Status Register (TCSR) 12.2.3 Register Access 12.3 Operation 12.3.1 Watchdog Timer Mode 12.3.2 Interval Timer Mode 12.3.3 Setting Overflow Flag 12.4 Application Notes. 12.4.1 Contention between TCNT Write Increment 12.4.2 Changing Clock Select Bits (CKS2 CKS0) 12.4.3 Recovery from Software Standby Mode
Section Serial Communication Interface
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Input Output Pins. 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Receive Shift Register (RSR). 13.2.2 Receive Data Register (RDR) 13.2.3 Transmit Shift Register (TSR) 13.2.4 Transmit Data Register (TDR). 13.2.5 Serial Mode Register (SMR). 13.2.6 Serial Control Register (SCR). 13.2.7 Serial Status Register (SSR). 13.2.8 Rate Register (BRR). 13.2.9 Serial Communication Mode Register (SCMR) 13.3 Operation 13.3.1 Overview 13.3.2 Asynchronous Mode 13.3.3 Synchronous Mode. 13.4 Interrupts 13.5 Application Notes.
Section Interface [Option]
14.1 Overview 14.1.1 Features 14.1.2 Block Diagram 14.1.3 Input/Output Pins
14.1.4 Register Configuration 14.2 Register Descriptions. 14.2.1 Data Register (ICDR) 14.2.2 Slave Address Register (SAR) 14.2.3 Mode Register (ICMR). 14.2.4 Control Register (ICCR). 14.2.5 Status Register (ICSR) 14.2.6 Serial/Timer Control Register (STCR) 14.3 Operation 14.3.1 Data Format 14.3.2 Master Transmit Operation 14.3.3 Master Receive Operation 14.3.4 Slave Transmit Operation. 14.3.5 Slave Receive Operation 14.3.6 IRIC Timing Control. 14.3.7 Noise Canceler 14.3.8 Sample Flowcharts 14.4 Application Notes.
Section Host Interface.
15.1 Overview 15.1.1 Block Diagram 15.1.2 Input Output Pins. 15.1.3 Register Configuration 15.2 Register Descriptions. 15.2.1 System Control Register (SYSCR) 15.2.2 Host Interface Control Register (HICR) 15.2.3 Input Data Register (IDR1). 15.2.4 Output Data Register (ODR1). 15.2.5 Status Register (STR1). 15.2.6 Input Data Register (IDR2). 15.2.7 Output Data Register (ODR2). 15.2.8 Status Register (STR2). 15.3 Operation 15.3.1 Host Interface Operation 15.3.2 Control States 15.3.3 Gate 15.4 Interrupts 15.4.1 IBF1, IBF2 15.4.2 HIRQ11, HIRQ1, HIRQ12 15.5 Application Note
Section
16.1 16.2 16.3 16.4 Overview Block Diagram. Enable (RAME). Operation 16.4.1 Expanded Modes (Modes 16.4.2 Single-Chip Mode (Mode
Section
17.1 Overview 17.1.1 Block Diagram 17.2 PROM Mode (H8/3217 H8/3214) 17.2.1 PROM Mode Setup 17.2.2 Socket Adapter Assignments Memory 17.3 Programming. 17.3.1 Selection Sub-Modes PROM Mode 17.3.2 Programming Verification. 17.3.3 Notes Writing 17.3.4 Reliability Written Data. 17.3.5 Erasing Data. 17.4 Handling Windowed Packages
Section Power-Down State
18.1 Overview 18.1.1 System Control Register (SYSCR) 18.2 Sleep Mode. 18.2.1 Transition Sleep Mode 18.2.2 Exit from Sleep Mode 18.3 Software Standby Mode 18.3.1 Transition Software Standby Mode 18.3.2 Exit from Software Standby Mode. 18.3.3 Clock Settling Time Exit from Software Standby Mode 18.3.4 Sample Application Software Standby Mode. 18.3.5 Note Current Dissipation. 18.4 Hardware Standby Mode. 18.4.1 Transition Hardware Standby Mode 18.4.2 Recovery from Hardware Standby Mode. 18.4.3 Timing Relationships
Section Electrical Specifications
19.1 Absolute Maximum Ratings. 19.2 Electrical Characteristics. 19.2.1 Characteristics
19.2.2 Characteristics 19.3 Operational Timing 19.3.1 Timing. 19.3.2 Control Signal Timing 19.3.3 16-Bit Free-Running Timer Timing. 19.3.4 8-Bit Timer Timing 19.3.5 Pulse Width Modulation Timer Output Timing. 19.3.6 Serial Communication Interface Timing. 19.3.7 Port Timing 19.3.8 Host Interface Timing 19.3.9 Interface (Option) Timing 19.3.10 External Clock Output Timing.
Appendix Instruction
Instruction List Operation Code Number States Required Execution.
Appendix Register Field
Register Addresses Names B.1.1 Registers Maximum Specification (Except H8/3212 H8/3202) B.1.2 H8/3212 Registers B.1.3 H8/3202 Registers Register Descriptions.
Appendix Port Block Diagrams.
Port Block Diagram. Port Block Diagram. Port Block Diagram. Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams
Appendix DPin States. Appendix Timing Transition Recovery from Hardware Standby Mode. Appendix Option List Appendix GProduct Code Lineup. Appendix Package Dimensions.
Section Overview
Overview
H8/3217 Series series single-chip microcomputers integrating core together with variety peripheral functions needed control systems. H8/300 high-speed processor featuring powerful bit-manipulation instructions, ideally suited realtime control applications. on-chip supporting modules include ROM, RAM, four types timers (16-bit free-running timer, 8-bit timer, timer, watchdog timer), serial communication interface, interface (option), host interface, ports. Note that H8/3212 H8/3202 have subset specification that does include certain on-chip supporting modules. H8/3217 Series operate single-chip mode expanded modes, depending memory requirements application. operating mode referred this manual mode (MCU: MicroComputer Unit). addition mask versions, ZTATTM* versions available with electrically programmable that programmed user site. Note: ZTAT trademark Hitachi, Ltd. Table lists features H8/3217 Series.
Table
Feature
Features
Description General register architecture Eight 16-bit general registers, Sixteen 8-bit general registers High speed Maximum clock rate: MHz/5 MHz/4 MHz/3 clock) Add/subtract: operation), operation), operation) Multiply/divide: operation), 1167 operation), 1400 operation) Concise, streamlined instruction instructions bytes long Register-register arithmetic logic operations Register-memory data transfer instruction Instruction features Multiply instruction bits bits) Divide instruction bits bits) Bit-accumulator instructions Register-indirect specification positions
Memory
H8/3217 ROM: kbytes RAM: kbytes H8/3216 ROM: kbytes RAM: kbytes H8/3214 ROM: kbytes RAM: kbyte H8/3212 H8/3202 ROM: kbytes RAM: bytes
16-Bit free-running timer module (FRT: channel) 8-bit timer module*1
16-bit free-running counter (also usable external event counting) compare outputs capture input Each channel has: 8-bit up-counter (also usable external event counting) time constant registers outputs Duty cycle settable from 100% Resolution: 1/256 maximum carrier frequency operation)
timers (except H8/3202)
Watchdog timer (WDT: channel)
Reset generation overflow switched interval timer mode
Table
Feature
Features (cont)
Description Selection asynchronous synchronous modes Simultaneous transmit receive (full duplex operation) On-chip baud rate generator Conforms Philips interface standard Single master mode/slave mode 8-bit host interface port Three host interrupt requests (HIRQ HIRQ11, HIRQ12) Normal fast gate output register sets (each comprising data registers status register)
Serial communication interface*2 interface (option) Host interface (HIF) (except H8/3212)
Keyboard controller (except H8/3212) ports Interrupts
Controls matrix keyboard using keyboard scan with wake-up interrupt sense port configuration input/output pins which drive large current loads) Four external interrupt pins: NMI, IRQ0 IRQ2 Eight key-sense interrupt pins: KEYIN0 KEYIN7 Twenty-six on-chip interrupt sources Mode expanded mode with on-chip enabled Mode expanded mode with on-chip enabled Mode single-chip mode Sleep mode Software standby mode Hardware standby mode On-chip clock oscillator
Type Code Series MHz), Series MHz) HD6473217C16
Operating modes
Power-down state
Other features Product lineup
Product Name H8/3217 ZTAT
Series MHz) HD6473217C16
Package 64-pin windowed shrink (DC-64S) 64-pin shrink (DP-64S) 64-pin (FP-64A) 80-pin TQFP (TFP-80C)
PROM
HD6473217P16 HD6473217F16 HD6473217TF16
HD6473217P16 HD6473217F16 HD6473217TF16
Table
Feature
Features (cont)
Description
Type Code Series MHz), Series Product Name MHz) H8/3217* HD6433217P16 HD6433217P12 HD6433217F16 HD6433217F12 HD6433217TF16 HD6433217TF12 H8/3216* HD6433216P16 HD6433216P12 HD6433216F16 HD6433216F12 HD6433216TF16 HD6433216TF12 H8/3214 ZTAT HD6473214P16 HD6473214F16 HD6473214TF16 H8/3214* HD6433214P16 HD6433214P12 HD6433214F16 HD6433214F12 HD6433214TF16 HD6433214TF12 H8/3212* HD6433212P16 HD6433212P12 HD6433212F16 HD6433212F12 HD6433212TF16 HD6433212TF12 H8/3202* HD6433202P16 HD6433202P12 HD6433202F16 HD6433202F12 HD6433202TF16 HD6433202TF12
Product lineup
Series MHz) HD6433217VP10 HD6433217VF10
Package 64-pin shrink (DP-64S) 64-pin (FP-64A)
Mask
HD6433217VTF10 80-pin TQFP (TFP-80C) HD6433216VP10 HD6433216VF10 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask
HD6433216VTF10 80-pin TQFP (TFP-80C) HD6473214P16 HD6473214F16 HD6473214TF16 HD6433214VP10 HD6433214VF10 64-pin shrink (DP-64S) 64-pin (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask PROM
HD6433214VTF10 80-pin TQFP (TFP-80C) HD6433212VP10 HD6433216VF10 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask
HD6433212VTF10 80-pin TQFP (TFP-80C) 64-pin shrink (DP-64S) HD6433202VF10 64-pin (FP-64A) HD6433202VTF10 80-pin TQFP (TFP-80C) HD6433202VP10 Mask
Table
Feature
Features (cont)
Description
Product Name Except H8/3212 H8/3202 H8/3212 H8/3202 TMR0 TMR1 TMRX, TIimer Connection HIF, Key-Sense Interrupt
On-chip peripheral functions
Notes: interface available option. Observe following notes when using this option. Please inform your Hitachi sales representative intend this option. mask-ROM versions, added part number products which this optional function used. Examples: HD6433217WF16, HD6433212WP12 product number identical ZTAT version. However, sure inform your Hitachi sales representative will using this option. Under development channels incorporated H8/3202, three channels other models. channel incorporated H8/3212, channels other models. channel incorporated H8/3202, channels other models.
Block Diagram
Figure shows block diagram H8/3217 Series. Note that H8/3212 H8/3202 have subset specification that does include certain on-chip supporting modules. tables 1-4, Assignments Each Operating Mode, differences functions.
EXTAL
Clock pulse generator
STBY
XTAL
H8/300
P10/A0/PW0 P11/A1/PW1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7
Data (low)
Data (high) Address Port Port
Watchdog timer
Host interface
P70/SCL0/KEYIN4 P71/SDA0/KEYIN5 P72/SCL1/KEYIN6 P73/SDA1/KEYIN7 P74/AS/CS1 P75/WR/IOW P76/RD/IOR P77/WAIT/HA0
Port
timer
P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14 P27/A15/PW15
16-bit free-running timer
Port
Serial communication interface channels) interface channel) (option)
8-bit timer channels) Timer connection
P30/D0/HDB0 P31/D1/HDB1 P32/D2/HDB2 P33/D3/HDB3 P34/D4/HDB4 P35/D5/HDB5 P36/D6/HDB6 P37/D7/HDB7
Port
P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1
Port
KEYIN0/P60/FTCI KEYIN1/P61/FTOA KEYIN2/VSYNCO/P62/FTOB KEYIN3/VSYNCI/P63/FTI P64/IRQ0 P65/IRQ1 P66/IRQ2
Port
P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/HSYNCI/P43/TMCI1 HIRQ1/HSYNCO/P44/TMO1 HIRQ12/CSYNCI/P45/TMRI1 GA20/CLAMPO/P47/TMOx
Figure Block Diagram
1.3.1
Assignments Functions
Arrangement
Figure shows arrangement H8/3217 Series DC-64S DP-64S packages. Figure shows arrangement FP-64A package. Figure shows arrangement TFP-80C package. Note that H8/3212 H8/3202 have subset specification that does include certain on-chip supporting modules. tables 1-4, Assignments Each Operating Mode, differences functions.
KEYIN0/P60/FTCI KEYIN1/P61/FTOA KEYIN2/VSYNCO/P62/FTOB KEYIN3/VSYNCI/P63/FTI P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/HSYNCI/P43/TMCI1 HIRQ1/HSYNCO/P44/TMO1 HIRQ12/CSYNCI/P45/TMRI1 GA20/CLAMPO/P47/TMOx P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 KEYIN4/P70/SCL0 KEYIN5/P71/SDA0
P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0 P10/A0/PW0 P11/A1/PW1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14 P27/A15/PW15 P77/WAIT/HA0 P76/RD/IOR P75/WR/IOW P74/AS/CS1 P73/SDA1/KEYIN7 P72/SCL1/KEYIN6
Figure Arrangement (DC-64S, DP-64S, View)
P62/FTOB/VSYNCO/KEYIN2
P63/FTI/VSYNCI/KEYIN3
P61/FTOA/KEYIN1
P60/FTCI/KEYIN0
P37/D7/HDB7
P36/D6/HDB6
P35/D5/HDB5
P34/D4/HDB4
P33/D3/HDB3
P32/D2/HDB2
P31/D1/HDB1
XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0
HIRQ11/HSYNCI/P43/TMCI1 HIRQ1/HSYNCO/P44/TMO1 HIRQ12/CSYNCI/P45/TMRI1 GA20/CLAMPO/P47/TMOx
P30/D0/HDB0
P66/IRQ2
P65/IRQ1
P64/IRQ0
P10/A0/PW0 P11/A1/PW1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14
IOW/P75/WR
KEYIN4/P70/SCL0
KEYIN6/P72/SCL1
EYIN5/P71/SDA0
EYIN7/P73/SDA1
HA0/P77/WAIT
IOR/P76/RD
Figure Arrangement (FP-64A, View)
PW15/P27/A15
CS1/P74/AS
P50/TxD0
P51/RxD0
P53/TxD1
P52/SCK0
P54/RxD1
P55/SCK1
Figure Arrangement (TFP-80C, View)
P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 KEYIN4/P70/SCL0 KEYIN5/P71/SDA0 KEYIN6/P72/SCL1 KEYIN7/P73/SDA1 CS1/P74/AS IOW/P75/WR IOR/P76/RD HA0/P77/WAIT PW15/P27/A15
XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/HSYNCI/P43/TMCI1 HIRQ1/HSYNCO/P44/TMO1 HIRQ12/CSYNCI/P45/TMRI1 GA20/CLAMPO/P47/TMOx
P66/IRQ2 P65/IRQ1 P64/IRQ0 P63/FTI/VSYNCI/KEYIN3 P62/FTOB/VSYNCO/KEYIN2 P61/FTOA/KEYIN1 P60/FTCI/KEYIN0 P37/D7/HDB7 P36/D6/HDB6 P35/D5/HDB5 P34/D4/HDB4 P33/D3/HDB3 P32/D2/HDB2 P31/D1/HDB1 P30/D0/HDB0
P10/A0/PW0 P11/A1/PW1 P12/A2/PW2 P13/A3/PW3 P14/A4/PW4 P15/A5/PW5 P16/A6/PW6 P17/A7/PW7 P20/A8/PW8 P21/A9/PW9 P22/A10/PW10 P23/A11/PW11 P24/A12/PW12 P25/A13/PW13 P26/A14/PW14
1.3.2
Functions
Assignments Each Operating Mode: Table table list assignments pins DC-64S, DP-64S, FP-64A, TFP-80C packages each operating mode. Table Assignments Each Operating Mode (Except H8/3212 H8/3202)
Expanded Modes Mode P60/FTCI/KEYIN0 P62/FTOB/ VSYNCO/KEYIN2 P63/FTI/VSYNCI/ KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 Single-Chip Mode Mode P60/FTCI/KEYIN0 P62/FTOB/ VSYNCO/KEYIN2 P63/FTI/VSYNCI/ KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 PROM Mode
DC-64S DP-64S FP-64A TFP-80C Mode
P60/FTCI/KEYIN0 P62/FTOB/ VSYNCO/KEYIN2 P63/FTI/VSYNCI/ KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0
P61/FTOA/KEYIN1 P61/FTOA/KEYIN1 P61/FTOA/KEYIN1
Table
Assignments Each Operating Mode (Except H8/3212 H8/3202) (cont)
Expanded Modes Mode P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P47/TMOx/ CLAMPO P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 Mode P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P47/TMOx/ CLAMPO P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 Single-Chip Mode Mode P43/TMCI1/ HSYNCI/HIRQ11 P44/TMO1/ HSYNCO/HIRQ1 P45/TMRI1/ CSYNCI/HIRQ12 P47/TMOx/ CLAMPO/GA P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 PROM Mode
DC-64S DP-64S FP-64A TFP-80C
EA15 EA16 EA14 EA13
P70/SCL0/KEYIN4 P70/SCL0/KEYIN4 P70/SCL0/KEYIN4 P71/SDA0/KEYIN5 P71/SDA0/KEYIN5 P71/SDA0/KEYIN5 P72/SCL1/KEYIN6 P72/SCL1/KEYIN6 P72/SCL1/KEYIN6 P73/SDA1/KEYIN7 P73/SDA1/KEYIN7 P73/SDA1/KEYIN7 P77/WAIT P77/WAIT P27/A 15/PW15 P26/A 14/PW14 P25/A 13/PW13 P74/CS P75/IOW P76/IOR P77/HA0 P27/PW15 P26/PW14 P25/PW13
Table
Assignments Each Operating Mode (Except H8/3212 H8/3202) (cont)
Expanded Modes TFP-80C Mode Mode P24/A 12/PW12 P23/A 11/PW11 P22/A 10/PW10 P21/A 9/PW9 P20/A 8/PW8 P17/A 7/PW7 P16/A 6/PW6 P15/A 5/PW5 P14/A 4/PW4 P13/A 3/PW3 P12/A 2/PW2 P11/A 1/PW1 P10/A 0/PW0 Single-Chip Mode Mode P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 P30/HDB0 P31/HDB1 P32/HDB2 P33/HDB3 P34/HDB4 P35/HDB5 P36/HDB6 P37/HDB7 PROM Mode EA12 EA11 EA10
DC-64S DP-64S Notes:
FP-64A
Pins marked should left unconnected. PROM mode non-operating mode used programming on-chip ROM. section ROM, details.
Table
Assignments Each Operating Mode (H8/3212)
Expanded Modes Mode P60/FTCI P61/FTOA P63/FTI/VSYNCI P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HSYNCI P45/TMRI1/CSYNCI Mode P60/FTCI P61/FTOA P63/FTI/VSYNCI P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HSYNCI P45/TMRI1/CSYNCI Single-Chip Mode Mode P60/FTCI P61/FTOA P63/FTI/VSYNCI P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HSYNCI P45/TMRI1/CSYNCI
DP-64S FP-64A TFP-80C
P62/FTOB/VSYNCO P62/FTOB/VSYNCO P62/FTOB/VSYNCO
P44/TMO1/HSYNCO P44/TMO1/HSYNCO P44/TMO1/HSYNCO
P47/TMOx/CLAMPO P47/TMOx/CLAMPO P47/TMOx/CLAMPO
Table
Assignments Each Operating Mode (H8/3212) (cont)
Expanded Modes Mode P50/TxD0 P51/RxD0 P52/SCK0 P70/SCL0 P71/SDA0 P72/SCL1 P73/SDA1 P77/WAIT Mode P50/TxD0 P51/RxD0 P52/SCK0 P70/SCL0 P71/SDA0 P72/SCL1 P73/SDA1 P77/WAIT P27/A 15/PW15 P26/A 14/PW14 P25/A 13/PW13 P24/A 12/PW12 P23/A 11/PW11 P22/A 10/PW10 P21/A 9/PW9 P20/A 8/PW8 Single-Chip Mode Mode P50/TxD0 P51/RxD0 P52/SCK0 P70/SCL0 P71/SDA0 P72/SCL1 P73/SDA1 P27/PW15 P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 P21/PW9 P20/PW8
DP-64S FP-64A TFP-80C
Table
Assignments Each Operating Mode (H8/3212) (cont)
Expanded Modes Mode Mode P17/A 7/PW7 P16/A 6/PW6 P15/A 5/PW5 P14/A 4/PW4 P13/A 3/PW3 P12/A 2/PW2 P11/A 1/PW1 P10/A 0/PW0 Single-Chip Mode Mode P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0
DP-64S FP-64A TFP-80C
Table
Assignments Each Operating Mode (H8/3202)
Expanded Modes Mode P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 Mode P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 Single-Chip Mode Mode P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P62/FTOB/KEYIN2 P63/FTI/KEYIN3 P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HIRQ11 P44/TMO1/HIRQ1 P45/TMRI1/HIRQ12 P47/GA
DP-64S FP-64A TFP-80C
Table
Assignments Each Operating Mode (H8/3202) (cont)
Expanded Modes Mode P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 P70/SCL0/KEYIN4 P71/SDA0/KEYIN5 P72/KEYIN6 P73/KEYIN7 P77/WAIT Mode P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 P70/SCL0/KEYIN4 P71/SDA0/KEYIN5 P72/KEYIN6 P73/KEYIN7 P77/WAIT P27/A P26/A P25/A P24/A P23/A P22/A P21/A P20/A Single-Chip Mode Mode P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1 P70/SCL0/KEYIN4 P71/SDA0/KEYIN5 P72/KEYIN6 P73/KEYIN7 P74/CS P75/IOW P76/IOR P77/HA0
DP-64S FP-64A TFP-80C
Table
Assignments Each Operating Mode (H8/3202) (cont)
Expanded Modes Mode Mode P17/A P16/A P15/A P14/A P13/A P12/A P11/A P10/A Single-Chip Mode Mode P30/HDB0 P31/HDB1 P32/HDB2 P33/HDB3 P34/HDB4 P35/HDB5 P36/HDB6 P37/HDB7
DP-64S FP-64A TFP-80C
Functions: Table gives concise description function each pin. Table Functions
Type Power Symbol DC-64S DP-64S FP-64A TFP-80C Name Function Power: Connected power supply. Connect both pins system power supply. Ground: Connected ground Connect pins system power supply
Clock
XTAL
Crystal: Connected crystal oscillator. crystal frequency must same desired system clock frequency. external clock input EXTAL pin, reversephase clock should input XTAL pin. External crystal: Connected crystal oscillator external clock. frequency external clock must same desired system clock frequency. section Clock Pulse Generator, examples connections crystal external clock. System clock: Supplies system clock peripheral devices. Reset: input causes chip reset. Standby: transition hardware standby mode power-down state) occurs when input received STBY pin. Address bus: Address output pins.
EXTAL
System control STBY
Address
Table
Functions (cont)
Type
Symbol
DC-64S DP-64S
FP-64A
TFP-80C
Name Function Data bus: 8-bit bidirectional data bus. Wait: Requests insert states into cycle when offchip address accessed. Read: Goes indicate that reading external address. Write: Goes indicate that writing external address. Address strobe: Goes indicate that there valid address address bus. maskable interrupt: Highestpriority interrupt request. NMIEG system control register determines whether interrupt requested rising falling edge input. Interrupt request Maskable interrupt request pins. Mode: Input pins setting operating mode according table below. Mode Mode Description Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Data control WAIT
Interrupt signals
IRQ0 IRQ2 Operating MD1, mode control
Mode
Mode
Table
Functions (cont)
Type 16-bit freerunning timer
Symbol FTCI
DC-64S DP-64S
FP-64A
TFP-80C
Name Function counter clock input: Input external clock signal freerunning counter. output compare Output pins controlled comparator freerunning timer. output compare Output pins controlled comparator freerunning timer. input capture: Input capture free-running timer. 8-bit timer output (channels Compare- match output pins 8-bit timers. 8-bit timer clock input (channels External clock input pins 8-bit timer counters. 8-bit timer reset input (channels High input these pins resets 8-bit timers. Serial transmit data (channels Data output pins serial communication interface. Serial receive data (channels Data input pins serial communication interface.
FTOA
FTOB
8-bit timer TMO0, (channel TMO1, except TMOx H8/3202) TMCI0, TMCI1, FBACKI TMRI0, TMRI1, FBACKI Serial communication interface (channel except H8/3212) TxD0 TxD1 RxD0 RxD1
Serial clock (channels Input/output pins serial clock signals.
Table
Functions (cont)
Type Generalpurpose
Symbol
DC-64S DP-64S
FP-64A
TFP-80C
Name Function Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P1DDR). Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P2DDR). Port 8-bit input/output port with programmable input pull-ups drive capability. direction each selected port data direction register (P3DDR). Port 8-bit input/output port. direction each (except P46) selected port data direction register (P4DDR). Port 6-bit input/output port. direction each selected port data direction register (P5DDR). Port 7-bit input/output port. direction each selected port data direction register (P6DDR). Port 8-bit input/output port. direction each selected port data direction register (P7DDR). timer outputs: timer pulse output pins.
PW15 timers (except H8/3202)
Table
Functions (cont)
Type Timer connection (except H8/3202)
Symbol VSYNCI HSYNCI CSYNCI FBACKI
DC-64S DP-64S
FP-64A
TFP-80C
Name Function Timer connection inputs: Timer connection (FRT, TMR1, TMRX) input pins. Timer connection outputs: Timer connection (FRT, TMR1, TMRX) output pins.
VSYNCO HSYNCO CLAMPO
interface (option) (channel except H8/3202)
clock input/output (channels clock input/output pin. driving function. data input/output (channels data input/output pin. driving function. Host interface data bus: Bidirectional 8-bit host interface access host. Chip select Input pins selecting host interface channel channel read: Input that enables reads host interface. write: Input that enables writes host interface. Command/data: Input that indicates data access command access. GATE A20: GATE control signal output pin. Host interrupt Output pins interrupt requests host. Keyboard input: Input pins matrix keyboard. (PI1 normally used keyboard scan outputs, enabling maximum 16output 8-input, 128-key matrix configured. number keys increased using other port outputs.)
HDB0 Host interface HDB7 (HIF) (except H8/3212)
GA20 HIRQ1 HIRQ11 HIRQ12 Keyboard KEYIN0 control (except KEYIN7 H8/3212)
Section
Overview
H8/3217 Series generic H8/300 CPU: 8-bit central processing unit with speedoriented architecture featuring sixteen general registers. This section describes features functions, including concise description addressing modes instruction set. further details instructions, H8/300 Series Programming Manual. 2.1.1 Features
main features H8/300 listed below. Two-way register configuration Sixteen 8-bit general registers, Eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment pre-decrement (@Rn+ @-Rn) Absolute address (@aa:8 @aa:16) Immediate (#xx:8 #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) Maximum 64-kbyte address space High-speed operation frequently-used instructions executed four states maximum clock rate MHz/5 MHz/4 MHz/3 clock) 16-bit register-register subtract: MHz), MHz) MHz) 8-bit multiply: MHz), 1167 MHz) 1400 MHz) 8-bit divide: MHz), 1167 MHz) 1400 MHz)
Power-down mode SLEEP instruction 2.1.2 Address Space
H8/300 supports address space kbytes storing program code data. memory different each mode (modes section 3.5, Address Space Maps Each Operating Mode, details. 2.1.3 Register Configuration
Figure shows register structure CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack pointer
Control registers (CR) UHUNZ Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used address registers, general registers accessed 16-bit registers R7). When used data registers, they accessed 16-bit registers, high bytes accessed separately 8-bit registers. also functions stack pointer, used implicitly hardware processing interrupts subroutine calls. assembly-language coding, also denoted letters indicated figure 2-2, (SP) points stack.
Unused area (R7) Stack area
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. Each instruction accessed bits word), least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), half-carry flags interrupt mask (I). 7-Interrupt Mask (I): When this interrupts except masked. This automatically reset start interrupt handling.
6-User (U): This written read software purposes (using LDC, STC, ANDC, ORC, XORC instructions). 5-Half-Carry (H): This when ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, CMP.B instruction causes carry borrow cleared otherwise. Similarly, when ADD.W, SUB.W, CMP.W instruction causes carry borrow cleared otherwise. used implicitly instructions. 4-User (U): This written read software purposes (using LDC, STC, ANDC, ORC, XORC instructions). 3-Negative (N): This indicates most significant (sign bit) result instruction. 2-Zero (Z): This indicate zero result cleared indicate nonzero result. 1-Overflow (V): This when arithmetic overflow occurs, cleared other times. 0-Carry (C): This used subtract instructions, indicate carry borrow most significant result Shift rotate instructions, store value shifted most significant least significant manipulation load instructions, accumulator LDC, STC, ANDC, ORC, XORC instructions enable load store CCR, clear selected bits logic operations. flags used conditional branching instructions (Bcc). Some instructions leave some flag bits unchanged. action each instruction flag bits shown Appendix A.1, Instruction List. H8/300 Series Programming Manual further details. 2.2.3 Initial Register Values
When reset, program counter (PC) loaded from vector table interrupt mask other bits general registers initialized. particular, stack pointer (R7) initialized. prevent program crashes stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300 process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand. arithmetic logic instructions except ADDS SUBS operate byte data. instruction perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data.
2.3.1
Data Formats General Registers
Data sizes above stored general registers shown figure 2-3.
Data Type
Register
Data Format
1-bit data
Don't care
1-bit data
Don't care
Byte data
Don't care
Byte data
Don't care
Word data
Upper digit
Lower digit
4-bit data
Don't care
Upper digit
Lower digit
4-bit data
Don't care
Legend RnH: Upper digit general register RnL: Lower digit general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. Word data stored memory must always begin even address. word access least significant address regarded address specified, address error occurs access performed preceding even address. This rule affects MOV.W instructions branching instructions, implies that only even addresses should stored vector table.
Data Type
Address
Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
Note: Ignored returning Legend CCR: Condition code register
Figure Memory Data Formats stack must always accessed word time. When pushed stack, identical copies pushed make complete word. When they returned, lower byte ignored.
2.4.1
Addressing Modes
Addressing Modes
H8/300 supports eight addressing modes. Each instruction uses subset these addressing modes. Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. most cases general register accessed 8-bit register. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register indirect-@Rn: register field instruction specifies 16-bit general register containing address operand. Register Indirect with Displacement-@(d:16, Rn): This mode, which used only instructions, similar register indirect instruction second word (bytes which added contents specified general register obtain operand address. MOV.W instruction, resulting address must even. Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with Post-Increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. similar register indirect mode, 16-bit general register specified register field instruction incremented after operand accessed. size increment depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even. Register Indirect with Pre-Decrement-@-Rn @-Rn mode used with instructions that store register contents memory. similar register indirect mode, 16-bit general register specified register field instruction decremented before operand accessed. size decrement depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. MOV.B instruction uses 8-bit absolute address form H'FFxx. upper bits assumed possible address range H'FF00 H'FFFF (65280 65535). MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. Immediate-#xx:8 #xx:16: instruction contains 8-bit operand second byte, 16-bit operand third fourth bytes. Only MOV.W instructions contain 16-bit
immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data (#xx:3) second fourth byte instruction, specifying number. PC-Relative-@(d:8, PC): This mode used generate branch addresses instructions. 8-bit value byte instruction code added sign-extended value program counter contents. result must even number. possible branching range -126 +128 bytes (-63 words) from current address. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address from H'0000 H'00FF 255). word located this address contains branch address. Note that part this area located vector table. section 3.5, Address Space Maps Each Operating Mode, details. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. section 2.3.2, Memory Data Formats, further information. 2.4.2 Effective Address Calculation
Table shows effective address (EA) calculated each addressing mode. Arithmetic logic instructions (ADD.B, ADDX, SUBX, CMP.B, AND, instructions) register direct immediate addressing modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect absolute (@aa:8) addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand.
Effective Address Calculation
Table Effective Address Calculation
Effective Address (EA)
regm
Addressing Mode Instruction Format
Register direct, (Rn)
regn
regm
regn
Operand regm/n contents contents bits)
Register indirect (@Rn)
contents bits) disp
Register indirect with displacement (@d:16, disp
Register indirect with post-increment pre-decrement Register indirect with post-increment, @Rn+
contents bits)
Register indirect with pre-decrement, @-Rn
contents bits)
Incremented decremented operand byte size, word size
Table Effective Address Calculation (cont)
Effective Address Calculation
H'FF
Addressing Mode Instruction Format Effective Address (EA)
Absolute address @aa:8
@aa:16
Immediate #xx:8 Operand 2-byte immediate data
#xx:16
Program-counter relative @(d:8,
contents
Sign extension
disp
disp
Effective Address Calculation Effective Address (EA)
Table Effective Address Calculation (cont)
Addressing Mode Instruction Format
Memory indirect, @@aa:8
H'00
Memory contents bits)
Legend reg, regm, regn: disp: IMM: abs: Register field Operation field Displacement Immediate data Absolute address
Instruction
Table lists H8/300 instruction set. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer Notes:
Instruction Classification
Instructions MOV, MOVTPE MOVFPE*1, PUSH*2, POP*2 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*3, JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV Types Total These instructions cannot used with H8/3217 Series. PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, conditional branch instruction which represents condition code.
following sections give concise summary instructions each category, indicate patterns their object code. notation used defined next.
Operation Notation
<EAs> (EAd) (EAs) #imm #xx:3 #xx:8 #xx:16 General register (destination) General register (source) General register General register field Effective address: general register memory location Destination operand Source operand Stack pointer Program counter Condition code register (negative) (zero) (overflow) (carry) Immediate data 3-bit immediate data 8-bit immediate data 16-bit immediate data disp Operation field Displacement Absolute address Byte Word Addition Subtraction Multiplication Division Logical Logical Exclusive logical Move Exchange (logical complement) Condition field
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:8 #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes. Cannot used with H8/3217 Series. Cannot used with H8/3217 Series. @-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP. @SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
MOVTPE MOVFPE PUSH
Note: Size: operand size Byte Word
@Rm,
disp
@(d:16, @(d:16,
@Rm+ @-Rm @aa:8 @aa:8
@aa:16 @aa:16
#imm
#xx:8
#imm
#xx:16
MOVFPE, MOVTPE MOVFPE: MOVTPE:
Legend Operation field Direction field (0-load from; 1-store Register field disp: Displacement abs: Absolute address #imm: Immediate data
PUSH,
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. figure section 2.5.4, Shift Operations their object codes. Table
Instruction
Arithmetic Instructions
Size* Function #imm Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #imm Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register. #imm Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed BCD) addition subtraction result general register referring CCR. Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result. Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder. #imm Compares data general register with data another general register with immediate data. Word data compared only between general registers. Obtains two's complement (arithmetic complement) data general register.
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Note: Size: operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. figure section 2.5.4, Shift Operations their object codes. Table
Instruction
Logic Operation Instructions
Size* Function #imm Performs logical operation general register another general register immediate data. #imm Performs logical operation general register another general register immediate data. #imm Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Obtains one's complement (logical complement) general register contents.
Note: Size: operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Figure shows object code formats arithmetic, logic, shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents. shift Performs logical shift operation general register contents. rotate Rotates general register contents. rotate through carry Rotates general register contents through (carry) bit.
Note: Size: operand size Byte
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
#imm
ADD, ADDX, SUBX, (#xx:8)
AND, (Rm)
#imm
AND, (#xx:8)
Legend Operation field Register field #imm: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory specified number, given 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory specified number, given 3-bit immediate data lower three bits general register. <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory. specified number, given 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory sets clears flag accordingly. specified number, given 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs flag with specified general register memory. (<bit-No.> <EAd>)] ANDs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit-No.> <EAd>) flag with specified general register memory. (<bit-No.> <EAd>)] flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit-No.> <EAd>) XORs flag with specified general register memory. [(<bit-No.> <EAd>)] XORs flag with inverse specified general register memory. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND BIAND
BIOR
BXOR BIXOR
Table
Instruction BILD
Bit-Manipulation Instructions (cont)
Size* Function (<bit-No.> <EAd>) Copies specified general register memory flag. (<bit-No.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies flag specified general register memory. (<bit-No.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BIST
Note: Size: operand size Byte
Notes Manipulation Instructions: BSET, BCLR, BNOT, BST, BIST readmodify-write instructions. They read byte data, modify byte, then write byte back. Care required when these instructions applied registers with write-only bits port registers.
Order Read Modify Write Operation Read data byte specified address Modify data byte Write modified data byte back specified address
Example: BCLR executed clear port data direction register (P4DDR) under following conditions. Input pin, Input pin, High 5-P4 Output pins, intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction
Input/output state Input Input High Output Output Output Output Output Output
Execution BCLR Instruction
BCLR.B @P4DDR Clear data direction register
After Execution BCLR Instruction
Input/output state Output Output High Output Output Output Output Output Input High
Explanation: execute BCLR instruction, begins reading P4DDR. Since P4DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P4DDR complete BCLR instruction. result, P40DDR cleared making input pin. addition, P47DDR P46DDR making output pins.
BSET, BCLR, BNOT, BTST
#imm
Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
#imm
Operand: register indirect (@Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.: register direct (Rm)
#imm
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Operand: absolute (@aa:8) No.: register direct (Rm)
BAND, BOR, BXOR, BLD,
#imm
Operand: register direct (Rn) No.: immediate (#xx:3)
#imm
Operand: register indirect (@Rn) No.: immediate (#xx:3)
#imm
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Legend Operation field Register field abs: Absolute address #imm: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
#imm
Operand: register direct (Rn) No.: immediate (#xx:3)
#imm
Operand: register indirect (@Rn) No.: immediate (#xx:3)
#imm
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Legend Operation field Register field abs: Absolute address #imm: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches condition true. Mnemonic (BT) (BF) (BHS) (BLO) Field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified displacement from current address. Returns from subroutine
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Legend Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table describes system control instructions. Figure shows their object code formats. Table
Instruction SLEEP
System Control Instructions
Size* Function Returns from exception-handling routine. Causes transition power-down state. CCR, #imm Moves immediate data general register contents condition code register. Copies condition code register specified general register. #imm Logically ANDs condition code register with immediate data. #imm Logically condition code register with immediate data. #imm Logically exclusive-ORs condition code register with immediate data. Only increments program counter.
ANDC XORC
Note: Size: operand size Byte
RTE, SLEEP,
LDC, (Rn)
#imm
ANDC, ORC, XORC, (#xx:8)
Legend Operation field Register field #imm: Immediate data
Figure System Control Instruction Codes 2.5.8 Block Data Transfer Instruction
Table describes EEPMOV instruction. Figure 2-10 shows object code format. Table
Instruction EEPMOV
Block Data Transfer Instruction
Size Function then repeat until else next; Moves data block according parameters general registers R4L, R4L: size block (bytes) starting source address starting destination address Execution next instruction starts soon block transfer completed. @R5+ @R6+
Legend Operation field
Figure 2-10 Block Data Transfer Instruction Notes EEPMOV Instruction EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
States
three states: program execution state, exception-handling state, power-down state. power-down state further divided into three modes: sleep mode, software standby mode, hardware standby mode. Figure 2-11 summarizes these states, figure 2-12 shows state transitions.
State
Program execution state executes successive program instructions. Exception-handling state transient state which changes processing flow reset interrupt Power-down state state which some chip functions stopped conserve power. Sleep mode Software standby mode Hardware standby mode
Figure 2-11 Operating States
Interrupt request Exceptionhandling state
Program execution state Exception handing Interrupt request
SLEEP instruction with SSBY SLEEP instruction
Sleep mode
IRQ0 IRQ2 IRQ6 input strobe interrupt
Software standby mode
Reset state
STBY
Hardware standby mode Power-down state
Notes: transition reset state occurs when goes low, except when chip hardware standby mode. transition from state hardware standby mode occurs when STBY goes low.
Figure 2-12 State Transitions 2.6.1 Program Execution State
this state executes program instructions sequence. main program, subroutines, interrupt-handling routines executed this state. 2.6.2 Exception-Handling State
exception-handling state transient state that occurs when reset accepts interrupt. this state carries hardware-controlled sequence that prepares execute user-coded exception-handling routine. hardware exception-handling sequence does following: Saves program counter condition code register stack (except case reset). Sets interrupt mask condition code register Fetches start address exception-handling routine from vector table.
Branches that address, returning program execution state.
section Exception Handling, further information exception-handling state. 2.6.3 Power-Down State
power-down state includes three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: sleep mode entered when SLEEP instruction executed. halts, register contents remain unchanged on-chip supporting modules continue function. When interrupt reset signal received, returns through exception-handling state program execution state. Software Standby Mode: software standby mode entered SLEEP instruction executed while SSBY (Software Standby) system control register (SYSCR) set. on-chip supporting modules halt. on-chip supporting modules initialized, contents on-chip registers remain unchanged. port outputs also remain unchanged. Hardware Standby Mode: hardware standby mode entered when input STBY goes low. chip functions halt, including port output. on-chip supporting modules initialized, on-chip contents held. section Power-Down State, further information.
Access Timing Cycle
driven system clock period from rising edge system clock next referred "state." Memory access performed two- three-state cycle described below. Different accesses performed on-chip memory, on-chip register field, external devices. more detailed timing diagrams cycles, section Electrical Specifications. 2.7.1 Access On-Chip Memory (RAM ROM)
On-chip accessed cycle states designated Either byte word data accessed, 16-bit data bus. Figure 2-13 shows on-chip memory access cycle. Figure 2-14 shows associated states.
cycle
state
state
Internal address
Address
Internal read signal
Internal data (read)
Read data
Internal write signal
Internal data (write)
Write data
Figure 2-13 On-Chip Memory Access Cycle
cycle
state
state
Address
Address
High High High Data bus: High impedance state
Figure 2-14 States during On-Chip Memory Access Cycle
2.7.2
Access On-Chip Register Field External Devices
on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) external devices accessed cycle consisting three states: Only byte data accessed cycle, 8-bit data bus. Access word data instruction codes requires consecutive cycles (six states). Figure 2-15 shows access cycle on-chip register field. Figure 2-16 shows associated states. Figures 2-17 show read write access timing external devices.
cycle
state Internal address Internal read signal Internal data (read) Internal write signal Internal data (write)
state
state
Address
Read data
Write data
Figure 2-15 On-Chip Register Field Access Cycle
cycle
state
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2-16 States during On-Chip Supporting Module Access
Read cycle
state
state
state
Address
Address
High Data
Read data
Figure 2-17 External Device Access Timing (Read)
Write cycle
state
state
state
Address
Address
High
Data
Write data
Figure 2-17 External Device Access Timing (Write)
Section Operating Modes Address Space
3.1.1
Overview
Operating Modes
H8/3217 Series operates three modes numbered additional non-operating mode (mode used PROM version programming. mode selected inputs mode pins (MD1 instant when chip comes reset. indicated table 3-1, mode determines size address space usage on-chip on-chip RAM. Table
High High
Operating Modes
High High Mode Mode Mode Mode Mode Address Space Expanded Expanded Single-chip On-Chip Disabled Enabled Enabled On-Chip Enabled* Enabled* Enabled
Note: RAME system control register (SYSCR) cleared off-chip memory accessed instead.
Modes expanded modes that permit access off-chip memory peripheral devices. maximum address space supported these externally expanded modes kbytes. mode (single-chip mode), only on-chip on-chip register field used. ports available general-purpose input output. Mode inoperative H8/3217 Series. Avoid setting mode pins mode 3.1.2 Mode System Control Registers
Table lists registers related chip's operating mode: system control register (SYSCR) mode control register (MDCR). mode control register indicates inputs mode pins MD0. Table
Name System control register Mode control register
Mode System Control Registers
Abbreviation SYSCR MDCR Read/Write Address H'FFC4 H'FFC5
System Control Register (SYSCR)
SSBY STS2 STS1 STS0 XRST NMIEG RAME
Initial value Read/Write
system control register (SYSCR) 8-bit register that controls operation chip. 7-Software Standby (SSBY): Enables transition software standby mode. details, section Power-Down State. recovery from software standby mode external interrupt, SSBY remains cleared writing
SSBY Description SLEEP instruction causes transition sleep mode. SLEEP instruction causes transition software standby mode. (Initial value)
Bits 4-Standby Timer Select (STS2 STS0): These bits select clock settling time when chip recovers from software standby mode external interrupt. During selected time on-chip supporting modules continue stand These bits should according clock frequency that settling time least specific settings, section 18.3.3, Clock Settling Time Exit from Software Standby Mode.
STS2 STS1 STS0 Description Settling time 8,192 states Settling time 16,384 states Settling time 32,768 states Settling time 65,536 states Settling time 131,072 states Unused (Initial value)
3-External Reset (XRST): Indicates source reset. reset generated input external reset signal, watchdog timer overflow when watchdog timer used. XRST read-only bit. external reset, cleared watchdog timer overflow.
XRST Description Reset caused watchdog timer overflow. Reset caused external input. (Initial value)
2-NMI Edge (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge input. interrupt requested rising edge input. (Initial value)
1-Host Interface Enable (HIE): Enables disables host interface function. When enabled, host interface processes host-slave data transfers, operating slave mode.
Description host interface disabled. host interface enabled (slave mode). (Initial value)
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized reset, initialized software standby mode.
RAME Description on-chip disabled. on-chip enabled. (Initial value)
Mode Control Register (MDCR)
MDS1 MDS0
Initial value Read/Write
Note: Initialized according inputs.
mode control register (MDCR) 8-bit register that indicates operating mode chip. Bits 5-Reserved: These bits cannot modified always read Bits 3-Reserved: These bits cannot modified always read 2-Reserved: This cannot modified always read Bits 0-Mode Select (MDS1 MDS0): These bits indicate values mode pins (MD1 thereby indicating current operating mode chip. MDS1 corresponds MDS0 MD0. These bits read written. When mode control register read, levels mode pins (MD1 latched these bits.
Mode Descriptions
Mode (Expanded Mode without On-Chip ROM): Mode supports 64-kbyte address space most which off-chip. particular, interrupt vector table located off-chip memory. on-chip used. Software select whether on-chip RAM. Ports used address data lines control signals follows: Ports Address Port Data Port (partly): control signals Mode (Expanded Mode with On-Chip ROM): Mode supports 64-kbyte address space which includes on-chip ROM. Software select whether on-chip RAM, select usage pins ports Ports Address (see note) Port Data Port (partly): control signals
Note: mode ports initially general-purpose input ports. Software must change desired pins output before using them address bus. section Ports details. Mode (Single-Chip Mode): this mode memory on-chip. Since off-chip memory accessed, there external address bus. ports available general-purpose input output.
Address Space Maps Each Operating Mode
Figures show memory maps H8/3217, H8/3216, H8/3214, H8/3212, H8/3202 each three operating modes.
Mode Expanded mode without on-chip H'0000 Vector table H'0063 H'0064 H'0063 H'0064 H'0000
Mode Expanded mode with on-chip H'0000 Vector table H'0063 H'0064
Mode Single-chip mode
Vector table
On-chip ROM, 61312 bytes External address space On-chip ROM, 63360 bytes
H'EF7F H'EF80 External address space H'F77F H'F780 On-chip RAM*, 2048 bytes H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'F77F H'F780 On-chip RAM*, 2048 bytes H'F77F H'F780 On-chip RAM*, 2048 bytes
H'FF7F External address space H'FF90 On-chip register field H'FFFF On-chip register field
External address space On-chip register field
Note: External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3217 Address Space
Mode Expanded mode without on-chip H'0000 Vector table H'0063 H'0064 H'0063 H'0064 H'0000
Mode Expanded mode with on-chip H'0000 Vector table H'0063 H'0064
Mode Single-chip mode
Vector table
On-chip ROM, 49152 bytes
On-chip ROM, 49152 bytes
External address space H'BFFF H'C000 Reserved*2 H'EF7F H'EF80 External address space H'F77F H'F780 On-chip RAM*1, 2048 bytes H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'F77F H'F780 On-chip RAM*1, 2048 bytes H'F77F H'F780 On-chip RAM, 2048 bytes Reserved*2 H'BFFF H'C000
H'FF7F External address space H'FF90 On-chip register field H'FFFF On-chip register field
External address space On-chip register field
Notes: External memory accessed these addresses when RAME system control register (SYSCR) cleared Data read write permitted these modes.
Figure H8/3216 Address Space
Mode Expanded mode without on-chip H'0000 Vector table H'0063 H'0064 H'0063 H'0064 H'0000
Mode Expanded mode with on-chip H'0000 Vector table H'0063 H'0064
Mode Single-chip mode
Vector table
On-chip ROM, 32768 bytes
On-chip ROM, 32768 bytes
External address space
H'7FFF H'8000
H'7FFF
External address space
H'FB7F H'FB80 H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF
On-chip RAM*, 1024 byte External address space On-chip register field
H'FB7F H'FB80 H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF
On-chip RAM*, 1024 byte External address space
H'FB80 H'FF7F
On-chip RAM, 1024 byte
H'FF90 On-chip register field H'FFFF On-chip register field
Note: External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3214 Address Space
Mode Expanded mode without on-chip H'0000 Vector table H'0063 H'0064 H'0063 H'0064 H'0000
Mode Expanded mode with on-chip H'0000 Vector table H'0063 H'0064
Mode Single-chip mode
Vector table
On-chip ROM, 16384 bytes
On-chip ROM, 16384 bytes
External address space H'3FFF H'4000 Reserved*2 H'7FFF H'8000 External address space H'B77F H'B780 Reserved*1, H'FD7F H'FD80 H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'FD7F H'FD80 H'FF7F H'FF80 H'FF8F H'FF90 H'FFFF H'FB7F H'FB80 Reserved*1, H'FD7F H'FD80 On-chip RAM, bytes H'FF7F External address space H'FF90 On-chip register field H'FFFF On-chip register field H'FB80 Reserved*2 H'7FFF H'3FFF
Reserved*2
On-chip RAM*1, bytes External address space On-chip register field
On-chip RAM*1, bytes
Notes: External memory accessed these addresses when RAME system control register (SYSCR) cleared Data read write permitted these modes.
Figure H8/3212 H8/3202 Address Space
Section Exception Handling
[Key-sense interrupt function incorporated models except H8/3212] Note that H8/3212 does have IRQ6 interrupt function controlled KEYIN0 KEYIN7 input signals KMIMR register.
Overview
H8/3217 Series recognizes only kinds exceptions: interrupts reset. Table indicates their priority timing their hardware exception-handling sequence. Table
Priority High
Reset Interrupt Exceptions
Type Exception Reset Detection Timing Clock synchronous Timing Exception-Handling Sequence When goes low, chip enters reset state immediately. hardware exceptionhandling sequence (reset sequence) begins soon goes high again. When interrupt requested, hardware exception-handling sequence (interrupt sequence) begins current instruction, current hardware exception-handling sequence.
Interrupt
completion instruction execution*
Note: detected case ANDC, ORC, XORC, instructions.
4.2.1
Reset
Overview
reset highest exception-handling priority. When goes watchdog reset started (watchdog timer overflow which reset option selected), current processing stops chip enters reset state. internal state registers on-chip supporting modules initialized. When returns from high watchdog reset pulse ends, chip comes reset state reset exception-handling sequence.
4.2.2
Reset Sequence
reset state begins when goes watchdog reset occurs. ensure correct resetting, power-on should held least reset during operation, should held least system clock cycles. watchdog reset pulse width always system clock cycles. details states reset, appendix States. When reset exception handling started, hardware carries following reset sequence. condition code register (CCR), mask interrupts. registers ports on-chip supporting modules initialized. loads program counter with first word vector table (stored addresses H'0000 H'0001) starts program execution.
should held when power switched off, well when power switched Figure indicates timing reset sequence when vector table reset routine located on-chip (mode Figure indicates timing when they off-chip memory (mode
Vector fetch RES/watchdog reset (internal) Internal address Internal read signal Internal write signal Internal data bits)
Internal Instruction processing prefetch
Reset exception handling vector address (H'0000) Program start address First instruction program
Figure Reset Sequence (Mode Program Area On-Chip ROM)
Vector fetch Internal processing Instruction prefetch
RES/watchdog reset (internal)
Figure Reset Sequence (Mode
bits)
(1), (2), (5), (6),
Reset exception handling vector address: H'0000, H'0001 Start address (contents reset exception handling vector address): upper byte, lower byte Start address: (4), First instruction program: first byte, second byte
4.2.3
Disabling Interrupts after Reset
interrupts, including NMI, disabled immediately after reset. first program instruction, located address specified vector table, therefore always executed. prevent program crashes, this instruction should initialize stack pointer (example: MOV.W #xx:16, SP). After execution this instruction, interrupt enabled. Other interrupts remain disabled until their enable bits After reset exception handling, manipulation instruction executed contents before instruction that initializes stack pointer. After manipulation instruction executed, interrupts, including NMI, disabled. next instruction should instruction that initializes stack pointer.
4.3.1
Interrupts
Overview
There twelve input pins five external interrupt sources (NMI, IRQ0 IRQ2, IRQ6). There also internal interrupts originating on-chip. features these interrupts are: internal external interrupts except masked CCR. IRQ0 IRQ2 falling-edge-sensed level-sensed. type sensing selected each interrupt individually. edge-sensed, either rising falling edge selected. Interrupts individually vectored. software interrupt-handling routine does have determine what type interrupt occurred. IRQ6 requested eight external sources (KEYIN0 KEYIN7). KEYIN0 KEYIN7 masked individually user program. watchdog timer made generate interrupt interrupt according use. details, section Watchdog Timer. Table lists interrupts their order priority gives their vector numbers addresses their entries vector table.
Table
Interrupts
(KEYIN0 KEYIN (except H8/3212) Address Entry Vector Table Priority H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'0013 H'0014 H'0015 High
Interrupt Source IRQ0 IRQ1 IRQ2 Reserved IRQ6 Reserved Host interface (except H8/3212) 16-bit free-running timer 8-bit timer IBF1 (IDR1 reception complete) IBF2 (IDR2 reception complete) OCIA OCIB FOVI (Input capture) (Output compare (Output compare (Overflow)
H'0016 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'0032 H'0033 H'0034 H'0035 H'0036 H'0037 H'0038 H'0039 H'003A H'003B H'003C H'003D H'003E H'003F H'0040 H'0041 H'0042 H'0043 H'0044 H'0045 H'0046 H'0047 H'0048 H'0049
CMI0A (Compare-match CMI0B (Compare-match OVI0 (Overflow) CMI1A (Compare-match CMI1B (Compare-match OVI1 (Overflow) ERI0 RXI0 TXI0 TEI0 ERI1 RXI1 TXI1 TEI1 (Receive error) (Receive end) (TDR empty) (TSR empty) (Receive error) (Receive end) (TDR empty) (TSR empty)
8-bit timer
Serial communication interface Serial communication interface (except H8/3212) Reserved Watchdog timer interface
H'004A H'0057 WOVF (WDT overflow) IICI0 IICI1 (Transfer end) (Transfer end) H0058 H'0059 H'005A H'005B H'005C H'005D
interface (except H8/3202) 8-bit timer (except H8/3202)
CMIXA (Compare-match CMIXB (Compare-match OVIX (Overflow)
H'005E H'005F H'0060 H'0061 H'0062 H'0063
Notes:
H'0000 H'0001 contain reset vector. H'0002 H'0005 reserved H8/3217 Series available user. interface option.
4.3.2
Interrupt-Related Registers
interrupt-related registers system control register (SYSCR), sense control register (ISCR), enable register (IER), keyboard matrix interrupt mask register (KMIMR). Table
Name System control register sense control register enable register Keyboard matrix interrupt mask register
Registers Read Interrupt Controller
Abbreviation SYSCR ISCR KMIMR Read/Write Address H'FFC4 H'FFC6 H'FFC7 H'FFF1
System Control Register (SYSCR)-H'FFC4
Initial value Read/Write SSBY STS2 STS1 STS0 XRST NMIEG RAME
2-Nonmaskable Interrupt Edge (NMIEG): Determines whether nonmaskable interrupt generated falling rising edge input signal.
NMIEG Description interrupt generated falling edge interrupt generated rising edge (Initial value)
section 3.2, System Control Register (SYSCR), information other SYSCR bits.
Sense Control Register (ISCR)-H'FFC6
Initial value Read/Write IRQ6SC
IRQ2SC IRQ1SC IRQ0SC
Bits 6-IRQ0 IRQ2, IRQ6 Sense Control (IRQ0SC IRQ2SC, IRQ6SC): These bits select input pins IRQ0 IRQ2 KEYIN0 KEYIN7 sensed.
IRQiSC Description level IRQ0 IRQ2 KEYIN0 KEYIN7 generates interrupt request falling edge IRQ0 IRQ2 KEYIN0 KEYIN7 generates interrupt request (Initial value)
Enable Register (IER)-H'FFC7
Initial value Read/Write IRQ6E IRQ2E IRQ1E IRQ0E
Bits 6-IRQ0 IRQ2 Enable (IRQ0E IRQ2E, IRQ6E): These bits enable disable IRQ1, IRQ2, IRQ6 interrupts individually.
IRQiE Description IRQ0 IRQ6 disabled IRQ0 IRQ6 enabled (Initial value)
When edge sensing selected setting bits IRQ0SC IRQ2SC IRQ6SC possible interrupt-handling routine executed even though corresponding enable (IRQ0E IRQ2E IRQ6E) cleared interrupt disabled. interrupt requested while enable (IRQ0E IRQ2E IRQ6E) request will held pending until served. enable cleared while request still pending, request will remain pending, although requests will recognized. interrupt mask cleared interrupt-handling routine executed even though enable
execution interrupt-handling routines under these conditions desired, avoided using following procedure disable clear interrupt requests. CCR, masking interrupts. Note that automatically when execution jumps interrupt vector. Clear desired bits from IRQ0E, IRQ1E, IRQ2E, IRQ6E disable interrupt requests. Clear corresponding bits from IRQ0SC, IRQ1SC, IRQ2SC, IRQ6SC then them again. Pending IRQn interrupt requests cleared when CCR, IRQnSC IRQnE
Keyboard Matrix Interrupt Mask Register (KMIMR) KMIMR 8-bit readable/writable register used keyboard matrix scanning sensing. enable key-sense input interrupts from more pins during keyboard scanning sensing, clear corresponding mask bits
Initial value Read/Write
KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0
Bits 0-Keyboard Matrix Interrupt Mask (KMIMR7 KMIMR0): These bits control key-sense input interrupt requests KEYIN7 KEYIN0.
Bits KMIMR7 KMIMR0 Description Key-sense input interrupt request enabled. Key-sense input interrupt request disabled. (Initial value)
Figure shows relationship between IRQ6 interrupt KMIMR.
KMIMR0 P60/KEYIN0 IRQ6 internal signal KMIMR1 P61/KEYIN1
Edge/level select enable/ disable control IRQ6E IRQ6SC
IRQ6 interrupt
KMIMR6 P72/KEYIN6
KMIMR7 P73/KEYIN7
Initial values given parentheses
Figure KMIMR IRQ6 Interrupt 4.3.3 External Interrupts
There five external interrupts: NMI, IRQ2, IRQ6. These used return from software standby mode. NMI: highest-priority interrupt, always accepted regardless value CCR. Interrupts from edge-sensed: rising edge falling edge specified NMIEG SYSCR. exception handling vector number exception handling sets IRQ0 IRQ2 IRQ6: Interrupts IRQ0 IRQ2 requested input signals pins IRQ0 IRQ2. IRQ6 interrupt requested input signals pins KEYIN0 KEYIN7. Interrupts IRQ2 specified falling-edge-sensed level-sensed bits IRQ0SC IRQ2SC IRQ6SC ISCR. Interrupt requests enabled bits IRQ0E IRQ2E IRQ6E IER. Interrupts masked setting CCR.
IRQ6 input signal generated logical key-sense inputs. When pins KEYIN0 KEYIN7 (P60 P73) used key-sense inputs, corresponding KMIMR bits should cleared enable corresponding key-sense interrupts. KMIMR bits corresponding unused key-sense inputs should disable those interrupts. eight key-sense input interrupts combined into single IRQ6 interrupt. When these interrupts accepted, IRQ0 IRQ2 have interrupt vector numbers They prioritized order from IRQ6 (low) IRQ0 (high). details, table 4-2. Interrupts IRQ2 depend whether pins IRQ0 IRQ2 KEYIN0 KEYIN7 used input pins output pins. When interrupts IRQ2 requested external signal, clear corresponding bits pins input/output pins. 4.3.4 Internal Interrupts
Twenty-six internal interrupts requested on-chip supporting modules. them masked when set. addition, they enabled disabled bits control registers on-chip supporting modules. When these interrupts accepted, mask further interrupts (except NMI). vector numbers these interrupts priority order these interrupts, table 4-2. 4.3.5 Interrupt Handling
Interrupts controlled interrupt controller that arbitrates between simultaneous interrupt requests, commands start hardware interrupt exception-handling sequence, furnishes necessary vector number. Figure shows block diagram interrupt controller.
interrupt IRQ0 flag IRQ0E IRQ0 interrupt Priority decision
Interrupt controller
Interrupt request
Vector number
OVIE
interrupt
(CCR)
Note: edge-sensed interrupts, these gates change circuit shown below. IRQ0 edge IRQ0E IRQ0 flag
IRQ0 interrupt
Figure Block Diagram Interrupt Controller interrupts interrupts from on-chip supporting modules (except reset selected watchdog timer overflow) have corresponding enable bits. When enable cleared interrupt signal sent interrupt controller, interrupt ignored. These interrupts also masked setting CPU's interrupt mask Accordingly, these interrupts accepted only when their enable cleared nonmaskable interrupt (NMI) always accepted, except reset state hardware standby mode. When another enabled interrupt requested, interrupt controller transfers interrupt request indicates corresponding vector number. (When more interrupts requested, interrupt controller selects vector number interrupt with highest priority.) When notified interrupt request, current instruction current hardware exception-handling sequence, starts hardware exception-handling sequence interrupt latches vector number.
Figure flowchart interrupt (and reset) operations. Figure shows interrupt timing sequence case which software interrupt-handling routine on-chip stack on-chip RAM. interrupt request sent interrupt controller when interrupt occurs, when interrupt occurs input line on-chip supporting module provided enable that interrupt interrupt controller checks accepts interrupt request cleared only requests accepted; other interrupt requests remain pending. Among accepted interrupt requests, interrupt controller selects request with highest priority passes CPU. Other interrupt requests remain pending. When receives interrupt request, waits until completion current instruction hardware exception-handling sequence, then starts hardware exceptionhandling sequence interrupt latches interrupt vector number. hardware exception-handling sequence, first pushes onto stack. figure 4-6. stacked indicates address first instruction that will executed return from software interrupt-handling routine. Next masking further interrupts except NMI. vector address corresponding vector number generated, vector table entry this vector address loaded into program counter, execution branches software interrupt-handling routine address indicated that entry.
Program execution
Interrupt requested? NMI?
IRQ0? IRQ1? OVI? Pending
Latch vector
Save
Reset
Save
Read vector address
Branch software interrupt-handling routine
Figure Hardware Interrupt-Handling Sequence
(R7) Stack area
SP(R7)
CCR*
(upper byte)
(lower byte) Even address
Before interrupt accepted
Pushed onto stack
After interrupt accepted
Program counter CCR: Condition code register Stack pointer Notes: contains address first instruction executed after return. Registers must saved restored word access even address. Ignored return.
Figure Usage Stack Interrupt Handling Although consists only byte, treated word data when pushed stack. hardware interrupt exception-handling sequence, identical bytes pushed onto stack make complete word. When popped from stack instruction, loaded from byte stored even address. byte stored address ignored.
Interrupt accepted Interrupt priority decision. Wait Instruction Internal instruction prefetch processing Interrupt request signal Vector table fetch
Stack
Instruction prefetch (first instruction Internal interrupt-handling process- routine)
Internal address
Internal read signal Internal write signal
Internal 16-bit data
(10)
Instruction prefetch address (Instruction executed. Address saved contents, becoming return address.) Instruction code (Not executed) Instruction prefetch address (Not executed) SP-2 SP-4 Vector address Start address interrupt-handling routine (contents vector) (10) First instruction interrupt-handling routine
Figure Timing Interrupt Sequence
4.3.6
Interrupt Response Time
Table indicates time that elapses from interrupt request signal until first instruction software interrupt-handling routine executed. Since H8/3217 Series accesses onchip memory bits time, very fast interrupt service obtained placing interrupthandling routines on-chip stack on-chip RAM. Table Number States before Interrupt Service
Number States Reason wait Interrupt priority decision Wait completion current instruction*1 Save Fetch vector Fetch instruction Internal processing Total Notes: On-Chip Memory External Memory 12*2 12*2
These values apply current instruction EEPMOV instruction. wait states inserted external memory access, these values longer. internal interrupts.
4.3.7
Precaution
Note that following type contention occur interrupt handling. When software clears enable interrupt disable interrupt, interrupt becomes disabled after execution clearing instruction. enable cleared BCLR instruction, example, interrupt requested during execution that instruction, instant when instruction ends interrupt still enabled, after execution instruction, hardware exception-handling sequence executed interrupt. higher-priority interrupt requested same time, however, hardware exception-handling sequence executed higher-priority interrupt interrupt that disabled ignored. Similar considerations apply when interrupt request flag cleared Figure shows example which OCIAE cleared
write cycle TIER Internal address TIER address
OCIA interrupt handling
Internal write signal OCIAE OCFA OCIA interrupt signal
Figure Contention between Interrupt Disabling Instruction above contention does occur enable flag cleared while interrupt mask
Note Stack Handling
word access, least significant address always assumed stack always accessed word access. Care should taken keep even value stack pointer (general register R7). PUSH MOV.W @-SP MOV.W @SP+, instructions push registers stack. Setting stack pointer value cause programs crash. Figure shows example damage caused when stack pointer contains address.
H'FECC H'FECD
H'FECF
instruction
MOV.B R1L, @-R7
H'FEFF
Stack accessed beyond
lost
PCH: PCL: R1L:
Upper byte program counter Lower byte program counter General register Stack pointer
Figure Example Damage Caused Setting Address
Notes Key-Sense Interrupts
H8/3217 Series incorporates key-sense interrupt function which used operating mode. When used mode other than slave mode (when host interface disabled), following points must noted. order key-sense interrupt function, necessary write KMIMR unmask relevant KEYIN pins. pull-up transistors provided pins P60, KMPCR must also written KMIMR KMPCR only accessed when SYSCR Consequently, chip slave mode during this period. slave mode, states vary. When KMIMR KMPCR initialization routine directly after reset External circuitry must used such that problem will caused irrespective whether host interface output pins retain high-impedance state output
state. There four host interface output pins-GA20, HIRQ12, HIRQ1, HIRQ11-all which port function (input state) initially. There eight host interface pins, HDB7 HDB0; single-chip mode, these outputs when P76/IOR either one, both, P75/CS1 P45/CS2 pins low. expanded mode, these pins function data pins D0), therefore states vary. When KMIMR KMPCR other than initialization routine states host interface input pins, pins with which they multiplexed, vary result setting bit. P77/HA0, 6/IOR, P75/IOW, 5/CS1, 6/CS2, P37/HDB7 P30/HDB0 automatically become input pins pins. When particular used, designated port input expanded control pin, single-chip mode, necessary prevent occurrence level P76/IOR together with level P75/CS1 P46/CS2 pin, both. expanded mode, external space accessed when both 6/IOR/RD P75/CS1/AS driven automatically. Note that output values P44/HIRQ12, P43/HIRQ1, P42/HIRQ11 vary result.
Section Wait-State Controller
Overview
H8/3217 Series on-chip wait-state controller that enables insertion wait states into cycles interfacing low-speed external devices. 5.1.1 Features
Features wait-state controller listed below. Three selectable wait modes: programmable wait mode, auto-wait mode, wait mode Automatic insertion zero three wait states 5.1.2 Block Diagram
Figure shows block diagram wait-state controller.
Internal data
Wait request signal
WAIT
Wait-state controller (WSC) WSCR
Legend WSCR: Wait-state control register
Figure Block Diagram Wait-State Controller
5.1.3
Input/Output Pins
Table summarizes wait-state controller's input pin. Table
Name Wait
Wait-State Controller Pins
Abbreviation WAIT Input Function Wait request signal access external addresses
5.1.4
Register Configuration
Table summarizes wait-state controller's register. Table
Name Wait-state control register
Register Configuration
Abbreviation WSCR Initial Value H'C8 Address H'FFC2
5.2.1
Register Description
Wait-State Control Register (WSCR)
WSCR 8-bit readable/writable register that selects wait mode wait-state controller (WSC) specifies number wait states. also controls frequency division clock signals supplied supporting modules.
Initial value Read/Write CKDBL WMS1 WMS0
WSCR initialized H'C8 reset hardware standby mode. initialized software standby mode.
Bits 6-Reserved: These bits cannot modified always read 5-Clock Double (CKDBL): Controls frequency division clock signals supplied supporting modules. details, section Clock Pulse Generator. 4-Reserved: This reserved, written read. initial value Bits 2-Wait Mode Select (WMS1 WMS0): These bits select wait mode.
WMS1 WMS0 Description Programmable wait mode wait states inserted wait-state controller wait mode auto-wait mode (Initial value)
Bits 0-Wait Count (WC1 WC0): These bits select number wait states inserted access external address areas.
Description wait states inserted wait-state controller state inserted states inserted states inserted (Initial value)
Wait Modes
Programmable Wait Mode: number wait states selected bits inserted accesses external addresses. Figure shows timing when wait count (WC1
Address
External address
Read access Data Read data
Write access Data Write data
Figure Programmable Wait Mode
Wait Mode: accesses external addresses, number wait states (TW) selected bits inserted. WAIT fall system clock last these wait states, additional wait state inserted. WAIT remains low, wait states continue inserted until WAIT signal goes high. wait mode useful inserting four more wait states, inserting different numbers wait states different external devices. Figure shows timing when wait count (WC1 additional wait state inserted WAIT input.
Inserted wait count
Inserted WAIT
WAIT Address External address
Read access
Read data Data
Write access Data Write data
Note: Arrows indicate time sampling WAIT pin.
Figure Wait Mode
Auto-Wait Mode: WAIT low, number wait states (TW) selected bits inserted. auto-wait mode, WAIT fall system clock state, number wait states selected bits inserted. additional wait states inserted even WAIT remains low. auto-wait mode used easy interface low-speed memory, simply routing chip select signal WAIT pin. Figure shows timing when wait count
WAIT
Address
External address
External address
Read access Data Read data Read data
Write access Data Write data Write data
Note: Arrows indicate time sampling WAIT pin.
Figure Auto-Wait Mode
Section Clock Pulse Generator
Overview
H8/3217 Series built-in clock pulse generator (CPG) consisting oscillator circuit, duty adjustment circuit, prescaler that generates clock signals on-chip supporting modules. 6.1.1 Block Diagram
Figure shows block diagram clock pulse generator.
XTAL EXTAL
Oscillator circuit
Duty adjustment circuit
(system clock)
(for supporting modules) Prescaler
Frequency divider (1/2) CKDBL
Figure Block Diagram Clock Pulse Generator Input external clock signal EXTAL pin, connect crystal resonator XTAL EXTAL pins. system clock frequency will same input frequency. This same system clock frequency supplied timers other supporting modules, divided two. selection made software, controlling CKDBL bit.
6.1.2
Wait-State Control Register (WSCR)
WSCR 8-bit readable/writable register that controls frequency division clock signals supplied supporting modules. also controls wait-state insertion. WSCR initialized H'C8 reset hardware standby mode. initialized software standby mode.
Initial value Read/Write CKDBL WMS1 WMS0
Bits 6-Reserved: These bits cannot modified always read 5-Clock Double (CKDBL): Controls frequency division clock signals supplied supporting modules.
CKDBL Description undivided system clock supplied clock supporting modules (Initial value)
system clock divided supplied clock supporting modules
4-Reserved: This reserved, written read. initial value Bits 2-Wait Mode Select (WMS1 WMS0) Bits 0-Wait Count (WC1 WC0) These bits control wait-state insertion. details, section Wait-State Controller.
Oscillator Circuit
external crystal connected across EXTAL XTAL pins, on-chip oscillator circuit generates system clock signal. Alternatively, external clock signal applied EXTAL pin. Connecting External Crystal Circuit Configuration: external crystal connected shown example figure Table indicates appropriate damping resistance AT-cut parallel resonance crystal should used.
EXTAL
XTAL
Figure Connection Crystal Oscillator (Example) Table Damping Resistance
Frequency (MHz)
Crystal Oscillator: Figure shows equivalent circuit crystal resonator. crystal resonator should have characteristics listed table 6-2.
XTAL EXTAL
AT-cut parallel resonating crystal
Figure Equivalent Circuit External Crystal Table External Crystal Parameters
Frequency (MHz) (pF)
crystal with same frequency desired system clock frequency
Note Board Design: When external crystal connected, other signal lines should kept away from crystal circuit prevent induction from interfering with correct oscillation. figure 6-4. crystal load capacitors should placed close possible XTAL EXTAL pins.
allowed
Signal
Signal
XTAL
EXTAL
Figure Notes Board Design around External Crystal
Input External Clock Signal Circuit Configuration: external clock signal input shown examples figure 6-5. example figure 6-5, external clock signal should kept high during standby. XTAL left open, make sure stray capacitance does exceed
EXTAL
External clock input
XTAL
Open
Connections with XTAL left open
EXTAL 74HC04 XTAL
External clock input
Connections with inverted clock input XTAL
Figure External Clock Input (Example)
External Clock Input: external clock signal should have same frequency desired system clock Clock timing parameters given table figure 6-6. Table Clock Timing
Item pulse width external clock input High pulse width external clock input External clock rise time External clock fall time Symbol ±10% Unit Test Conditions Figure
Clock pulse width Clock pulse width high
Figure 19-4
tEXH
tEXL
EXTAL
tEXr
tEXf
Figure External Clock Input Timing
Table shows external clock output settling delay time, figure shows external clock output settling delay timing. oscillator circuit duty adjustment circuit have function adjusting waveform external clock input EXTAL pin. When specified clock signal input EXTAL pin, internal clock signal output fixed after elapse external clock output settling delay time (tDEXT). clock signal output fixed during tDEXT period, reset signal should driven maintain reset state during this time. Table External Clock Output Settling Delay Time
(Conditions: AVCC AVSS
Item External clock output settling delay time Symbol DEXT Unit Notes Figure
Note: DEXT includes pulse width RESW)
STBY
EXTAL (internal external) tDEXT*
Note: tDEXT includes pulse width (tRESW) tcyc
Figure External Clock Output Settling Delay Time Timing
Duty Adjustment Circuit
When clock frequency above, duty adjustment circuit adjusts duty cycle signal from oscillator circuit generate system clock
Prescaler
frequency divider generates on-chip supporting module clock from system clock according setting CKDBL bit. prescaler divides frequency generate internal clock signals with frequencies from
Section Ports
Overview
H8/3217 Series five 8-bit input/output ports, 7-bit input/output port, 6-bit input/output port. Table lists functions each port each operating mode. table indicates, port pins multiplexed, functions differ depending operating mode. Each port data direction register (DDR) that selects input output, data register (DR) that stores output data. manipulation instructions will executed port data direction registers, "Notes Manipulation Instructions" section 2.5.5, Manipulations. Ports drive load 90-pF capacitive load. Port (excluding port drive load 30-pF capacitive load. Ports drive LEDs (with 10-mA current sink). Ports drive Darlington transistor. Ports pins have built-in pull-ups. Pins (including SDA) port drive buffer. section Interface, details buffer driving. Note that H8/3212 H8/3202 have subset specification that does include certain on-chip supporting modules. tables 1-4, Assignments Each Operating Mode, table 7-1, Port Functions, differences functions. block diagrams ports, appendix Port Block Diagrams.
Table H8/3217, H8/3216, H8/3214 Port Functions
Expanded Modes Port Port Description 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port Pins Mode Lower address output Mode Lower address output A0), general input, timer output (PW7 PW0) Upper address output A8), general input, timer output (PW15 PW8) Single-Chip Mode Mode timer output (PW7 PW0) general input/output
Port
PW15
Upper address output
timer output (PW15 PW8) general input/output
Port
Data HDB7
Host interface data (HDB7 HDB0) general input/ output
Port
P47/TMOx/ CLAMPO/ GA20 FBACKI/CS
Host interface control output (GA20), 8-bit timer output (TMO general input/output, timer connection output (CLAMPO) output Host interface control input general input, timer connection input (FBACKI), output
P45/TMRI1/ CSYNCI/ HIRQ12 P44/TMO1/ HSYNCO/ HIRQ1 P43/TMCI1/ HSYNCI/ HIRQ11 P42/TMRI0 P41/TMO0 P40/TMCI0
Host interface host interrupt request output (HIRQ12, HIRQ1, HIRQ11), 8-bit timer input/output (TMCI TMO0, TMRI0, TMCI1, TMO1, TMRI1), timer connection input/output (CSYNCI, HSYNCO, HSYNCI), general input/output
Table H8/3217, H8/3216, H8/3214 Port Functions (cont)
Expanded Modes Port Port Description 6-bit port Pins P55/SCK1 P54/RxD1 P53/TxD1 P52/SCK0 P51/RxD0 P50/TxD0 P66/IRQ2 P65/IRQ1 P64/IRQ0 P63/FTI/ VSYNCI/ KEYIN3 P62/FTOB/ VSYNCO/ KEYIN2 P61/FTOA/ KEYIN1 P60/FTCI/ KEYIN0 Port 8-bit port buffer drive capability (P73 Built-in input pull-ups (P73 P70) Mode Mode Single-Chip Mode Mode
Serial communication interface input/output (TxD0, RxD0, TxD1, RxD1, 6-bit general input/output
Port
7-bit port Built-in input pull-ups (P63
IRQ2 IRQ0 general input/output
16-bit free-running timer input/output (FTCI, FTOA, FTOB, FTI), timer connection input/output (VSYNCI, VSYNCO), general input/output (Can also used key-scanning key-sense input (KEYIN3 KEYIN0))
P77/WAIT/ Expanded data control input/ output (WAIT, P76/RD/IOR P75/WR/IOW P74/AS/CS
Host interface control input/ output (HA0, IOR, IOW, general input/ output
P73/SDA1/ KEYIN7 P72/SCL1/ KEYIN6 P71/SDA0/ KEYIN5 P70/SCL0/ KEYIN4
interface input/output (SDA SCL0, general input/output (Can also used key-scanning key-sense input (KEYIN7 KEYIN4))
Table H8/3212 Port Functions
Expanded Modes Port Port Description 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port Pins Mode Lower address output Mode Lower address output A0), general input, timer output (PW7 PW0) Upper address output A8), general input, timer output (PW15 PW8) Single-Chip Mode Mode timer output (PW7 PW0) general input/output
Port
PW15
Upper address output
timer output (PW15 PW8) general input/output
Port
Data
General input/ output
Port
P47/TMOX/ CLAMPO FBACKI
8-bit timer output (TMOX), general input/output, timer connection output (CLAMPO) output General input, timer connection input (FBACKI), output
P45/TMRI1/ CSYNCI P44/TMO1/ HSYNCO P43/TMCI1/ HSYNCI P42/TMRI0 P41/TMO0 P40/TMCI0
8-bit timer input/output (TMCI TMO0, TMRI0, TMCI1, TMO1, TMRI1), timer connection input/output (CSYNCI, HSYNCO, HSYNCI), general input/ output
Table H8/3212 Port Functions (cont)
Expanded Modes Port Port Description 6-bit port Pins P52/SCK0 P51/RxD0 P50/TxD0 P66/IRQ2 P65/IRQ1 P64/IRQ0 P63/FTI/ VSYNCI P62/FTOB/ VSYNCO P61/FTOA P60/FTCI Port 8-bit port buffer drive capability (P73 P77/WAIT P76/RD P75/WR P74/AS P73/SDA1 P72/SCL1 P71/SDA0 P70/SCL0 Mode Mode Single-Chip Mode Mode
Serial communication interface input/output (TxD0, RxD0, 6-bit general input/output
Port
7-bit port
IRQ2 IRQ0 general input/output
16-bit free-running timer input/output (FTCI, FTOA, FTOB, FTI), timer connection input/output (VSYNCI, VSYNCO), general input/output
Expanded data control input/output (WAIT,
General input/ output
interface input/output (SDA general input/output
Table H8/3202 Port Functions
Expanded Modes Port Port Description 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port Pins Mode Lower address output Mode Lower address output general input Single-Chip Mode Mode General input/ output
Port
Upper address output
Upper address output general input
General input/ output
Port
Data HDB7
Host interface data (HDB7 HDB0) general input/ output
Port
P47/GA
Host interface control output (GA20) general input/ output output Host interface control input general input, output
P45/TMRI1/ HIRQ12 P44/TMO1/ HIRQ1 P43/TMCI1/ HIRQ11 P42/TMRI0 P41/TMO0 P40/TMCI0
Host interface host interrupt request output (HIRQ12, HIRQ1, HIRQ11), 8-bit timer input/ output (TMCI0, TMO0, TMRI0, TMCI1, TMO1, TMRI1), general input/output
Table H8/3202 Port Functions (cont)
Expanded Modes Port Port Description 6-bit port Pins P55/SCK1 P54/RxD1 P53/TxD1 P52/SCK0 P51/RxD0 P50/TxD0 P66/IRQ2 P65/IRQ1 P64/IRQ0 P63/FTI/ KEYIN3 P62/FTOB/ KEYIN2 P61/FTOA/ KEYIN1 P60/FTCI/ KEYIN0 Port 8-bit port buffer drive capability (P73 Built-in input pull-ups (P73 P70) Mode Mode Single-Chip Mode Mode
Serial communication interface input/output (TxD0, RxD0, TxD1, RxD1, 6-bit general input/output
Port
7-bit port Built-in input pull-ups (P63 P60)
IRQ2 IRQ0 general input/output
16-bit free-running timer input/output (FTCI, FTOA, FTOB, FTI) general input/output (Can also used key-scanning key-sense input (KEYIN3 KEYIN0))
P77/WAIT/ Expanded data control input/ output (WAIT, P76/RD/IOR P75/WR/IOW P74/AS/CS
Host interface control input (HA0, IOR, IOW, general input/output
P73/KEYIN7 P72/KEYIN6 P71/SDA0/ KEYIN5 P70/SCL0/ KEYIN4
interface input/output (SDA general input/output (Can also used key-scanning key-sense input (KEYIN7 KEYIN4))
7.2.1
Port
Overview
Port 8-bit input/output port with configuration shown figure 7-1. functions differ depending operating mode. Port built-in programmable input pull-ups that used modes Pins port drive load 90-pF capacitive load. They also drive LEDs Darlington transistors.
Port pins P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 Port P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0
configuration mode (expanded mode with on-chip disabled) (output) (output) (output) (output) (output) (output) (output) (output)
configuration mode (expanded mode with on-chip enabled) (output)/P17 (input)/PW7 (output) (output)/P16 (input)/PW6 (output) (output)/P15 (input)/PW5 (output) (output)/P14 (input)/PW4 (output) (output)/P13 (input)/PW3 (output) (output)/P12 (input)/PW2 (output) (output)/P11 (input)/PW1 (output) (output)/P10 (input)/PW0 (output)
configuration mode (single-chip mode) (input/output)/PW7 (output) (input/output)/PW6 (output) (input/output)/PW5 (output) (input/output)/PW4 (output) (input/output)/PW3 (output) (input/output)/PW2 (output) (input/output)/PW1 (output) (input/output)/PW0 (output)
Figure Port Configuration
7.2.2
Register Configuration Descriptions
Table summarizes port registers. Table
Name Port data direction register Port data register Port input pull-up control register
Port Registers
Abbreviation P1DDR P1DR P1PCR Read/Write Initial Value Address
H'FF (mode H'FFB0 H'00 (modes H'00 H'00 H'FFB2 H'FFAC
Port Data Direction Register (P1DDR)
Mode Initial value Read/Write Modes Initial value Read/Write
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
P1DDR controls input/output direction each port Mode P1DDR values fixed Port consists lower address output pins. P1DDR values cannot modified always read hardware standby mode,
Other recent searches
TNETA1560 - TNETA1560 TNETA1560 Datasheet
LPC2926 - LPC2926 LPC2926 Datasheet
2927 - 2927 2927 Datasheet
2929 - 2929 2929 Datasheet
LM27CIM5-2HJ - LM27CIM5-2HJ LM27CIM5-2HJ Datasheet
FSS923A0D - FSS923A0D FSS923A0D Datasheet
FSS923A0R - FSS923A0R FSS923A0R Datasheet
DTB513ZE - DTB513ZE DTB513ZE Datasheet
DTB513ZM - DTB513ZM DTB513ZM Datasheet
74VHC574 - 74VHC574 74VHC574 Datasheet
74LVC1G57 - 74LVC1G57 74LVC1G57 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
