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H8S/2655 Series H8S/2655
HD6432655, HD6472655,
H8S/2653
HD6432653
Hardware Manual
ADE-602-094C Rev. 3/6/03 Hitachi, Ltd. MC-Setsu
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Preface
H8S/2655 Series series high-performance microcontrollers with 32-bit H8S/2600 core, on-chip supporting functions required system configuration. H8S/2600 execute basic instructions state, provided with sixteen 16-bit general registers with 32-bit internal configuration, concise optimized instruction set. handle Mbyte linear address space (architecturally Gbytes). Programs based high-level language also efficiently. address space divided into eight areas. data width access states selected each these areas, various kinds memory connected fast easily. On-chip memory consists large-capacity RAM. PROM (ZTATTM*) mask versions available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. On-chip supporting functions include 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. addition, on-chip controller (DMAC) data transfer controller (DTC) provided, enabling high-speed data transfer without intervention. H8S/2655 Series enables compact, high-performance systems implemented easily. This manual describes hardware H8S/2655 Series. Refer H8S/2600 Series H8S/2000 Series Programming Manual detailed description instruction set. Note: ZTAT trademark Hitachi, Ltd.
Main Revisions Additions This Edition
Page Section Revision Contents 6.2.6. Memory Control Register (MCR): description Description amendments Figure 6-14 Example Wait State Insertion Timing Figure 6-47 Bus-Released State Transition Timing Table Register Functions Single Address Mode 7.5.8 DMAC Activation Sources Single Address Mode 10.2.1 Timer Control Register (TCR) 10.2.2 Timer Mode Register (TMDR) 10.2.3 Timer Control Register (TIOR) 10.2.8 Timer Start Register (TSTR) 10.7 Usage Notes: Contention between TCNT Write Overflow/Underflow 10.7 Usage Notes: Interrupts Module Stop Mode 14.2.9 Smart Card Mode Register (SCMR): description Figure 14-15 Sample Initialization Flowchart Figure 14-20 Sample Flowchart Simultaneous Serial Transmit Receive Operations 15.2.3 Serial Mode Register (SMR): description 15.2.4 Serial Control Register (SCR) Figure amended Figure amended Table amendments Description amendments Description amendments Descriptive text added Note amended Description amendments Descriptive text added addition Descriptive text added Note added Note amended Amended Amended
19.2.1 Control Register (BCRL): description Bits Added Figure 19-2 Wiring Socket Adapter Figure amended Table amendments Note deleted Note deleted Note deleted Note deleted Note deleted Note deleted Note deleted Figure amended
Table Instruction 1005 1006 1007 1008 1009 1010 1011 1026 Figure Port1 Block Diagram (Pins Figure Port1 Block Diagram (Pins P12, P13, P15, Figure Port1 Block Diagram (Pins P16) Figure Port2 Block Diagram (Pins Figure Port2 Block Diagram (Pins Figure Port2 Block Diagram (Pins P25) Figure Port2 Block Diagram (Pins Figure PortA Block Diagram (Pins
Page 1027 1028 1031 1032 1044, 1047
Section Figure PortA Block Diagram (Pin PA4) Figure PortA Block Diagram (Pins Figure C-10 PortD Block Diagram (Pin PDn) Figure C-11 PortE Block Diagram (Pin PEn) Table Port States Each Processing State Port Port
Revision Contents Figure amended Figure amended Figure amended Figure amended Table added
Contents
Section
Overview. Overview. Block Diagram Description. 1.3.1 Arrangement 1.3.2 Functions Each Operating Mode. 1.3.3 Functions
Section
Overview. 2.1.1 Features 2.1.2 Differences from H8/300 2.1.3 Differences from H8/300H Operating Modes Address Space. Register Configuration 2.4.1 Overview. 2.4.2 General Registers. 2.4.3 Control Registers 2.4.4 Initial Register Values Data Formats. 2.5.1 General Register Data Formats. 2.5.2 Memory Data Formats. Instruction 2.6.1 Overview. 2.6.2 Instructions Addressing Modes. 2.6.3 Table Instructions Classified Function. 2.6.4 Basic Instruction Formats Addressing Modes Effective Address Calculation. 2.7.1 Addressing Mode 2.7.2 Effective Address Calculation Processing States. 2.8.1 Overview. 2.8.2 Reset State 2.8.3 Exception-Handling State 2.8.4 Program Execution State 2.8.5 Bus-Released State. 2.8.6 Power-Down State Basic Timing.
2.9.1 2.9.2 2.9.3 2.9.4
Overview. On-Chip Memory (ROM, RAM). On-Chip Supporting Module Access Timing External Address Space Access Timing
Section
Operating Modes
Overview. 3.1.1 Operating Mode Selection 3.1.2 Register Configuration. Register Descriptions 3.2.1 Mode Control Register (MDCR). 3.2.2 System Control Register (SYSCR). Operating Mode Descriptions 3.3.1 Mode 3.3.2 Mode 3.3.3 Mode 3.3.4 Mode 3.3.5 Mode 3.3.6 Mode 3.3.7 Mode Functions Each Operating Mode Memory Each Operating Mode
Section
Exception Handling Overview. 4.1.1 Exception Handling Types Priority. 4.1.2 Exception Handling Operation 4.1.3 Exception Vector Table Reset. 4.2.1 Overview. 4.2.2 Reset Types. 4.2.3 Reset Sequence 4.2.4 Interrupts after Reset. Traces Interrupts Trap Instruction. Stack Status after Exception Handling Notes Stack. Interrupt Controller Overview. 5.1.1 Features 5.1.2 Block Diagram.
Section
5.1.3 Configuration. 5.1.4 Register Configuration. Register Descriptions 5.2.1 System Control Register (SYSCR). 5.2.2 Interrupt Control Registers (ICRA ICRC). 5.2.3 Interrupt Priority Registers (IPRA IPRK) 5.2.4 Enable Register (IER) 5.2.5 Sense Control Registers (ISCRH, ISCRL) 5.2.6 Status Register (ISR) Interrupt Sources. 5.3.1 External Interrupts 5.3.2 Internal Interrupts. 5.3.3 Interrupt Exception Handling Vector Table Interrupt Operation. 5.4.1 Interrupt Control Modes Interrupt Operation 5.4.2 Interrupt Control Mode 5.4.3 Interrupt Control Mode 5.4.4 Interrupt Control Mode 5.4.5 Interrupt Control Mode 5.4.6 Interrupt Exception Handling Sequence 5.4.7 Interrupt Response Times Usage Notes 5.5.1 Contention between Interrupt Generation Disabling 5.5.2 Instructions that Disable Interrupts. 5.5.3 Times when Interrupts Disabled 5.5.4 Interrupts during Execution EEPMOV Instruction DMAC Activation Interrupt. 5.6.1 Overview. 5.6.2 Block Diagram. 5.6.3 Operation
Section
Controller Overview. 6.1.1 Features 6.1.2 Block Diagram. 6.1.3 Configuration. 6.1.4 Register Configuration. Register Descriptions 6.2.1 Width Control Register (ABWCR) 6.2.2 Access State Control Register (ASTCR). 6.2.3 Wait Control Registers (WCRH, WCRL) 6.2.4 Control Register (BCRH) 6.2.5 Control Register (BCRL)
6.2.6 Memory Control Register (MCR) 6.2.7 DRAM Control Register (DRAMCR). 6.2.8 Refresh Timer/Counter (RTCNT) 6.2.9 Refresh Time Constant Register (RTCOR). Overview Control 6.3.1 Area Partitioning. 6.3.2 Specifications 6.3.3 Memory Interfaces. 6.3.4 Advanced Mode. 6.3.5 Areas Normal Mode. 6.3.6 Chip Select Signals Basic Interface 6.4.1 Overview. 6.4.2 Data Size Data Alignment. 6.4.3 Valid Strobes 6.4.4 Basic Timing. 6.4.5 Wait Control. DRAM Interface 6.5.1 Overview. 6.5.2 Setting DRAM Space. 6.5.3 Address Multiplexing. 6.5.4 Data Bus. 6.5.5 Pins Used DRAM Interface 6.5.6 Basic Timing. 6.5.7 Precharge State Control 6.5.8 Wait Control. 6.5.9 Byte Access Control 6.5.10 Burst Operation. 6.5.11 Caution Concerning 2-CAS System 6.5.12 Refresh Control. Pseudo-SRAM Interface 6.6.1 Overview. 6.6.2 Setting PSRAM Space. 6.6.3 Data Bus. 6.6.4 Pins Used PSRAM Interface 6.6.5 Basic Timing. 6.6.6 Precharge State Control 6.6.7 Wait Control. 6.6.8 Burst Operation. 6.6.9 Refresh Control. 6.6.10 Power-On Sequence. DMAC Single Address Mode DRAM/PSRAM Interface 6.7.1 When DDS=1.
6.10 6.11
6.12
6.13
6.7.2 When DDS=0. Burst Interface. 6.8.1 Overview. 6.8.2 Basic Timing. 6.8.3 Wait Control. Idle Cycle 6.9.1 Operation 6.9.2 States Idle Cycle Write Data Buffer Function Release. 6.11.1 Overview. 6.11.2 Operation 6.11.3 States External Released State 6.11.4 Transition Timing Arbitration. 6.12.1 Overview. 6.12.2 Operation 6.12.3 Transfer Timing 6.12.4 External Release Usage Note Resets Controller.
Section
Controller
Overview. 7.1.1 Features 7.1.2 Block Diagram. 7.1.3 Overview Functions. 7.1.4 Configuration. 7.1.5 Register Configuration. Register Descriptions (Short Address Mode). 7.2.1 Memory Address Registers (MAR). 7.2.2 Address Register (IOAR) 7.2.3 Execute Transfer Count Register (ETCR). 7.2.4 Control Register (DMACR) 7.2.5 Band Control Register (DMABCR) Register Descriptions (Full Address Mode) 7.3.1 Memory Address Register (MAR). 7.3.2 Address Register (IOAR) 7.3.3 Execute Transfer Count Register (ETCR). 7.3.4 Control Register (DMACR) 7.3.5 Band Control Register (DMABCR) Register Descriptions 7.4.1 Write Enable Register (DMAWER) 7.4.2 Terminal Control Register (DMATCR)
7.4.3 Module Stop Control Register (MSTPCR). Operation. 7.5.1 Transfer Modes 7.5.2 Sequential Mode 7.5.3 Idle Mode. 7.5.4 Repeat Mode 7.5.5 Single Address Mode. 7.5.6 Normal Mode. 7.5.7 Block Transfer Mode. 7.5.8 DMAC Activation Sources 7.5.9 Basic DMAC Cycles. 7.5.10 DMAC Cycles (Dual Address Mode). 7.5.11 DMAC Cycles (Single Address Mode) 7.5.12 Write Data Buffer Function 7.5.13 DMAC Multi-Channel Operation 7.5.14 Relation Between External Requests, Refresh Cycles, DTC, DMAC. 7.5.15 Interrupts DMAC 7.5.16 Forced Termination DMAC Operation 7.5.17 Clearing Full Address Mode. Interrupts Usage Notes
Section
Data Transfer Controller Overview. 8.1.1 Features 8.1.2 Block Diagram. 8.1.3 Register Configuration. Register Descriptions 8.2.1 Mode Register (MRA) 8.2.2 Mode Register (MRB). 8.2.3 Source Address Register (SAR) 8.2.4 Destination Address Register (DAR) 8.2.5 Transfer Count Register (CRA) 8.2.6 Transfer Count Register (CRB). 8.2.7 Enable Registers (DTCER). 8.2.8 Vector Register (DTVECR) 8.2.9 Module Stop Control Register (MSTPCR). Operation. 8.3.1 Overview. 8.3.2 Activation Sources. 8.3.3 Vector Table 8.3.4 Location Register Information Address Space.
8.3.5 Normal Mode. 8.3.6 Repeat Mode 8.3.7 Block Transfer Mode. 8.3.8 Chain Transfer 8.3.9 Operation Timing. 8.3.10 Number Execution States 8.3.11 Procedures Using DTC. 8.3.12 Examples DTC. Interrupts Usage Notes
Section
Ports Overview. Port 9.2.1 Overview. 9.2.2 Register Configuration. 9.2.3 Functions Port 9.3.1 Overview. 9.3.2 Register Configuration. 9.3.3 Functions Port 9.4.1 Overview. 9.4.2 Register Configuration. 9.4.3 Functions Port 9.5.1 Overview. 9.5.2 Register Configuration. 9.5.3 Functions Port 9.6.1 Overview. 9.6.2 Register Configuration. 9.6.3 Functions Port 9.7.1 Overview. 9.7.2 Register Configuration. 9.7.3 Functions Port 9.8.1 Overview. 9.8.2 Register Configuration. 9.8.3 Functions 9.8.4 Input Pull-Up Function. Port
9.10
9.11
9.12
9.13
9.14
9.9.1 Overview. 9.9.2 Register Configuration. 9.9.3 Functions 9.9.4 Input Pull-Up Function. Port 9.10.1 Overview. 9.10.2 Register Configuration. 9.10.3 Functions 9.10.4 Input Pull-Up Function. Port 9.11.1 Overview. 9.11.2 Register Configuration. 9.11.3 Functions 9.11.4 Input Pull-Up Function. Port 9.12.1 Overview. 9.12.2 Register Configuration. 9.12.3 Functions 9.12.4 Input Pull-Up Function. Port 9.13.1 Overview. 9.13.2 Register Configuration. 9.13.3 Functions Port 9.14.1 Overview. 9.14.2 Register Configuration. 9.14.3 Functions
Section 16-Bit Timer Pulse Unit (TPU)
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Configuration. 10.1.4 Register Configuration. 10.2 Register Descriptions 10.2.1 Timer Control Register (TCR). 10.2.2 Timer Mode Register (TMDR). 10.2.3 Timer Control Register (TIOR). 10.2.4 Timer Interrupt Enable Register (TIER). 10.2.5 Timer Status Register (TSR) 10.2.6 Timer Counter (TCNT). 10.2.7 Timer General Register (TGR) 10.2.8 Timer Start Register (TSTR)
viii
10.3
10.4
10.5
10.6
10.7
10.2.9 Timer Synchro Register (TSYR) 10.2.10 Module Stop Control Register (MSTPCR). Interface Master. 10.3.1 16-Bit Registers 10.3.2 8-Bit Registers Operation. 10.4.1 Overview. 10.4.2 Basic Functions. 10.4.3 Synchronous Operation 10.4.4 Buffer Operation 10.4.5 Cascaded Operation 10.4.6 Modes 10.4.7 Phase Counting Mode Interrupts 10.5.1 Interrupt Sources Priorities 10.5.2 DTC/DMAC Activation. 10.5.3 Converter Activation. Operation Timing 10.6.1 Input/Output Timing 10.6.2 Interrupt Signal Timing Usage Notes
Section Programmable Pulse Generator (PPG)
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Configuration. 11.1.4 Registers. 11.2 Register Descriptions 11.2.1 Next Data Enable Registers (NDERH, NDERL) 11.2.2 Output Data Registers (PODRH, PODRL) 11.2.3 Next Data Registers (NDRH, NDRL) 11.2.4 Notes Access 11.2.5 Output Control Register (PCR) 11.2.6 Output Mode Register (PMR) 11.2.7 Port Data Direction Register (P1DDR). 11.2.8 Port Data Direction Register (P2DDR). 11.2.9 Module Stop Control Register (MSTPCR). 11.3 Operation. 11.3.1 Overview. 11.3.2 Output Timing 11.3.3 Normal Pulse Output 11.3.4 Non-Overlapping Pulse Output
11.3.5 Inverted Pulse Output 11.3.6 Pulse Output Triggered Input Capture. Usage Notes 11.4.1 Operation Pulse Output Pins 11.4.2 Note Non-Overlapping Output
Section 8-Bit Timers.
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Configuration. 12.1.4 Register Configuration. 12.2 Register Descriptions 12.2.1 Timer Counters (TCNT0, TCNT1). 12.2.2 Time Constant Registers (TCORA0, TCORA1). 12.2.3 Time Constant Registers (TCORB0, TCORB1) 12.2.4 Time Control Registers (TCR0, TCR1) 12.2.5 Timer Control/Status Registers (TCSR0, TCSR1) 12.2.6 Module Stop Control Register (MSTPCR). 12.3 Operation. 12.3.1 TCNT Incrementation Timing. 12.3.2 Compare Match Timing. 12.3.3 Timing External RESET TCNT 12.3.4 Timing Overflow Flag (OVF) Setting. 12.3.5 Operation with Cascaded Connection 12.4 Interrupt Sources. 12.5 Sample Application. 12.6 Usage Notes 12.6.1 Contention between TCNT Write Clear 12.6.2 Contention between TCNT Write Increment. 12.6.3 Contention between TCOR Write Compare Match 12.6.4 Contention between Compare Matches 12.6.5 Switching Internal Clocks TCNT Operation
Section Watchdog Timer.
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram. 13.1.3 Configuration. 13.1.4 Register Configuration. 13.2 Register Descriptions 13.2.1 Timer Counter (TCNT). 13.2.2 Timer Control/Status Register (TCSR)
13.2.3 Reset Control/Status Register (RSTCSR) 13.2.4 Notes Register Access. 13.3 Operation. 13.3.1 Watchdog Timer Operation 13.3.2 Interval Timer Operation 13.3.3 Timing Setting Overflow Flag (OVF). 13.3.4 Timing Setting Watchdog Timer Overflow Flag (WOVF) 13.4 Interrupts 13.5 Usage Notes 13.5.1 Contention between Timer Counter (TCNT) Write Increment. 13.5.2 Changing Value CKS2 CKS0 13.5.3 Switching between Watchdog Timer Mode Interval Timer Mode. 13.5.4 System Reset WDTOVF Signal 13.5.5 Internal Reset Watchdog Timer Mode.
Section Serial Communication Interface (SCI)
14.1 Overview. 14.1.1 Features 14.1.2 Block Diagram. 14.1.3 Configuration. 14.1.4 Register Configuration. 14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) 14.2.2 Receive Data Register (RDR). 14.2.3 Transmit Shift Register (TSR). 14.2.4 Transmit Data Register (TDR). 14.2.5 Serial Mode Register (SMR) 14.2.6 Serial Control Register (SCR) 14.2.7 Serial Status Register (SSR) 14.2.8 Rate Register (BRR) 14.2.9 Smart Card Mode Register (SCMR). 14.2.10 Module Stop Control Register (MSTPCR). 14.3 Operation. 14.3.1 Overview. 14.3.2 Operation Asynchronous Mode. 14.3.3 Multiprocessor Communication Function 14.3.4 Operation Clocked Synchronous Mode. 14.4 Interrupts 14.5 Usage Notes
Section Smart Card Interface
15.1 Overview. 15.1.1 Features
15.1.2 Block Diagram. 15.1.3 Configuration. 15.1.4 Register Configuration. 15.2 Register Descriptions 15.2.1 Smart Card Mode Register (SCMR). 15.2.2 Serial Status Register (SSR) 15.2.3 Serial Mode Register (SMR) 15.2.4 Serial Control Register (SCR) 15.3 Operation. 15.3.1 Overview. 15.3.2 Connections 15.3.3 Data Format 15.3.4 Register Settings 15.3.5 Clock 15.3.6 Data Transfer Operations. 15.3.7 Example Software Standby Mode 15.3.8 Powering 15.4 Usage Notes
Section Converter.
16.1 Overview. 16.1.1 Features 16.1.2 Block Diagram. 16.1.3 Configuration. 16.1.4 Register Configuration. 16.2 Register Descriptions 16.2.1 Data Registers (ADDRA ADDRH). 16.2.2 Control/Status Register (ADCSR) 16.2.3 Control Register (ADCR) 16.2.4 Module Stop Control Register (MSTPCR). 16.3 Interface Master. 16.4 Operation. 16.4.1 Select Single Mode 16.4.2 Select Scan Mode. 16.4.3 Group Single Mode. 16.4.4 Group Scan Mode 16.4.5 Buffer Operation 16.4.6 Simultaneous Sampling Operation 16.4.7 Conversion Start Modes. 16.4.8 Starting Conversion External Input. 16.4.9 Conversion Time. 16.5 Interrupts 16.6 Usage Notes
Section Converter.
17.1 Overview. 17.1.1 Features 17.1.2 Block Diagram. 17.1.3 Configuration. 17.1.4 Register Configuration. 17.2 Register Descriptions 17.2.1 Data Registers (DADR0, DADR1). 17.2.2 Control Register (DACR) 17.2.3 Module Stop Control Register (MSTPCR). 17.3 Operation.
Section RAM.
18.1 Overview. 18.1.1 Block Diagram. 18.1.2 Register Configuration. 18.2 Register Descriptions 18.2.1 System Control Register (SYSCR). 18.3 Operation. 18.4 Usage Notes
Section ROM.
19.1 Overview. 19.1.1 Block Diagram. 19.1.2 Register Configuration. 19.2 Register Descriptions 19.2.1 Control Register (BCRL) 19.3 Operation. 19.4 PROM Mode. 19.4.1 PROM Mode Setting 19.4.2 Socket Adapter Memory Map. 19.5 Programming. 19.5.1 Overview. 19.5.2 Programming Verification. 19.5.3 Programming Precautions. 19.5.4 Reliability Programmed Data
Section Clock Pulse Generator
20.1 Overview. 20.1.1 Block Diagram. 20.1.2 Register Configuration. 20.2 Register Descriptions
xiii
20.2.1 System Clock Control Register (SCKCR). 20.3 Oscillator. 20.3.1 Connecting Crystal Resonator. 20.3.2 External Clock Input 20.4 Duty Adjustment Circuit. 20.5 Medium-Speed Clock Divider 20.6 Master Clock Selection Circuit.
Section Power-Down Modes
21.1 Overview. 21.1.1 Register Configuration. 21.2 Register Descriptions 21.2.1 Standby Control Register (SBYCR) 21.2.2 System Clock Control Register (SCKCR). 21.2.3 Module Stop Control Register (MSTPCR). 21.3 Medium-Speed Mode. 21.4 Sleep Mode 21.5 Module Stop Mode 21.5.1 Module Stop Mode 21.5.2 Usage Notes 21.6 Software Standby Mode. 21.6.1 Software Standby Mode. 21.6.2 Clearing Software Standby Mode. 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode 21.6.4 Software Standby Mode Application Example 21.6.5 Usage Notes 21.7 Hardware Standby Mode 21.7.1 Hardware Standby Mode 21.7.2 Hardware Standby Mode Timing. 21.8 Clock Output Disabling Function
Section Electrical Characteristics
22.1 Absolute Maximum Ratings 22.2 Characteristics 22.3 Characteristics 22.3.1 Clock Timing 22.3.2 Control Signal Timing 22.3.3 Timing 22.3.4 DMAC Timing. 22.3.5 Timing On-Chip Supporting Modules. 22.4 Conversion Characteristics 22.5 Conversion Characteristics
22.6 Usage Notes
Appendix Instruction
Instruction List Instruction Codes Operation Code Map. Number States Required Instruction Execution. States During Instruction Execution Condition Code Modification
Appendix Internal Register
Addresses Functions.
Appendix Port Block Diagrams 1005
C.10 C.11 C.12 C.13 Port Block Diagram 1005 Port Block Diagram 1008 Port Block Diagram 1012 Port Block Diagram 1015 Port Block Diagram 1016 Port Block Diagram 1020 Port Block Diagram 1026 Port Block Diagram. 1029 Port Block Diagram. 1030 Port Block Diagram .1031 Port Block Diagram 1032 Port Block Diagram 1033 Port Block Diagram .1041
Appendix States 1044
Port States Each Mode 1044
Appendix Timing Transition Recovery from Hardware Standby Mode 1049 Appendix Product Code Lineup 1050 Appendix Package Dimensions 1051
Section Overview
Overview
H8S/2655 Series series microcomputers (MCUs: microcomputer units), built around H8S/2600 CPU, employing Hitachi's proprietary architecture, equipped with peripheral functions on-chip. H8S/2600 internal 32-bit architecture, provided with sixteen 16-bit general registers concise, optimized instruction designed high-speed operation, address 16-Mbyte linear address space. instruction upward-compatible with H8/300 H8/300H instructions object-code level, facilitating migration from H8/300, H8/300L, H8/300H Series. On-chip peripheral functions required system configuration include controller (DMAC) data transfer controller (DTC) masters, memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), converter, converter, ports. on-chip either PROM (ZTATTM*) mask ROM, with capacity kbytes. connected 16-bit data bus, enabling both byte word data accessed state. Instruction fetching been speeded processing speed increased. Seven operating modes, modes provided, there choice address space single-chip mode external expansion mode. features H8S/2655 Series shown Table 1-1. Note: ZTATis trademark Hitachi, Ltd.
Table
Item
Overview
Specification General-register machine Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) High-speed operation suitable realtime control Maximum clock rate: High-speed arithmetic operations 8/16/32-bit register-register add/subtract 16-bit register-register multiply 42-bit multiply accumulate 16-bit register-register divide 1000 Instruction suitable high-speed operation Sixty-nine basic instructions 8/16/32-bit move/arithmetic logic instructions Unsigned/signed multiply divide instructions Multiply-and accumulate instruction Powerful bit-manipulation instructions operating modes Normal mode 64-kbyte address space Advanced mode 16-Mbyte address space Address space divided into areas, with specifications settable independently each area Chip select output possible each area Choice 8-bit 16-bit access space each area 2-state 3-state access space designated each area Number program wait states each area Burst directly connectable Maximum 8-Mbyte DRAM PSRAM directly connectable interval timer possible) External release function Choice short address mode full address mode channels short address mode channels full address mode Transfer possible repeat mode, block transfer mode, etc. Single address mode transfer possible activated internal interrupt
controller
controller (DMAC)
Table
Item
Overview (cont)
Specification activated internal interrupt software Multiple transfers multiple types transfer possible activation source Transfer possible repeat mode, block transfer mode, etc. Request sent interrupt that activated 6-channel 16-bit timer on-chip Pulse processing capability pins' Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with time base Output trigger selectable 4-bit groups Non-overlap margin Direct output inverse output setting possible 8-bit up-counter (external event count capability) time constant registers Two-channel connection possible Watchdog timer interval timer selectable Asynchronous mode synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: bits Input: channels High-speed conversion minimum conversion time operation) Single scan mode selectable Sample hold circuit conversion activated external trigger timer trigger Resolution: bits Output: channels pins, input-only pins PROM mask High-speed static kbytes kbytes kbytes kbytes
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG) 8-bit timer channels Watchdog timer Serial communication interface (SCI) channels converter converter ports Memory
Product Name H8S/2655 H8S/2653 Interrupt controller
Nine external interrupt pins (NMI, IRQ0 IRQ7) internal interrupt sources Eight priority levels settable
Table
Item
Overview (cont)
Specification Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode External Data On-Chip Disabled Enabled Enabled Disabled Disabled Enabled Enabled Initial Value bits bits bits bits bits bits bits bits Maximum Value bits bits
Power-down state
Operating modes
Seven operating modes Operating Mode Mode Description Advanced Normal On-chip disabled expansion mode On-chip enabled expansion mode Single-chip mode On-chip disabled expansion mode On-chip disabled expansion mode On-chip enabled expansion mode Single-chip mode Built-in duty correction circuit 120-pin plastic TQFP (TFP-120) 128-pin plastic (FP-128) Model Name Version (VCC 10%) HD6472655TE HD6472655F HD6432655(***)TE HD6432655(***)F HD6432653(***)TE HD6432653(***)F Low-Voltage Version (VCC HD6472655VTE HD6472655VF HD6432655(***)TE HD6432655(***)F HD6432653(***)TE HD6432653(***)F Mask PROM Packages TFP-120 FP-128 TFP-120 FP-128 TFP-120 FP-128
Clock pulse generator Packages Product lineup
Legend: Marked (***) code.
Block Diagram
Figure shows internal block diagram H8S/2655 Series.
/D15 /D14 /D13 /D12 /D11 /D10 Port
Port
Internal data
H8S/2600
Internal address
controller
EXTAL XTAL STBY WDTOVF
Port Clock pulse generator
/A23 /IRQ7 /A22 /IRQ6 /A21 /IRQ5 /A20 /IRQ4 /A19 /A18 /A17 /A16 /A15 /A14 /A13 /A12 /A10 /SCK1 /SCK0 /RxD1 /RxD0 /TxD1 /TxD0 /TxD2 /RxD2 /SCK2 /ADTRG
Interrupt controller /HWR /LWR /LCAS/WAIT/BREQO /BACK /BREQ /CS0 /CS1 /CS2 /CS3 /CAS/ /CS7 /IRQ3 /CS6 /IRQ2 /IRQ1 /IRQ0 /TEND1 /DREQ1 /TEND0 /CS5 /DREQ0 /CS4
Port
Peripheral address Peripheral data
Port
DMAC
Port Port 8-bit timer
converter Port
Port
converter
Port
Port /PO8 /TIOCA0/DACK0 /PO9 /TIOCB0/DACK1 /PO10 /TIOCC0/TCLKA /PO11 /TIOCD0/TCLKB /PO12 /TIOCA1 /PO13 /TIOCB1/TCLKC /PO14 /TIOCA2 /PO15 /TIOCB2/TCLKD
Port Vref AVCC AVSS
Port
Figure Block Diagram
/PO0 /TIOCA3 /PO1 /TIOCB3 /PO2 /TIOCC3/TMRI0 /PO3 /TIOCD3/TMCI0 /PO4 /TIOCA4/TMRI1 /PO5 /TIOCB4/TMCI1 /PO6 /TIOCA5/TMO0 /PO7 /TIOCB5/TMO1
/AN7 /DA1 /AN6 /DA0 /AN5 /AN4 /AN3 /AN2 /AN1 /AN0
1.3.1
Description
Arrangement
Figures show arrangement H8S/2655 Series.
TIOCA0 DACK0 TIOCB0 DACK1 PO10 TIOCC0 TCLKA PO11 TIOCD0 TCLKB PO12 TIOCA1 PO13 TIOCB1 TCLKC PO14 TIOCA2 PO15 TIOCB2 TCLKD AVSS Vref AVCC ADTRG SCK2
/IRQ1 /IRQ0 /D10 /D11 /D12 /D13 /D14 /D15 TxD0 TxD1 RxD0 RxD1 SCK0 SCK1 /DREQ0 /CS4
/A17 IRQ4 IRQ5 IRQ6 IRQ7 CS7/ IRQ3 CS6/ IRQ2
RxD2 TxD2 /BREQ /BACK /LCAS/WAIT /BREQO /LWR /HWR EXTAL XTAL STBY WDTOVF /PO0 TIOCA3 /PO1 TIOCB3 /PO2 TIOCC3 TMRI0 /PO3 TIOCD3 TMCI0 /PO4 TIOCA4 TMRI1 /PO5 TIOCB4 TMCI1 /PO6 TIOCA5 TMO0 /PO7 TIOCB5 TMO1 /TEND1 /DREQ1 /TEND0 /CS5
Figure Arrangement (TFP-120: View)
/D10 /D11 /D12 /D13 /D14 /D15 TxD0 TxD1 RxD0 RxD1 SCK0 SCK1
/CS1 /CS0 /A10 /A11 /A12 /A13 /A14 /A15 /A16 /A17 /A18 /A19 /A20 /IRQ4 /A21 /IRQ5 /A22 /IRQ6 /A23 /IRQ7 /CS7/IRQ3 /CS6/IRQ2 /IRQ1 /IRQ0
TIOCA0 DACK0 TIOCB0 DACK1 PO10 TIOCC0 TCLKA PO11 TIOCD0 TCLKB PO12 TIOCA1 PO13 TIOCB1 TCLKC PO14 TIOCA2 PO15 TIOCB2 TCLKD AVSS Vref AVCC /ADTRG SCK2 RxD2 TxD2 /BREQ /BACK /LCAS/WAIT /BREQO /LWR /HWR EXTAL XTAL STBY WDTOVF /PO0 TIOCA3 /PO1 TIOCB3 /PO2 TIOCC3 TMRI0 /PO3 TIOCD3 TMCI0 /PO4 TIOCA4 TMRI1 /PO5 TIOCB4 TMCI1 /PO6 TIOCA5 TMO0 /PO7 TIOCB5 TMO1 /TEND1 /DREQ1 /TEND0 /CS5 /DREQ0 /CS4
Figure Arrangement (FP-128: View)
1.3.2
Functions Each Operating Mode
Table shows functions H8S/2655 Series each operating modes. Table
TFP-120 FP-128 Mode 4/IRQ4 5/IRQ5 6/IRQ6 Mode PC0/A PC1/A PC2/A PC3/A PC4/A PC5/A PC6/A PC7/A 4/IRQ4 5/IRQ5 6/IRQ6 Mode 4/IRQ4 5/IRQ5 6/IRQ6
Functions Each Operating Mode
Name Mode IRQ5 IRQ6 Mode IRQ5 IRQ6 Mode PC0/A PC1/A PC2/A PC3/A PC4/A PC5/A PC6/A PC7/A IRQ4 IRQ5 IRQ6 Mode 4/IRQ4 5/IRQ5 6/IRQ6 PROM Mode
Table
Functions Each Operating Mode (cont)
Name Mode 7/IRQ7 P67/IRQ3 P66/IRQ2 P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 Mode 7/IRQ7 P67/IRQ3 P66/IRQ2 P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 Mode 7/IRQ7 P67/IRQ3 P66/IRQ2 P65/IRQ1 P64/IRQ0 P30/TxD0 P31/TxD1 P32/RxD0 Mode IRQ7 Mode IRQ7 Mode IRQ7 Mode 7/IRQ7 PROM Mode
TFP-120 FP-128
P67/IRQ3/ P67/IRQ3/ P67/IRQ3/ P67/IRQ3 P66/IRQ2/ P66/IRQ2/ P66/IRQ2/ P66/IRQ2 P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 P65/IRQ1 P64/IRQ0 0/D0 1/D1 2/D2 3/D3 4/D4 5/D5 6/D6 7/D7 P30/TxD0 P31/TxD1 P32/RxD0 P65/IRQ1 P64/IRQ0 P30/TxD0 P31/TxD1 P32/RxD0
Table
Functions Each Operating Mode (cont)
Name Mode P33/RxD1 Mode P33/RxD1 Mode P33/RxD1 Mode P33/RxD1 Mode P33/RxD1 Mode P33/RxD1 Mode P33/RxD1 PROM Mode
TFP-120 FP-128
P34/SCK P34/SCK P34/SCK P34/SCK P34/SCK P34/SCK P34/SCK P35/SCK P35/SCK P35/SCK P35/SCK P35/SCK P35/SCK P35/SCK P60/ DREQ0 P61/ TEND0 P62/ DREQ1 P63/ TEND P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P60/ DREQ0 P61/ TEND P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P60/ DREQ0 P61/ TEND P62/ DREQ1 P63/ TEND P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P60/ DREQ0/ P61/ TEND P62/ DREQ1 P63/ TEND P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P60/ DREQ0/ P61/ TEND P62/ DREQ1 P63/ TEND P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P60/ DREQ0/ P61/ TEND P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P60/ DREQ0 P61/ TEND P62/ DREQ1 P63/ TEND P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 P25/PO5/ TIOCB4/ TMCI P24/PO4/ TIOCA4/ TMRI P23/PO3/ TIOCD3/ TMCI P22/PO2/ TIOCC3/ TMRI P21/PO1/ TIOCB3 P20/PO0/ TIOCA3
WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF
Table
Functions Each Operating Mode (cont)
Name Mode STBY XTAL EXTAL Mode STBY XTAL EXTAL Mode STBY XTAL EXTAL Mode STBY XTAL EXTAL Mode STBY XTAL EXTAL Mode STBY XTAL EXTAL Mode STBY XTAL EXTAL PROM Mode
TFP-120 FP-128
PF2/WAIT/ PF2/WAIT/ BREQO BREQO PF1/BACK PF1/BACK PF0/BREQ PF0/BREQ P50/TxD2 P51/RxD2 P50/TxD2 P51/RxD2 P50/TxD2 P51/RxD2
PF2/LCAS/ PF2/LCAS/ PF2/LCAS/ WAIT/ WAIT/ WAIT/ BREQO BREQO BREQO PF1/BACK PF1/BACK PF1/BACK PF0/BREQ PF0/BREQ PF0/BREQ P50/TxD2 P51/RxD2 P50/TxD2 P51/RxD2 P50/TxD2 P51/RxD2 P50/TxD2 P51/RxD2
P52/SCK P52/SCK P52/SCK P52/SCK P52/SCK P52/SCK P52/SCK P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ P53/ ADTRG Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/
Table
Functions Each Operating Mode (cont)
Name Mode P47/AN7/ Mode P47/AN7/ Mode P47/AN7/ Mode P47/AN7/ Mode P47/AN7/ Mode P47/AN7/ Mode P47/AN7/ PROM Mode
TFP-120 FP-128
P17/PO15 P17/PO15 P17/PO15 P17/PO15 P17/PO15 P17/PO15 P17/PO15 TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TCLKD TCLKD TCLKD TCLKD TCLKD TCLKD TCLKD P16/PO14 P16/PO14 P16/PO14 P16/PO14 P16/PO14 P16/PO14 P16/PO14 TIOCA2 TIOCA2 TIOCA2 TIOCA2 TIOCA2 TIOCA2 TIOCA2 P15/PO13 P15/PO13 P15/PO13 P15/PO13 P15/PO13 P15/PO13 P15/PO13 TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TCLKC TCLKC TCLKC TCLKC TCLKC TCLKC TCLKC P14/PO12 P14/PO12 P14/PO12 P14/PO12 P14/PO12 P14/PO12 P14/PO12 TIOCA1 TIOCA1 TIOCA1 TIOCA1 TIOCA1 TIOCA1 TIOCA1 P13/PO11 P13/PO11 P13/PO11 P13/PO11 P13/PO11 P13/PO11 P13/PO11 TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TCLKB TCLKB TCLKB TCLKB TCLKB TCLKB TCLKB P12/PO10 P12/PO10 P12/PO10 P12/PO10 P12/PO10 P12/PO10 P12/PO10 TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TCLKA TCLKA TCLKA TCLKA TCLKA TCLKA TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 4/CS0 P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 4/CS0 P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0
0/CAS/ 0/CAS/ 0/CAS/ 1/CS3 2/CS2 3/CS1 4/CS0 1/CS3 2/CS2 3/CS1 4/CS0 1/CS3 2/CS2 3/CS1 4/CS0
Note: pins should connected left open.
1.3.3
Functions
Table outlines functions H8S/2655 Series. Table Functions
Type Power Symbol TFP-120 FP-128 100, Input Name Function Power supply: connection power supply. pins should connected system power supply. Ground: connection ground pins should connected system power supply
Input
Clock
XTAL
Input
Connects crystal oscillator. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input. Connects crystal oscillator. EXTAL also input external clock. section Clock Pulse Generator, typical connection diagrams crystal oscillator external clock input.
EXTAL
Input
Output System clock: Supplies system clock external device.
Table
Functions (cont)
Type
Symbol
TFP-120
FP-128
Input
Name Function Mode pins: These pins operating mode. relation between settings pins operating mode shown below. These pins should changed while H8S/2655 Series operating. Operating Mode Mode Mode Mode Mode Mode Mode Mode
Operating mode control
System control
Input
Reset input: When this driven low, chip reset. type reset selected according input level. power-on, input level should high. Standby: When this driven low, transition made hardware standby mode. request: Used external master issue request H8S/2655 Series.
STBY
Input
BREQ
Input
BREQO
Output request output: external request signal used when internal master accesses external space external bus-released state. Output request acknowledge: Indicates that been released external master.
BACK
Table
Functions (cont)
Type Interrupts
Symbol
TFP-120
FP-128
Input
Name Function Nonmaskable interrupt: Requests nonmaskable interrupt. When this used, should fixed high. Interrupt request These pins request maskable interrupt.
IRQ7 IRQ0 Address
Input
Output Address bus: These pins output address.
Data
Data bus: These pins constitute bidirectional data bus.
control
Output Chip select: Signals selecting areas 127, 128, Output Address strobe: When this low, indicates that address output address enabled. Output Read: When this low, indicates that external address space read. Output High write/write enable/upper write enable: strobe signal that writes external space indicates that upper half (D15 data enabled. 2CAS type DRAM write enable signal. type DRAM upper write enable signal.
Table
Functions (cont)
Type control
Symbol
TFP-120
FP-128
Name Function
Output write/lower column address strobe/lower write enable: strobe signal that writes external space indicates that lower half data enabled. 2CAS type (LCASS DRAM lower column address strobe signal. type DRAM lower write enable signal. Output Upper column address strobe/column address strobe/output enable/refresh: 2CAS type DRAM upper column address strobe signal. type DRAM column address strobe signal. PSRAM output enable signal. Input Wait: Requests insertion wait state cycle when accessing external 3-state address space.
CAS/
WAIT
LCAS
Output Lower column address strobe: 2CAS type (LCASS DRAM lower column address strobe signal Input request These pins request DMAC activation.
controller (DMAC)
DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0
Output transfer These pins indicate DMAC data transfer. Output transfer acknowledge These DMAC single address transfer acknowledge pins.
111,
121,
Table
Functions (cont)
Type 16-bit timerpulse unit (TPU)
Symbol TCLKD TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1
TFP-120
FP-128
Name Function Clock input These pins input external clock. Input capture/ output compare match TGR0A TGR0D input capture input output compare output, output pins. Input capture/ output compare match TGR1A TGR1B input capture input output compare output, output pins. Input capture/ output compare match TGR2A TGR2B input capture input output compare output, output pins. Input capture/ output compare match TGR3A TGR3D input capture input output compare output, output pins. Input capture/ output compare match TGR4A TGR4B input capture input output compare output, output pins. Input capture/ output compare match TGR5A TGR5B input capture input output compare output, output pins.
105, 107, 115, 117, Input 109, 119,
108,
118,
TIOCA2, TIOCB2
106,
116,
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
TIOCA5, TIOCB5
Table
Functions (cont)
Type
Symbol
TFP-120 112,
FP-128 122,
Name Function
Programmable PO15 pulse generator (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 Watchdog timer (WDT) Serial communication interface (SCI) Smart Card interface WDTOVF
Output Pulse output Pulse output pins. Output Compare match output: compare match output pins. Input Counter external clock input: Input pins external clock input counter. Counter external reset input: counter reset input pins.
Input
Output Watchdog timer overflows: counter overflows signal output watchdog timer mode. Output Transmit data (channel Data output pins. Input Receive data (channel Data input pins. Serial clock (channel Clock pins. Analog Analog input pins. conversion external trigger input: input external trigger start conversion.
TxD2, TxD1, TxD0 RxD2, RxD1, RxD0
101,
converter
ADTRG
Input Input
converter
102,
112,
Output Analog output: converter analog output pins.
Table
Functions (cont)
Type converter converters
Symbol AVCC
TFP-120
FP-128
Input
Name Function This power supply converter converter. When converter converter used, this should connected system power supply This ground converter converter. When converter converter used, this should connected system power supply This reference voltage input converter converter. When converter converter used, this should connected system power supply Port 8-bit port. Input output designated each means port data direction register (P1DDR). Port 8-bit port. Input output designated each means port data direction register (P2DDR). Port 6-bit port. Input output designated each means port data direction register (P3DDR). Port 8-bit input port. Port 4-bit port. Input output designated each means port data direction register (P5DDR).
AVSS
Input
Vref
Input
ports
Input
102, 101,
Table
Functions (cont)
Type ports
Symbol
TFP-120
FP-128
Name Function Port 8-bit port. Input output designated each means port data direction register (P6DDR). Port 8-bit port. Input output designated each means port data direction register (PADDR). Port 8-bit port. Input output designated each means port data direction register (PBDDR). Port 8-bit port. Input output designated each means port data direction register (PCDDR). Port 8-bit port. Input output designated each means port data direction register (PDDDR). Port 8-bit port. Input output designated each means port data direction register (PEDDR). Port 8-bit port. Input output designated each means port data direction register (PFDDR). Port 5-bit port. Input output designated each means port data direction register (PGDDR).
Section
Overview
H8S/2600 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2600 sixteen 16-bit general registers, address 16-Mbyte (architecturally 4-Gbyte) linear address space, ideal realtime control. 2.1.1 Features
H8S/2600 following features. Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers (also usable sixteen 8-bit registers eight 32-bit registers) Sixty-nine basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes Gbytes architecturally)
High-speed operation frequently-used instructions execute states Maximum clock rate 8/16/32-bit register-register add/subtract 8-bit register-register multiply 8-bit register-register divide 16-bit register-register multiply 16-bit register-register divide 1000 operating modes Normal mode Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection 2.1.2 Differences from H8/300
comparison H8/300 CPU, H8S/2600 following enhancements. More general registers control registers Eight 16-bit expanded registers, 8-bit 32-bit control registers, have been added. Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space.
Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. multiply-and-accumulate instruction been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.3 Differences from H8/300H
comparison H8/300H CPU, H8S/2600 following enhancements. Additional control register 8-bit 32-bit control registers have been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. multiply-and-accumulate instruction been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Operating Modes
H8S/2600 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space (architecturally maximum 16-Mbyte program area maximum Gbytes program data areas combined). mode selected mode pins microcontroller.
Normal mode
Maximum kbytes, program data areas combined
operating modes
Advanced mode
Maximum 16-Mbytes program data areas combined
Figure Operating Modes Normal Mode exception vector table stack have same structure H8/300 CPU. Address Space: maximum address space kbytes accessed. Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction Set: instructions addressing modes used. Only lower bits effective addresses (EA) valid.
Exception Vector Table Memory Indirect Branch Addresses: normal mode area starting H'0000 allocated exception vector table. branch address stored bits (figure 2-2). exception vector table differs depending microcontroller. details exception vector table, section Exception Handling.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Power-on reset exception vector Manual reset exception vector
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table.
Stack Structure: When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-3. When invalid, pushed onto stack. details, section Exception Handling.
bits)
EXR*1 Reserved*1,*3 CCR*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Normal Mode Advanced Mode Address Space: Linear access provided 16-Mbyte maximum address space (architecturally maximum 16-Mbyte program area maximum 4-Gbyte data area, with maximum Gbytes program data areas combined). Extended Registers (En): extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction Set: instructions addressing modes used.
Exception Vector Table Memory Indirect Branch Addresses: advanced mode area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2-4). details exception vector table, section Exception Handling.
H'00000000
Reserved Power-on reset exception vector
H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table.
Stack Structure: advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-5. When invalid, pushed onto stack. details, section Exception Handling.
Reserved bits)
EXR*1 Reserved*1,*3 bits)
Subroutine Branch
Exception Handling
Notes: When used stored stack. when used. Ignored when returning.
Figure Stack Structure Advanced Mode
Address Space
Figure shows memory H8S/2600 CPU. H8S/2600 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode.
H'0000
H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot used H8S/2655 Series
H'FFFFFFFF Normal Mode Advanced Mode
Figure Memory
2.4.1
Register Configuration
Overview
internal registers shown figure 2-7. There types registers: general registers control registers.
General Registers (Rn) Extended Registers (En) (SP) Control Registers (CR) Legend EXR: CCR: Sign extension MACL MACH
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask
MAC:
Half-carry flag User Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register
Figure Registers
2.4.2
General Registers
eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. Figure illustrates usage general registers. usage each register selected independently.
Address registers 32-bit registers
16-bit registers registers (extended registers)
8-bit registers
registers (ER0 ER7) registers
registers (R0H R7H)
registers (R0L R7L)
Figure Usage General Registers
General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Free area
(ER7)
Stack area
Figure Stack 2.4.3 Control Registers
control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 64-bit multiply-accumulate register (MAC). Program Counter (PC): This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded Extended Control Register (EXR): This 8-bit register contains trace three interrupt mask bits I0). 7-Trace (T): Selects trace mode. When this cleared instructions executed sequence. When this trace exception generated each time instruction executed. Bits 3-Reserved: These bits reserved. They always read
Bits 0-Interrupt Mask Bits I0): These bits designate interrupt mask level details, refer section Interrupt Controller. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. interrupts, including NMI, disabled three states after these instructions executed, except STC. Condition-Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. 7-Interrupt Mask (I): Masks interrupts other than when (NMI accepted regardless setting.) hardware start exceptionhandling sequence. details, refer section Interrupt Controller. 6-User Interrupt Mask (UI): written read software using LDC, STC, ANDC, ORC, XORC instructions. This also used interrupt mask bit. details, refer section Interrupt Controller. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise. 4-User (U): written read software using LDC, STC, ANDC, ORC, XORC instructions. 3-Negative Flag (N): Stores value most significant (sign bit) data. 2-Zero Flag (Z): indicate zero data, cleared indicate non-zero data. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, store value shifted carry flag also used accumulator manipulation instructions.
Some instructions leave some flag bits unchanged. action each instruction flag bits, refer Appendix A.1, List Instructions. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions. Multiply-Accumulate Register (MAC): This 64-bit register stores results multiplyand-accumulate operations. consists 32-bit registers denoted MACH MACL. lower bits MACH valid; upper bits sign extension. 2.4.4 Initial Register Values
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure 2-10 shows data formats general registers.
Data Type
Register Number
Data Format
1-bit data
Don't care
1-bit data
Don't care
4-bit data
Upper
Lower
Don't care
4-bit data
Don't care
Upper
Lower
Byte data
Don't care Don't care
Byte data
Figure 2-10 General Register Data Formats
Data Type
Register Number
Data Format
Word data
Word data Longword data
Legend ERn: General register General register General register RnH: General register RnL: General register MSB: Most significant LSB: Least significant
Figure 2-10 General Register Data Formats (cont)
2.5.2
Memory Data Formats
Figure 2-11 shows data formats memory. access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches.
Data Type Address 1-bit data Address
Data Format
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure 2-11 Memory Data Formats When used address register access stack, operand size should word size longword size.
2.6.1
Instruction
Overview
H8S/2600 types instructions. instructions classified function table 2-1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE, MOVTPE
Size
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS MAC, LDMAC, STMAC, CLRMAC
Logic operations Shift manipulation Branch System control Block data transfer
AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: B-byte size; W-word size; L-longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions.
2.6.2
Addressing Modes
Table
Function
Instruction
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Data transfer
POP, PUSH
LDM, S
MOVEPE, MOVTPE
Arithmetic operations
ADD,
ADDX, SUBX
ADDS, SUBS
INC,
DAA,
Instructions Addressing Modes
MULXU, DIVXU MULXS, DIVXS
EXTU, EXTS
CLRMAC
Combinations Instructions Addressing Modes
Table indicates combinations instructions addressing modes that H8S/2600 use.
LDMAC, STMAC
@ERn
@(d:16,ERn)
@(d:32,ERn)
@-ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8,PC)
@(d:16,PC)
@@aa:8
Logic operations AND,
Shift Bcc, JMP, TRAPA SLEEP ANDC, ORC, XORC
manipulation
Branch
System control
Block data transfer
Combinations Instructions Addressing Modes (cont)
Legend Byte Word Longword
Addressing Modes Instruction
Table
Function
2.6.3
Table Instructions Classified Function
Table summarizes instructions each functional category. notation used table defined below.
Operation Notation (EAd) (EAs) #IMM disp :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Table
Type Data transfer
Instructions Classified Function
Instruction Size* B/W/L Function (EAs) (Ead) Moves data between general registers between general register memory, moves immediate data general register. Cannot used H8S/2655 Series. Cannot used H8S/2655 Series. @SP+ Pops register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
MOVFPE MOVTPE
PUSH
S
Note: Size refers operand size. Byte Word Longword
Table
Type Arithmetic operations
Instructions Classified Function (cont)
Instruction Size* B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry borrow byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder.
ADDX SUBX
B/W/L
ADDS SUBS
MULXU
MULXS
DIVXU
Note: Size refers operand size. Byte Word Longword
Table
Type Arithmetic operations
Instructions Classified Function (cont)
Instruction DIVXS Size* Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @Erd) Tests memory contents, sets most significant (bit (EAs) (EAd) Performs signed multiplication memory contents adds result multiply-accumulate register. following operations performed: bits bits bits bits, saturating bits bits bits bits, non-saturating Clears multiply-accumulate register zero. MAC, Transfers data between general register multiply-accumulate register.
B/W/L
B/W/L
EXTU
EXTS
CLRMAC LDMAC STMAC
Note: Size refers operand size. Byte Word Longword
Table
Type Logic operations
Instructions Classified Function (cont)
Instruction Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement general register contents. (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shift possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shift possible. (rotate) Rotates general register contents. 1-bit 2-bit rotation possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotation possible.
B/W/L
B/W/L
B/W/L
Shift operations
SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
B/W/L
B/W/L
B/W/L
B/W/L
Note: Size refers operand size. Byte Word Longword
Table
Type Bitmanipulation instructions
Instructions Classified Function (cont)
Instruction BSET Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Note: Size refers operand size. Byte
Table
Type Bitmanipulation instructions
Instructions Classified Function (cont)
Instruction BXOR Size* Function (<bit-No.> <EAd>) Exclusive-ORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) Exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIXOR
BILD
BIST
Note: Size refers operand size. Byte
Table
Type Branch instructions
Instructions Classified Function (cont)
Instruction Size* Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine
Table
Type
Instructions Classified Function (cont)
Instruction Size* Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter.
System control TRAPA instructions SLEEP
ANDC
XORC
Note: Size refers operand size. Byte Word
Table
Type Block data transfer instruction
Instructions Classified Function (cont)
Instruction EEPMOV.B Size* Function then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Transfers data block according parameters general registers ER5, ER6. size block (bytes) ER5: starting source address ER6: starting destination address Execution next instruction begins soon transfer completed.
EEPMOV.W
2.6.4
Basic Instruction Formats
H8S/2655 Series instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Operation Field: Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field: Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension: Eight, bits specifying immediate data, absolute address, displacement. Condition Field: Specifies branching condition instructions.
Figure 2-12 shows examples instruction formats.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension (disp) Operation field, effective address extension, condition field (disp) d:16, MOV.B @(d:16, Rn), etc.
Figure 2-12 Instruction Formats (Examples)
2.7.1
Addressing Modes Effective Address Calculation
Addressing Mode
supports eight addressing modes listed table 2-4. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table
Addressing Modes
Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. Register Indirect-@ERn: register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn): 16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn: Register indirect with post-increment-@ERn+ register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Register indirect with pre-decrement-@-ERn value subtracted from address register (ERn) specified register field instruction code, result becomes address memory operand. result also stored address register. value subtracted byte access, word transfer instruction, longword transfer instruction. word longword transfer instruction, register value should even. Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32: instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table indicates accessible absolute address ranges. Table Absolute Address Access Ranges
Normal Mode bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Absolute Address Data address
Immediate-#xx:8, #xx:16, #xx:32: instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. Program-Counter Relative-@(d:8, @(d:16, PC): This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. Memory Indirect-@@aa:8: This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode memory operand word operand branch address bits long. advanced mode memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, refer section Exception Handling.
Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode
Advanced Mode
Figure 2-13 Branch Address Specification Memory Indirect Mode
address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation
Table indicates effective addresses calculated each addressing mode. normal mode upper bits effective address ignored order generate 16-bit address.
Effective Address Calculation Effective Address (EA) Operand general register contents. Don't care General register contents General register contents disp Sign extension disp Don't care General register contents Don't care General register contents Don't care Operand Size Value added Byte Word Longword
Addressing Mode Instruction Format
Table
Register direct (Rn)
Register indirect (@ERn)
Register indirect with displacement @(d:16, ERn) @(d:32, ERn)
Effective Address Calculation
Register indirect with post-increment pre-decrement Register indirect with post-increment @ERn+
Register indirect with pre-decrement @-ERn
Effective Address Calculation
Addressing Mode Instruction Format
Effective Address (EA)
Table
H'FFFF
Don't care
Absolute address
@aa:8
@aa:16
Don't care
Sign extension
@aa:24
Don't care
@aa:32
Don't care
Effective Address Calculation (cont)
Immediate #xx:8/#xx:16/#xx:32 Operand immediate data.
Effective Address Calculation contents Effective Address (EA) disp Sign extension disp
Don't care
Addressing Mode Instruction Format
Table
Program-counter relative
@(d:8, PC)/@(d:16,
Memory indirect @@aa:8
Normal mode
H'000000
Effective Address Calculation (cont)
Don't care
H'00
Memory contents
Advanced mode
H'000000 Memory contents
Don't care
2.8.1
Processing States
Overview
five main processing states: reset state, exception handling state, program execution state, bus-released state, power-down state. Figure 2-14 shows diagram processing states. Figure 2-15 indicates state transitions.
Reset state on-chip supporting modules have been initialized stopped. Exception-handling state transient state which changes normal processing flow response reset, interrupt, trap instruction. Processing states Program execution state executes program instructions sequence. Bus-released state external been released response request signal from master other than CPU. Sleep mode
Power-down state operation stopped conserve power.*
Software standby mode Hardware standby mode
Note: power-down state also includes medium-speed mode, module stop mode etc.
Figure 2-14 Processing States
request request
Program execution state request request SLEEP instruction with SSBY
Bus-released state exception handling Request exception handling
SLEEP instruction with SSBY
Sleep mode
Interrupt request Exception-handling state External interrupt high Software standby mode
Reset state*1
STBY high,
Hardware standby mode*2 Power-down state
Notes: From state except hardware standby mode, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows. From state, transition hardware standby mode occurs when STBY goes low.
Figure 2-15 State Transitions 2.8.2 Reset State
When input goes current processing stops enters reset state. interrupts masked reset state. Reset exception handling starts when signal changes from high. reset state also entered watchdog timer overflow. details, refer section Watchdog Timer.
2.8.3
Exception-Handling State
exception-handling state transient state that occurs when alters normal processing flow reset, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. Types Exception Handling Their Priority Exception handling performed traces, resets, interrupts, trap instructions. Table indicates types exception handling their priority. Trap instruction exception handling always accepted, program execution state. Exception handling stack structure depend interrupt control mode SYSCR. Table
Priority High
Exception Handling Types Priority
Type Exception Reset Detection Timing Synchronized with clock Start Exception Handling Exception handling starts immediately after low-to-high transition pin, when watchdog timer overflows. When trace trace starts current instruction current exception-handling sequence When interrupt requested, exception handling starts current instruction current exception-handling sequence Exception handling starts when trap (TRAPA) instruction executed*
Trace
instruction execution exception-handling sequence* instruction execution exception-handling sequence* When TRAPA instruction executed
Interrupt
Trap instruction
Notes: Traces enabled only interrupt control modes Trace exception-handling executed instruction. Interrupts detected ANDC, ORC, XORC, instructions, immediately after reset exception handling. Trap instruction exception handling always accepted, program execution state.
Reset Exception Handling After gone reset state been entered, when goes high again, reset exception handling starts. When reset exception handling starts fetches start address (vector) from exception vector table starts program execution from that address. interrupts, including NMI, disabled during reset exception handling after ends. Traces Traces enabled only interrupt control modes Trace mode entered when When trace mode established, trace exception handling starts each instruction. trace exception-handling sequence, cleared trace mode cleared. Interrupt masks affected. saved stack retains value when instruction executed return from trace exception-handling routine, trace mode entered again. Trace exceptionhandling executed instruction. Trace mode entered interrupt control modes regardless state bit. Interrupt Exception Handling Trap Instruction Exception Handling When interrupt trap-instruction exception handling begins, references stack pointer (ER7) pushes program counter other control registers onto stack. Next, alters settings interrupt mask bits control registers. Then fetches start address (vector) from exception vector table program execution starts from that start address. Figure 2-16 shows stack after exception handling ends.
Normal mode
CCR* bits)
Reserved* CCR* bits)
Interrupt control modes
Interrupt control modes
Advanced mode
bits)
Reserved* bits)
Interrupt control modes Note: *Ignored when returning.
Interrupt control modes
Figure 2-16 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
this state executes program instructions sequence. 2.8.5 Bus-Released State
This state which been released response request from master other than CPU. While released, halts operations. masters other than direct memory access controller (DMAC) data transfer controller (DTC). further details, refer section Controller. 2.8.6 Power-Down State
power-down state includes both modes which stops operating modes which does stop. There three modes which stops operating: sleep mode, software standby mode, hardware standby mode. There also other power-down modes: medium-speed mode, module stop mode. medium-speed mode other masters operate medium-speed clock. Module stop mode permits halting operation individual modules, other than CPU. details, refer section Power-Down State. Sleep Mode: transition sleep mode made SLEEP instruction executed while software standby (SSBY) standby control register (SBYCR) cleared sleep mode, operations stop immediately after execution SLEEP instruction. contents registers retained. Software Standby Mode: transition software standby mode made SLEEP instruction executed while SSBY SBYCR software standby mode, clock halt operations stop. long specified voltage supplied, contents registers on-chip retained. ports also remain their existing states. Hardware Standby Mode: transition hardware standby mode made when STBY goes low. hardware standby mode, clock halt operations stop. on-chip supporting modules reset, long specified voltage supplied, on-chip contents retained.
2.9.1
Basic Timing
Overview
H8S/2600 driven system clock, denoted symbol period from rising edge next referred "state." memory cycle cycle consists one, two, three states. Different methods used access on-chip memory, on-chip supporting modules, external address space. 2.9.2 On-Chip Memory (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure 2-17 shows on-chip memory access cycle. Figure 2-18 shows states.
cycle Internal address Internal read signal Internal data Internal write signal Write access Internal data Write data Read data Address
Read access
Figure 2-17 On-Chip Memory Access Cycle
cycle
Address HWR, Data
Unchanged High High High High-impedance state
Figure 2-18 States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
on-chip supporting modules accessed states. data either bits bits wide, depending particular internal register being accessed. Figure 2-19 shows access timing on-chip supporting modules. Figure 2-20 shows states.
cycle
Internal address
Address
Internal read signal Read access Internal data Internal write signal Write access Internal data Write data
Read data
Figure 2-19 On-Chip Supporting Module Access Cycle
cycle
Address
Unchanged
HWR,
High
High
High
Data
High-impedance state
Figure 2-20 States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing
external address space accessed with 8-bit 16-bit data width two-state three-state cycle. three-state access, wait states inserted. further details, refer section Controller.
Section Operating Modes
3.1.1
Overview
Operating Mode Selection
H8S/2655 Series seven operating modes (modes These modes enable selection operating mode, enabling/disabling on-chip ROM, initial width setting, setting mode pins (MD2 MD0). Table lists operating modes. Table Operating Mode Selection
External Data On-Chip Initial Width bits bits Max. Width
Operating Operating Description Mode Mode Normal
On-chip disabled, Disabled bits expanded mode On-chip enabled, Enabled bits expanded mode Single-chip mode
Advanced On-chip disabled, Disabled bits expanded mode bits On-chip enabled, Enabled bits expanded mode Single-chip mode
bits bits bits
CPU's architecture allows Gbytes address space, H8S/2655 Series actually accesses maximum Mbytes. Modes externally expanded modes that allow access external memory peripheral devices. external expansion modes allow switching between 8-bit 16-bit modes. After program execution starts, 8-bit 16-bit address space each area, depending controller setting. 16-bit access selected area, 16-bit mode set; 8-bit access selected areas, 8-bit mode set.
Note that functions each depend operating mode. H8S/2655 Series used only modes This means that mode pins must select these modes. change inputs mode pins during operation. 3.1.2 Register Configuration
H8S/2655 Series mode control register (MDCR) that indicates inputs mode pins MD0), system control register (SYSCR) that controls operation H8S/2655 Series. Table summarizes these registers. Table
Name Mode control register System control register
Registers
Abbreviation MDCR SYSCR Initial Value Undetermined H'01 Address* H'FF3B H'FF39
Note: Lower bits address.
3.2.1
Register Descriptions
Mode Control Register (MDCR)
MDS2 MDS1 MDS0
Initial value:
Note: Determined pins MD0.
MDCR 8-bit read-only register that indicates current operating mode H8S/2655 Series. 7-Reserved: Read-only bit, always read Bits 3-Reserved: Read-only bits, always read Bits 0-Mode Select (MDS2 MDS0): These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond MD0. MDS2 MDS0 read-only bits-they cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled power-on reset, retained after manual reset. 3.2.2
System Control Register (SYSCR)
MACS INTM1 INTM0 NMIEG RAME
Initial value:
7-MAC Saturation (MACS): Selects either saturating non-saturating calculation instruction.
MACS Description Non-saturating calculation instruction Saturating calculation instruction (Initial value)
6-Reserved: Read-only bit, always read Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select control mode interrupt controller. details interrupt control modes, section 5.4.1, Interrupt Control Modes Interrupt Operation.
INTM1 INTM0 Interrupt Control Mode
Description Control interrupts (Initial value)
Control interrupts bit, bit, Control interrupts bits Control interrupts bits,
3-NMI Edge Select (NMIEG): Selects valid edge interrupt input.
NMIEG Description interrupt requested falling edge input interrupt requested rising edge input (Initial value)
Bits 1-Reserved: Read-only bits, always read 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized when reset status released. initialized software standby mode.
RAME Description On-chip disabled On-chip enabled (Initial value)
3.3.1
Operating Mode Descriptions
Mode
access 64-kbyte address space normal mode. on-chip disabled, 8-bit mode set, immediately after reset. Ports function address bus, port functions data bus, part port carries control signals. However, note that 16-bit access designated controller, mode switches bits port becomes data bus. 3.3.2 Mode
access 64-kbyte address space normal mode. on-chip enabled, 8-bit mode set. immediately after reset. Ports function input ports immediately after reset. They each output addresses setting corresponding bits data direction register (DDR) Port functions data bus, part port carries control signals. However, note that 16-bit access designated controller, mode switches bits port becomes data bus. amount on-chip that used limited kbytes. 3.3.3 Mode
access 64-kbyte address space normal mode. on-chip enabled, external addresses cannot accessed. ports available input-output ports. amount on-chip that used limited kbytes. 3.3.4 Mode
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, part port carries control signals. initial mode after reset bits, with 16-bit access areas. However, note that 8-bit access designated controller areas, mode switches bits.
3.3.5
Mode
access 16-Mbyte address space advanced mode. on-chip disabled. Ports function address bus, ports function data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. However, note that least area designated 16-bit access controller, mode switches bits port becomes data bus. 3.3.6 Mode
access 16-Mbyte address space advanced mode. on-chip enabled. Ports function input ports immediately after reset. They each output addresses setting corresponding bits data direction register (DDR) Port functions data bus, part port carries control signals. initial mode after reset bits, with 8-bit access areas. 3.3.7 Mode
access 16-Mbyte address space advanced mode. on-chip enabled, external addresses cannot accessed. ports available input-output ports.
Functions Each Operating Mode
functions ports vary depending operating mode. Table shows their functions each operating mode. Table
Port Port Port Port Port Port Port P*/D P*/C* P*/C P*/A P*/A P*/D P*/C* P*/C P*/C
Functions Each Mode
Mode Mode Mode Mode P*/A P*/D P*/C* P*/C Mode P*/A P*/D P*/C* P*/C P*/A P*/A P*/D P*/C* P*/C P*/C Mode P*/A Mode
Legend port Address output Data Control signals, clock After reset
Memory Each Operating Mode
Figure shows memory each operating modes. address space kbytes modes (normal modes), Mbytes modes (advanced modes). on-chip H8S/2655 contains kbytes, only kbytes available modes (normal modes). address space divided into eight areas modes details, section Controller.
Mode (normal expanded mode with on-chip disabled) H'0000 Mode (normal expanded mode with on-chip enabled) H'0000 Mode (normal single-chip mode)
H'0000
On-chip External address space
On-chip
H'DFFF H'E000 H'EC00 On-chip RAM* H'FBFF H'FC00 External address H'FE3F space Internal registers H'FF08 External address
space
H'DFFF External address space H'EC00 On-chip RAM* On-chip H'FBFF
External address space
H'EC00
H'FBFF H'FC00 H'FE3F H'FF08
Internal registers
External address space
H'FE40 Internal registers H'FF07 H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
H'FF28 Internal registers H'FFFF
Note: External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode
Modes (advanced expanded modes with on-chip disabled) H'000000
Mode (advanced expanded mode with on-chip enabled) H'000000
Mode (advanced single-chip mode)
H'000000
On-chip
On-chip
External address space
H'00FFFF H'010000 On-chip ROM/ external address space/reserved area*1
H'00FFFF H'010000 On-chip ROM/ reserved area*2
H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal registers H'FFFF08 External address
space
H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE3F Internal registers H'FFFF08 External address
space
H'01FFFF
H'FFEC00 On-chip H'FFFBFF H'FFFE40 Internal registers H'FFFF07 H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
H'FFFF28 Internal registers H'FFFFFF
Notes: When BCRL this area external address space. When cleared on-chip H8S/2655, reserved area H8S/2653. H8S/2655, this area reserved when BCRL on-chip when cleared H8S/2653, reserved area. External addresses accessed clearing RAME SYSCR
Figure Memory Each Operating Mode (cont)
Section Exception Handling
4.1.1
Overview
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 4-1. more exceptions occur simultaneously, they accepted processed order priority. Trap instruction exceptions accepted times, program execution state. appendix D.1, Port States Each Mode. Exception handling sources, stack structure, operation vary depending interrupt control mode INTM0 INTM1 bits SYSCR. Table
Priority High
Exception Types Priority
Exception Type Reset Trace* Interrupt Start Exception Handling Starts immediately after low-to-high transition pin, when watchdog timer overflows. Starts when execution current instruction exception handling ends, trace Starts when execution current instruction exception handling ends, interrupt request been issued*
Trap instruction (TRAPA)*3 Started execution trap instruction (TRAPA)
Notes: Traces enabled only interrupt control modes Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions interrupts handled follows: program counter (PC), condition code register (CCR), extended register (EXR) pushed onto stack. interrupt mask bits updated. cleared vector address corresponding exception source generated, program execution starts from that address.
reset exception, steps above carried out. 4.1.3 Exception Vector Table
exception sources classified shown figure 4-1. Different vector addresses assigned different exception sources. Table lists exception sources their vector addresses.
Reset Trace Exception sources Interrupts
Power-on reset Manual reset External interrupts: NMI, IRQ7 IRQ0 Internal interrupts: interrupt sources on-chip supporting modules
Trap instruction
Figure Exception Sources modes H8S/2655, on-chip available after power-on reset 64-kbyte area comprising addresses H'000000 H'00FFFF. Care required when setting vector addresses. this case, clearing BCRL enables 128-kbyte area comprising addresses H'000000 H'01FFFF used.
Table
Exception Vector Table
Vector Address*
Exception Source Power-on reset Manual reset Reserved system
Vector Number
Normal Mode H'0000 H'0001 H'0002 H'0003 H'0004 H'0006 H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'00B6 H'00B7
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 H'016C H'016F
Trace Reserved system External interrupt
Trap instruction sources)
Reserved system
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Internal interrupt*
Notes: Lower bits address. details internal interrupt vectors, section 5.3.3, Interrupt Exception Handling Vector Table.
4.2.1
Reset
Overview
reset highest exception priority. When goes low, processing halts H8S/2655 Series enters reset state. reset initializes internal state registers on-chip supporting modules. Immediately after reset, interrupt control mode set. Reset exception handling begins when changes from high. level reset determines whether type reset power-on reset manual reset. H8S/2655 Series also reset overflow watchdog timer. details section Watchdog Timer. 4.2.2 Reset Types
reset either types: power-on reset manual reset. Reset types shown table 4-3. power-on reset should used when powering internal state initialized either type reset. power-on reset also initializes registers on-chip supporting modules, while manual reset initializes registers on-chip supporting modules except controller ports, which retain their previous states. With manual reset, since on-chip supporting modules initialized, ports used on-chip supporting module pins switched ports controlled Table Reset Types
Reset Transition Conditions Type Power-on reset Manual reset High Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except controller ports
reset caused watchdog timer also either types: power-on reset manual reset.
4.2.3
Reset Sequence
H8S/2655 Series enters reset state when goes low. ensure that H8S/2655 Series reset, hold least power-up. reset H8S/2655 Series during operation, hold least states. When goes high after being held necessary time, H8S/2655 Series starts reset exception handling follows: internal state registers on-chip supporting modules initialized, CCR. reset exception handling vector address read transferred program execution starts from address indicated Figures show examples reset sequence.
Vector Internal Prefetch first program fetch processing instruction
Internal address Internal read signal Internal write signal Internal data
High
Reset exception handling vector address ((1) H'0000) Start address (contents reset exception handling vector address) Start address ((3) (2)) First program instruction
Figure Reset Sequence (Modes
Vector fetch
Internal Prefetch first processing program instruction
Address HWR,
High
Reset exception handling vector address ((1) H'000000, H'000002) Start address (contents reset exception handling vector address) Start address ((5) (4)) First program instruction Note: program wait states inserted.
Figure Reset Sequence (Mode 4.2.4 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. Since first instruction program always executed immediately after reset state ends, make sure that this instruction initializes stack pointer (example: MOV.L #xx:32, SP).
Traces
Traces enabled interrupt control modes Trace mode activated interrupt control modes irrespective state bit. details interrupt control modes, section Interrupt Controller. trace mode activated. trace mode, trace exception occurs completion each instruction. Trace mode canceled clearing affected interrupt masking. Table shows state after execution trace exception handling. Interrupts accepted even within trace exception handling routine. saved stack retains value when control returned from trace exception handling routine instruction, trace mode resumes. Trace exception handling carried after execution instruction. Table Status after Trace Exception Handling
Interrupt Control Mode
Trace exception handling cannot used.
Legend Cleared Retains value prior execution.
Interrupts
Interrupt exception handling requested nine external sources (NMI, IRQ7 IRQ0) internal sources on-chip supporting modules. Figure classifies interrupt sources number interrupts each type. on-chip supporting modules that request interrupts include watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), controller (DMAC), converter. Each interrupt source separate vector address. highest-priority interrupt, always accepted. Interrupts controlled interrupt controller. interrupt controller four interrupt control modes assign interrupts other than either three eight priority/mask levels enable multiplexed interrupt control. details interrupts, section Interrupt Controller.
External interrupts Interrupts
IRQ7 IRQ0 WDT*1 Refresh timer*2 (26) 8-bit timer (12) DMAC converter
Internal interrupts
Notes:
Numbers parentheses numbers interrupt sources. When watchdog timer used interval timer, generates interrupt request each counter overflow. When refresh timer used interval timer, generates interrupt request each compare match.
Figure Interrupt Sources Number Interrupts
Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. Trap instruction exception handling executed times program execution state. TRAPA instruction fetches start address from vector table entry corresponding vector number from specified instruction code. Table shows status after execution trap instruction exception handling. Table Status after Trap Instruction Exception Handling
Interrupt Control Mode
Legend Cleared Retains value prior execution.
Stack Status after Exception Handling
Figure shows stack after completion trap instruction exception handling interrupt exception handling.
CCR* bits)
Reserved* CCR* bits)
Interrupt control modes Note: Ignored return.
Interrupt control modes
Figure Stack Status after Exception Handling (Normal Modes)
(24bits)
Reserved* (24bits)
Interrupt control modes Note: Ignored return.
Interrupt control modes
Figure Stack Status after Exception Handling (Advanced Modes)
Notes Stack
When accessing word data longword data, H8S/2655 Series assumes that lowest address stack should always accessed word transfer instruction longword transfer instruction, value stack pointer (SP, ER7) should always kept even. following instructions save registers:
PUSH.W PUSH.L MOV.W @-SP) MOV.L ERn, @-SP)
following instructions restore registers:
POP.W POP.L MOV.W @SP+, MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF
TRAP instruction executed MOV.B R1L, @-ER7
H'FFFEFF
Data saved above
Contents lost
Legend CCR: Condition code register Program counter R1L: General register Stack pointer Note: This diagram illustrates example which interrupt control mode advanced mode.
Figure Operation when Value
Section Interrupt Controller
5.1.1
Overview
Features
H8S/2655 Series controls interrupts means interrupt controller. interrupt controller following features: Four interrupt control modes four interrupt control modes means INTM1 INTM0 bits system control register (SYSCR). Priorities settable with interrupt control register (ICR) provided setting interrupt priorities. Three priority levels each module interrupts except NMI. Priorities settable with interrupt priority register (IPR) provided setting interrupt priorities. Eight priority levels each module interrupts except NMI. assigned highest priority level accepted times. Independent vector addresses interrupt sources assigned independent vector addresses, making unnecessary source identified interrupt handling routine. Nine external interrupts highest-priority interrupt, accepted times. Rising edge falling edge selected NMI. Falling edge, rising edge, both edge detection, level sensing, selected IRQ7 IRQ0. DMAC control DMAC activation performed means interrupts.
5.1.2
Block Diagram
block diagram interrupt controller shown Figure 5-1.
INTM1 INTM0 SYSCR NMIEG input input input unit input unit ISCR Priority determination Interrupt request Vector number
Internal interrupt request WOVI
Interrupt controller
Legend ISCR SYSCR
sense control register enable register status register Interrupt priority register Interrupt control register System control register
Figure Block Diagram Interrupt Controller 5.1.3 Configuration
Table summarizes pins interrupt controller.
Table
Name
Interrupt Controller Pins
Symbol IRQ7 IRQ0 Input Input Function Nonmaskable external interrupt; rising falling edge selected Maskable external interrupts; rising, falling, both edges, level sensing, selected
Nonmaskable interrupt External interrupt requests
5.1.4
Register Configuration
Table summarizes registers interrupt controller. Table
Name System control register sense control register sense control register enable register status register Interrupt control register Interrupt control register Interrupt control register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register Interrupt priority register
Interrupt Controller Registers
Abbreviation SYSCR ISCRH ISCRL ICRA ICRB ICRC IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/(W)*
Initial Value H'01 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77
Address* H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC0 H'FEC1 H'FEC2 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
Notes: Lower bits address. only written with flag clearing.
5.2.1
Register Descriptions
System Control Register (SYSCR)
MACS INTM1 INTM0 NMIEG RAME
Initial value:
SYSCR 8-bit readable/writable register that selects interrupt control mode, detected edge NMI. Only bits described here; details other bits, section 3.2.2, System Control Register (SYSCR). SYSCR initialized H'01 reset hardware standby mode. initialized software standby mode. Bits 4-Interrupt Control Mode (INTM1, INTM0): These bits select four interrupt control modes interrupt controller.
INTM1 INTM0 Interrupt Control Mode
Description Interrupts controlled (Initial value)
Interrupts controlled bits Interrupts controlled bits Interrupts controlled bits ICR,
3-NMI Edge Select (NMIE
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