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250MHz Video Buffer HA-5033 unity gain monolithic designed applic
Top Searches for this datasheetHA-5033 250MHz Video Buffer HA-5033 unity gain monolithic designed application requiring fast, wideband buffer. Featuring bandwidth 250MHz outstanding differential phase/ gain characteristics, this high performance voltage follower excellent choice video circuit design. Other features, which include minimum slew rate 1000V/µs high output drive capability, make HA-5033 applicable line driver high speed data conversion circuits. high performance this product result Harris Dielectric Isolation process. major feature this process that produces both high frequency transistors which makes wide bandwidth designs, such HA-5033, practical. Alternative process methods typically produce lower performance. April 1997 Features Differential Phase Error. 0.02 Degrees Differential Gain Error 0.03% High Slew Rate 1100V/µs Wide Bandwidth (Small Signal) 250MHz Wide Power Bandwidth 17.5MHz Fast Rise Time High Output Drive ±10V With Load Wide Power Supply Range ±16V Replace Costly Hybrids Applications Video Buffer High Frequency Buffer Isolation Buffer High Speed Line Driver Impedance Matching Current Boosters High Speed Input Buffers Related Literature AN548, Designer's Guide HA-5033 Ordering Information PART NUMBER (BRAND) HA2-5033-2 HA2-5033-5 HA3-5033-5 HA4P5033-5 HA9P5033-5 (H50335) TEMP. RANGE (oC) (Note PACKAGE Metal Metal PDIP PLCC PSOP PKG. T12.C T12.C E8.3 N20.35 M8.15A Pinouts HA-5033 (PDIP, PSOP) VIEW HA-5033 (PLCC) VIEW HA-5033 (METAL CAN) VIEW CASE SUBSTRATE SUBSTRATE CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright Harris Corporation 1997 File Number 2924.3 HA-5033 Absolute Maximum Ratings Voltage Between Pins Input Voltage VOutput Current (Peak) (50ms On/1 Second Off) ±200mA Rating Human Body Model (Per MIL-STD-883 Method 3015.7) 2000V Thermal Information Thermal Resistance (Typical, Note (oC/W) (oC/W) Metal Package PDIP Package PSOP Package (Note PLCC Package Maximum Junction Temperature (Note 175oC Maximum Junction Temperature (Plastic Packages) 150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (PSOP PLCC Lead Tips Only) Operating Conditions Temperature Ranges HA-5033-2. -55oC 125oC HA-5033-5 (Note 75oC HA9P5033-5 (Notes -40oC 60oC CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied. NOTES: Maximum power dissipation, including load conditions, must designed maintain maximum junction temperature below metal package, below 150oC plastic packages (See Figure 5.). measured with component mounted evaluation board free air. Maximum operating temperature PSOP package limited 60oC, VSUPPLY ±12V prevent junction temperature from exceeding 150oC. maximum operating temperature have derated further, depending output load condition. operating temperature increased HA9P5033 operated lower VSUPPLY. example, quiescent operating temperature increased 75oC operating VSUPPLY ±9.7V. Figure more information. Direct attach PSOP copper slug copper area reduce value <100oC/W. Consult Harris Application Group more information. Electrical Specifications PARAMETER INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Bias Current Input Resistance Input Capacitance Input Noise Voltage Voltage Gain VSUPPLY ±12V, 100, 10pF, Unless Otherwise Specified TEST CONDITIONS TEMP. (oC) Full Full Full 10Hz 100MHz Full ±15V Full Full VOUT 1VRMS VOUT 500mV HA-5033-2 0.93 0.93 0.92 15.9 0.99 ±100 17.5 0.93 0.93 0.92 15.9 HA-5033-5 0.99 ±100 17.5 UNITS µV/oC µVP-P V/ns TRANSFER CHARACTERISTICS -3dB Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Resistance Full Power Bandwidth Full Power Bandwidth (Note TRANSIENT RESPONSE Rise Time Propagation Delay Overshoot Slew Rate (Note Settling Time 0.1% HA-5033 Electrical Specifications PARAMETER Differential Phase Error (Note Differential Gain Error (Note POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio Harmonic Distortion 1VRMS 100kHz Full Full <0.1 <0.1 VSUPPLY ±12V, 100, 10pF, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (oC) HA-5033-2 0.02 0.03 HA-5033-5 0.02 0.03 UNITS Degree NOTES: VSUPPLY ±15V, VOUT ±10V, Differential gain phase error nonlinear signal distortions found video systems defined follows: Differential gain error defined change amplitude color subcarrier frequency picture signal varied from blanking white level. Differential phase error defined change phase color subcarrier picture signal varied from blanking white level. 300. Test Circuits Waveforms +15V 0.1µF +12V 0.1µF 0.1µF -15V 0.1µF -12V FIGURE SLEW RATE SETTLING TIME FIGURE TRANSIENT RESPONSE 500mV INPUT INPUT OVERSHOOT OUTPUT SLEW RATE ERROR BAND ±10mV FROM FINAL VALUE OUTPUT NOTE: Measured both positive negative transitions. FIGURE RISE TIME FIGURE SETTLING TIME VOUT VOUT 25oC, +10V RESPONSE 25oC, +10V RESPONSE HA-5033 Test Circuits Waveforms 500mV (Continued) 500mV VOUT 25oC, PULSE RESPONSE Schematic Diagram VOUT Application Information Layout Considerations wide bandwidth HA-5033 necessitates that high frequency circuit layout procedures followed. Failure follow these guidelines result marginal performance. Probably most crucial RF/video layout rules ground plane. ground plane provides isolation minimizes distributed circuit capacitance inductance which will degrade high frequency performance. This ground plane shielding also incorporate metal case HA-5033 since internally tied package. This feature allows user make metal metal contact between ground plane package, which extends shielding, provides additional heat sinking eliminates socket, sockets contribute inter-lead capacitance which limits device bandwidth should avoided. PDIP, tied either supply, grounded, simply used. optimize device performance improve isolation, recommended that this grounded. Other considerations proper power supply bypassing keeping input output connections short possible which minimizes distributed capacitance reduces board space. Power Supply Decoupling optimum device performance, recommended that positive negative power supplies bypassed with capacitors ground. Ceramic capacitors ranging value from 0.01µF 0.1µF will minimize high frequency variations supply voltage. Solid tantalum capacitors larger will optimize frequency performance. also recommended that bypass capacitors connected close HA-5033 (preferably directly supply pins). HA-5033 MAXIMUM TOTAL POWER DISSIPATION TEMPERATURE (oC) QUIESCENT 0.72W ±12V, 30mA PSOP PDIP PLCC Graph based JMAX DMAX Where: TJMAX Maximum Junction Temperature Device Ambient Temperature Junction Ambient Thermal Resistance FIGURE FREE POWER DISSIPATION Typical Applications (Also Application Note AN548) HA-2539 VIDEO SIGNAL INPUT VIDEO OUTPUT +12V 0.1µF HA-5033 V900 0.1µF -12V FIGURE VIDEO COAXIAL LINE DRIVER SYSTEM FIGURE VIDEO GAIN BLOCK VOUT VOUT 25oC, POSITIVE PULSE RESPONSE 25oC, NEGATIVE PULSE RESPONSE HA-5033 Typical Performance Curves OFFSET VOLTAGE (mV) ±10V ±12V ±15V ±10V INPUT BIAS CURRENT (µA) ±12V ±15V TEMPERATURE (oC) TEMPERATURE (oC) FIGURE INPUT OFFSET VOLTAGE TEMPERATURE FIGURE INPUT BIAS CURRENT TEMPERATURE ±15V SUPPLY CURRENT (mA) SLEW RATE (V/µs) 3000 ±15V, ±10V FALL 2000 FALL 100) ±12V ±10V 1000 RISE RISE 100) TEMPERATURE (oC) TEMPERATURE (oC) FIGURE SUPPLY CURRENT TEMPERATURE FIGURE SLEW RATE TEMPERATURE 2400 2200 ±15V, 25oC, ±10V 2000 1800 SLEW RATE (V/µs) 1600 1400 1200 1000 1000 5000 10,000 RISE FALL SLEW RATE (V/µs) 1400 1300 1200 1100 1000 ±15V, 25oC, ±10V FALL RISE 1000 5000 10,000 CAPACITANCE (pF) CAPACITANCE (pF) FIGURE SLEW RATE LOAD CAPACITANCE FIGURE SLEW RATE LOAD CAPACITANCE HA-5033 Typical Performance Curves OUTPUT INPUT (mV) OUTPUT INPUT (mV) ±15V, 25oC (Continued) -100 -300 -500 -700 -900 INPUT VOLTAGE ±15V, 25oC INPUT VOLTAGE FIGURE GAIN ERROR INPUT VOLTAGE ±15V, ±10V OUTPUT INPUT (mV) VOUT (mV) FIGURE GAIN ERROR INPUT VOLTAGE ±15, 25oC VOUT SOURCING CURRENT VOUT SINKING CURRENT VOUT VOUT TEMPERATURE (oC) IOUT (mA) FIGURE GAIN ERROR TEMPERATURE PHASE ANGLE (DEGREES) -135 -180 10-1 MAGNITUDE 10-2 FIGURE VOUT IOUT Y21, 10-3 10-4 10-5 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE PARAMETERS PHASE FREQUENCY FIGURE PARAMETER MAGNITUDE FREQUENCY HA-5033 Typical Performance Curves POWER SUPPLY REJECTION RATIO (dB) (Continued) 0.10 TOTAL HARMONIC DISTORTION 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 FREQUENCY (Hz) 100K ±12V, 1VRMS ±12V, 25oC 100K FREQUENCY (Hz) FIGURE POWER SUPPLY REJECTION RATIO FREQUENCY TOTAL HARMONIC DISTORTION ±12V ±12V, 100kHz FIGURE TOTAL HARMONIC DISTORTION FREQUENCY 25oC ±10V LOAD RESISTANCE ±15V ±12V 0.01 INPUT VOLTAGE (RMS) FIGURE TOTAL HARMONIC DISTORTION INPUT VOLTAGE OUTPUT VOLTAGE (VRMS) 100K FREQUENCY (Hz) 100M HEAT SINK FREE ±15V, FIGURE OUTPUT VOLTAGE SWING LOAD RESISTANCE OUTPUT VOLTAGE (VRMS) 100K FREQUENCY (Hz) 100M HEAT SINK FREE ±15V, FIGURE OUTPUT SWING FREQUENCY (NOTE) PEAK PEAK OUTPUT VOLTAGE FIGURE OUTPUT SWING FREQUENCY (NOTE) NOTE: This curve obtained noting output voltage necessary produce observable distortion given frequency. higher distortion acceptable, then higher output voltage given frequency obtained. However, operating HA-5033 with increased distortion right curve shown), will also accompanied increase supply current. resulting increase chip temperature must considered heat sinking will necessary prevent thermal runaway. This characteristic result output transistor operation. signal amplitude signal frequency both increased beyond curve shown, NPN, output transistors will approach condition being simultaneously Under this condition, thermal runaway occur. Characteristics HA-5033 DIMENSIONS: mils mils mils 1300µm 1700µm 483µm METALLIZATION: Type: Thickness: PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2 Phos.) Silox Thickness: Nitride Thickness: SUBSTRATE POTENTIAL (Powered Up): Unbiased TRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5033 HA-5033 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE INDEX AREA -B-AD BASE PLANE SEATING PLANE 0.010 (0.25) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL MILLIMETERS 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES Rev. 12/93 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm). 0.100 0.300 0.115 0.430 0.150 2.54 7.62 10.92 3.81 2.93 HA-5033 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) 0.004 (0.10) N20.35 (JEDEC MS-018AA ISSUE LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 0.385 0.350 0.141 0.385 0.350 0.141 0.180 0.120 0.395 0.356 0.169 0.395 0.356 0.169 MILLIMETERS 4.20 2.29 9.78 8.89 3.59 9.78 8.89 3.59 4.57 3.04 10.03 9.04 4.29 10.03 9.04 4.29 NOTES Rev. 3/95 0.025 (0.64) 0.045 (1.14) D2/E2 D2/E2 VIEW 0.020 (0.51) PLCS 0.020 (0.51) SEATING PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.045 (1.14) 0.025 (0.64) VIEW TYP. NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions. HA-5033 Power Small Outline Plastic Packages (PSOP) INDEX AREA SEATING PLANE 0.25(0.010) M8.15A LEAD POWER SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL MILLIMETERS 1.35 0.10 0.33 0.19 4.80 2.72 3.80 1.80 1.75 0.25 0.51 0.25 5.00 3.12 4.00 2.21 NOTES Rev. 10/96 0.0532 0.0040 0.0130 0.0075 0.1890 0.107 0.1497 0.071 0.0688 0.0098 0.0200 0.0098 0.1968 0.123 0.1574 0.087 0.10(0.004) 0.25(0.010) 0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050 1.27 5.80 0.25 0.40 6.20 0.50 1.27 BOTTOM VIEW NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch) Exposed copper heat slug flush with bottom surface package. other dimensions conform JEDEC MS-012 Issue Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. POWER PACKAGE (HEAT SLUG SURFACE ELECTRICALLY FLOATING) HA-5033 Metal Packages (Can) REFERENCE PLANE T12.C LEAD METAL PACKAGE SYMBOL INCHES 0.130 0.016 0.016 0.585 0.540 0.150 0.019 0.021 0.615 0.560 MILLIMETERS 3.30 0.41 0.41 14.86 13.72 3.81 0.48 0.53 15.62 14.22 NOTES Rev. 5/18/94 BASE METAL LEAD FINISH 0.400 0.100 0.020 0.027 0.027 0.500 0.040 0.034 0.045 0.560 10.16 2.54 0.51 0.69 0.69 12.70 1.02 0.86 1.14 14.22 SECTION NOTES: reference, base, seating planes same this variation. Measured from maximum diameter product. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH. Harris Semiconductor products manufactured, assembled tested under ISO9000 quality systems certification. Harris Semiconductor products sold description only. Harris Semiconductor reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. 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