MCT/IGBT Gate Driver HIP2030 medium voltage integrated circuit (M

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

MCT/IGBT Gate Driver HIP2030 medium voltage integrated circuit (M

Datasheet Thumbnail

Top Searches for this datasheet

HIP2030
MCT/IGBT Gate Driver
HIP2030 medium voltage integrated circuit (MVIC) capable driving large capacitive loads high voltage slew rates (dv/dts). This device optimized driving 60nF gate capacitance peak peak less than 200ns. half bridge gate driver ideal driving Controlled Thyristor (MCT) IGBT modules. architecture HIP2030 includes four comparator input channels, regulator, clamp, high side charge pump. device provides user with ability control minimum time (MLT) minimum high time (MHT) gate channel output (GO) varying external capacitances. addition, device contains uncommitted comparator channels (channels that used monitors (temperature sensing), indicators (LEDs opto-couplers), input signal conditioning (both contain Schmitt triggers), oscillators. power requirements HIP2030 low. driver easily configured operate three power configurations. This allows small mountable transformer battery provide isolated power driver chip. HIP2030 supplies high output current drive large capacitive loads requires external components implement wide variety gate driver circuits.
PACKAGE Lead PLCC
March 1995
Features
Polarity Gate Drive High Output Voltage Swing. Peak Output Current 6.0A Fast Rise Time .200ns 60,000pF Ability Interface Drive P-MCTs Programmable Minimum ON/OFF Time Gate Output Inhibit Latch Reference .Sinks 30mA High Side Charge Pump 120kHz Operation. 15,000pF
Applications
Motor Controllers Uninterruptible Power Supplies Resonant Inverters Static Circuit Breakers Inverters Converters Welders
Ordering Information
PART NUMBER HIP2030IM TEMPERATURE RANGE -40oC +110oC
Pinout
HIP2030 (PLCC) VIEW
B1NC
Functional Block Diagram
CMOS
PMOS
NMOS CHARGE PUMP
CLMP
LATCH LOGIC POWER RESET
CLMP
TIME
HIGH TIME
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1995
File Number
3691.2
Specifications HIP2030
Absolute Maximum Ratings
Gate Channel Supply Voltage, -0.5V Logic Supply Voltage, Other Voltages (A+, B1+, B1-, B2+, B2-, .(P-)-0.5 (P+)+0.5
Thermal Information
Thermal Resistance PLCC Package 60oC/W Storage Temperature Range -65oC +150oC Junction Temperature +150oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Recommended Operating Conditions
-40oC +150oC Unless Otherwise Noted, Voltages Referenced PMax Output Source Current, Channels 10mA Output Sink Current, Channels 10mA Load Current, (Required Proper Chip Operation) Load Current, 30mA
Gate Channel Supply Voltage, -0.5V Logic Supply Voltage, Other Voltages (A+, B1+, B1-, B2+, B2-, (P-)+2V (P0)+2V
Static Electrical Specifications
SYMBOL IQPOS BVP+ VREG RREG VCLMP RCLMP VOCP VOCP RGOSRC RGOSNK RDSSRC RDSSNK
15V, 30V, 2mA. Full Temp -40oC +150oC TEST CONDITIONS TEMP Full +25oC Full 26.5 (VP-)+2 12.5 28.5 27.5 28.5 VP0+2 UNITS
PARAMETER Quiescent Supply Current Quiescent Supply Current
Quiescent Supply Current Breakdown Voltage Regulator Voltage,
Freq 100kHz 100µA IREG IREG 10mA, 30mA ICLMP 15mA ICLMP 15mA, 30mA
Full Full +25oC Full
Regulator Impedance, Clamp Voltage, CLMP PClamp Impedance, CLMP PCharge Pump Frequency Charge Pump Duty Cycle Charge Pump VOUT, PCharge Pump VOUT, PComparator Input Leakage Comparator Offset Voltage Comparator Common Mode Voltage Range Output RDS, Sourcing
Full Full Full Full Full
500µA VINCMP VP0/2 VP0/2 ISRC ISNK ISRC 10mA ISNK 10mA
Full Full Full Full Full +25oC Full +25oC Full +25oC Full +25oC Full
Output RDS, Sinking
Output RDS, Sourcing
Output RDS, Sinking
Dynamic Electrical Specifications
SYMBOL THMIN TLMIN TPLHAB TPLHL TPHLA TRAB PARAMETER Output Duration Output Duration Prop Delay, Chs. Prop Delay, Prop Delay, Rise Time, Channels
15V, 30V, 2mA. Full Temp -40oC +150oC TEST CONDITIONS CLOAD 20pF CLOAD 20pF CLOAD 300pF CLOAD 300pF, CLOAD 300pF, CLOAD 300pF, TEMP Full Full Full Full Full Full 1100 1600 1500 UNITS
Specifications HIP2030
Dynamic Electrical Specifications
SYMBOL TFAL TPLHG TPHLG PARAMETER Fall Time Channels Prop Delay, 15V, 30V, 2mA. Full Temp -40oC +150oC (Continued) TEST CONDITIONS CLOAD 300pF, CLOAD 60nF, CLOAD 60nF, CLOAD 60nF, CLOAD 60nF, TEMP Full +25oC Full Prop Delay, +25oC Full Rise Time, Channel +25oC Full Fall Time Channel +25oC Full UNITS
Timing Waveforms
(LOW)
(LAST STATE) (OUTPUT) (OUTPUT) (HIGH)
FIGURE
(HIGH)
(LAST STATE) (OUTPUT)
(OUTPUT) (UNDEFINED STATE)
Refers state input comparator output
FIGURE
HIP2030 Descriptions
NUMBER SYMBOL ADESCRIPTION Negative Comparator input channel. This input Protected Comparator Input that clamped through resistor. common mode input voltage, Protected Comparator Input, ranges from (VP-) (VP0) +2V. CMOS output (Pin when input "True" input "False". Positive Comparator Input channel. CMOS output (Pin high when input "True" input "False". Negative Comparator input channel. output internal B1-channel comparator when input "True" input "False". Positive Comparator Input channel. output internal B1-channel comparator high when input "True" input "False". Negative Comparator Input channel. output internal B2-channel comparator when input "True" input "False". Positive Comparator Input channel. output internal B2-channel comparator high when input "True" input "False". Negative Comparator Input (Latch) channel. Latch mode operation disabled when "True" "False". NMOS output (Pin active high latch state. output (Pin controlled Gchannel inputs. Positive Comparator Input (Latch) channel. Latch mode operation enabled when "True" "False". NMOS output (Pin active latch state. output (Pin goes "P-MCT OFF" state (VGO VP+) controlled internal L-channel latch; which bypasses G-channel inputs. Latch mode always overrides R-channel. Negative Comparator Input (Reset) channel. Reset mode, internal L-channel latch, disabled when "True" "False". Positive Comparator Input (Reset) channel. Reset mode, internal L-channel latch, enabled when "True" "False". Reset mode (enabled) unlatches internal L-channel latch; which allows G-channel inputs control output (Pin 23). Latch mode must disabled operate reset mode. Negative Comparator Input (Main) channel. G-channel output (Pin goes "P-MCT OFF" state (VGO VP+) when "True" "False". Positive Comparator Input (Main) channel. G-channel output (Pin goes "P-MCT state (VGO VP-) when "True" "False". Input programmable Minimum Time timing capacitor (CT). connecting capacitor between (Pin (Pin 13). approximated equation: (CT)(5V)/(100uA). Input programmable Minimum High Time timing capacitor (CT). connecting capacitor between (Pin (Pin 14). approximated equation: (CT)(5V)/(100µA). becomes Minimum Time function turning N-MCT's. regulator output. opto-coupler fiber-optic receiver power connecting positive voltage (Pin common (Pin 15). internal regulator (REG) must sink current minimum functions work properly. Chip negative supply. This generally used bias power supply common. regulator transistor, charge pump logic referenced (Pin 16). Output Charge Pump Oscillator Inverter stage. 0.47µF capacitor normally connected from this output (Pin 19). Unused pin. Input charge pump steering diode. 0.47µF capacitor normally connected from this input (Pin 18).
HIP2030 Descriptions (Continued)
NUMBER SYMBOL CLMP DESCRIPTION internal clamp that used additional regulation across (Pin (Pin 16). Positive supply rail charge pump. Chip positive supply. This generally used bias power supply positive input. Main channel output (Gate Output). gate output controls switching power devices normally connected P-MCT gate. sink source greater than peak equal 30V. A-Channel Output. CMOS output that switches from (Pin (Pin 16). source sink 10mA current. B-Channel Output. B-channel PMOS output that connects (Pin when turned source 10mA current from L-Channel Output. L-channel NMOS output that connects (Pin latch mode. sink 10mA current. Unused pin. High side output. Connects output charge pump steering diode. 10.0µF capacitor normally connected from this output (Pin supply high side gate voltage.
HIP2030 Application Information
Harris Photo-Coupled Isolated Gate Drive (HPCIGD) circuit, illustrated Figure contains four subcircuits: Single Supply bias, Regulated voltage divider reference, Local Energy Source Capacitance, Photo-Couple Receiver. Single Supply Bias Circuit, shown Figure consists single external dropping resistor (R1) connected between pins (U1-28) (U1-22). When input voltage applied across pins (U1-16), forms resistive divider network with input impedance located between pins (RVP0). This allows circuit designer adjust value obtain desired bias voltage between pins (VP0.). value RVP0 calculated evaluating equivalent Quiescent Input Impedance (RQ) reference impedance (RR) parallel resistances. values RVP0 determined using Equations 1(A, shown Appendix Exercise 1.1. Regulated Voltage Divider Reference comprised resistors connected series located across pins REG. This voltage divider provides stable voltage reference HIP2030 comparator inputs. Resistors selected equal value create midpoint bias reference between peak peak input signal Also, midpoint bias method ensures that input signals generated from midpoint bias reference voltages within safe common mode voltage range comparators. Local Energy Source Capacitances, needed supply charge required drive large capacitance loads high dv/dts. HPCIGD circuit uses cost "oversized" tantalum capacitors 10µF) that used rise times overshoot critical, ceramic capacitors with should used improve gate drive signals. power circuit, where gate driver exposed high dv/dts, network directs noise current away from HIP2030. This allows HFOIGD circuit operate well half bridge power circuits that transformer coupled power source. Photo-Coupled Receiver subcircuit consists photocoupler which combines infrared emitter diode (IRED) high speed photo detector translate light pulses voltage input signals. These signals routed channel used control output Component used limit current through IRED when input signal voltage switches most positive level. wide range input voltages accommodated varying limit IRED current 25mA. speed capacitor selected match forward bias capacitance diode. last component, optional part intended termination resistor with value user. Harris HIP2030 Evaluation Board (HIP2030EVAL) printed circuit board (PCB) developed help evaluate performance HIP2030 MCT/IGBT Driver power switching circuits. component layout HIP2030DB circuit enables user conveniently populate either Photo-Coupled fiber-optic receivers. addition, layout provisions board prototyping" special function components. This facilitates gate drive circuit design allows user exercise internal architecture special functions HIP2030. schematic HIP2030DB, illustrated Figure uses basic HPCIGD circuitry provisions board prototyping" special function components.
HIP2030
TABLE LOGIC INPUTS Input True Input False OUTPUTS Undefined Last State
LLOAD
LSNUBBER
B2B2+
CLMP
GATE RETURN POWER CIRCUIT
HARRIS HIP2030 LEAD PLCC
TLP2601 CONTROL SIGNAL
FIGURE HARRIS PHOTO-COUPLED ISOLATED GATE DRIVE
CSNUBBER
PMCT
CSOURCE
RSNUBBER
VSOURCE
HIP2030
B1P2 10.0 HIP2030 PCPB CLMP 47pF GATE
30VDC
B2B2+ P10GP11
INPUT
SIGNAL
0.10
10µF
TLP2601
FIGURE HARRIS HIP2030 EVALUATION BOARD (NOTE NOTES: Capacitors special function components which control MHT. Asymmetrical gate drive obtained opening adjusting desired voltage ratio. Insert charge pump operation. Open disable charge pump oscillator. Open disable internal regulator. added noise rejection high Cdv/dts. internal reference (REF) must operational functions work properly. access pads comparator inputs. Request Harris File #3918 full description HIP2030EVAL board.
HIP2030 Typical Performance Curves
SUPPLY CURRENT (mA) VOLTAGE +150oC +100 -40oC SUPPLY CURRENT (mA) +25oC
+150oC +100oC +25oC -40oC
VOLTAGE (CHARGE PUMP)
FIGURE SUPPLY CURRENT (IP0) SUPPLY VOLTAGE (P0)
FIGURE SUPPLY CURRENT (IPOS) SUPPLY VOLTAGE (POS)
LOAD CURRENT (mA) -40oC +25oC +100oC +150oC CLAMP VOLTAGE
13.0 12.5 12.0 11.5 11.0 10.5 10.0 CLAMP CURRENT (mA) -40oC +25oC +100oC +150oC
REGULATOR VOLTAGE
FIGURE REGULATOR VOLTAGE LOAD CURRENT
FIGURE CLAMP VOLTAGE CLAMP CURRENT
PROPAGATION DELAY (ns) PROPAGATION DELAY (ns)
+150oC +100oC +25oC -40oC 0.01
+150oC +100oC +25oC
-40oC
0.02 0.03
0.05
0.01
0.02 0.03
0.05
OVERDRIVE VOLTAGE
OVERDRIVE VOLTAGE
FIGURE PROPAGATION DELAY VOLTAGE OVERDRIVE CHANNELS
FIGURE PROPAGATION DELAY VOLTAGE OVERDRIVE CHANNEL
HIP2030 Typical Performance Curves
(Continued)
+150 PROPAGATION DELAY (ns) TEMPERATURE (oC) 0.05 +125 +100 0.02 0.03 FREQUENCY (kHz)
+150oC +100oC +25oC
-40oC
0.01
OVERDRIVE VOLTAGE
FIGURE PROPAGATION DELAY VOLTAGE OVERDRIVE CHANNELS
FIGURE OSCILLATOR FREQUENCY OVER TEMPERATURE CHARGE PUMP
Appendix Exercises
Exercise calculate value series dropping resistor shown Figure values RVPO determined using Equations
maximum value easily determined four design steps: Assume following values: IQPO 2.75mA IOPTO IVDR 2.5mA IRP(ON) 5mA, Select usable value between
-QPO
(EQ.
OPTO
(EQ.
Solve RVP0 using Equations
(EQ.
5.45K
2.75mA
Where: Voltage between pins U16). IQPO Quiescent current flowing into IQPTO Quiescent current HBR-2521 fiberoptic receiver. IVDR Current flowing through (voltage divider reference). Current flowing through pull resistor "ON" "OFF" state)
1.20K 2.5mA
-5.45K 1.20K
Solve using Equation 1(D):
(EQ.
HIP2030 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) 0.004 (0.10)
N28.45 (JEDEC MS-018AB ISSUE
LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES Rev. 3/95
0.025 (0.64) 0.045 (1.14)
D2/E2
D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51)
SEATING PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14)
0.025 (0.64) VIEW TYP.
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
Harris Semiconductor products sold description only. Harris Semiconductor reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Harris believed accurate reliable. However, responsibility assumed Harris subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Harris subsidiaries.
Sales Office Headquarters
general information regarding Harris Semiconductor products, call 1-800-4-HARRIS UNITED STATES Harris Semiconductor 883, Mail Stop 53-210 Melbourne, 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Fusee 1130 Brussels, Belgium TEL: (32) 2-724-2111 SOUTH ASIA Harris Semiconductor H.K. Ltd. 13/F Fourseas Building 208-212 Nathan Road Tsimshatsui, Kowloon Hong Kong TEL: (852) 723-6339 NORTH ASIA Harris K.K. Kojimachi-Nakata Bldg. 5-3-5 Kojimachi Chiyoda-ku, Tokyo Japan TEL: (81) 3-3265-7571 TEL: (81) 3-3265-7572 (Sales)

MCT/IGBT Gate Driver HIP2030 medium voltage integrated circuit (M

Top Searches for this datasheet

Other recent searches