Dual 4-Input NAND Gate Functional Diagram June 1997 COM
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CD54HC20/3A CD54HCT20/3A
Dual 4-Input NAND Gate
Functional Diagram
June 1997
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Description
CD54HC20/3A CD54HCT20/3A logic gates utilize silicon-gate CMOS technology achieve operating speeds similar LSTTL gates with power consumption standard CMOS integrated circuits. devices have ability drive LSTTL loads. CD54HCT logic family functionally well compatible with standard 54LS logic family.
INPUT LOAD TABLE INPUT NOTE: Unit load limit specified Electrical Specifications Table, e.g., 360µA +25oC. UNIT LOAD (NOTE 0.15
Absolute Maximum Ratings
Supply Voltage, Voltages Referenced -0.5V +7.0V Input Voltage Range, Inputs, -0.5V +0.5V Output Voltage Range, Outputs, VOUT -0.5V +0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V Standard Output .±25mA Driver Output. .±35mA Current, Standard Output .±50mA Driver Output. .±70mA Power Dissipation Package, -55oC +100oC (Package 500mW +100oC +125oC (Package Derate Linearly 8mW/ 300mW Operating Temperature Range, Package Type -55oC +125oC Storage Temperature, TSTG -65oC +150oC Lead Temperature (During Soldering) Distance 1/16in. 1/32in. (1.59mm 0.79mm) From Case +265oC Unit Inserted Into Board (Min Thickness 1/16in., 1.59mm) With Solder Contacting Lead Tips Only. +300oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Recommended Operating Conditions
Supply Voltage Range, Full Package Temperature Range CD54HC Types CD54HCT Types .4.5V 5.5V Input Output Voltage, VIN, VOUT Operating Temperature Range, -55oC +125oC Input Rise Fall Times, 1000ns 4.5V 500ns 400ns
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright
Harris Corporation 1994
File Number
3761
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