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EE-283

Technical notes on using Analog Devices DSPs, processors and development tools

Engineer-to-Engineer Note
EE-283
Technical notes on using Analog Devices DSPs, processors and development tools
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External Bus Arbitration with ADSP-TS20x TigerSHARC® Processors
Contributed by Stephen Francis Rev 1 - February 10, 2006
1 Introduction
The following Engineer-to-Engineer note discusses external port bus arbitration on ADSP-TS20x TigerSHARC® processors. The intention of this EE-Note is to complement the Multiprocessing Interface and Bus Arbitration Protocol sections of the External Port chapter of the ADSP-TS201 TigerSHARC Processor Hardware Reference manual1. Example code, in which each TigerSHARC processor in a three-processor system uses the shared external bus to transfer data from its internal memory to the internal memory of another TigerSHARC processor and the resulting captured waveforms highlight the ADSP-TS20x external bus arbitration scheme.
Figure 1. ADSP-TS201 Processor Block Diagram
2 Table of Contents
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3 Bus Arbitration Protocol
The rotating bus arbitration protocol implemented on TigerSHARC processors ensures bus fairness among TigerSHARC processors in a cluster. After reset, the TigerSHARC processor with ID0 becomes the bus master and the external bus priority rotates in a round-robin fashion, going up from the present master. The bus arbitration is determined by the current external bus master and the state of the / BRx pins of each TigerSHARC processor in the multiprocessing system. A host or a TigerSHARC processor with a higher priority request than the current bus master can gain control of the external bus from the current bus master. A host will assert its / HBR signal to request the external bus. A processor requesting the external bus with a core access will assert its / CPA signal in addition to its / BR signal to signify the high-priority external bus request. A processor requesting the external bus with a DMA access configured for high priority will assert its / DPA signal (but only if / CPA is not asserted) in addition to its / BR signal to signify the high-priority external bus request. The external bus priority in descending order is: 1. Host 2. TigerSHARC processor ( / BR and / CPA asserted) 3. TigerSHARC processor ( / BR and / DPA asserted) 4. TigerSHARC processor ( / BR asserted) The following sections discuss the effects of normal-priority external bus accesses and high-priority external bus accesses on the external bus arbitration protocol. Example code and resulting waveforms captured from a three-processor system highlight the bus arbitration protocol implemented on the TigerSHARC processor. For more information on the multiprocessing interface and bus arbitration protocol implemented on the TigerSHARC, refer to the External Port and SDRAM Interface chapter in the ADSP-TS201 TigerSHARC Processor Hardware Reference.
4 Normal Priority Accesses
4.1 Normal-Priority External Bus Arbitration Sequence: / CPA, / DPA Inactive (no Host Present) (Example 1) Table 1 shows the external bus settings and the data transfer details for each TigerSHARC processor in Example 1. The captured signals for this example appear in Figure 2.
External Bus Settings Bus width: 64 bits Bus speed: 60 MHz. Processor A (ID0) B (ID1) C (ID2) Table 1. Bus Settings and Data Transfer Details Data Transfer 64 normal word external port DMA transfer Quad-word transfer, normal priority 64 normal word external port DMA transfer Quad-word transfer, normal priority 64 normal word external port DMA transfer Quad-word transfer, normal priority
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As shown in Figure 2, processor A (ID0) gains control of the external bus first and completes its DMA transfer. Processor B (ID1) is next to gain control of the external bus and completes its DMA transfer. Processor C (ID2) is next to gain control of the external bus and completes its DMA transfer. Because each of the transfers is an external port DMA transfer with normal priority (and not a core access or host access), the / CPA, / DPA, and / HBR signals (Channel 4) are inactive in this example thus, the external bus mastership is determined by the Processor IDs (ID0-ID2 in this example).
Figure 2. Normal-Priority External Bus Arbitration Sequence: / CPA, / DPA Inactive (no Host present) (Example 1)
5 High-Priority Accesses
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than one TigerSHARC processor requests the bus by asserting their / BR signals along with / DPA, the TigerSHARC processor with the highest priority gains the bus mastership. The following two examples highlight the external bus arbitration scheme on the TigerSHARC processor for high-priority DMA accesses over the external port.
5.1.1 High-Priority External Bus DMA Transfer by a TigerSHARC Processor (Processor B) in a Three-Processor Multiprocessing System (Example 2)
External Bus Settings Bus width: 64 bits Bus speed: 60 MHz. Processor A (ID0) B (ID1) C (ID2) Table 2. Bus Settings and Data Transfer Details Data Transfer External port DMA transfer: 64 words Quad-word transfer, normal priority 64 normal word external port DMA transfer Quad-word transfer, high priority 64 normal word external port DMA transfer Quad-word transfer, normal priority
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Figure 3. High-Priority External Bus DMA Transfer by a TigerSHARC Processor (Processor B) in a ThreeProcessor Multiprocessing System (Example 2)
Table 3 shows the external bus settings and the data transfer details for each processor in Example 3. In this example, the DMA transfers of processor B and processor C are intentionally delayed by a few
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External Bus Settings Bus width: 64 bits Bus Speed: 60 MHz Processor A (ID0) B (ID1) C (ID2) Table 3. Bus Settings and Data Transfer Details Data Transfer 64 normal word external port DMA transfer Quad-word transfer, normal priority 64 normal word external port DMA transfer Quad-word transfer, normal priority 64 normal word external port DMA transfer Quad-word transfer, high priority
Figure 5. High-Priority External Bus DMA Transfer by a TigerSHARC Processor (Processor C) in a ThreeProcessor Multiprocessing System (Example 3)
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to complete its normal-priority DMA transfer, then gains control of the external bus after processor A and completes the DMA transfer. 5.2 Core Priority Access ( / CPA) The core priority access ( / CPA) pin is asserted when the TigerSHARC processor core accesses the external bus. This allows a slave TigerSHARC processor to interrupt background transfers of a DMA channel belonging to a master TigerSHARC processor and gain control of the external bus. After completing the current transaction (a normal, long, or quad-word transfer), the current TigerSHARC external bus master passes the external bus mastership to the requesting TigerSHARC processor by deasserting its / BR. In a multiprocessing system, when one TigerSHARC processor asserts the / CPA signal, TigerSHARC processors with DMA transactions de-assert their / BR signals (and / DPA signals in highpriority DMA transactions). When more than one TigerSHARC processor requests the bus by asserting its / BR and / CPA, the TigerSHARC processor with the highest priority gains bus mastership. The following two examples highlight the external bus arbitration scheme on the TigerSHARC processor for core priority accesses over the external port.
5.2.1 Core Access Over the External Bus by a TigerSHARC Processor in a Three-Processor Multiprocessing System (Example 4)
Table 4. Example 4-Bus Settings and Data Transfer Details
priority DMA transfer occurred, gains control of the external bus after processor C and completes its normal-priority DMA transfer.
Figure 6. Core Access Over the External Bus by a TigerSHARC Processor in a Three-Processor Multiprocessing System (Example 4)
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5.2.2 Core Accesses over External Bus by two TigerSHARC processors in a three TigerSHARC Processor Multiprocessing System (Example 5)
Table 5. Example 5 Bus Settings and Data Transfer Details
Figure 8. Core Accesses Over External Bus by Two TigerSHARC Processors in a Three-Processor Multiprocessing System (Example 5)
When processor B (ID1) completes its core access over the external bus, it de-asserts its / BR and processor C (ID2) gains control of the external bus and performs its core access. The / CPA signal
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(Channel 4 (green)) remains asserted. When processor C completes its core access over the external bus, it de-asserts its / BR and the / CPA signal is also de-asserted. Processor A (ID0), which had not completed its normal-priority DMA transfer, then regains control of the external bus after processor C (ID2) and completes its normal-priority DMA transfer. 5.3 / DPA and / CPA Accesses in a TigerSHARC Multiprocessing System In a TigerSHARC processor cluster system, the requesting bus agents with an active / CPA have higher priority over requesting the bus agents with an active / DPA. So, requesting bus agents with an active / DPA de-assert their / BR signals (and / DPA signals) upon sensing that a / CPA is asserted by other bus agents. The following three examples highlight how the external bus arbitration scheme on the TigerSHARC processor functions when there are both / CPA and / DPA accesses in a TigerSHARC processor cluster system.
5.3.1 High-Priority DMA Transfer, Core Access Over the External Bus in a TigerSHARC Processor Multiprocessing System (Example 6)
Table 6. Example 6-Bus Settings and Data Transfer Details
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Figure 9. High-Priority DMA Transfer, Core Access Over the External Bus in a TigerSHARC Processor Multiprocessing System (Example 6)
Figure 10. High-Priority DMA Transfer, Core Access Over the External Bus in a TigerSHARC Processor Multiprocessing System (Example 6) 5.3.2 High-Priority DMA Transfer, Core Access, Normal-Priority DMA Transfer Over the External Bus in a ThreeProcessor Multiprocessing System (Example 7)
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Table 7. Example 7-Bus Settings and Data Transfer Details
Figure 11. High-Priority DMA Transfer, Core Access, Normal-Priority DMA Transfer Over the External Bus in a Three-Processor Multiprocessing System (Example 7)
Processor A and processor C assert their / BR signals, and processor A also asserts its / DPA signal. Processor C is next after processor B in the ADSP-TS201 arbitration scheme but recognizes that processor A has a high-priority DMA transfer and de-asserts its / BR signal. Processor A completes its high-priority DMA transfer and de-asserts its / BR and / DPA signals. Processor B is not requesting the bus
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Table 8. Example 8-Bus Settings and Data Transfer Details
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Figure 13. High-Priority DMA Transfer, Core Access, High-Priority DMA Transfer Over the External Bus in a ThreeProcessor Multiprocessing System (Example 8)
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6 Conclusion
This EE-Note discusses the TigerSHARC multiprocessing interface and how each TigerSHARC processor and host in a TigerSHARC multiprocessing system arbitrates for the use of the shared external bus in the multiprocessing system. Accompanying example code and resulting waveforms captured from a threeprocessor system highlight the bus arbitration scheme.
7 References
1 ADSP-TS201 TigerSHARC Processor Hardware Reference. Rev.1.1, December 2004. Analog Devices, Inc. 2 ADSP-TS201 TigerSHARC Processor Programming Reference. Rev.1.1, April 2004. Analog Devices, Inc.
8 Document History
Revision Rev 1 - February 10, 2006 by S. Francis Description Initial Release
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