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EE-283
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External Arbitration with ADSP-TS20x TigerSHARC® Processors
Contributed Stephen Francis February 2006
Introduction
following Engineer-to-Engineer note discusses external port arbitration ADSP-TS20x TigerSHARC® processors. intention this EE-Note complement Multiprocessing Interface Arbitration Protocol sections External Port chapter ADSP-TS201 TigerSHARC Processor Hardware Reference manual[1]. Example code, which each TigerSHARC processor three-processor system uses shared external transfer data from internal memory internal memory another TigerSHARC processor resulting captured waveforms highlight ADSP-TS20x external arbitration scheme.
Figure ADSP-TS201 Processor Block Diagram
Copyright 2006, Analog Devices, Inc. rights reserved. Analog Devices assumes responsibility customer product design application customers' products infringements patents rights others which result from Analog Devices assistance. trademarks logos property their respective holders. Information furnished Analog Devices applications development tools engineers believed accurate reliable, however responsibility assumed Analog Devices regarding technical accuracy topicality content provided Analog Devices Engineer-to-Engineer Notes.
Table Contents
Introduction. Table Contents. Arbitration Protocol Normal Priority Accesses Normal-Priority External Arbitration Sequence: /CPA, /DPA Inactive Host Present) (Example High-Priority Accesses Priority Access (/DPA). 5.1.1 High-Priority External Transfer TigerSHARC Processor (Processor Three-Processor Multiprocessing System (Example 5.1.2 High Priority External Transfer TigerSHARC Processor (Processor Three-Processor Multiprocessing System (Example Core Priority Access (/CPA) 5.2.1 Core Access Over External TigerSHARC Processor Three-Processor Multiprocessing System (Example 5.2.2 Core Accesses over External TigerSHARC processors three TigerSHARC Processor Multiprocessing System (Example /DPA /CPA Accesses TigerSHARC Multiprocessing System. 5.3.1 High-Priority Transfer, Core Access Over External TigerSHARC Processor Multiprocessing System (Example 5.3.2 High-Priority Transfer, Core Access, Normal-Priority Transfer Over External Three-Processor Multiprocessing System (Example 5.3.3 High-Priority Transfer, Core Access, High-Priority Transfer Over External Three-Processor Multiprocessing System (Example Host Accesses Conclusion References Document History
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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Arbitration Protocol
rotating arbitration protocol implemented TigerSHARC processors ensures fairness among TigerSHARC processors cluster. After reset, TigerSHARC processor with becomes master external priority rotates round-robin fashion, going from present master. arbitration determined current external master state /BRx pins each TigerSHARC processor multiprocessing system. host TigerSHARC processor with higher priority request than current master gain control external from current master. host will assert /HBR signal request external bus. processor requesting external with core access will assert /CPA signal addition signal signify high-priority external request. processor requesting external with access configured high priority will assert /DPA signal (but only /CPA asserted) addition signal signify high-priority external request. external priority descending order Host TigerSHARC processor (/BR /CPA asserted) TigerSHARC processor (/BR /DPA asserted) TigerSHARC processor (/BR asserted) following sections discuss effects normal-priority external accesses high-priority external accesses external arbitration protocol. Example code resulting waveforms captured from three-processor system highlight arbitration protocol implemented TigerSHARC processor. more information multiprocessing interface arbitration protocol implemented TigerSHARC, refer External Port SDRAM Interface chapter ADSP-TS201 TigerSHARC Processor Hardware Reference.
Normal Priority Accesses
Normal-Priority External Arbitration Sequence: /CPA, /DPA Inactive Host Present) (Example Table shows external settings data transfer details each TigerSHARC processor Example captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Table Settings Data Transfer Details Data Transfer normal word external port transfer Quad-word transfer, normal priority normal word external port transfer Quad-word transfer, normal priority normal word external port transfer Quad-word transfer, normal priority
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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shown Figure processor (ID0) gains control external first completes transfer. Processor (ID1) next gain control external completes transfer. Processor (ID2) next gain control external completes transfer. Because each transfers external port transfer with normal priority (and core access host access), /CPA, /DPA, /HBR signals (Channel inactive this example; thus, external mastership determined Processor (ID0-ID2 this example).
Figure Normal-Priority External Arbitration Sequence: /CPA, /DPA Inactive Host present) (Example
High-Priority Accesses
arbitration scheme TigerSHARC processor allows host processor gain temporary priority over current external master. TigerSHARC processor cluster also gain temporary access over current external master with high-priority external port access, core access over external bus, using corresponding /DPA /CPA pins. Priority Access (/DPA) priority access (/DPA) asserted when TigerSHARC processor's channel configured high priority accesses external bus. This allows channel configured high priority (belonging slave TigerSHARC processor) interrupt background transfers normalpriority channel belonging master TigerSHARC processor gain control external bus. this case, current external master this case completes current transaction (normal, long, quad-word transfer) passes external mastership requesting TigerSHARC processor de-asserting /BR. multiprocessing system, when TigerSHARC processors assert /DPA signal, TigerSHARC processors with normal-priority transactions de-assert their signals. When more
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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than TigerSHARC processor requests asserting their signals along with /DPA, TigerSHARC processor with highest priority gains mastership. following examples highlight external arbitration scheme TigerSHARC processor high-priority accesses over external port.
5.1.1 High-Priority External Transfer TigerSHARC Processor (Processor Three-Processor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example this example, transfers processor processor intentionally delayed cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Table Settings Data Transfer Details Data Transfer External port transfer: words Quad-word transfer, normal priority normal word external port transfer Quad-word transfer, high priority normal word external port transfer Quad-word transfer, normal priority
shown Figure processor (ID0) gains control external first starts normalpriority transfer. Processor (ID1) processor (ID2) assert their signals after intentional delay. means high-priority transfer, processor (ID1) breaks gains control external from processor completes high-priority transfer. Processor /DPA (Channel (green)) signal also asserted, which signifies high-priority transfer. Processor (after completing current external transaction) processor de-assert their signals when processor /DPA signals asserted. When processor completed highpriority transfer, de-asserts /DPA signals. Processor processor then re-assert their signals. arbitration protocol ADSP-TS201 dictates that processor next receive control external (Figure processor (ID2) gains control external completes normalpriority transfer. Figure shows captured signals from same example with Channel (green) processor signal, showing that processor gained control external bus. Processor (ID0), which completed normal-priority transfer when processor highpriority transfer occurred gains control external after processor completes normal-priority transfer.
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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Figure High-Priority External Transfer TigerSHARC Processor (Processor ThreeProcessor Multiprocessing System (Example
Figure High-Priority External Transfer TigerSHARC Processor (Processor ThreeProcessor Multiprocessing System, Showing Processor signal (Example 5.1.2 High Priority External Transfer TigerSHARC Processor (Processor Three-Processor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example this example, transfers processor processor intentionally delayed
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits Speed: Processor (ID0) (ID1) (ID2) Table Settings Data Transfer Details Data Transfer normal word external port transfer Quad-word transfer, normal priority normal word external port transfer Quad-word transfer, normal priority normal word external port transfer Quad-word transfer, high priority
Figure High-Priority External Transfer TigerSHARC Processor (Processor ThreeProcessor Multiprocessing System (Example
shown Figure processor (ID0) gains control external first starts normalpriority transfer. Processor (ID1) processor (ID2) assert their signals after intentional delay. means high-priority transfer, processor (ID2) breaks gains control external from processor completes high-priority transfer. Processor /DPA (Channel (green)) signal also asserted, which signifies high-priority transfer. Processor (after completing current external transaction) processor de-assert their signals when processor /DPA signals asserted. When processor completed transfer, de-asserts /DPA signals. Processor processor then re-assert their signals. arbitration scheme ADSP-TS201 dictates that processor next receive control external after processor (ID2) completed transfer this three-processor system shown Figure Processor (ID0) gains control external completes normal-priority transfer. Processor (ID1), which next arbitration scheme still waiting
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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complete normal-priority transfer, then gains control external after processor completes transfer. Core Priority Access (/CPA) core priority access (/CPA) asserted when TigerSHARC processor core accesses external bus. This allows slave TigerSHARC processor interrupt background transfers channel belonging master TigerSHARC processor gain control external bus. After completing current transaction normal, long, quad-word transfer), current TigerSHARC external master passes external mastership requesting TigerSHARC processor deasserting /BR. multiprocessing system, when TigerSHARC processor asserts /CPA signal, TigerSHARC processors with transactions de-assert their signals (and /DPA signals highpriority transactions). When more than TigerSHARC processor requests asserting /CPA, TigerSHARC processor with highest priority gains mastership. following examples highlight external arbitration scheme TigerSHARC processor core priority accesses over external port.
5.2.1 Core Access Over External TigerSHARC Processor Three-Processor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example data transfers processor processor intentionally delayed cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Data Transfer normal word external port transfer Quad-word transfer, normal priority Core data transfer another processor's internal memory over external normal word external port transfer Quad-word transfer, normal priority
Table Example 4-Bus Settings Data Transfer Details
shown Figure processor (ID0) gains control external first starts normalpriority transfer. Processor (ID1) attempting acquire external core access will therefore assert both corresponding /CPA signals. Processor (ID2) asserts signal signify data transfer. assertion /CPA causes processor de-assert because attempting core access over cluster bus. same reason, processor also deasserts (after completing current external transaction) thus relinquishing processor When processor completed core access over external bus, de-asserts /CPA signals. Processor processor then re-assert their corresponding signals. arbitration scheme ADSP-TS201 dictates that processor next receive control external (Figure processor (ID2) gains control external completes normalpriority transfer. Figure shows captured signals from same example with Channel (green) processor signal, showing that processor gained control external bus. Processor (ID0), which completed normal-priority transfer when processor highExternal Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283) Page
priority transfer occurred, gains control external after processor completes normal-priority transfer.
Figure Core Access Over External TigerSHARC Processor Three-Processor Multiprocessing System (Example
Figure Core Access Over External TigerSHARC Processor Three-Processor Multiprocessing System, Showing Processor signal (Example
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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5.2.2 Core Accesses over External TigerSHARC processors three TigerSHARC Processor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example Processor processor core accesses another processor over external intentionally delayed cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Data Transfer normal word external port transfer Quad-word transfer, normal priority Core data transfer another processor's internal memory over external Core data transfer another processor's internal memory over external
Table Example Settings Data Transfer Details
shown Figure processor (ID0) gains control external first starts normalpriority transfer. Processor (ID1) processor (ID2) assert their /CPA signals after intentional delay signify their core accesses other processors cluster over external bus. Because core accesses over external have higher priority than processor normal-priority transfer, processor (ID1), which highest priority, gains control external performs core access over external bus. Processor de-asserts signal (after completing current external transaction).
Figure Core Accesses Over External TigerSHARC Processors Three-Processor Multiprocessing System (Example
When processor (ID1) completes core access over external bus, de-asserts processor (ID2) gains control external performs core access. /CPA signal
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283) Page
(Channel (green)) remains asserted. When processor completes core access over external bus, de-asserts /CPA signal also de-asserted. Processor (ID0), which completed normal-priority transfer, then regains control external after processor (ID2) completes normal-priority transfer. /DPA /CPA Accesses TigerSHARC Multiprocessing System TigerSHARC processor cluster system, requesting agents with active /CPA have higher priority over requesting agents with active /DPA. requesting agents with active /DPA de-assert their signals (and /DPA signals) upon sensing that /CPA asserted other agents. following three examples highlight external arbitration scheme TigerSHARC processor functions when there both /CPA /DPA accesses TigerSHARC processor cluster system.
5.3.1 High-Priority Transfer, Core Access Over External TigerSHARC Processor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example this example, processor core accesses intentionally delayed cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Data Transfer normal word external port transfer Quad-word transfer, high priority Core data transfer another processor's internal memory over external Idle
Table Example 6-Bus Settings Data Transfer Details
shown Figure processor (ID0) gains control external first starts high-priority transfer. Processor /DPA signal also asserted signify high-priority transfer. Processor (ID1) asserts signal after intentional delay signify core accesses processor over external bus. Processor /CPA signal also asserted, which signifies core access over external bus. Processor recognizes higher priority core access over external from processor relinquishes control external de-asserting /DPA signals (after completing current external transaction). Processor completes core accesses processor over external de-asserts /CPA signals. Processor which completed high-priority transfer, then re-asserts /DPA signals completes transfer. Figure shows another screen capture same signals same example.
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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Figure High-Priority Transfer, Core Access Over External TigerSHARC Processor Multiprocessing System (Example
Figure High-Priority Transfer, Core Access Over External TigerSHARC Processor Multiprocessing System (Example 5.3.2 High-Priority Transfer, Core Access, Normal-Priority Transfer Over External ThreeProcessor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example this example, processor core accesses processor normal transfer intentionally
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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delayed cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Data Transfer normal word external port transfer Quad-word transfer, high priority Core data transfer another processor's internal memory over external normal word external port transfer Quad-word transfer, normal priority
Table Example 7-Bus Settings Data Transfer Details
shown Figure processor (ID0) gains control external first starts high-priority transfer. Processor /DPA signal also asserted signify high-priority transfer. Processor (ID1) asserts signal after intentional delay signify core accesses processor over external bus. Processor /CPA signal (not shown Figure also asserted, which signifies core access over external bus. Processor recognizes higher priority core access from processor relinquishes control external de-asserting /DPA signals (after completing current external transaction). Processor completes core accesses processor over external de-asserts /CPA signals.
Figure High-Priority Transfer, Core Access, Normal-Priority Transfer Over External Three-Processor Multiprocessing System (Example
Processor processor assert their signals, processor also asserts /DPA signal. Processor next after processor ADSP-TS201 arbitration scheme recognizes that processor high-priority transfer de-asserts signal. Processor completes high-priority transfer de-asserts /DPA signals. Processor requesting
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283) Page
this time processor gains control external completes normal-priority transfer. Figure shows captured signals same example, shows processor signal.
Figure High-Priority Transfer, Core Access, Normal-Priority Transfer Over External Three-Processor Multiprocessing System, Showing Processor signal (Example 5.3.3 High-Priority Transfer, Core Access, High-Priority Transfer Over External ThreeProcessor Multiprocessing System (Example
Table shows external settings data transfer details each processor Example this example, processor core accesses processor normal transfer intentionally delayed cycles allow processor transfer start. captured signals this example appear Figure
External Settings width: bits speed: MHz. Processor (ID0) (ID1) (ID2) Data Transfer normal word external port transfer Quad-word transfer, high priority Core data transfer another processor's internal memory over external normal word external port transfer Quad-word transfer, high priority
Table Example 8-Bus Settings Data Transfer Details
shown Figure processor (ID0) gains control external first starts high-priority transfer. Processor /DPA signal also asserted signify high-priority transfer. Processor (ID1) asserts signal after intentional delay signify core accesses processor over external bus. Processor /CPA signal (not shown) also asserted, which signifies core access over external bus. Processor recognizes higher priority core access from
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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processor relinquishes control external de-asserting /DPA signals (after completing current external transaction). Processor completes core accesses processor over external de-asserts /CPA signals. Processor processor assert their /DPA signals. Processor which next after processor ADSP-TS201 arbitration scheme, completes high-priority transfer deasserts /DPA signal. Processor completes high-priority transfer de-asserts /DPA signals. /DPA signal (Channel (green)) remains asserted high-priority transfers both processor processor because /DPA signals tied together this board. Figure shows captured signals same example, shows processor signal.
Figure High-Priority Transfer, Core Access, High-Priority Transfer Over External ThreeProcessor Multiprocessing System (Example
Host Accesses host master TigerSHARC processor's external bus-it uses /HBR /HBG gain control bus. order host become master, host must assert /HBR wait until /HBG asserted current TigerSHARC processor master. TigerSHARC processor relinquishes external indicates this asserting /HBG. After completing outstanding transactions, host keeps /HBR asserted long needs bus. master that last relinquished keeps line asserted, that when host de-asserts /HBR, becomes master again.
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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Figure High-Priority Transfer, Core Access, High-Priority Transfer Over External ThreeProcessor Multiprocessing System, Showing Processor signal (Example
Conclusion
This EE-Note discusses TigerSHARC multiprocessing interface each TigerSHARC processor host TigerSHARC multiprocessing system arbitrates shared external multiprocessing system. Accompanying example code resulting waveforms captured from threeprocessor system highlight arbitration scheme.
References
ADSP-TS201 TigerSHARC Processor Hardware Reference. Rev.1.1, December 2004. Analog Devices, Inc. ADSP-TS201 TigerSHARC Processor Programming Reference. Rev.1.1, April 2004. Analog Devices, Inc.
Document History
Revision February 2006 Francis Description Initial Release
External Arbitration with ADSP-TS20x TigerSHARC® Processors (EE-283)
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